MBED-DEV only fro Nucleo STM32F303K8T6
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.h@151:acf04f8e7d03, 2016-11-19 (annotated)
- Committer:
- pravinautosys
- Date:
- Sat Nov 19 10:38:54 2016 +0000
- Revision:
- 151:acf04f8e7d03
- Parent:
- 149:156823d33999
MyMBED-DEVWithSTM32F303K8T6;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f3xx_hal_nand.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.3.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 01-July-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief Header file of NAND HAL module. |
<> | 144:ef7eb2e8f9f7 | 8 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 9 | * @attention |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 19 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 21 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 22 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 36 | */ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 39 | #ifndef __STM32F3xx_HAL_NAND_H |
<> | 144:ef7eb2e8f9f7 | 40 | #define __STM32F3xx_HAL_NAND_H |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 43 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 47 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
<> | 144:ef7eb2e8f9f7 | 48 | #include "stm32f3xx_ll_fmc.h" |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /** @addtogroup STM32F3xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 51 | * @{ |
<> | 144:ef7eb2e8f9f7 | 52 | */ |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | /** @addtogroup NAND |
<> | 144:ef7eb2e8f9f7 | 55 | * @{ |
<> | 144:ef7eb2e8f9f7 | 56 | */ |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | /** @addtogroup NAND_Private_Constants |
<> | 144:ef7eb2e8f9f7 | 59 | * @{ |
<> | 144:ef7eb2e8f9f7 | 60 | */ |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | #define NAND_DEVICE1 FMC_BANK2 |
<> | 144:ef7eb2e8f9f7 | 63 | #define NAND_DEVICE2 FMC_BANK3 |
<> | 144:ef7eb2e8f9f7 | 64 | #define NAND_WRITE_TIMEOUT ((uint32_t)1000) |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ |
<> | 144:ef7eb2e8f9f7 | 67 | #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | #define NAND_CMD_AREA_A ((uint8_t)0x00) |
<> | 144:ef7eb2e8f9f7 | 70 | #define NAND_CMD_AREA_B ((uint8_t)0x01) |
<> | 144:ef7eb2e8f9f7 | 71 | #define NAND_CMD_AREA_C ((uint8_t)0x50) |
<> | 144:ef7eb2e8f9f7 | 72 | #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | #define NAND_CMD_WRITE0 ((uint8_t)0x80) |
<> | 144:ef7eb2e8f9f7 | 75 | #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) |
<> | 144:ef7eb2e8f9f7 | 76 | #define NAND_CMD_ERASE0 ((uint8_t)0x60) |
<> | 144:ef7eb2e8f9f7 | 77 | #define NAND_CMD_ERASE1 ((uint8_t)0xD0) |
<> | 144:ef7eb2e8f9f7 | 78 | #define NAND_CMD_READID ((uint8_t)0x90) |
<> | 144:ef7eb2e8f9f7 | 79 | #define NAND_CMD_STATUS ((uint8_t)0x70) |
<> | 144:ef7eb2e8f9f7 | 80 | #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) |
<> | 144:ef7eb2e8f9f7 | 81 | #define NAND_CMD_RESET ((uint8_t)0xFF) |
<> | 144:ef7eb2e8f9f7 | 82 | |
<> | 144:ef7eb2e8f9f7 | 83 | /* NAND memory status */ |
<> | 144:ef7eb2e8f9f7 | 84 | #define NAND_VALID_ADDRESS ((uint32_t)0x00000100) |
<> | 144:ef7eb2e8f9f7 | 85 | #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) |
<> | 144:ef7eb2e8f9f7 | 86 | #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) |
<> | 144:ef7eb2e8f9f7 | 87 | #define NAND_BUSY ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 88 | #define NAND_ERROR ((uint32_t)0x00000001) |
<> | 144:ef7eb2e8f9f7 | 89 | #define NAND_READY ((uint32_t)0x00000040) |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | /** |
<> | 144:ef7eb2e8f9f7 | 92 | * @} |
<> | 144:ef7eb2e8f9f7 | 93 | */ |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | /** @addtogroup NAND_Private_Macros |
<> | 144:ef7eb2e8f9f7 | 96 | * @{ |
<> | 144:ef7eb2e8f9f7 | 97 | */ |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /** |
<> | 144:ef7eb2e8f9f7 | 100 | * @brief NAND memory address computation. |
<> | 144:ef7eb2e8f9f7 | 101 | * @param __ADDRESS__: NAND memory address. |
<> | 144:ef7eb2e8f9f7 | 102 | * @param __HANDLE__ : NAND handle. |
<> | 144:ef7eb2e8f9f7 | 103 | * @retval NAND Raw address value |
<> | 144:ef7eb2e8f9f7 | 104 | */ |
<> | 144:ef7eb2e8f9f7 | 105 | #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ |
<> | 144:ef7eb2e8f9f7 | 106 | (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize)))) |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | /** |
<> | 144:ef7eb2e8f9f7 | 109 | * @brief NAND memory address cycling. |
<> | 144:ef7eb2e8f9f7 | 110 | * @param __ADDRESS__: NAND memory address. |
<> | 144:ef7eb2e8f9f7 | 111 | * @retval NAND address cycling value. |
<> | 144:ef7eb2e8f9f7 | 112 | */ |
<> | 144:ef7eb2e8f9f7 | 113 | #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 114 | #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 115 | #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 116 | #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 144:ef7eb2e8f9f7 | 118 | /** |
<> | 144:ef7eb2e8f9f7 | 119 | * @} |
<> | 144:ef7eb2e8f9f7 | 120 | */ |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | /* Exported typedef ----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 123 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 124 | /** @defgroup NAND_Exported_Types NAND Exported Types |
<> | 144:ef7eb2e8f9f7 | 125 | * @{ |
<> | 144:ef7eb2e8f9f7 | 126 | */ |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | /** |
<> | 144:ef7eb2e8f9f7 | 129 | * @brief HAL NAND State structures definition |
<> | 144:ef7eb2e8f9f7 | 130 | */ |
<> | 144:ef7eb2e8f9f7 | 131 | typedef enum |
<> | 144:ef7eb2e8f9f7 | 132 | { |
<> | 144:ef7eb2e8f9f7 | 133 | HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ |
<> | 144:ef7eb2e8f9f7 | 134 | HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ |
<> | 144:ef7eb2e8f9f7 | 135 | HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 136 | HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ |
<> | 144:ef7eb2e8f9f7 | 137 | }HAL_NAND_StateTypeDef; |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /** |
<> | 144:ef7eb2e8f9f7 | 140 | * @brief NAND Memory electronic signature Structure definition |
<> | 144:ef7eb2e8f9f7 | 141 | */ |
<> | 144:ef7eb2e8f9f7 | 142 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 143 | { |
<> | 144:ef7eb2e8f9f7 | 144 | /*<! NAND memory electronic signature maker and device IDs */ |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | uint8_t Maker_Id; |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | uint8_t Device_Id; |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | uint8_t Third_Id; |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | uint8_t Fourth_Id; |
<> | 144:ef7eb2e8f9f7 | 153 | }NAND_IDTypeDef; |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /** |
<> | 144:ef7eb2e8f9f7 | 156 | * @brief NAND Memory address Structure definition |
<> | 144:ef7eb2e8f9f7 | 157 | */ |
<> | 144:ef7eb2e8f9f7 | 158 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 159 | { |
<> | 144:ef7eb2e8f9f7 | 160 | uint16_t Page; /*!< NAND memory Page address */ |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | uint16_t Zone; /*!< NAND memory Zone address */ |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | uint16_t Block; /*!< NAND memory Block address */ |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | }NAND_AddressTypeDef; |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | /** |
<> | 144:ef7eb2e8f9f7 | 169 | * @brief NAND Memory info Structure definition |
<> | 144:ef7eb2e8f9f7 | 170 | */ |
<> | 144:ef7eb2e8f9f7 | 171 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 172 | { |
<> | 144:ef7eb2e8f9f7 | 173 | uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */ |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */ |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | uint32_t BlockSize; /*!< NAND memory block size number of pages */ |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | uint32_t BlockNbr; /*!< NAND memory number of blocks */ |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */ |
<> | 144:ef7eb2e8f9f7 | 182 | }NAND_InfoTypeDef; |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | /** |
<> | 144:ef7eb2e8f9f7 | 185 | * @brief NAND handle Structure definition |
<> | 144:ef7eb2e8f9f7 | 186 | */ |
<> | 144:ef7eb2e8f9f7 | 187 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 188 | { |
<> | 144:ef7eb2e8f9f7 | 189 | FMC_NAND_TypeDef *Instance; /*!< Register base address */ |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | HAL_LockTypeDef Lock; /*!< NAND locking object */ |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */ |
<> | 144:ef7eb2e8f9f7 | 198 | }NAND_HandleTypeDef; |
<> | 144:ef7eb2e8f9f7 | 199 | |
<> | 144:ef7eb2e8f9f7 | 200 | /** |
<> | 144:ef7eb2e8f9f7 | 201 | * @} |
<> | 144:ef7eb2e8f9f7 | 202 | */ |
<> | 144:ef7eb2e8f9f7 | 203 | |
<> | 144:ef7eb2e8f9f7 | 204 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 205 | /* Exported macro ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 206 | /** @defgroup NAND_Exported_Macros NAND Exported Macros |
<> | 144:ef7eb2e8f9f7 | 207 | * @{ |
<> | 144:ef7eb2e8f9f7 | 208 | */ |
<> | 144:ef7eb2e8f9f7 | 209 | |
<> | 144:ef7eb2e8f9f7 | 210 | /** @brief Reset NAND handle state |
<> | 144:ef7eb2e8f9f7 | 211 | * @param __HANDLE__: specifies the NAND handle. |
<> | 144:ef7eb2e8f9f7 | 212 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 213 | */ |
<> | 144:ef7eb2e8f9f7 | 214 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 215 | |
<> | 144:ef7eb2e8f9f7 | 216 | /** |
<> | 144:ef7eb2e8f9f7 | 217 | * @} |
<> | 144:ef7eb2e8f9f7 | 218 | */ |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 221 | /** @addtogroup NAND_Exported_Functions NAND Exported Functions |
<> | 144:ef7eb2e8f9f7 | 222 | * @{ |
<> | 144:ef7eb2e8f9f7 | 223 | */ |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 226 | * @{ |
<> | 144:ef7eb2e8f9f7 | 227 | */ |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | /* Initialization/de-initialization functions ********************************/ |
<> | 144:ef7eb2e8f9f7 | 230 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); |
<> | 144:ef7eb2e8f9f7 | 231 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 232 | void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 233 | void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 234 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 235 | void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 236 | |
<> | 144:ef7eb2e8f9f7 | 237 | /** |
<> | 144:ef7eb2e8f9f7 | 238 | * @} |
<> | 144:ef7eb2e8f9f7 | 239 | */ |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions |
<> | 144:ef7eb2e8f9f7 | 242 | * @{ |
<> | 144:ef7eb2e8f9f7 | 243 | */ |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | /* IO operation functions ****************************************************/ |
<> | 144:ef7eb2e8f9f7 | 246 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); |
<> | 144:ef7eb2e8f9f7 | 247 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 248 | HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); |
<> | 144:ef7eb2e8f9f7 | 249 | HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); |
<> | 144:ef7eb2e8f9f7 | 250 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); |
<> | 144:ef7eb2e8f9f7 | 251 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); |
<> | 144:ef7eb2e8f9f7 | 252 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
<> | 144:ef7eb2e8f9f7 | 253 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 254 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | /** |
<> | 144:ef7eb2e8f9f7 | 257 | * @} |
<> | 144:ef7eb2e8f9f7 | 258 | */ |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 261 | * @{ |
<> | 144:ef7eb2e8f9f7 | 262 | */ |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | /* NAND Control functions ****************************************************/ |
<> | 144:ef7eb2e8f9f7 | 265 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 266 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 267 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | /** |
<> | 144:ef7eb2e8f9f7 | 270 | * @} |
<> | 144:ef7eb2e8f9f7 | 271 | */ |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 274 | * @{ |
<> | 144:ef7eb2e8f9f7 | 275 | */ |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | /* NAND State functions *******************************************************/ |
<> | 144:ef7eb2e8f9f7 | 278 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 279 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | /** |
<> | 144:ef7eb2e8f9f7 | 282 | * @} |
<> | 144:ef7eb2e8f9f7 | 283 | */ |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /** |
<> | 144:ef7eb2e8f9f7 | 286 | * @} |
<> | 144:ef7eb2e8f9f7 | 287 | */ |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | /** |
<> | 144:ef7eb2e8f9f7 | 290 | * @} |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | /** |
<> | 144:ef7eb2e8f9f7 | 294 | * @} |
<> | 144:ef7eb2e8f9f7 | 295 | */ |
<> | 144:ef7eb2e8f9f7 | 296 | |
<> | 144:ef7eb2e8f9f7 | 297 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | #endif |
<> | 144:ef7eb2e8f9f7 | 302 | |
<> | 144:ef7eb2e8f9f7 | 303 | #endif /* __STM32F3xx_HAL_NAND_H */ |
<> | 144:ef7eb2e8f9f7 | 304 | |
<> | 144:ef7eb2e8f9f7 | 305 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |