MBED-DEV only fro Nucleo STM32F303K8T6
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.c@151:acf04f8e7d03, 2016-11-19 (annotated)
- Committer:
- pravinautosys
- Date:
- Sat Nov 19 10:38:54 2016 +0000
- Revision:
- 151:acf04f8e7d03
- Parent:
- 149:156823d33999
MyMBED-DEVWithSTM32F303K8T6;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f3xx_hal_nand.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.3.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 01-July-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief NAND HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides a generic firmware to drive NAND memories mounted |
<> | 144:ef7eb2e8f9f7 | 9 | * as external device. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 12 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 13 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 14 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | [..] |
<> | 144:ef7eb2e8f9f7 | 16 | This driver is a generic layered driver which contains a set of APIs used to |
<> | 144:ef7eb2e8f9f7 | 17 | control NAND flash memories. It uses the FMC layer functions to interface |
<> | 144:ef7eb2e8f9f7 | 18 | with NAND devices. This driver is used as follows: |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() |
<> | 144:ef7eb2e8f9f7 | 21 | with control and timing parameters for both common and attribute spaces. |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | (+) Read NAND flash memory maker and device IDs using the function |
<> | 144:ef7eb2e8f9f7 | 24 | HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef |
<> | 144:ef7eb2e8f9f7 | 25 | structure declared by the function caller. |
<> | 144:ef7eb2e8f9f7 | 26 | |
<> | 144:ef7eb2e8f9f7 | 27 | (+) Access NAND flash memory by read/write operations using the functions |
<> | 144:ef7eb2e8f9f7 | 28 | HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() |
<> | 144:ef7eb2e8f9f7 | 29 | to read/write page(s)/spare area(s). These functions use specific device |
<> | 144:ef7eb2e8f9f7 | 30 | information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef |
<> | 144:ef7eb2e8f9f7 | 31 | structure. The read/write address information is contained by the Nand_Address_Typedef |
<> | 144:ef7eb2e8f9f7 | 32 | structure passed as parameter. |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). |
<> | 144:ef7eb2e8f9f7 | 37 | The erase block address information is contained in the Nand_Address_Typedef |
<> | 144:ef7eb2e8f9f7 | 38 | structure passed as parameter. |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ |
<> | 144:ef7eb2e8f9f7 | 43 | HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction |
<> | 144:ef7eb2e8f9f7 | 44 | feature or the function HAL_NAND_GetECC() to get the ECC correction code. |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | (+) You can monitor the NAND device HAL state by calling the function |
<> | 144:ef7eb2e8f9f7 | 47 | HAL_NAND_GetState() |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | [..] |
<> | 144:ef7eb2e8f9f7 | 50 | (@) This driver is a set of generic APIs which handle standard NAND flash operations. |
<> | 144:ef7eb2e8f9f7 | 51 | If a NAND flash device contains different operations and/or implementations, |
<> | 144:ef7eb2e8f9f7 | 52 | it should be implemented separately. |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 55 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 56 | * @attention |
<> | 144:ef7eb2e8f9f7 | 57 | * |
<> | 144:ef7eb2e8f9f7 | 58 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 59 | * |
<> | 144:ef7eb2e8f9f7 | 60 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 61 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 62 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 63 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 65 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 66 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 68 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 69 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 70 | * |
<> | 144:ef7eb2e8f9f7 | 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 81 | * |
<> | 144:ef7eb2e8f9f7 | 82 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 83 | */ |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 86 | #include "stm32f3xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /** @addtogroup STM32F3xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 91 | * @{ |
<> | 144:ef7eb2e8f9f7 | 92 | */ |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | #ifdef HAL_NAND_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 95 | |
<> | 144:ef7eb2e8f9f7 | 96 | /** @defgroup NAND NAND |
<> | 144:ef7eb2e8f9f7 | 97 | * @brief NAND HAL module driver |
<> | 144:ef7eb2e8f9f7 | 98 | * @{ |
<> | 144:ef7eb2e8f9f7 | 99 | */ |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 102 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 103 | /** @defgroup NAND_Private_Constants NAND Private Constants |
<> | 144:ef7eb2e8f9f7 | 104 | * @{ |
<> | 144:ef7eb2e8f9f7 | 105 | */ |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | /** |
<> | 144:ef7eb2e8f9f7 | 108 | * @} |
<> | 144:ef7eb2e8f9f7 | 109 | */ |
<> | 144:ef7eb2e8f9f7 | 110 | |
<> | 144:ef7eb2e8f9f7 | 111 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 112 | /** @defgroup NAND_Private_Macros NAND Private Macros |
<> | 144:ef7eb2e8f9f7 | 113 | * @{ |
<> | 144:ef7eb2e8f9f7 | 114 | */ |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | /** |
<> | 144:ef7eb2e8f9f7 | 117 | * @} |
<> | 144:ef7eb2e8f9f7 | 118 | */ |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 121 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 122 | /** @defgroup NAND_Private_Functions NAND Private Functions |
<> | 144:ef7eb2e8f9f7 | 123 | * @{ |
<> | 144:ef7eb2e8f9f7 | 124 | */ |
<> | 144:ef7eb2e8f9f7 | 125 | static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address); |
<> | 144:ef7eb2e8f9f7 | 126 | /** |
<> | 144:ef7eb2e8f9f7 | 127 | * @} |
<> | 144:ef7eb2e8f9f7 | 128 | */ |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | /** @defgroup NAND_Exported_Functions NAND Exported Functions |
<> | 144:ef7eb2e8f9f7 | 133 | * @{ |
<> | 144:ef7eb2e8f9f7 | 134 | */ |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 137 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 138 | * |
<> | 144:ef7eb2e8f9f7 | 139 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 140 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 141 | ##### NAND Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 142 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 143 | [..] |
<> | 144:ef7eb2e8f9f7 | 144 | This section provides functions allowing to initialize/de-initialize |
<> | 144:ef7eb2e8f9f7 | 145 | the NAND memory |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 148 | * @{ |
<> | 144:ef7eb2e8f9f7 | 149 | */ |
<> | 144:ef7eb2e8f9f7 | 150 | |
<> | 144:ef7eb2e8f9f7 | 151 | /** |
<> | 144:ef7eb2e8f9f7 | 152 | * @brief Perform NAND memory Initialization sequence |
<> | 144:ef7eb2e8f9f7 | 153 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 154 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 155 | * @param ComSpace_Timing: pointer to Common space timing structure |
<> | 144:ef7eb2e8f9f7 | 156 | * @param AttSpace_Timing: pointer to Attribute space timing structure |
<> | 144:ef7eb2e8f9f7 | 157 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 158 | */ |
<> | 144:ef7eb2e8f9f7 | 159 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) |
<> | 144:ef7eb2e8f9f7 | 160 | { |
<> | 144:ef7eb2e8f9f7 | 161 | /* Check the NAND handle state */ |
<> | 144:ef7eb2e8f9f7 | 162 | if(hnand == NULL) |
<> | 144:ef7eb2e8f9f7 | 163 | { |
<> | 144:ef7eb2e8f9f7 | 164 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | if(hnand->State == HAL_NAND_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 168 | { |
<> | 144:ef7eb2e8f9f7 | 169 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 170 | hnand->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | /* Initialize the low level hardware (MSP) */ |
<> | 144:ef7eb2e8f9f7 | 173 | HAL_NAND_MspInit(hnand); |
<> | 144:ef7eb2e8f9f7 | 174 | } |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /* Initialize NAND control Interface */ |
<> | 144:ef7eb2e8f9f7 | 177 | FMC_NAND_Init(hnand->Instance, &(hnand->Init)); |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | /* Initialize NAND common space timing Interface */ |
<> | 144:ef7eb2e8f9f7 | 180 | FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | /* Initialize NAND attribute space timing Interface */ |
<> | 144:ef7eb2e8f9f7 | 183 | FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | /* Enable the NAND device */ |
<> | 144:ef7eb2e8f9f7 | 186 | __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 189 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 192 | } |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | /** |
<> | 144:ef7eb2e8f9f7 | 195 | * @brief Perform NAND memory De-Initialization sequence |
<> | 144:ef7eb2e8f9f7 | 196 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 197 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 198 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 199 | */ |
<> | 144:ef7eb2e8f9f7 | 200 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 201 | { |
<> | 144:ef7eb2e8f9f7 | 202 | /* Initialize the low level hardware (MSP) */ |
<> | 144:ef7eb2e8f9f7 | 203 | HAL_NAND_MspDeInit(hnand); |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | /* Configure the NAND registers with their reset values */ |
<> | 144:ef7eb2e8f9f7 | 206 | FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | /* Reset the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 209 | hnand->State = HAL_NAND_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 212 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 213 | |
<> | 144:ef7eb2e8f9f7 | 214 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 215 | } |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | /** |
<> | 144:ef7eb2e8f9f7 | 218 | * @brief NAND MSP Init |
<> | 144:ef7eb2e8f9f7 | 219 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 220 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 221 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 222 | */ |
<> | 144:ef7eb2e8f9f7 | 223 | __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 224 | { |
<> | 144:ef7eb2e8f9f7 | 225 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 226 | UNUSED(hnand); |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 229 | the HAL_NAND_MspInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 230 | */ |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | /** |
<> | 144:ef7eb2e8f9f7 | 234 | * @brief NAND MSP DeInit |
<> | 144:ef7eb2e8f9f7 | 235 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 236 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 237 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 238 | */ |
<> | 144:ef7eb2e8f9f7 | 239 | __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 240 | { |
<> | 144:ef7eb2e8f9f7 | 241 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 242 | UNUSED(hnand); |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 245 | the HAL_NAND_MspDeInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 246 | */ |
<> | 144:ef7eb2e8f9f7 | 247 | } |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | /** |
<> | 144:ef7eb2e8f9f7 | 251 | * @brief This function handles NAND device interrupt request. |
<> | 144:ef7eb2e8f9f7 | 252 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 253 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 254 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 255 | */ |
<> | 144:ef7eb2e8f9f7 | 256 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 257 | { |
<> | 144:ef7eb2e8f9f7 | 258 | /* Check NAND interrupt Rising edge flag */ |
<> | 144:ef7eb2e8f9f7 | 259 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) |
<> | 144:ef7eb2e8f9f7 | 260 | { |
<> | 144:ef7eb2e8f9f7 | 261 | /* NAND interrupt callback*/ |
<> | 144:ef7eb2e8f9f7 | 262 | HAL_NAND_ITCallback(hnand); |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | /* Clear NAND interrupt Rising edge pending bit */ |
<> | 144:ef7eb2e8f9f7 | 265 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE); |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | /* Check NAND interrupt Level flag */ |
<> | 144:ef7eb2e8f9f7 | 269 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) |
<> | 144:ef7eb2e8f9f7 | 270 | { |
<> | 144:ef7eb2e8f9f7 | 271 | /* NAND interrupt callback*/ |
<> | 144:ef7eb2e8f9f7 | 272 | HAL_NAND_ITCallback(hnand); |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | /* Clear NAND interrupt Level pending bit */ |
<> | 144:ef7eb2e8f9f7 | 275 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL); |
<> | 144:ef7eb2e8f9f7 | 276 | } |
<> | 144:ef7eb2e8f9f7 | 277 | |
<> | 144:ef7eb2e8f9f7 | 278 | /* Check NAND interrupt Falling edge flag */ |
<> | 144:ef7eb2e8f9f7 | 279 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) |
<> | 144:ef7eb2e8f9f7 | 280 | { |
<> | 144:ef7eb2e8f9f7 | 281 | /* NAND interrupt callback*/ |
<> | 144:ef7eb2e8f9f7 | 282 | HAL_NAND_ITCallback(hnand); |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | /* Clear NAND interrupt Falling edge pending bit */ |
<> | 144:ef7eb2e8f9f7 | 285 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE); |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | /* Check NAND interrupt FIFO empty flag */ |
<> | 144:ef7eb2e8f9f7 | 289 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) |
<> | 144:ef7eb2e8f9f7 | 290 | { |
<> | 144:ef7eb2e8f9f7 | 291 | /* NAND interrupt callback*/ |
<> | 144:ef7eb2e8f9f7 | 292 | HAL_NAND_ITCallback(hnand); |
<> | 144:ef7eb2e8f9f7 | 293 | |
<> | 144:ef7eb2e8f9f7 | 294 | /* Clear NAND interrupt FIFO empty pending bit */ |
<> | 144:ef7eb2e8f9f7 | 295 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT); |
<> | 144:ef7eb2e8f9f7 | 296 | } |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | /** |
<> | 144:ef7eb2e8f9f7 | 300 | * @brief NAND interrupt feature callback |
<> | 144:ef7eb2e8f9f7 | 301 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 302 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 303 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 304 | */ |
<> | 144:ef7eb2e8f9f7 | 305 | __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 306 | { |
<> | 144:ef7eb2e8f9f7 | 307 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 308 | UNUSED(hnand); |
<> | 144:ef7eb2e8f9f7 | 309 | |
<> | 144:ef7eb2e8f9f7 | 310 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 311 | the HAL_NAND_ITCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 312 | */ |
<> | 144:ef7eb2e8f9f7 | 313 | } |
<> | 144:ef7eb2e8f9f7 | 314 | |
<> | 144:ef7eb2e8f9f7 | 315 | /** |
<> | 144:ef7eb2e8f9f7 | 316 | * @} |
<> | 144:ef7eb2e8f9f7 | 317 | */ |
<> | 144:ef7eb2e8f9f7 | 318 | |
<> | 144:ef7eb2e8f9f7 | 319 | /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions |
<> | 144:ef7eb2e8f9f7 | 320 | * @brief Input Output and memory control functions |
<> | 144:ef7eb2e8f9f7 | 321 | * |
<> | 144:ef7eb2e8f9f7 | 322 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 323 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 324 | ##### NAND Input and Output functions ##### |
<> | 144:ef7eb2e8f9f7 | 325 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 326 | [..] |
<> | 144:ef7eb2e8f9f7 | 327 | This section provides functions allowing to use and control the NAND |
<> | 144:ef7eb2e8f9f7 | 328 | memory |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 331 | * @{ |
<> | 144:ef7eb2e8f9f7 | 332 | */ |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /** |
<> | 144:ef7eb2e8f9f7 | 335 | * @brief Read the NAND memory electronic signature |
<> | 144:ef7eb2e8f9f7 | 336 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 337 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 338 | * @param pNAND_ID: NAND ID structure |
<> | 144:ef7eb2e8f9f7 | 339 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 340 | */ |
<> | 144:ef7eb2e8f9f7 | 341 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) |
<> | 144:ef7eb2e8f9f7 | 342 | { |
<> | 144:ef7eb2e8f9f7 | 343 | __IO uint32_t data = 0; |
<> | 144:ef7eb2e8f9f7 | 344 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 347 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 350 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 351 | { |
<> | 144:ef7eb2e8f9f7 | 352 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 353 | } |
<> | 144:ef7eb2e8f9f7 | 354 | |
<> | 144:ef7eb2e8f9f7 | 355 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 356 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 357 | { |
<> | 144:ef7eb2e8f9f7 | 358 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 359 | } |
<> | 144:ef7eb2e8f9f7 | 360 | else |
<> | 144:ef7eb2e8f9f7 | 361 | { |
<> | 144:ef7eb2e8f9f7 | 362 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 363 | } |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 366 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 367 | |
<> | 144:ef7eb2e8f9f7 | 368 | /* Send Read ID command sequence */ |
<> | 144:ef7eb2e8f9f7 | 369 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; |
<> | 144:ef7eb2e8f9f7 | 370 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | /* Read the electronic signature from NAND flash */ |
<> | 144:ef7eb2e8f9f7 | 373 | data = *(__IO uint32_t *)deviceaddress; |
<> | 144:ef7eb2e8f9f7 | 374 | |
<> | 144:ef7eb2e8f9f7 | 375 | /* Return the data read */ |
<> | 144:ef7eb2e8f9f7 | 376 | pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); |
<> | 144:ef7eb2e8f9f7 | 377 | pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); |
<> | 144:ef7eb2e8f9f7 | 378 | pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); |
<> | 144:ef7eb2e8f9f7 | 379 | pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); |
<> | 144:ef7eb2e8f9f7 | 380 | |
<> | 144:ef7eb2e8f9f7 | 381 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 382 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 383 | |
<> | 144:ef7eb2e8f9f7 | 384 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 385 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 386 | |
<> | 144:ef7eb2e8f9f7 | 387 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 388 | } |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | /** |
<> | 144:ef7eb2e8f9f7 | 391 | * @brief NAND memory reset |
<> | 144:ef7eb2e8f9f7 | 392 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 393 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 394 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 395 | */ |
<> | 144:ef7eb2e8f9f7 | 396 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 397 | { |
<> | 144:ef7eb2e8f9f7 | 398 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 399 | |
<> | 144:ef7eb2e8f9f7 | 400 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 401 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 402 | |
<> | 144:ef7eb2e8f9f7 | 403 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 404 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 405 | { |
<> | 144:ef7eb2e8f9f7 | 406 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 407 | } |
<> | 144:ef7eb2e8f9f7 | 408 | |
<> | 144:ef7eb2e8f9f7 | 409 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 410 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 411 | { |
<> | 144:ef7eb2e8f9f7 | 412 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 413 | } |
<> | 144:ef7eb2e8f9f7 | 414 | else |
<> | 144:ef7eb2e8f9f7 | 415 | { |
<> | 144:ef7eb2e8f9f7 | 416 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 417 | } |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 420 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 421 | |
<> | 144:ef7eb2e8f9f7 | 422 | /* Send NAND reset command */ |
<> | 144:ef7eb2e8f9f7 | 423 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; |
<> | 144:ef7eb2e8f9f7 | 424 | |
<> | 144:ef7eb2e8f9f7 | 425 | |
<> | 144:ef7eb2e8f9f7 | 426 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 427 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 430 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 431 | |
<> | 144:ef7eb2e8f9f7 | 432 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 433 | |
<> | 144:ef7eb2e8f9f7 | 434 | } |
<> | 144:ef7eb2e8f9f7 | 435 | |
<> | 144:ef7eb2e8f9f7 | 436 | /** |
<> | 144:ef7eb2e8f9f7 | 437 | * @brief Read Page(s) from NAND memory block |
<> | 144:ef7eb2e8f9f7 | 438 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 439 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 440 | * @param pAddress: pointer to NAND address structure |
<> | 144:ef7eb2e8f9f7 | 441 | * @param pBuffer: pointer to destination read buffer |
<> | 144:ef7eb2e8f9f7 | 442 | * @param NumPageToRead: number of pages to read from block |
<> | 144:ef7eb2e8f9f7 | 443 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 444 | */ |
<> | 144:ef7eb2e8f9f7 | 445 | HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) |
<> | 144:ef7eb2e8f9f7 | 446 | { |
<> | 144:ef7eb2e8f9f7 | 447 | __IO uint32_t index = 0; |
<> | 144:ef7eb2e8f9f7 | 448 | uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 449 | NAND_AddressTypeDef nandaddress; |
<> | 144:ef7eb2e8f9f7 | 450 | uint32_t addressoffset = 0; |
<> | 144:ef7eb2e8f9f7 | 451 | |
<> | 144:ef7eb2e8f9f7 | 452 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 453 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 454 | |
<> | 144:ef7eb2e8f9f7 | 455 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 456 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 457 | { |
<> | 144:ef7eb2e8f9f7 | 458 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 459 | } |
<> | 144:ef7eb2e8f9f7 | 460 | |
<> | 144:ef7eb2e8f9f7 | 461 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 462 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 463 | { |
<> | 144:ef7eb2e8f9f7 | 464 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 465 | } |
<> | 144:ef7eb2e8f9f7 | 466 | else |
<> | 144:ef7eb2e8f9f7 | 467 | { |
<> | 144:ef7eb2e8f9f7 | 468 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 469 | } |
<> | 144:ef7eb2e8f9f7 | 470 | |
<> | 144:ef7eb2e8f9f7 | 471 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 472 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 473 | |
<> | 144:ef7eb2e8f9f7 | 474 | /* Save the content of pAddress as it will be modified */ |
<> | 144:ef7eb2e8f9f7 | 475 | nandaddress.Block = pAddress->Block; |
<> | 144:ef7eb2e8f9f7 | 476 | nandaddress.Page = pAddress->Page; |
<> | 144:ef7eb2e8f9f7 | 477 | nandaddress.Zone = pAddress->Zone; |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | /* Page(s) read loop */ |
<> | 144:ef7eb2e8f9f7 | 480 | while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
<> | 144:ef7eb2e8f9f7 | 481 | { |
<> | 144:ef7eb2e8f9f7 | 482 | /* update the buffer size */ |
<> | 144:ef7eb2e8f9f7 | 483 | size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); |
<> | 144:ef7eb2e8f9f7 | 484 | |
<> | 144:ef7eb2e8f9f7 | 485 | /* Get the address offset */ |
<> | 144:ef7eb2e8f9f7 | 486 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
<> | 144:ef7eb2e8f9f7 | 487 | |
<> | 144:ef7eb2e8f9f7 | 488 | /* Send read page command sequence */ |
<> | 144:ef7eb2e8f9f7 | 489 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
<> | 144:ef7eb2e8f9f7 | 492 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 493 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 494 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 495 | |
<> | 144:ef7eb2e8f9f7 | 496 | /* for 512 and 1 GB devices, 4th cycle is required */ |
<> | 144:ef7eb2e8f9f7 | 497 | if(hnand->Info.BlockNbr >= 1024) |
<> | 144:ef7eb2e8f9f7 | 498 | { |
<> | 144:ef7eb2e8f9f7 | 499 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 500 | } |
<> | 144:ef7eb2e8f9f7 | 501 | |
<> | 144:ef7eb2e8f9f7 | 502 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; |
<> | 144:ef7eb2e8f9f7 | 503 | |
<> | 144:ef7eb2e8f9f7 | 504 | /* Get Data into Buffer */ |
<> | 144:ef7eb2e8f9f7 | 505 | for(; index < size; index++) |
<> | 144:ef7eb2e8f9f7 | 506 | { |
<> | 144:ef7eb2e8f9f7 | 507 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; |
<> | 144:ef7eb2e8f9f7 | 508 | } |
<> | 144:ef7eb2e8f9f7 | 509 | |
<> | 144:ef7eb2e8f9f7 | 510 | /* Increment read pages number */ |
<> | 144:ef7eb2e8f9f7 | 511 | numpagesread++; |
<> | 144:ef7eb2e8f9f7 | 512 | |
<> | 144:ef7eb2e8f9f7 | 513 | /* Decrement pages to read */ |
<> | 144:ef7eb2e8f9f7 | 514 | NumPageToRead--; |
<> | 144:ef7eb2e8f9f7 | 515 | |
<> | 144:ef7eb2e8f9f7 | 516 | /* Increment the NAND address */ |
<> | 144:ef7eb2e8f9f7 | 517 | addressstatus = NAND_AddressIncrement(hnand, &nandaddress); |
<> | 144:ef7eb2e8f9f7 | 518 | } |
<> | 144:ef7eb2e8f9f7 | 519 | |
<> | 144:ef7eb2e8f9f7 | 520 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 521 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 522 | |
<> | 144:ef7eb2e8f9f7 | 523 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 524 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 525 | |
<> | 144:ef7eb2e8f9f7 | 526 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | } |
<> | 144:ef7eb2e8f9f7 | 529 | |
<> | 144:ef7eb2e8f9f7 | 530 | /** |
<> | 144:ef7eb2e8f9f7 | 531 | * @brief Write Page(s) to NAND memory block |
<> | 144:ef7eb2e8f9f7 | 532 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 533 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 534 | * @param pAddress: pointer to NAND address structure |
<> | 144:ef7eb2e8f9f7 | 535 | * @param pBuffer: pointer to source buffer to write |
<> | 144:ef7eb2e8f9f7 | 536 | * @param NumPageToWrite: number of pages to write to block |
<> | 144:ef7eb2e8f9f7 | 537 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 538 | */ |
<> | 144:ef7eb2e8f9f7 | 539 | HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) |
<> | 144:ef7eb2e8f9f7 | 540 | { |
<> | 144:ef7eb2e8f9f7 | 541 | __IO uint32_t index = 0; |
<> | 144:ef7eb2e8f9f7 | 542 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 543 | uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 544 | NAND_AddressTypeDef nandaddress; |
<> | 144:ef7eb2e8f9f7 | 545 | uint32_t addressoffset = 0; |
<> | 144:ef7eb2e8f9f7 | 546 | |
<> | 144:ef7eb2e8f9f7 | 547 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 548 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 549 | |
<> | 144:ef7eb2e8f9f7 | 550 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 551 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 552 | { |
<> | 144:ef7eb2e8f9f7 | 553 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 554 | } |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 557 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 558 | { |
<> | 144:ef7eb2e8f9f7 | 559 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 560 | } |
<> | 144:ef7eb2e8f9f7 | 561 | else |
<> | 144:ef7eb2e8f9f7 | 562 | { |
<> | 144:ef7eb2e8f9f7 | 563 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 564 | } |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 567 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 568 | |
<> | 144:ef7eb2e8f9f7 | 569 | /* Save the content of pAddress as it will be modified */ |
<> | 144:ef7eb2e8f9f7 | 570 | nandaddress.Block = pAddress->Block; |
<> | 144:ef7eb2e8f9f7 | 571 | nandaddress.Page = pAddress->Page; |
<> | 144:ef7eb2e8f9f7 | 572 | nandaddress.Zone = pAddress->Zone; |
<> | 144:ef7eb2e8f9f7 | 573 | |
<> | 144:ef7eb2e8f9f7 | 574 | /* Page(s) write loop */ |
<> | 144:ef7eb2e8f9f7 | 575 | while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
<> | 144:ef7eb2e8f9f7 | 576 | { |
<> | 144:ef7eb2e8f9f7 | 577 | /* update the buffer size */ |
<> | 144:ef7eb2e8f9f7 | 578 | size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten); |
<> | 144:ef7eb2e8f9f7 | 579 | |
<> | 144:ef7eb2e8f9f7 | 580 | /* Get the address offset */ |
<> | 144:ef7eb2e8f9f7 | 581 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | /* Send write page command sequence */ |
<> | 144:ef7eb2e8f9f7 | 584 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; |
<> | 144:ef7eb2e8f9f7 | 585 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; |
<> | 144:ef7eb2e8f9f7 | 586 | |
<> | 144:ef7eb2e8f9f7 | 587 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
<> | 144:ef7eb2e8f9f7 | 588 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 589 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 590 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | /* for 512 and 1 GB devices, 4th cycle is required */ |
<> | 144:ef7eb2e8f9f7 | 593 | if(hnand->Info.BlockNbr >= 1024) |
<> | 144:ef7eb2e8f9f7 | 594 | { |
<> | 144:ef7eb2e8f9f7 | 595 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 596 | } |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | /* Write data to memory */ |
<> | 144:ef7eb2e8f9f7 | 599 | for(; index < size; index++) |
<> | 144:ef7eb2e8f9f7 | 600 | { |
<> | 144:ef7eb2e8f9f7 | 601 | *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; |
<> | 144:ef7eb2e8f9f7 | 602 | } |
<> | 144:ef7eb2e8f9f7 | 603 | |
<> | 144:ef7eb2e8f9f7 | 604 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; |
<> | 144:ef7eb2e8f9f7 | 605 | |
<> | 144:ef7eb2e8f9f7 | 606 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 607 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | /* Read status until NAND is ready */ |
<> | 144:ef7eb2e8f9f7 | 610 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
<> | 144:ef7eb2e8f9f7 | 611 | { |
<> | 144:ef7eb2e8f9f7 | 612 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 613 | { |
<> | 144:ef7eb2e8f9f7 | 614 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 615 | } |
<> | 144:ef7eb2e8f9f7 | 616 | } |
<> | 144:ef7eb2e8f9f7 | 617 | |
<> | 144:ef7eb2e8f9f7 | 618 | /* Increment written pages number */ |
<> | 144:ef7eb2e8f9f7 | 619 | numpageswritten++; |
<> | 144:ef7eb2e8f9f7 | 620 | |
<> | 144:ef7eb2e8f9f7 | 621 | /* Decrement pages to write */ |
<> | 144:ef7eb2e8f9f7 | 622 | NumPageToWrite--; |
<> | 144:ef7eb2e8f9f7 | 623 | |
<> | 144:ef7eb2e8f9f7 | 624 | /* Increment the NAND address */ |
<> | 144:ef7eb2e8f9f7 | 625 | addressstatus = NAND_AddressIncrement(hnand, &nandaddress); |
<> | 144:ef7eb2e8f9f7 | 626 | } |
<> | 144:ef7eb2e8f9f7 | 627 | |
<> | 144:ef7eb2e8f9f7 | 628 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 629 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 630 | |
<> | 144:ef7eb2e8f9f7 | 631 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 632 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 633 | |
<> | 144:ef7eb2e8f9f7 | 634 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 635 | } |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | /** |
<> | 144:ef7eb2e8f9f7 | 638 | * @brief Read Spare area(s) from NAND memory |
<> | 144:ef7eb2e8f9f7 | 639 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 640 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 641 | * @param pAddress: pointer to NAND address structure |
<> | 144:ef7eb2e8f9f7 | 642 | * @param pBuffer: pointer to source buffer to write |
<> | 144:ef7eb2e8f9f7 | 643 | * @param NumSpareAreaToRead: Number of spare area to read |
<> | 144:ef7eb2e8f9f7 | 644 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 645 | */ |
<> | 144:ef7eb2e8f9f7 | 646 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) |
<> | 144:ef7eb2e8f9f7 | 647 | { |
<> | 144:ef7eb2e8f9f7 | 648 | __IO uint32_t index = 0; |
<> | 144:ef7eb2e8f9f7 | 649 | uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 650 | NAND_AddressTypeDef nandaddress; |
<> | 144:ef7eb2e8f9f7 | 651 | uint32_t addressoffset = 0; |
<> | 144:ef7eb2e8f9f7 | 652 | |
<> | 144:ef7eb2e8f9f7 | 653 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 654 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 655 | |
<> | 144:ef7eb2e8f9f7 | 656 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 657 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 658 | { |
<> | 144:ef7eb2e8f9f7 | 659 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 660 | } |
<> | 144:ef7eb2e8f9f7 | 661 | |
<> | 144:ef7eb2e8f9f7 | 662 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 663 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 664 | { |
<> | 144:ef7eb2e8f9f7 | 665 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 666 | } |
<> | 144:ef7eb2e8f9f7 | 667 | else |
<> | 144:ef7eb2e8f9f7 | 668 | { |
<> | 144:ef7eb2e8f9f7 | 669 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 670 | } |
<> | 144:ef7eb2e8f9f7 | 671 | |
<> | 144:ef7eb2e8f9f7 | 672 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 673 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 674 | |
<> | 144:ef7eb2e8f9f7 | 675 | /* Save the content of pAddress as it will be modified */ |
<> | 144:ef7eb2e8f9f7 | 676 | nandaddress.Block = pAddress->Block; |
<> | 144:ef7eb2e8f9f7 | 677 | nandaddress.Page = pAddress->Page; |
<> | 144:ef7eb2e8f9f7 | 678 | nandaddress.Zone = pAddress->Zone; |
<> | 144:ef7eb2e8f9f7 | 679 | |
<> | 144:ef7eb2e8f9f7 | 680 | /* Spare area(s) read loop */ |
<> | 144:ef7eb2e8f9f7 | 681 | while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
<> | 144:ef7eb2e8f9f7 | 682 | { |
<> | 144:ef7eb2e8f9f7 | 683 | /* update the buffer size */ |
<> | 144:ef7eb2e8f9f7 | 684 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read); |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | /* Get the address offset */ |
<> | 144:ef7eb2e8f9f7 | 687 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
<> | 144:ef7eb2e8f9f7 | 688 | |
<> | 144:ef7eb2e8f9f7 | 689 | /* Send read spare area command sequence */ |
<> | 144:ef7eb2e8f9f7 | 690 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
<> | 144:ef7eb2e8f9f7 | 693 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 694 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 695 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 696 | |
<> | 144:ef7eb2e8f9f7 | 697 | /* for 512 and 1 GB devices, 4th cycle is required */ |
<> | 144:ef7eb2e8f9f7 | 698 | if(hnand->Info.BlockNbr >= 1024) |
<> | 144:ef7eb2e8f9f7 | 699 | { |
<> | 144:ef7eb2e8f9f7 | 700 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 701 | } |
<> | 144:ef7eb2e8f9f7 | 702 | |
<> | 144:ef7eb2e8f9f7 | 703 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; |
<> | 144:ef7eb2e8f9f7 | 704 | |
<> | 144:ef7eb2e8f9f7 | 705 | /* Get Data into Buffer */ |
<> | 144:ef7eb2e8f9f7 | 706 | for ( ;index < size; index++) |
<> | 144:ef7eb2e8f9f7 | 707 | { |
<> | 144:ef7eb2e8f9f7 | 708 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; |
<> | 144:ef7eb2e8f9f7 | 709 | } |
<> | 144:ef7eb2e8f9f7 | 710 | |
<> | 144:ef7eb2e8f9f7 | 711 | /* Increment read spare areas number */ |
<> | 144:ef7eb2e8f9f7 | 712 | num_spare_area_read++; |
<> | 144:ef7eb2e8f9f7 | 713 | |
<> | 144:ef7eb2e8f9f7 | 714 | /* Decrement spare areas to read */ |
<> | 144:ef7eb2e8f9f7 | 715 | NumSpareAreaToRead--; |
<> | 144:ef7eb2e8f9f7 | 716 | |
<> | 144:ef7eb2e8f9f7 | 717 | /* Increment the NAND address */ |
<> | 144:ef7eb2e8f9f7 | 718 | addressstatus = NAND_AddressIncrement(hnand, &nandaddress); |
<> | 144:ef7eb2e8f9f7 | 719 | } |
<> | 144:ef7eb2e8f9f7 | 720 | |
<> | 144:ef7eb2e8f9f7 | 721 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 722 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 723 | |
<> | 144:ef7eb2e8f9f7 | 724 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 725 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 726 | |
<> | 144:ef7eb2e8f9f7 | 727 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | /** |
<> | 144:ef7eb2e8f9f7 | 731 | * @brief Write Spare area(s) to NAND memory |
<> | 144:ef7eb2e8f9f7 | 732 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 733 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 734 | * @param pAddress: pointer to NAND address structure |
<> | 144:ef7eb2e8f9f7 | 735 | * @param pBuffer: pointer to source buffer to write |
<> | 144:ef7eb2e8f9f7 | 736 | * @param NumSpareAreaTowrite: number of spare areas to write to block |
<> | 144:ef7eb2e8f9f7 | 737 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 738 | */ |
<> | 144:ef7eb2e8f9f7 | 739 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) |
<> | 144:ef7eb2e8f9f7 | 740 | { |
<> | 144:ef7eb2e8f9f7 | 741 | __IO uint32_t index = 0; |
<> | 144:ef7eb2e8f9f7 | 742 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 743 | uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 744 | NAND_AddressTypeDef nandaddress; |
<> | 144:ef7eb2e8f9f7 | 745 | uint32_t addressoffset = 0; |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 748 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 749 | |
<> | 144:ef7eb2e8f9f7 | 750 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 751 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 752 | { |
<> | 144:ef7eb2e8f9f7 | 753 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 754 | } |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 757 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 758 | { |
<> | 144:ef7eb2e8f9f7 | 759 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | else |
<> | 144:ef7eb2e8f9f7 | 762 | { |
<> | 144:ef7eb2e8f9f7 | 763 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | /* Update the FMC_NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 767 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 768 | |
<> | 144:ef7eb2e8f9f7 | 769 | /* Save the content of pAddress as it will be modified */ |
<> | 144:ef7eb2e8f9f7 | 770 | nandaddress.Block = pAddress->Block; |
<> | 144:ef7eb2e8f9f7 | 771 | nandaddress.Page = pAddress->Page; |
<> | 144:ef7eb2e8f9f7 | 772 | nandaddress.Zone = pAddress->Zone; |
<> | 144:ef7eb2e8f9f7 | 773 | |
<> | 144:ef7eb2e8f9f7 | 774 | /* Spare area(s) write loop */ |
<> | 144:ef7eb2e8f9f7 | 775 | while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
<> | 144:ef7eb2e8f9f7 | 776 | { |
<> | 144:ef7eb2e8f9f7 | 777 | /* update the buffer size */ |
<> | 144:ef7eb2e8f9f7 | 778 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); |
<> | 144:ef7eb2e8f9f7 | 779 | |
<> | 144:ef7eb2e8f9f7 | 780 | /* Get the address offset */ |
<> | 144:ef7eb2e8f9f7 | 781 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
<> | 144:ef7eb2e8f9f7 | 782 | |
<> | 144:ef7eb2e8f9f7 | 783 | /* Send write Spare area command sequence */ |
<> | 144:ef7eb2e8f9f7 | 784 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; |
<> | 144:ef7eb2e8f9f7 | 785 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; |
<> | 144:ef7eb2e8f9f7 | 786 | |
<> | 144:ef7eb2e8f9f7 | 787 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
<> | 144:ef7eb2e8f9f7 | 788 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 789 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 790 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | /* for 512 and 1 GB devices, 4th cycle is required */ |
<> | 144:ef7eb2e8f9f7 | 793 | if(hnand->Info.BlockNbr >= 1024) |
<> | 144:ef7eb2e8f9f7 | 794 | { |
<> | 144:ef7eb2e8f9f7 | 795 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
<> | 144:ef7eb2e8f9f7 | 796 | } |
<> | 144:ef7eb2e8f9f7 | 797 | |
<> | 144:ef7eb2e8f9f7 | 798 | /* Write data to memory */ |
<> | 144:ef7eb2e8f9f7 | 799 | for(; index < size; index++) |
<> | 144:ef7eb2e8f9f7 | 800 | { |
<> | 144:ef7eb2e8f9f7 | 801 | *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; |
<> | 144:ef7eb2e8f9f7 | 802 | } |
<> | 144:ef7eb2e8f9f7 | 803 | |
<> | 144:ef7eb2e8f9f7 | 804 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; |
<> | 144:ef7eb2e8f9f7 | 805 | |
<> | 144:ef7eb2e8f9f7 | 806 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 807 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 808 | |
<> | 144:ef7eb2e8f9f7 | 809 | /* Read status until NAND is ready */ |
<> | 144:ef7eb2e8f9f7 | 810 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 813 | { |
<> | 144:ef7eb2e8f9f7 | 814 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 815 | } |
<> | 144:ef7eb2e8f9f7 | 816 | } |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | /* Increment written spare areas number */ |
<> | 144:ef7eb2e8f9f7 | 819 | num_spare_area_written++; |
<> | 144:ef7eb2e8f9f7 | 820 | |
<> | 144:ef7eb2e8f9f7 | 821 | /* Decrement spare areas to write */ |
<> | 144:ef7eb2e8f9f7 | 822 | NumSpareAreaTowrite--; |
<> | 144:ef7eb2e8f9f7 | 823 | |
<> | 144:ef7eb2e8f9f7 | 824 | /* Increment the NAND address */ |
<> | 144:ef7eb2e8f9f7 | 825 | addressstatus = NAND_AddressIncrement(hnand, &nandaddress); |
<> | 144:ef7eb2e8f9f7 | 826 | } |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 144:ef7eb2e8f9f7 | 828 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 829 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 832 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 833 | |
<> | 144:ef7eb2e8f9f7 | 834 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 835 | } |
<> | 144:ef7eb2e8f9f7 | 836 | |
<> | 144:ef7eb2e8f9f7 | 837 | /** |
<> | 144:ef7eb2e8f9f7 | 838 | * @brief NAND memory Block erase |
<> | 144:ef7eb2e8f9f7 | 839 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 840 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 841 | * @param pAddress: pointer to NAND address structure |
<> | 144:ef7eb2e8f9f7 | 842 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 843 | */ |
<> | 144:ef7eb2e8f9f7 | 844 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) |
<> | 144:ef7eb2e8f9f7 | 845 | { |
<> | 144:ef7eb2e8f9f7 | 846 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 847 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 850 | __HAL_LOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 853 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 854 | { |
<> | 144:ef7eb2e8f9f7 | 855 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 856 | } |
<> | 144:ef7eb2e8f9f7 | 857 | |
<> | 144:ef7eb2e8f9f7 | 858 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 859 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 860 | { |
<> | 144:ef7eb2e8f9f7 | 861 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 862 | } |
<> | 144:ef7eb2e8f9f7 | 863 | else |
<> | 144:ef7eb2e8f9f7 | 864 | { |
<> | 144:ef7eb2e8f9f7 | 865 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 866 | } |
<> | 144:ef7eb2e8f9f7 | 867 | |
<> | 144:ef7eb2e8f9f7 | 868 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 869 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 870 | |
<> | 144:ef7eb2e8f9f7 | 871 | /* Send Erase block command sequence */ |
<> | 144:ef7eb2e8f9f7 | 872 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; |
<> | 144:ef7eb2e8f9f7 | 873 | |
<> | 144:ef7eb2e8f9f7 | 874 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
<> | 144:ef7eb2e8f9f7 | 875 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
<> | 144:ef7eb2e8f9f7 | 876 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
<> | 144:ef7eb2e8f9f7 | 877 | |
<> | 144:ef7eb2e8f9f7 | 878 | /* for 512 and 1 GB devices, 4th cycle is required */ |
<> | 144:ef7eb2e8f9f7 | 879 | if(hnand->Info.BlockNbr >= 1024) |
<> | 144:ef7eb2e8f9f7 | 880 | { |
<> | 144:ef7eb2e8f9f7 | 881 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
<> | 144:ef7eb2e8f9f7 | 882 | } |
<> | 144:ef7eb2e8f9f7 | 883 | |
<> | 144:ef7eb2e8f9f7 | 884 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; |
<> | 144:ef7eb2e8f9f7 | 885 | |
<> | 144:ef7eb2e8f9f7 | 886 | /* Update the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 887 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 888 | |
<> | 144:ef7eb2e8f9f7 | 889 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 890 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 891 | |
<> | 144:ef7eb2e8f9f7 | 892 | /* Read status until NAND is ready */ |
<> | 144:ef7eb2e8f9f7 | 893 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
<> | 144:ef7eb2e8f9f7 | 894 | { |
<> | 144:ef7eb2e8f9f7 | 895 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 896 | { |
<> | 144:ef7eb2e8f9f7 | 897 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 898 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 899 | |
<> | 144:ef7eb2e8f9f7 | 900 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 901 | } |
<> | 144:ef7eb2e8f9f7 | 902 | } |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 905 | __HAL_UNLOCK(hnand); |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 908 | } |
<> | 144:ef7eb2e8f9f7 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | /** |
<> | 144:ef7eb2e8f9f7 | 911 | * @brief NAND memory read status |
<> | 144:ef7eb2e8f9f7 | 912 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 913 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 914 | * @retval NAND status |
<> | 144:ef7eb2e8f9f7 | 915 | */ |
<> | 144:ef7eb2e8f9f7 | 916 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 917 | { |
<> | 144:ef7eb2e8f9f7 | 918 | uint32_t data = 0; |
<> | 144:ef7eb2e8f9f7 | 919 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 920 | |
<> | 144:ef7eb2e8f9f7 | 921 | /* Identify the device address */ |
<> | 144:ef7eb2e8f9f7 | 922 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 923 | { |
<> | 144:ef7eb2e8f9f7 | 924 | deviceaddress = NAND_DEVICE1; |
<> | 144:ef7eb2e8f9f7 | 925 | } |
<> | 144:ef7eb2e8f9f7 | 926 | else |
<> | 144:ef7eb2e8f9f7 | 927 | { |
<> | 144:ef7eb2e8f9f7 | 928 | deviceaddress = NAND_DEVICE2; |
<> | 144:ef7eb2e8f9f7 | 929 | } |
<> | 144:ef7eb2e8f9f7 | 930 | |
<> | 144:ef7eb2e8f9f7 | 931 | /* Send Read status operation command */ |
<> | 144:ef7eb2e8f9f7 | 932 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; |
<> | 144:ef7eb2e8f9f7 | 933 | |
<> | 144:ef7eb2e8f9f7 | 934 | /* Read status register data */ |
<> | 144:ef7eb2e8f9f7 | 935 | data = *(__IO uint8_t *)deviceaddress; |
<> | 144:ef7eb2e8f9f7 | 936 | |
<> | 144:ef7eb2e8f9f7 | 937 | /* Return the status */ |
<> | 144:ef7eb2e8f9f7 | 938 | if((data & NAND_ERROR) == NAND_ERROR) |
<> | 144:ef7eb2e8f9f7 | 939 | { |
<> | 144:ef7eb2e8f9f7 | 940 | return NAND_ERROR; |
<> | 144:ef7eb2e8f9f7 | 941 | } |
<> | 144:ef7eb2e8f9f7 | 942 | else if((data & NAND_READY) == NAND_READY) |
<> | 144:ef7eb2e8f9f7 | 943 | { |
<> | 144:ef7eb2e8f9f7 | 944 | return NAND_READY; |
<> | 144:ef7eb2e8f9f7 | 945 | } |
<> | 144:ef7eb2e8f9f7 | 946 | |
<> | 144:ef7eb2e8f9f7 | 947 | return NAND_BUSY; |
<> | 144:ef7eb2e8f9f7 | 948 | } |
<> | 144:ef7eb2e8f9f7 | 949 | |
<> | 144:ef7eb2e8f9f7 | 950 | /** |
<> | 144:ef7eb2e8f9f7 | 951 | * @brief Increment the NAND memory address |
<> | 144:ef7eb2e8f9f7 | 952 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 953 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 954 | * @param pAddress: pointer to NAND address structure |
<> | 144:ef7eb2e8f9f7 | 955 | * @retval The new status of the increment address operation. It can be: |
<> | 144:ef7eb2e8f9f7 | 956 | * - NAND_VALID_ADDRESS: When the new address is valid address |
<> | 144:ef7eb2e8f9f7 | 957 | * - NAND_INVALID_ADDRESS: When the new address is invalid address |
<> | 144:ef7eb2e8f9f7 | 958 | */ |
<> | 144:ef7eb2e8f9f7 | 959 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) |
<> | 144:ef7eb2e8f9f7 | 960 | { |
<> | 144:ef7eb2e8f9f7 | 961 | uint32_t status = NAND_VALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 962 | |
<> | 144:ef7eb2e8f9f7 | 963 | /* Increment page address */ |
<> | 144:ef7eb2e8f9f7 | 964 | pAddress->Page++; |
<> | 144:ef7eb2e8f9f7 | 965 | |
<> | 144:ef7eb2e8f9f7 | 966 | /* Check NAND address is valid */ |
<> | 144:ef7eb2e8f9f7 | 967 | if(pAddress->Page == hnand->Info.BlockSize) |
<> | 144:ef7eb2e8f9f7 | 968 | { |
<> | 144:ef7eb2e8f9f7 | 969 | pAddress->Page = 0; |
<> | 144:ef7eb2e8f9f7 | 970 | pAddress->Block++; |
<> | 144:ef7eb2e8f9f7 | 971 | |
<> | 144:ef7eb2e8f9f7 | 972 | if(pAddress->Block == hnand->Info.ZoneSize) |
<> | 144:ef7eb2e8f9f7 | 973 | { |
<> | 144:ef7eb2e8f9f7 | 974 | pAddress->Block = 0; |
<> | 144:ef7eb2e8f9f7 | 975 | pAddress->Zone++; |
<> | 144:ef7eb2e8f9f7 | 976 | |
<> | 144:ef7eb2e8f9f7 | 977 | if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) |
<> | 144:ef7eb2e8f9f7 | 978 | { |
<> | 144:ef7eb2e8f9f7 | 979 | status = NAND_INVALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 980 | } |
<> | 144:ef7eb2e8f9f7 | 981 | } |
<> | 144:ef7eb2e8f9f7 | 982 | } |
<> | 144:ef7eb2e8f9f7 | 983 | |
<> | 144:ef7eb2e8f9f7 | 984 | return (status); |
<> | 144:ef7eb2e8f9f7 | 985 | } |
<> | 144:ef7eb2e8f9f7 | 986 | /** |
<> | 144:ef7eb2e8f9f7 | 987 | * @} |
<> | 144:ef7eb2e8f9f7 | 988 | */ |
<> | 144:ef7eb2e8f9f7 | 989 | |
<> | 144:ef7eb2e8f9f7 | 990 | /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 991 | * @brief management functions |
<> | 144:ef7eb2e8f9f7 | 992 | * |
<> | 144:ef7eb2e8f9f7 | 993 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 994 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 995 | ##### NAND Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 996 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 997 | [..] |
<> | 144:ef7eb2e8f9f7 | 998 | This subsection provides a set of functions allowing to control dynamically |
<> | 144:ef7eb2e8f9f7 | 999 | the NAND interface. |
<> | 144:ef7eb2e8f9f7 | 1000 | |
<> | 144:ef7eb2e8f9f7 | 1001 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1002 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1003 | */ |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | |
<> | 144:ef7eb2e8f9f7 | 1006 | /** |
<> | 144:ef7eb2e8f9f7 | 1007 | * @brief Enables dynamically NAND ECC feature. |
<> | 144:ef7eb2e8f9f7 | 1008 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1009 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 1010 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1011 | */ |
<> | 144:ef7eb2e8f9f7 | 1012 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 1013 | { |
<> | 144:ef7eb2e8f9f7 | 1014 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 1015 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 1016 | { |
<> | 144:ef7eb2e8f9f7 | 1017 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1018 | } |
<> | 144:ef7eb2e8f9f7 | 1019 | |
<> | 144:ef7eb2e8f9f7 | 1020 | /* Update the NAND state */ |
<> | 144:ef7eb2e8f9f7 | 1021 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1022 | |
<> | 144:ef7eb2e8f9f7 | 1023 | /* Enable ECC feature */ |
<> | 144:ef7eb2e8f9f7 | 1024 | FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); |
<> | 144:ef7eb2e8f9f7 | 1025 | |
<> | 144:ef7eb2e8f9f7 | 1026 | /* Update the NAND state */ |
<> | 144:ef7eb2e8f9f7 | 1027 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1028 | |
<> | 144:ef7eb2e8f9f7 | 1029 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1030 | } |
<> | 144:ef7eb2e8f9f7 | 1031 | |
<> | 144:ef7eb2e8f9f7 | 1032 | /** |
<> | 144:ef7eb2e8f9f7 | 1033 | * @brief Disables dynamically FMC_NAND ECC feature. |
<> | 144:ef7eb2e8f9f7 | 1034 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1035 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 1036 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1037 | */ |
<> | 144:ef7eb2e8f9f7 | 1038 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 1039 | { |
<> | 144:ef7eb2e8f9f7 | 1040 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 1041 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 1042 | { |
<> | 144:ef7eb2e8f9f7 | 1043 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1044 | } |
<> | 144:ef7eb2e8f9f7 | 1045 | |
<> | 144:ef7eb2e8f9f7 | 1046 | /* Update the NAND state */ |
<> | 144:ef7eb2e8f9f7 | 1047 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1048 | |
<> | 144:ef7eb2e8f9f7 | 1049 | /* Disable ECC feature */ |
<> | 144:ef7eb2e8f9f7 | 1050 | FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); |
<> | 144:ef7eb2e8f9f7 | 1051 | |
<> | 144:ef7eb2e8f9f7 | 1052 | /* Update the NAND state */ |
<> | 144:ef7eb2e8f9f7 | 1053 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1054 | |
<> | 144:ef7eb2e8f9f7 | 1055 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1056 | } |
<> | 144:ef7eb2e8f9f7 | 1057 | |
<> | 144:ef7eb2e8f9f7 | 1058 | /** |
<> | 144:ef7eb2e8f9f7 | 1059 | * @brief Disables dynamically NAND ECC feature. |
<> | 144:ef7eb2e8f9f7 | 1060 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1061 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 1062 | * @param ECCval: pointer to ECC value |
<> | 144:ef7eb2e8f9f7 | 1063 | * @param Timeout: maximum timeout to wait |
<> | 144:ef7eb2e8f9f7 | 1064 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1065 | */ |
<> | 144:ef7eb2e8f9f7 | 1066 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1067 | { |
<> | 144:ef7eb2e8f9f7 | 1068 | HAL_StatusTypeDef status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1069 | |
<> | 144:ef7eb2e8f9f7 | 1070 | /* Check the NAND controller state */ |
<> | 144:ef7eb2e8f9f7 | 1071 | if(hnand->State == HAL_NAND_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 1072 | { |
<> | 144:ef7eb2e8f9f7 | 1073 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1074 | } |
<> | 144:ef7eb2e8f9f7 | 1075 | |
<> | 144:ef7eb2e8f9f7 | 1076 | /* Update the NAND state */ |
<> | 144:ef7eb2e8f9f7 | 1077 | hnand->State = HAL_NAND_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1078 | |
<> | 144:ef7eb2e8f9f7 | 1079 | /* Get NAND ECC value */ |
<> | 144:ef7eb2e8f9f7 | 1080 | status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); |
<> | 144:ef7eb2e8f9f7 | 1081 | |
<> | 144:ef7eb2e8f9f7 | 1082 | /* Update the NAND state */ |
<> | 144:ef7eb2e8f9f7 | 1083 | hnand->State = HAL_NAND_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1084 | |
<> | 144:ef7eb2e8f9f7 | 1085 | return status; |
<> | 144:ef7eb2e8f9f7 | 1086 | } |
<> | 144:ef7eb2e8f9f7 | 1087 | |
<> | 144:ef7eb2e8f9f7 | 1088 | /** |
<> | 144:ef7eb2e8f9f7 | 1089 | * @} |
<> | 144:ef7eb2e8f9f7 | 1090 | */ |
<> | 144:ef7eb2e8f9f7 | 1091 | |
<> | 144:ef7eb2e8f9f7 | 1092 | |
<> | 144:ef7eb2e8f9f7 | 1093 | /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1094 | * @brief Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1095 | * |
<> | 144:ef7eb2e8f9f7 | 1096 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1097 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1098 | ##### NAND State functions ##### |
<> | 144:ef7eb2e8f9f7 | 1099 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1100 | [..] |
<> | 144:ef7eb2e8f9f7 | 1101 | This subsection permits to get in run-time the status of the NAND controller |
<> | 144:ef7eb2e8f9f7 | 1102 | and the data flow. |
<> | 144:ef7eb2e8f9f7 | 1103 | |
<> | 144:ef7eb2e8f9f7 | 1104 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1105 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1106 | */ |
<> | 144:ef7eb2e8f9f7 | 1107 | |
<> | 144:ef7eb2e8f9f7 | 1108 | /** |
<> | 144:ef7eb2e8f9f7 | 1109 | * @brief return the NAND state |
<> | 144:ef7eb2e8f9f7 | 1110 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1111 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 1112 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1113 | */ |
<> | 144:ef7eb2e8f9f7 | 1114 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) |
<> | 144:ef7eb2e8f9f7 | 1115 | { |
<> | 144:ef7eb2e8f9f7 | 1116 | return hnand->State; |
<> | 144:ef7eb2e8f9f7 | 1117 | } |
<> | 144:ef7eb2e8f9f7 | 1118 | |
<> | 144:ef7eb2e8f9f7 | 1119 | /** |
<> | 144:ef7eb2e8f9f7 | 1120 | * @} |
<> | 144:ef7eb2e8f9f7 | 1121 | */ |
<> | 144:ef7eb2e8f9f7 | 1122 | |
<> | 144:ef7eb2e8f9f7 | 1123 | /** |
<> | 144:ef7eb2e8f9f7 | 1124 | * @} |
<> | 144:ef7eb2e8f9f7 | 1125 | */ |
<> | 144:ef7eb2e8f9f7 | 1126 | |
<> | 144:ef7eb2e8f9f7 | 1127 | /** @addtogroup NAND_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 1128 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1129 | */ |
<> | 144:ef7eb2e8f9f7 | 1130 | |
<> | 144:ef7eb2e8f9f7 | 1131 | /** |
<> | 144:ef7eb2e8f9f7 | 1132 | * @brief Increment the NAND memory address. |
<> | 144:ef7eb2e8f9f7 | 1133 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1134 | * the configuration information for NAND module. |
<> | 144:ef7eb2e8f9f7 | 1135 | * @param Address: address to be incremented. |
<> | 144:ef7eb2e8f9f7 | 1136 | * @retval The new status of the increment address operation. It can be: |
<> | 144:ef7eb2e8f9f7 | 1137 | * - NAND_VALID_ADDRESS: When the new address is valid address |
<> | 144:ef7eb2e8f9f7 | 1138 | * - NAND_INVALID_ADDRESS: When the new address is invalid address |
<> | 144:ef7eb2e8f9f7 | 1139 | */ |
<> | 144:ef7eb2e8f9f7 | 1140 | static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address) |
<> | 144:ef7eb2e8f9f7 | 1141 | { |
<> | 144:ef7eb2e8f9f7 | 1142 | uint32_t status = NAND_VALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 1143 | |
<> | 144:ef7eb2e8f9f7 | 1144 | Address->Page++; |
<> | 144:ef7eb2e8f9f7 | 1145 | |
<> | 144:ef7eb2e8f9f7 | 1146 | if(Address->Page == hnand->Info.BlockSize) |
<> | 144:ef7eb2e8f9f7 | 1147 | { |
<> | 144:ef7eb2e8f9f7 | 1148 | Address->Page = 0; |
<> | 144:ef7eb2e8f9f7 | 1149 | Address->Block++; |
<> | 144:ef7eb2e8f9f7 | 1150 | |
<> | 144:ef7eb2e8f9f7 | 1151 | if(Address->Block == hnand->Info.ZoneSize) |
<> | 144:ef7eb2e8f9f7 | 1152 | { |
<> | 144:ef7eb2e8f9f7 | 1153 | Address->Block = 0; |
<> | 144:ef7eb2e8f9f7 | 1154 | Address->Zone++; |
<> | 144:ef7eb2e8f9f7 | 1155 | |
<> | 144:ef7eb2e8f9f7 | 1156 | if(Address->Zone == hnand->Info.BlockNbr) |
<> | 144:ef7eb2e8f9f7 | 1157 | { |
<> | 144:ef7eb2e8f9f7 | 1158 | status = NAND_INVALID_ADDRESS; |
<> | 144:ef7eb2e8f9f7 | 1159 | } |
<> | 144:ef7eb2e8f9f7 | 1160 | } |
<> | 144:ef7eb2e8f9f7 | 1161 | } |
<> | 144:ef7eb2e8f9f7 | 1162 | |
<> | 144:ef7eb2e8f9f7 | 1163 | return (status); |
<> | 144:ef7eb2e8f9f7 | 1164 | } |
<> | 144:ef7eb2e8f9f7 | 1165 | |
<> | 144:ef7eb2e8f9f7 | 1166 | /** |
<> | 144:ef7eb2e8f9f7 | 1167 | * @} |
<> | 144:ef7eb2e8f9f7 | 1168 | */ |
<> | 144:ef7eb2e8f9f7 | 1169 | |
<> | 144:ef7eb2e8f9f7 | 1170 | /** |
<> | 144:ef7eb2e8f9f7 | 1171 | * @} |
<> | 144:ef7eb2e8f9f7 | 1172 | */ |
<> | 144:ef7eb2e8f9f7 | 1173 | |
<> | 144:ef7eb2e8f9f7 | 1174 | #endif /* HAL_NAND_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1175 | |
<> | 144:ef7eb2e8f9f7 | 1176 | /** |
<> | 144:ef7eb2e8f9f7 | 1177 | * @} |
<> | 144:ef7eb2e8f9f7 | 1178 | */ |
<> | 144:ef7eb2e8f9f7 | 1179 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
<> | 144:ef7eb2e8f9f7 | 1180 | |
<> | 144:ef7eb2e8f9f7 | 1181 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |