MBED-DEV only fro Nucleo STM32F303K8T6
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.h@151:acf04f8e7d03, 2016-11-19 (annotated)
- Committer:
- pravinautosys
- Date:
- Sat Nov 19 10:38:54 2016 +0000
- Revision:
- 151:acf04f8e7d03
- Parent:
- 149:156823d33999
MyMBED-DEVWithSTM32F303K8T6;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f3xx_hal_irda.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.3.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 01-July-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief This file contains all the functions prototypes for the IRDA |
<> | 144:ef7eb2e8f9f7 | 8 | * firmware library. |
<> | 144:ef7eb2e8f9f7 | 9 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 10 | * @attention |
<> | 144:ef7eb2e8f9f7 | 11 | * |
<> | 144:ef7eb2e8f9f7 | 12 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 15 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 17 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 19 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 20 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 22 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 23 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 24 | * |
<> | 144:ef7eb2e8f9f7 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 35 | * |
<> | 144:ef7eb2e8f9f7 | 36 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 37 | */ |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 40 | #ifndef __STM32F3xx_HAL_IRDA_H |
<> | 144:ef7eb2e8f9f7 | 41 | #define __STM32F3xx_HAL_IRDA_H |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 44 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 45 | #endif |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 48 | #include "stm32f3xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /** @addtogroup STM32F3xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 51 | * @{ |
<> | 144:ef7eb2e8f9f7 | 52 | */ |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | /** @addtogroup IRDA |
<> | 144:ef7eb2e8f9f7 | 55 | * @{ |
<> | 144:ef7eb2e8f9f7 | 56 | */ |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 59 | /** @defgroup IRDA_Exported_Types IRDA Exported Types |
<> | 144:ef7eb2e8f9f7 | 60 | * @{ |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | /** |
<> | 144:ef7eb2e8f9f7 | 64 | * @brief IRDA Init Structure definition |
<> | 144:ef7eb2e8f9f7 | 65 | */ |
<> | 144:ef7eb2e8f9f7 | 66 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 67 | { |
<> | 144:ef7eb2e8f9f7 | 68 | uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. |
<> | 144:ef7eb2e8f9f7 | 69 | The baud rate register is computed using the following formula: |
<> | 144:ef7eb2e8f9f7 | 70 | Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */ |
<> | 144:ef7eb2e8f9f7 | 71 | |
<> | 144:ef7eb2e8f9f7 | 72 | uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. |
<> | 144:ef7eb2e8f9f7 | 73 | This parameter can be a value of @ref IRDAEx_Word_Length */ |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | uint32_t Parity; /*!< Specifies the parity mode. |
<> | 144:ef7eb2e8f9f7 | 76 | This parameter can be a value of @ref IRDA_Parity |
<> | 144:ef7eb2e8f9f7 | 77 | @note When parity is enabled, the computed parity is inserted |
<> | 144:ef7eb2e8f9f7 | 78 | at the MSB position of the transmitted data (9th bit when |
<> | 144:ef7eb2e8f9f7 | 79 | the word length is set to 9 data bits; 8th bit when the |
<> | 144:ef7eb2e8f9f7 | 80 | word length is set to 8 data bits). */ |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. |
<> | 144:ef7eb2e8f9f7 | 83 | This parameter can be a value of @ref IRDA_Transfer_Mode */ |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock |
<> | 144:ef7eb2e8f9f7 | 86 | to achieve low-power frequency. |
<> | 144:ef7eb2e8f9f7 | 87 | @note Prescaler value 0 is forbidden */ |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | uint16_t PowerMode; /*!< Specifies the IRDA power mode. |
<> | 144:ef7eb2e8f9f7 | 90 | This parameter can be a value of @ref IRDA_Low_Power */ |
<> | 144:ef7eb2e8f9f7 | 91 | }IRDA_InitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | /** |
<> | 144:ef7eb2e8f9f7 | 94 | * @brief HAL IRDA State structures definition |
<> | 144:ef7eb2e8f9f7 | 95 | * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. |
<> | 144:ef7eb2e8f9f7 | 96 | * - gState contains IRDA state information related to global Handle management |
<> | 144:ef7eb2e8f9f7 | 97 | * and also information related to Tx operations. |
<> | 144:ef7eb2e8f9f7 | 98 | * gState value coding follow below described bitmap : |
<> | 144:ef7eb2e8f9f7 | 99 | * b7-b6 Error information |
<> | 144:ef7eb2e8f9f7 | 100 | * 00 : No Error |
<> | 144:ef7eb2e8f9f7 | 101 | * 01 : (Not Used) |
<> | 144:ef7eb2e8f9f7 | 102 | * 10 : Timeout |
<> | 144:ef7eb2e8f9f7 | 103 | * 11 : Error |
<> | 144:ef7eb2e8f9f7 | 104 | * b5 IP initilisation status |
<> | 144:ef7eb2e8f9f7 | 105 | * 0 : Reset (IP not initialized) |
<> | 144:ef7eb2e8f9f7 | 106 | * 1 : Init done (IP not initialized. HAL IRDA Init function already called) |
<> | 144:ef7eb2e8f9f7 | 107 | * b4-b3 (not used) |
<> | 144:ef7eb2e8f9f7 | 108 | * xx : Should be set to 00 |
<> | 144:ef7eb2e8f9f7 | 109 | * b2 Intrinsic process state |
<> | 144:ef7eb2e8f9f7 | 110 | * 0 : Ready |
<> | 144:ef7eb2e8f9f7 | 111 | * 1 : Busy (IP busy with some configuration or internal operations) |
<> | 144:ef7eb2e8f9f7 | 112 | * b1 (not used) |
<> | 144:ef7eb2e8f9f7 | 113 | * x : Should be set to 0 |
<> | 144:ef7eb2e8f9f7 | 114 | * b0 Tx state |
<> | 144:ef7eb2e8f9f7 | 115 | * 0 : Ready (no Tx operation ongoing) |
<> | 144:ef7eb2e8f9f7 | 116 | * 1 : Busy (Tx operation ongoing) |
<> | 144:ef7eb2e8f9f7 | 117 | * - RxState contains information related to Rx operations. |
<> | 144:ef7eb2e8f9f7 | 118 | * RxState value coding follow below described bitmap : |
<> | 144:ef7eb2e8f9f7 | 119 | * b7-b6 (not used) |
<> | 144:ef7eb2e8f9f7 | 120 | * xx : Should be set to 00 |
<> | 144:ef7eb2e8f9f7 | 121 | * b5 IP initilisation status |
<> | 144:ef7eb2e8f9f7 | 122 | * 0 : Reset (IP not initialized) |
<> | 144:ef7eb2e8f9f7 | 123 | * 1 : Init done (IP not initialized) |
<> | 144:ef7eb2e8f9f7 | 124 | * b4-b2 (not used) |
<> | 144:ef7eb2e8f9f7 | 125 | * xxx : Should be set to 000 |
<> | 144:ef7eb2e8f9f7 | 126 | * b1 Rx state |
<> | 144:ef7eb2e8f9f7 | 127 | * 0 : Ready (no Rx operation ongoing) |
<> | 144:ef7eb2e8f9f7 | 128 | * 1 : Busy (Rx operation ongoing) |
<> | 144:ef7eb2e8f9f7 | 129 | * b0 (not used) |
<> | 144:ef7eb2e8f9f7 | 130 | * x : Should be set to 0. |
<> | 144:ef7eb2e8f9f7 | 131 | */ |
<> | 144:ef7eb2e8f9f7 | 132 | typedef enum |
<> | 144:ef7eb2e8f9f7 | 133 | { |
<> | 144:ef7eb2e8f9f7 | 134 | HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized |
<> | 144:ef7eb2e8f9f7 | 135 | Value is allowed for gState and RxState */ |
<> | 144:ef7eb2e8f9f7 | 136 | HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use |
<> | 144:ef7eb2e8f9f7 | 137 | Value is allowed for gState and RxState */ |
<> | 144:ef7eb2e8f9f7 | 138 | HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing |
<> | 144:ef7eb2e8f9f7 | 139 | Value is allowed for gState only */ |
<> | 144:ef7eb2e8f9f7 | 140 | HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing |
<> | 144:ef7eb2e8f9f7 | 141 | Value is allowed for gState only */ |
<> | 144:ef7eb2e8f9f7 | 142 | HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing |
<> | 144:ef7eb2e8f9f7 | 143 | Value is allowed for RxState only */ |
<> | 144:ef7eb2e8f9f7 | 144 | HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing |
<> | 144:ef7eb2e8f9f7 | 145 | Not to be used for neither gState nor RxState. |
<> | 144:ef7eb2e8f9f7 | 146 | Value is result of combination (Or) between gState and RxState values */ |
<> | 144:ef7eb2e8f9f7 | 147 | HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state |
<> | 144:ef7eb2e8f9f7 | 148 | Value is allowed for gState only */ |
<> | 144:ef7eb2e8f9f7 | 149 | HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error |
<> | 144:ef7eb2e8f9f7 | 150 | Value is allowed for gState only */ |
<> | 144:ef7eb2e8f9f7 | 151 | }HAL_IRDA_StateTypeDef; |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | /** |
<> | 144:ef7eb2e8f9f7 | 154 | * @brief IRDA clock sources definition |
<> | 144:ef7eb2e8f9f7 | 155 | */ |
<> | 144:ef7eb2e8f9f7 | 156 | typedef enum |
<> | 144:ef7eb2e8f9f7 | 157 | { |
<> | 144:ef7eb2e8f9f7 | 158 | IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ |
<> | 144:ef7eb2e8f9f7 | 159 | IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ |
<> | 144:ef7eb2e8f9f7 | 160 | IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ |
<> | 144:ef7eb2e8f9f7 | 161 | IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ |
<> | 144:ef7eb2e8f9f7 | 162 | IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ |
<> | 144:ef7eb2e8f9f7 | 163 | IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ |
<> | 144:ef7eb2e8f9f7 | 164 | }IRDA_ClockSourceTypeDef; |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | /** |
<> | 144:ef7eb2e8f9f7 | 167 | * @brief IRDA handle Structure definition |
<> | 144:ef7eb2e8f9f7 | 168 | */ |
<> | 144:ef7eb2e8f9f7 | 169 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 170 | { |
<> | 144:ef7eb2e8f9f7 | 171 | USART_TypeDef *Instance; /*!< USART registers base address */ |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | uint16_t Mask; /*!< USART RX RDR register mask */ |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | HAL_LockTypeDef Lock; /*!< Locking object */ |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management |
<> | 144:ef7eb2e8f9f7 | 196 | and also related to Tx operations. |
<> | 144:ef7eb2e8f9f7 | 197 | This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. |
<> | 144:ef7eb2e8f9f7 | 200 | This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | __IO uint32_t ErrorCode; /*!< IRDA Error code |
<> | 144:ef7eb2e8f9f7 | 203 | This parameter can be a value of @ref IRDA_Error */ |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | }IRDA_HandleTypeDef; |
<> | 144:ef7eb2e8f9f7 | 206 | |
<> | 144:ef7eb2e8f9f7 | 207 | /** |
<> | 144:ef7eb2e8f9f7 | 208 | * @brief IRDA Configuration enumeration values definition |
<> | 144:ef7eb2e8f9f7 | 209 | */ |
<> | 144:ef7eb2e8f9f7 | 210 | typedef enum |
<> | 144:ef7eb2e8f9f7 | 211 | { |
<> | 144:ef7eb2e8f9f7 | 212 | IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */ |
<> | 144:ef7eb2e8f9f7 | 213 | IRDA_PARITY = 0x01, /*!< IRDA frame parity */ |
<> | 144:ef7eb2e8f9f7 | 214 | IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */ |
<> | 144:ef7eb2e8f9f7 | 215 | IRDA_MODE = 0x03, /*!< IRDA communication mode */ |
<> | 144:ef7eb2e8f9f7 | 216 | IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */ |
<> | 144:ef7eb2e8f9f7 | 217 | IRDA_POWERMODE = 0x05 /*!< IRDA power mode */ |
<> | 144:ef7eb2e8f9f7 | 218 | }IRDA_ControlTypeDef; |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | /** |
<> | 144:ef7eb2e8f9f7 | 221 | * @} |
<> | 144:ef7eb2e8f9f7 | 222 | */ |
<> | 144:ef7eb2e8f9f7 | 223 | |
<> | 144:ef7eb2e8f9f7 | 224 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 225 | /** @defgroup IRDA_Exported_Constants IRDA Exported Constants |
<> | 144:ef7eb2e8f9f7 | 226 | * @{ |
<> | 144:ef7eb2e8f9f7 | 227 | */ |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | /** @defgroup IRDA_Error IRDA Error |
<> | 144:ef7eb2e8f9f7 | 230 | * @{ |
<> | 144:ef7eb2e8f9f7 | 231 | */ |
<> | 144:ef7eb2e8f9f7 | 232 | #define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
<> | 144:ef7eb2e8f9f7 | 233 | #define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ |
<> | 144:ef7eb2e8f9f7 | 234 | #define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ |
<> | 144:ef7eb2e8f9f7 | 235 | #define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ |
<> | 144:ef7eb2e8f9f7 | 236 | #define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ |
<> | 144:ef7eb2e8f9f7 | 237 | #define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ |
<> | 144:ef7eb2e8f9f7 | 238 | /** |
<> | 144:ef7eb2e8f9f7 | 239 | * @} |
<> | 144:ef7eb2e8f9f7 | 240 | */ |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | /** @defgroup IRDA_Parity IRDA Parity |
<> | 144:ef7eb2e8f9f7 | 243 | * @{ |
<> | 144:ef7eb2e8f9f7 | 244 | */ |
<> | 144:ef7eb2e8f9f7 | 245 | #define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ |
<> | 144:ef7eb2e8f9f7 | 246 | #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ |
<> | 144:ef7eb2e8f9f7 | 247 | #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ |
<> | 144:ef7eb2e8f9f7 | 248 | /** |
<> | 144:ef7eb2e8f9f7 | 249 | * @} |
<> | 144:ef7eb2e8f9f7 | 250 | */ |
<> | 144:ef7eb2e8f9f7 | 251 | |
<> | 144:ef7eb2e8f9f7 | 252 | /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode |
<> | 144:ef7eb2e8f9f7 | 253 | * @{ |
<> | 144:ef7eb2e8f9f7 | 254 | */ |
<> | 144:ef7eb2e8f9f7 | 255 | #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ |
<> | 144:ef7eb2e8f9f7 | 256 | #define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ |
<> | 144:ef7eb2e8f9f7 | 257 | #define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ |
<> | 144:ef7eb2e8f9f7 | 258 | /** |
<> | 144:ef7eb2e8f9f7 | 259 | * @} |
<> | 144:ef7eb2e8f9f7 | 260 | */ |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | /** @defgroup IRDA_Low_Power IRDA Low Power |
<> | 144:ef7eb2e8f9f7 | 263 | * @{ |
<> | 144:ef7eb2e8f9f7 | 264 | */ |
<> | 144:ef7eb2e8f9f7 | 265 | #define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */ |
<> | 144:ef7eb2e8f9f7 | 266 | #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */ |
<> | 144:ef7eb2e8f9f7 | 267 | /** |
<> | 144:ef7eb2e8f9f7 | 268 | * @} |
<> | 144:ef7eb2e8f9f7 | 269 | */ |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | /** @defgroup IRDA_State IRDA State |
<> | 144:ef7eb2e8f9f7 | 272 | * @{ |
<> | 144:ef7eb2e8f9f7 | 273 | */ |
<> | 144:ef7eb2e8f9f7 | 274 | #define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */ |
<> | 144:ef7eb2e8f9f7 | 275 | #define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */ |
<> | 144:ef7eb2e8f9f7 | 276 | /** |
<> | 144:ef7eb2e8f9f7 | 277 | * @} |
<> | 144:ef7eb2e8f9f7 | 278 | */ |
<> | 144:ef7eb2e8f9f7 | 279 | |
<> | 144:ef7eb2e8f9f7 | 280 | /** @defgroup IRDA_Mode IRDA Mode |
<> | 144:ef7eb2e8f9f7 | 281 | * @{ |
<> | 144:ef7eb2e8f9f7 | 282 | */ |
<> | 144:ef7eb2e8f9f7 | 283 | #define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */ |
<> | 144:ef7eb2e8f9f7 | 284 | #define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */ |
<> | 144:ef7eb2e8f9f7 | 285 | /** |
<> | 144:ef7eb2e8f9f7 | 286 | * @} |
<> | 144:ef7eb2e8f9f7 | 287 | */ |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | /** @defgroup IRDA_One_Bit IRDA One Bit Sampling |
<> | 144:ef7eb2e8f9f7 | 290 | * @{ |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | #define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */ |
<> | 144:ef7eb2e8f9f7 | 293 | #define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */ |
<> | 144:ef7eb2e8f9f7 | 294 | /** |
<> | 144:ef7eb2e8f9f7 | 295 | * @} |
<> | 144:ef7eb2e8f9f7 | 296 | */ |
<> | 144:ef7eb2e8f9f7 | 297 | |
<> | 144:ef7eb2e8f9f7 | 298 | /** @defgroup IRDA_DMA_Tx IRDA DMA Tx |
<> | 144:ef7eb2e8f9f7 | 299 | * @{ |
<> | 144:ef7eb2e8f9f7 | 300 | */ |
<> | 144:ef7eb2e8f9f7 | 301 | #define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */ |
<> | 144:ef7eb2e8f9f7 | 302 | #define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */ |
<> | 144:ef7eb2e8f9f7 | 303 | /** |
<> | 144:ef7eb2e8f9f7 | 304 | * @} |
<> | 144:ef7eb2e8f9f7 | 305 | */ |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | /** @defgroup IRDA_DMA_Rx IRDA DMA Rx |
<> | 144:ef7eb2e8f9f7 | 308 | * @{ |
<> | 144:ef7eb2e8f9f7 | 309 | */ |
<> | 144:ef7eb2e8f9f7 | 310 | #define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */ |
<> | 144:ef7eb2e8f9f7 | 311 | #define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */ |
<> | 144:ef7eb2e8f9f7 | 312 | /** |
<> | 144:ef7eb2e8f9f7 | 313 | * @} |
<> | 144:ef7eb2e8f9f7 | 314 | */ |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | /** @defgroup IRDA_Request_Parameters IRDA Request Parameters |
<> | 144:ef7eb2e8f9f7 | 317 | * @{ |
<> | 144:ef7eb2e8f9f7 | 318 | */ |
<> | 144:ef7eb2e8f9f7 | 319 | #define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ |
<> | 144:ef7eb2e8f9f7 | 320 | #define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ |
<> | 144:ef7eb2e8f9f7 | 321 | #define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ |
<> | 144:ef7eb2e8f9f7 | 322 | /** |
<> | 144:ef7eb2e8f9f7 | 323 | * @} |
<> | 144:ef7eb2e8f9f7 | 324 | */ |
<> | 144:ef7eb2e8f9f7 | 325 | |
<> | 144:ef7eb2e8f9f7 | 326 | /** @defgroup IRDA_Flags IRDA Flags |
<> | 144:ef7eb2e8f9f7 | 327 | * Elements values convention: 0xXXXX |
<> | 144:ef7eb2e8f9f7 | 328 | * - 0xXXXX : Flag mask in the ISR register |
<> | 144:ef7eb2e8f9f7 | 329 | * @{ |
<> | 144:ef7eb2e8f9f7 | 330 | */ |
<> | 144:ef7eb2e8f9f7 | 331 | #define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */ |
<> | 144:ef7eb2e8f9f7 | 332 | #define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */ |
<> | 144:ef7eb2e8f9f7 | 333 | #define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */ |
<> | 144:ef7eb2e8f9f7 | 334 | #define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */ |
<> | 144:ef7eb2e8f9f7 | 335 | #define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */ |
<> | 144:ef7eb2e8f9f7 | 336 | #define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */ |
<> | 144:ef7eb2e8f9f7 | 337 | #define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */ |
<> | 144:ef7eb2e8f9f7 | 338 | #define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */ |
<> | 144:ef7eb2e8f9f7 | 339 | #define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */ |
<> | 144:ef7eb2e8f9f7 | 340 | #define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */ |
<> | 144:ef7eb2e8f9f7 | 341 | #define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */ |
<> | 144:ef7eb2e8f9f7 | 342 | #define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */ |
<> | 144:ef7eb2e8f9f7 | 343 | /** |
<> | 144:ef7eb2e8f9f7 | 344 | * @} |
<> | 144:ef7eb2e8f9f7 | 345 | */ |
<> | 144:ef7eb2e8f9f7 | 346 | |
<> | 144:ef7eb2e8f9f7 | 347 | /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition |
<> | 144:ef7eb2e8f9f7 | 348 | * Elements values convention: 0000ZZZZ0XXYYYYYb |
<> | 144:ef7eb2e8f9f7 | 349 | * - YYYYY : Interrupt source position in the XX register (5bits) |
<> | 144:ef7eb2e8f9f7 | 350 | * - XX : Interrupt source register (2bits) |
<> | 144:ef7eb2e8f9f7 | 351 | * - 01: CR1 register |
<> | 144:ef7eb2e8f9f7 | 352 | * - 10: CR2 register |
<> | 144:ef7eb2e8f9f7 | 353 | * - 11: CR3 register |
<> | 144:ef7eb2e8f9f7 | 354 | * - ZZZZ : Flag position in the ISR register(4bits) |
<> | 144:ef7eb2e8f9f7 | 355 | * @{ |
<> | 144:ef7eb2e8f9f7 | 356 | */ |
<> | 144:ef7eb2e8f9f7 | 357 | #define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */ |
<> | 144:ef7eb2e8f9f7 | 358 | #define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */ |
<> | 144:ef7eb2e8f9f7 | 359 | #define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */ |
<> | 144:ef7eb2e8f9f7 | 360 | #define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */ |
<> | 144:ef7eb2e8f9f7 | 361 | #define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */ |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | /** Elements values convention: 000000000XXYYYYYb |
<> | 144:ef7eb2e8f9f7 | 364 | * - YYYYY : Interrupt source position in the XX register (5bits) |
<> | 144:ef7eb2e8f9f7 | 365 | * - XX : Interrupt source register (2bits) |
<> | 144:ef7eb2e8f9f7 | 366 | * - 01: CR1 register |
<> | 144:ef7eb2e8f9f7 | 367 | * - 10: CR2 register |
<> | 144:ef7eb2e8f9f7 | 368 | * - 11: CR3 register |
<> | 144:ef7eb2e8f9f7 | 369 | */ |
<> | 144:ef7eb2e8f9f7 | 370 | #define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */ |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | /** Elements values convention: 0000ZZZZ00000000b |
<> | 144:ef7eb2e8f9f7 | 373 | * - ZZZZ : Flag position in the ISR register(4bits) |
<> | 144:ef7eb2e8f9f7 | 374 | */ |
<> | 144:ef7eb2e8f9f7 | 375 | #define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */ |
<> | 144:ef7eb2e8f9f7 | 376 | #define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */ |
<> | 144:ef7eb2e8f9f7 | 377 | #define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */ |
<> | 144:ef7eb2e8f9f7 | 378 | /** |
<> | 144:ef7eb2e8f9f7 | 379 | * @} |
<> | 144:ef7eb2e8f9f7 | 380 | */ |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags |
<> | 144:ef7eb2e8f9f7 | 383 | * @{ |
<> | 144:ef7eb2e8f9f7 | 384 | */ |
<> | 144:ef7eb2e8f9f7 | 385 | #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 386 | #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 387 | #define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 388 | #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 389 | #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 390 | /** |
<> | 144:ef7eb2e8f9f7 | 391 | * @} |
<> | 144:ef7eb2e8f9f7 | 392 | */ |
<> | 144:ef7eb2e8f9f7 | 393 | |
<> | 144:ef7eb2e8f9f7 | 394 | /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask |
<> | 144:ef7eb2e8f9f7 | 395 | * @{ |
<> | 144:ef7eb2e8f9f7 | 396 | */ |
<> | 144:ef7eb2e8f9f7 | 397 | #define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */ |
<> | 144:ef7eb2e8f9f7 | 398 | /** |
<> | 144:ef7eb2e8f9f7 | 399 | * @} |
<> | 144:ef7eb2e8f9f7 | 400 | */ |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /** |
<> | 144:ef7eb2e8f9f7 | 403 | * @} |
<> | 144:ef7eb2e8f9f7 | 404 | */ |
<> | 144:ef7eb2e8f9f7 | 405 | |
<> | 144:ef7eb2e8f9f7 | 406 | |
<> | 144:ef7eb2e8f9f7 | 407 | /* Exported macros -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 408 | /** @defgroup IRDA_Exported_Macros IRDA Exported Macros |
<> | 144:ef7eb2e8f9f7 | 409 | * @{ |
<> | 144:ef7eb2e8f9f7 | 410 | */ |
<> | 144:ef7eb2e8f9f7 | 411 | |
<> | 144:ef7eb2e8f9f7 | 412 | /** @brief Reset IRDA handle state. |
<> | 144:ef7eb2e8f9f7 | 413 | * @param __HANDLE__: IRDA handle. |
<> | 144:ef7eb2e8f9f7 | 414 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 415 | */ |
<> | 144:ef7eb2e8f9f7 | 416 | #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
<> | 144:ef7eb2e8f9f7 | 417 | (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ |
<> | 144:ef7eb2e8f9f7 | 418 | (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ |
<> | 144:ef7eb2e8f9f7 | 419 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 420 | |
<> | 144:ef7eb2e8f9f7 | 421 | /** @brief Flush the IRDA Data registers. |
<> | 144:ef7eb2e8f9f7 | 422 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 423 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 424 | */ |
<> | 144:ef7eb2e8f9f7 | 425 | #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ |
<> | 144:ef7eb2e8f9f7 | 426 | do{ \ |
<> | 144:ef7eb2e8f9f7 | 427 | SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ |
<> | 144:ef7eb2e8f9f7 | 428 | SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ |
<> | 144:ef7eb2e8f9f7 | 429 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | /** @brief Clear the specified IRDA pending flag. |
<> | 144:ef7eb2e8f9f7 | 432 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 433 | * @param __FLAG__: specifies the flag to check. |
<> | 144:ef7eb2e8f9f7 | 434 | * This parameter can be any combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 435 | * @arg IRDA_CLEAR_PEF |
<> | 144:ef7eb2e8f9f7 | 436 | * @arg IRDA_CLEAR_FEF |
<> | 144:ef7eb2e8f9f7 | 437 | * @arg IRDA_CLEAR_NEF |
<> | 144:ef7eb2e8f9f7 | 438 | * @arg IRDA_CLEAR_OREF |
<> | 144:ef7eb2e8f9f7 | 439 | * @arg IRDA_CLEAR_TCF |
<> | 144:ef7eb2e8f9f7 | 440 | * @arg IRDA_CLEAR_IDLEF |
<> | 144:ef7eb2e8f9f7 | 441 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 442 | */ |
<> | 144:ef7eb2e8f9f7 | 443 | #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | /** @brief Clear the IRDA PE pending flag. |
<> | 144:ef7eb2e8f9f7 | 446 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 447 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 448 | */ |
<> | 144:ef7eb2e8f9f7 | 449 | #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) |
<> | 144:ef7eb2e8f9f7 | 450 | |
<> | 144:ef7eb2e8f9f7 | 451 | |
<> | 144:ef7eb2e8f9f7 | 452 | /** @brief Clear the IRDA FE pending flag. |
<> | 144:ef7eb2e8f9f7 | 453 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 454 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 455 | */ |
<> | 144:ef7eb2e8f9f7 | 456 | #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) |
<> | 144:ef7eb2e8f9f7 | 457 | |
<> | 144:ef7eb2e8f9f7 | 458 | /** @brief Clear the IRDA NE pending flag. |
<> | 144:ef7eb2e8f9f7 | 459 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 460 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 461 | */ |
<> | 144:ef7eb2e8f9f7 | 462 | #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) |
<> | 144:ef7eb2e8f9f7 | 463 | |
<> | 144:ef7eb2e8f9f7 | 464 | /** @brief Clear the IRDA ORE pending flag. |
<> | 144:ef7eb2e8f9f7 | 465 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 466 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 467 | */ |
<> | 144:ef7eb2e8f9f7 | 468 | #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) |
<> | 144:ef7eb2e8f9f7 | 469 | |
<> | 144:ef7eb2e8f9f7 | 470 | /** @brief Clear the IRDA IDLE pending flag. |
<> | 144:ef7eb2e8f9f7 | 471 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 472 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 473 | */ |
<> | 144:ef7eb2e8f9f7 | 474 | #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) |
<> | 144:ef7eb2e8f9f7 | 475 | |
<> | 144:ef7eb2e8f9f7 | 476 | /** @brief Check whether the specified IRDA flag is set or not. |
<> | 144:ef7eb2e8f9f7 | 477 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 478 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 479 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 480 | * @param __FLAG__: specifies the flag to check. |
<> | 144:ef7eb2e8f9f7 | 481 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 482 | * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag |
<> | 144:ef7eb2e8f9f7 | 483 | * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag |
<> | 144:ef7eb2e8f9f7 | 484 | * @arg IRDA_FLAG_BUSY: Busy flag |
<> | 144:ef7eb2e8f9f7 | 485 | * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag |
<> | 144:ef7eb2e8f9f7 | 486 | * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag |
<> | 144:ef7eb2e8f9f7 | 487 | * @arg IRDA_FLAG_TXE: Transmit data register empty flag |
<> | 144:ef7eb2e8f9f7 | 488 | * @arg IRDA_FLAG_TC: Transmission Complete flag |
<> | 144:ef7eb2e8f9f7 | 489 | * @arg IRDA_FLAG_RXNE: Receive data register not empty flag |
<> | 144:ef7eb2e8f9f7 | 490 | * @arg IRDA_FLAG_IDLE: Idle Line detection flag |
<> | 144:ef7eb2e8f9f7 | 491 | * @arg IRDA_FLAG_ORE: OverRun Error flag |
<> | 144:ef7eb2e8f9f7 | 492 | * @arg IRDA_FLAG_NE: Noise Error flag |
<> | 144:ef7eb2e8f9f7 | 493 | * @arg IRDA_FLAG_FE: Framing Error flag |
<> | 144:ef7eb2e8f9f7 | 494 | * @arg IRDA_FLAG_PE: Parity Error flag |
<> | 144:ef7eb2e8f9f7 | 495 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 496 | */ |
<> | 144:ef7eb2e8f9f7 | 497 | #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) |
<> | 144:ef7eb2e8f9f7 | 498 | |
<> | 144:ef7eb2e8f9f7 | 499 | |
<> | 144:ef7eb2e8f9f7 | 500 | /** @brief Enable the specified IRDA interrupt. |
<> | 144:ef7eb2e8f9f7 | 501 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 502 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 503 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 504 | * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. |
<> | 144:ef7eb2e8f9f7 | 505 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 506 | * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
<> | 144:ef7eb2e8f9f7 | 507 | * @arg IRDA_IT_TC: Transmission complete interrupt |
<> | 144:ef7eb2e8f9f7 | 508 | * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
<> | 144:ef7eb2e8f9f7 | 509 | * @arg IRDA_IT_IDLE: Idle line detection interrupt |
<> | 144:ef7eb2e8f9f7 | 510 | * @arg IRDA_IT_PE: Parity Error interrupt |
<> | 144:ef7eb2e8f9f7 | 511 | * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
<> | 144:ef7eb2e8f9f7 | 512 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 513 | */ |
<> | 144:ef7eb2e8f9f7 | 514 | #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ |
<> | 144:ef7eb2e8f9f7 | 515 | ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ |
<> | 144:ef7eb2e8f9f7 | 516 | ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) |
<> | 144:ef7eb2e8f9f7 | 517 | |
<> | 144:ef7eb2e8f9f7 | 518 | /** @brief Disable the specified IRDA interrupt. |
<> | 144:ef7eb2e8f9f7 | 519 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 520 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 521 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 522 | * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. |
<> | 144:ef7eb2e8f9f7 | 523 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 524 | * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
<> | 144:ef7eb2e8f9f7 | 525 | * @arg IRDA_IT_TC: Transmission complete interrupt |
<> | 144:ef7eb2e8f9f7 | 526 | * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
<> | 144:ef7eb2e8f9f7 | 527 | * @arg IRDA_IT_IDLE: Idle line detection interrupt |
<> | 144:ef7eb2e8f9f7 | 528 | * @arg IRDA_IT_PE: Parity Error interrupt |
<> | 144:ef7eb2e8f9f7 | 529 | * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
<> | 144:ef7eb2e8f9f7 | 530 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 531 | */ |
<> | 144:ef7eb2e8f9f7 | 532 | #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ |
<> | 144:ef7eb2e8f9f7 | 533 | ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ |
<> | 144:ef7eb2e8f9f7 | 534 | ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 144:ef7eb2e8f9f7 | 537 | /** @brief Check whether the specified IRDA interrupt has occurred or not. |
<> | 144:ef7eb2e8f9f7 | 538 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 539 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 540 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 541 | * @param __IT__: specifies the IRDA interrupt source to check. |
<> | 144:ef7eb2e8f9f7 | 542 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 543 | * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
<> | 144:ef7eb2e8f9f7 | 544 | * @arg IRDA_IT_TC: Transmission complete interrupt |
<> | 144:ef7eb2e8f9f7 | 545 | * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
<> | 144:ef7eb2e8f9f7 | 546 | * @arg IRDA_IT_IDLE: Idle line detection interrupt |
<> | 144:ef7eb2e8f9f7 | 547 | * @arg IRDA_IT_ORE: OverRun Error interrupt |
<> | 144:ef7eb2e8f9f7 | 548 | * @arg IRDA_IT_NE: Noise Error interrupt |
<> | 144:ef7eb2e8f9f7 | 549 | * @arg IRDA_IT_FE: Framing Error interrupt |
<> | 144:ef7eb2e8f9f7 | 550 | * @arg IRDA_IT_PE: Parity Error interrupt |
<> | 144:ef7eb2e8f9f7 | 551 | * @retval The new state of __IT__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 552 | */ |
<> | 144:ef7eb2e8f9f7 | 553 | #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) |
<> | 144:ef7eb2e8f9f7 | 554 | |
<> | 144:ef7eb2e8f9f7 | 555 | /** @brief Check whether the specified IRDA interrupt source is enabled or not. |
<> | 144:ef7eb2e8f9f7 | 556 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 557 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 558 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 559 | * @param __IT__: specifies the IRDA interrupt source to check. |
<> | 144:ef7eb2e8f9f7 | 560 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 561 | * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt |
<> | 144:ef7eb2e8f9f7 | 562 | * @arg IRDA_IT_TC: Transmission complete interrupt |
<> | 144:ef7eb2e8f9f7 | 563 | * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt |
<> | 144:ef7eb2e8f9f7 | 564 | * @arg IRDA_IT_IDLE: Idle line detection interrupt |
<> | 144:ef7eb2e8f9f7 | 565 | * @arg IRDA_IT_ORE: OverRun Error interrupt |
<> | 144:ef7eb2e8f9f7 | 566 | * @arg IRDA_IT_NE: Noise Error interrupt |
<> | 144:ef7eb2e8f9f7 | 567 | * @arg IRDA_IT_FE: Framing Error interrupt |
<> | 144:ef7eb2e8f9f7 | 568 | * @arg IRDA_IT_PE: Parity Error interrupt |
<> | 144:ef7eb2e8f9f7 | 569 | * @retval The new state of __IT__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 570 | */ |
<> | 144:ef7eb2e8f9f7 | 571 | #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ |
<> | 144:ef7eb2e8f9f7 | 572 | (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) |
<> | 144:ef7eb2e8f9f7 | 573 | |
<> | 144:ef7eb2e8f9f7 | 574 | |
<> | 144:ef7eb2e8f9f7 | 575 | /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. |
<> | 144:ef7eb2e8f9f7 | 576 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 577 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 578 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 579 | * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set |
<> | 144:ef7eb2e8f9f7 | 580 | * to clear the corresponding interrupt |
<> | 144:ef7eb2e8f9f7 | 581 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 582 | * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag |
<> | 144:ef7eb2e8f9f7 | 583 | * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag |
<> | 144:ef7eb2e8f9f7 | 584 | * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag |
<> | 144:ef7eb2e8f9f7 | 585 | * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag |
<> | 144:ef7eb2e8f9f7 | 586 | * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag |
<> | 144:ef7eb2e8f9f7 | 587 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 588 | */ |
<> | 144:ef7eb2e8f9f7 | 589 | #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) |
<> | 144:ef7eb2e8f9f7 | 590 | |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | /** @brief Set a specific IRDA request flag. |
<> | 144:ef7eb2e8f9f7 | 593 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 594 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 595 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 596 | * @param __REQ__: specifies the request flag to set |
<> | 144:ef7eb2e8f9f7 | 597 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 598 | * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request |
<> | 144:ef7eb2e8f9f7 | 599 | * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request |
<> | 144:ef7eb2e8f9f7 | 600 | * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request |
<> | 144:ef7eb2e8f9f7 | 601 | * |
<> | 144:ef7eb2e8f9f7 | 602 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 603 | */ |
<> | 144:ef7eb2e8f9f7 | 604 | #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) |
<> | 144:ef7eb2e8f9f7 | 605 | |
<> | 144:ef7eb2e8f9f7 | 606 | /** @brief Enable the IRDA one bit sample method. |
<> | 144:ef7eb2e8f9f7 | 607 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 608 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 609 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 610 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 611 | */ |
<> | 144:ef7eb2e8f9f7 | 612 | #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) |
<> | 144:ef7eb2e8f9f7 | 613 | |
<> | 144:ef7eb2e8f9f7 | 614 | /** @brief Disable the IRDA one bit sample method. |
<> | 144:ef7eb2e8f9f7 | 615 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 616 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 617 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 618 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 619 | */ |
<> | 144:ef7eb2e8f9f7 | 620 | #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | /** @brief Enable UART/USART associated to IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 623 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 624 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 625 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 626 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 627 | */ |
<> | 144:ef7eb2e8f9f7 | 628 | #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | /** @brief Disable UART/USART associated to IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 631 | * @param __HANDLE__: specifies the IRDA Handle. |
<> | 144:ef7eb2e8f9f7 | 632 | * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or |
<> | 144:ef7eb2e8f9f7 | 633 | * UART peripheral |
<> | 144:ef7eb2e8f9f7 | 634 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 635 | */ |
<> | 144:ef7eb2e8f9f7 | 636 | #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
<> | 144:ef7eb2e8f9f7 | 637 | |
<> | 144:ef7eb2e8f9f7 | 638 | /** |
<> | 144:ef7eb2e8f9f7 | 639 | * @} |
<> | 144:ef7eb2e8f9f7 | 640 | */ |
<> | 144:ef7eb2e8f9f7 | 641 | |
<> | 144:ef7eb2e8f9f7 | 642 | /* Private macros --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 643 | /** @defgroup IRDA_Private_Macros IRDA Private Macros |
<> | 144:ef7eb2e8f9f7 | 644 | * @{ |
<> | 144:ef7eb2e8f9f7 | 645 | */ |
<> | 144:ef7eb2e8f9f7 | 646 | |
<> | 144:ef7eb2e8f9f7 | 647 | /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. |
<> | 144:ef7eb2e8f9f7 | 648 | * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. |
<> | 144:ef7eb2e8f9f7 | 649 | * @retval True or False |
<> | 144:ef7eb2e8f9f7 | 650 | */ |
<> | 144:ef7eb2e8f9f7 | 651 | #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) |
<> | 144:ef7eb2e8f9f7 | 652 | |
<> | 144:ef7eb2e8f9f7 | 653 | /** @brief Ensure that IRDA prescaler value is strictly larger than 0. |
<> | 144:ef7eb2e8f9f7 | 654 | * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. |
<> | 144:ef7eb2e8f9f7 | 655 | * @retval True or False |
<> | 144:ef7eb2e8f9f7 | 656 | */ |
<> | 144:ef7eb2e8f9f7 | 657 | #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) |
<> | 144:ef7eb2e8f9f7 | 658 | |
<> | 144:ef7eb2e8f9f7 | 659 | /** |
<> | 144:ef7eb2e8f9f7 | 660 | * @brief Ensure that IRDA frame parity is valid. |
<> | 144:ef7eb2e8f9f7 | 661 | * @param __PARITY__: IRDA frame parity. |
<> | 144:ef7eb2e8f9f7 | 662 | * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 663 | */ |
<> | 144:ef7eb2e8f9f7 | 664 | #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ |
<> | 144:ef7eb2e8f9f7 | 665 | ((__PARITY__) == IRDA_PARITY_EVEN) || \ |
<> | 144:ef7eb2e8f9f7 | 666 | ((__PARITY__) == IRDA_PARITY_ODD)) |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | /** |
<> | 144:ef7eb2e8f9f7 | 669 | * @brief Ensure that IRDA communication mode is valid. |
<> | 144:ef7eb2e8f9f7 | 670 | * @param __MODE__: IRDA communication mode. |
<> | 144:ef7eb2e8f9f7 | 671 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 672 | */ |
<> | 144:ef7eb2e8f9f7 | 673 | #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) |
<> | 144:ef7eb2e8f9f7 | 674 | |
<> | 144:ef7eb2e8f9f7 | 675 | /** |
<> | 144:ef7eb2e8f9f7 | 676 | * @brief Ensure that IRDA power mode is valid. |
<> | 144:ef7eb2e8f9f7 | 677 | * @param __MODE__: IRDA power mode. |
<> | 144:ef7eb2e8f9f7 | 678 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 679 | */ |
<> | 144:ef7eb2e8f9f7 | 680 | #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ |
<> | 144:ef7eb2e8f9f7 | 681 | ((__MODE__) == IRDA_POWERMODE_NORMAL)) |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | /** |
<> | 144:ef7eb2e8f9f7 | 684 | * @brief Ensure that IRDA state is valid. |
<> | 144:ef7eb2e8f9f7 | 685 | * @param __STATE__: IRDA state mode. |
<> | 144:ef7eb2e8f9f7 | 686 | * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 687 | */ |
<> | 144:ef7eb2e8f9f7 | 688 | #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 689 | ((__STATE__) == IRDA_STATE_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 690 | |
<> | 144:ef7eb2e8f9f7 | 691 | /** |
<> | 144:ef7eb2e8f9f7 | 692 | * @brief Ensure that IRDA associated UART/USART mode is valid. |
<> | 144:ef7eb2e8f9f7 | 693 | * @param __MODE__: IRDA associated UART/USART mode. |
<> | 144:ef7eb2e8f9f7 | 694 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 695 | */ |
<> | 144:ef7eb2e8f9f7 | 696 | #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 697 | ((__MODE__) == IRDA_MODE_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 698 | |
<> | 144:ef7eb2e8f9f7 | 699 | /** |
<> | 144:ef7eb2e8f9f7 | 700 | * @brief Ensure that IRDA sampling rate is valid. |
<> | 144:ef7eb2e8f9f7 | 701 | * @param __ONEBIT__: IRDA sampling rate. |
<> | 144:ef7eb2e8f9f7 | 702 | * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 703 | */ |
<> | 144:ef7eb2e8f9f7 | 704 | #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 705 | ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 706 | |
<> | 144:ef7eb2e8f9f7 | 707 | /** |
<> | 144:ef7eb2e8f9f7 | 708 | * @brief Ensure that IRDA DMA TX mode is valid. |
<> | 144:ef7eb2e8f9f7 | 709 | * @param __DMATX__: IRDA DMA TX mode. |
<> | 144:ef7eb2e8f9f7 | 710 | * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 711 | */ |
<> | 144:ef7eb2e8f9f7 | 712 | #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 713 | ((__DMATX__) == IRDA_DMA_TX_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 714 | |
<> | 144:ef7eb2e8f9f7 | 715 | /** |
<> | 144:ef7eb2e8f9f7 | 716 | * @brief Ensure that IRDA DMA RX mode is valid. |
<> | 144:ef7eb2e8f9f7 | 717 | * @param __DMARX__: IRDA DMA RX mode. |
<> | 144:ef7eb2e8f9f7 | 718 | * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 719 | */ |
<> | 144:ef7eb2e8f9f7 | 720 | #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 721 | ((__DMARX__) == IRDA_DMA_RX_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 722 | |
<> | 144:ef7eb2e8f9f7 | 723 | /** |
<> | 144:ef7eb2e8f9f7 | 724 | * @brief Ensure that IRDA request is valid. |
<> | 144:ef7eb2e8f9f7 | 725 | * @param __PARAM__: IRDA request. |
<> | 144:ef7eb2e8f9f7 | 726 | * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 727 | */ |
<> | 144:ef7eb2e8f9f7 | 728 | #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 729 | ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 730 | ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) |
<> | 144:ef7eb2e8f9f7 | 731 | /** |
<> | 144:ef7eb2e8f9f7 | 732 | * @} |
<> | 144:ef7eb2e8f9f7 | 733 | */ |
<> | 144:ef7eb2e8f9f7 | 734 | |
<> | 144:ef7eb2e8f9f7 | 735 | /* Include IRDA HAL Extended module */ |
<> | 144:ef7eb2e8f9f7 | 736 | #include "stm32f3xx_hal_irda_ex.h" |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 739 | /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions |
<> | 144:ef7eb2e8f9f7 | 740 | * @{ |
<> | 144:ef7eb2e8f9f7 | 741 | */ |
<> | 144:ef7eb2e8f9f7 | 742 | |
<> | 144:ef7eb2e8f9f7 | 743 | /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 744 | * @{ |
<> | 144:ef7eb2e8f9f7 | 745 | */ |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | /* Initialization and de-initialization functions ****************************/ |
<> | 144:ef7eb2e8f9f7 | 748 | HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 749 | HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 750 | void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 751 | void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | /** |
<> | 144:ef7eb2e8f9f7 | 754 | * @} |
<> | 144:ef7eb2e8f9f7 | 755 | */ |
<> | 144:ef7eb2e8f9f7 | 756 | |
<> | 144:ef7eb2e8f9f7 | 757 | /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 758 | * @{ |
<> | 144:ef7eb2e8f9f7 | 759 | */ |
<> | 144:ef7eb2e8f9f7 | 760 | |
<> | 144:ef7eb2e8f9f7 | 761 | /* IO operation functions *****************************************************/ |
<> | 144:ef7eb2e8f9f7 | 762 | HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 763 | HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 764 | HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 765 | HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 766 | HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 767 | HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 768 | HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 769 | HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 770 | HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 771 | void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 772 | void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 773 | void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 774 | void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 775 | void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 776 | void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 777 | |
<> | 144:ef7eb2e8f9f7 | 778 | /** |
<> | 144:ef7eb2e8f9f7 | 779 | * @} |
<> | 144:ef7eb2e8f9f7 | 780 | */ |
<> | 144:ef7eb2e8f9f7 | 781 | |
<> | 144:ef7eb2e8f9f7 | 782 | /* Peripheral Control functions ************************************************/ |
<> | 144:ef7eb2e8f9f7 | 783 | |
<> | 144:ef7eb2e8f9f7 | 784 | /** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions |
<> | 144:ef7eb2e8f9f7 | 785 | * @{ |
<> | 144:ef7eb2e8f9f7 | 786 | */ |
<> | 144:ef7eb2e8f9f7 | 787 | |
<> | 144:ef7eb2e8f9f7 | 788 | /* Peripheral State and Error functions ***************************************/ |
<> | 144:ef7eb2e8f9f7 | 789 | HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 790 | uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | /** |
<> | 144:ef7eb2e8f9f7 | 793 | * @} |
<> | 144:ef7eb2e8f9f7 | 794 | */ |
<> | 144:ef7eb2e8f9f7 | 795 | |
<> | 144:ef7eb2e8f9f7 | 796 | /** |
<> | 144:ef7eb2e8f9f7 | 797 | * @} |
<> | 144:ef7eb2e8f9f7 | 798 | */ |
<> | 144:ef7eb2e8f9f7 | 799 | |
<> | 144:ef7eb2e8f9f7 | 800 | /** |
<> | 144:ef7eb2e8f9f7 | 801 | * @} |
<> | 144:ef7eb2e8f9f7 | 802 | */ |
<> | 144:ef7eb2e8f9f7 | 803 | |
<> | 144:ef7eb2e8f9f7 | 804 | /** |
<> | 144:ef7eb2e8f9f7 | 805 | * @} |
<> | 144:ef7eb2e8f9f7 | 806 | */ |
<> | 144:ef7eb2e8f9f7 | 807 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 808 | } |
<> | 144:ef7eb2e8f9f7 | 809 | #endif |
<> | 144:ef7eb2e8f9f7 | 810 | |
<> | 144:ef7eb2e8f9f7 | 811 | #endif /* __STM32F3xx_HAL_IRDA_H */ |
<> | 144:ef7eb2e8f9f7 | 812 | |
<> | 144:ef7eb2e8f9f7 | 813 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |