pravin sarode / Mymbed-dev

MBED-DEV only fro Nucleo STM32F303K8T6

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c@151:acf04f8e7d03, 2016-11-19 (annotated)

Committer:
pravinautosys
Date:
Sat Nov 19 10:38:54 2016 +0000
Revision:
151:acf04f8e7d03
Parent:
149:156823d33999 
MyMBED-DEVWithSTM32F303K8T6;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2S HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The I2S HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
<> 144:ef7eb2e8f9f7 22 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 23 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 24 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 25 (+++) Configure these I2S pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 27 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 28 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 29 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 31 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 32 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 38 DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 41 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 44 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 46 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 47 (+@) I2S clock is configured based on SYSCLK or
<> 144:ef7eb2e8f9f7 48 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Three mode of operations are available within this driver :
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 54 =================================
<> 144:ef7eb2e8f9f7 55 [..]
<> 144:ef7eb2e8f9f7 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 60 ===================================
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 76 ==============================
<> 144:ef7eb2e8f9f7 77 [..]
<> 144:ef7eb2e8f9f7 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 =============================================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 Below the list of most used macros in I2S HAL driver.
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 [..]
<> 144:ef7eb2e8f9f7 106 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 @endverbatim
<> 144:ef7eb2e8f9f7 109 ******************************************************************************
<> 144:ef7eb2e8f9f7 110 * @attention
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 115 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 116 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 117 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 119 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 120 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 122 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 123 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 ******************************************************************************
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 145 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 146 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
<> 144:ef7eb2e8f9f7 147 defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 154 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 155 * @{
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 162 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 163 /** @defgroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 167 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 168 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 169 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 170 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 171 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 172 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 173 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 185 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 186 *
<> 144:ef7eb2e8f9f7 187 @verbatim
<> 144:ef7eb2e8f9f7 188 ===============================================================================
<> 144:ef7eb2e8f9f7 189 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 190 ===============================================================================
<> 144:ef7eb2e8f9f7 191 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 192 de-initialiaze the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 195 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 198 the selected configuration:
<> 144:ef7eb2e8f9f7 199 (++) Mode
<> 144:ef7eb2e8f9f7 200 (++) Standard
<> 144:ef7eb2e8f9f7 201 (++) Data Format
<> 144:ef7eb2e8f9f7 202 (++) MCLK Output
<> 144:ef7eb2e8f9f7 203 (++) Audio frequency
<> 144:ef7eb2e8f9f7 204 (++) Polarity
<> 144:ef7eb2e8f9f7 205 (++) Full duplex mode
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 208 of the selected I2Sx periperal.
<> 144:ef7eb2e8f9f7 209 @endverbatim
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 215 * in the I2S_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 216 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 217 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 218 * @retval HAL status
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 223 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /* Note : This function is defined into this file for library reference. */
<> 144:ef7eb2e8f9f7 226 /* Function content is located into file stm32f3xx_hal_i2s_ex.c to */
<> 144:ef7eb2e8f9f7 227 /* handle the possible I2S interfaces defined in STM32F3xx devices */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Return error status as not implemented here */
<> 144:ef7eb2e8f9f7 230 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief DeInitializes the I2S peripheral
<> 144:ef7eb2e8f9f7 235 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 236 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 237 * @retval HAL status
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 242 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Check the parameters */
<> 144:ef7eb2e8f9f7 248 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 253 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 256 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Release Lock */
<> 144:ef7eb2e8f9f7 259 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 return HAL_OK;
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief I2S MSP Init
<> 144:ef7eb2e8f9f7 266 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 267 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 268 * @retval None
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 273 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 276 the HAL_I2S_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @brief I2S MSP DeInit
<> 144:ef7eb2e8f9f7 282 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 283 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 284 * @retval None
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 289 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 292 the HAL_I2S_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 301 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 302 *
<> 144:ef7eb2e8f9f7 303 @verbatim
<> 144:ef7eb2e8f9f7 304 ===============================================================================
<> 144:ef7eb2e8f9f7 305 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 306 ===============================================================================
<> 144:ef7eb2e8f9f7 307 [..]
<> 144:ef7eb2e8f9f7 308 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 309 transfers.
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 312 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 313 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 314 after finishing transfer.
<> 144:ef7eb2e8f9f7 315 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 316 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 317 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 318 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 319 using DMA mode.
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 322 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 323 (++) HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 326 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 327 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 330 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 331 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 334 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 335 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 336 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 @endverbatim
<> 144:ef7eb2e8f9f7 339 * @{
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 344 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 345 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 346 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 347 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 348 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 349 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 350 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 351 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 352 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 353 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 354 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 355 * @retval HAL status
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 367 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 370 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372 else
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 375 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Process Locked */
<> 144:ef7eb2e8f9f7 379 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 382 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 385 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 388 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 while(hi2s->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 hi2s->Instance->DR = (*pData++);
<> 144:ef7eb2e8f9f7 394 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 395 /* Wait until TXE flag is set */
<> 144:ef7eb2e8f9f7 396 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 399 hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 400 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 401 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Check if an underrun occurs */
<> 144:ef7eb2e8f9f7 405 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 408 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 411 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 414 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 415 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 423 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 return HAL_OK;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427 else
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 435 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 436 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 437 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 438 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 439 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 440 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 441 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 442 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 443 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 444 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 445 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 446 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
<> 144:ef7eb2e8f9f7 447 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
<> 144:ef7eb2e8f9f7 448 * @retval HAL status
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 460 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 463 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465 else
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 468 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470 /* Process Locked */
<> 144:ef7eb2e8f9f7 471 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 474 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 477 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 480 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 484 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 487 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 488 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Receive data */
<> 144:ef7eb2e8f9f7 492 while(hi2s->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 495 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 498 hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 499 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 500 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Check if an overrun occurs */
<> 144:ef7eb2e8f9f7 504 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 507 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 510 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 513 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 514 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 (*pData++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 520 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 526 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 return HAL_OK;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 else
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 538 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 539 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 540 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 541 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 542 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 543 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 544 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 545 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 546 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 547 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 548 * @retval HAL status
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 560 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 561 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 564 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566 else
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 569 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Process Locked */
<> 144:ef7eb2e8f9f7 573 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 576 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 579 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 582 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 585 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 589 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 return HAL_OK;
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593 else
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 601 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 602 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 603 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 604 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 605 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 606 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 607 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 608 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 609 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 610 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 611 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
<> 144:ef7eb2e8f9f7 612 * between Master and Slave otherwise the I2S interrupt should be optimized.
<> 144:ef7eb2e8f9f7 613 * @retval HAL status
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 625 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 626 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 629 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631 else
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 634 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636 /* Process Locked */
<> 144:ef7eb2e8f9f7 637 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 640 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 643 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 646 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 649 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 653 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 return HAL_OK;
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657 else
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @brief Transmit an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 665 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 666 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 667 * @param pData: a 16-bit pointer to the Transmit data buffer.
<> 144:ef7eb2e8f9f7 668 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 669 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 670 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 671 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 672 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 673 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 674 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 675 * @retval HAL status
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 689 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 690 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 693 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695 else
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 698 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Process Locked */
<> 144:ef7eb2e8f9f7 702 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 705 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /* Set the I2S Tx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 708 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* Set the I2S Tx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 711 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 714 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 717 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 718 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 721 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 724 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 728 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 731 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 return HAL_OK;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 else
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /**
<> 144:ef7eb2e8f9f7 742 * @brief Receive an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 743 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 744 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 745 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 746 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 747 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 748 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 749 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 750 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 751 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 752 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 753 * @retval HAL status
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 765 {
<> 144:ef7eb2e8f9f7 766 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 767 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 768 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 771 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773 else
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 776 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 /* Process Locked */
<> 144:ef7eb2e8f9f7 779 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 782 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Set the I2S Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 785 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Set the I2S Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 788 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 791 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 794 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 797 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 798 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 802 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 803 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 806 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 809 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 813 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 816 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 return HAL_OK;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 else
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /**
<> 144:ef7eb2e8f9f7 827 * @brief Pauses the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 828 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 829 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 830 * @retval HAL status
<> 144:ef7eb2e8f9f7 831 */
<> 144:ef7eb2e8f9f7 832 __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 /* Process Locked */
<> 144:ef7eb2e8f9f7 835 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 840 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 845 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 849 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 return HAL_OK;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /**
<> 144:ef7eb2e8f9f7 855 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 856 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 857 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 858 * @retval HAL status
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860 __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 /* Process Locked */
<> 144:ef7eb2e8f9f7 863 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 868 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 871 {
<> 144:ef7eb2e8f9f7 872 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 873 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* If the I2S peripheral is still not enabled, enable it */
<> 144:ef7eb2e8f9f7 877 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 880 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 884 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 return HAL_OK;
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /**
<> 144:ef7eb2e8f9f7 890 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 891 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 892 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 893 * @retval HAL status
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895 __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 /* Process Locked */
<> 144:ef7eb2e8f9f7 898 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /* Disable the I2S Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 901 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 902 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Abort the I2S DMA tx channel */
<> 144:ef7eb2e8f9f7 905 if(hi2s->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 908 __HAL_DMA_DISABLE(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 909 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911 /* Abort the I2S DMA rx channel */
<> 144:ef7eb2e8f9f7 912 if(hi2s->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 915 __HAL_DMA_DISABLE(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 916 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 920 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 925 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 return HAL_OK;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /**
<> 144:ef7eb2e8f9f7 931 * @brief This function handles I2S interrupt request.
<> 144:ef7eb2e8f9f7 932 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 933 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 934 * @retval None
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 __IO uint32_t i2ssr = hi2s->Instance->SR;
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 /* I2S in mode Receiver ----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 943 if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 I2S_Receive_IT(hi2s);
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* I2S Overrun error interrupt occured -------------------------------------*/
<> 144:ef7eb2e8f9f7 949 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 950 {
<> 144:ef7eb2e8f9f7 951 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 952 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 955 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 958 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 959 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 960 }
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 963 {
<> 144:ef7eb2e8f9f7 964 /* I2S in mode Tramitter ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 965 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 I2S_Transmit_IT(hi2s);
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /* I2S Underrun error interrupt occured ------------------------------------*/
<> 144:ef7eb2e8f9f7 971 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 974 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 977 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 980 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 981 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 982 }
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 }
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /**
<> 144:ef7eb2e8f9f7 987 * @}
<> 144:ef7eb2e8f9f7 988 */
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /**
<> 144:ef7eb2e8f9f7 991 * @}
<> 144:ef7eb2e8f9f7 992 */
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 997 * @{
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 1001 * @{
<> 144:ef7eb2e8f9f7 1002 */
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Tx Transfer Half completed callbacks
<> 144:ef7eb2e8f9f7 1005 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1006 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1007 * @retval None
<> 144:ef7eb2e8f9f7 1008 */
<> 144:ef7eb2e8f9f7 1009 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1012 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1015 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /**
<> 144:ef7eb2e8f9f7 1020 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1021 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1022 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1023 * @retval None
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1028 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1031 the HAL_I2S_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @brief Rx Transfer half completed callbacks
<> 144:ef7eb2e8f9f7 1037 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1038 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1039 * @retval None
<> 144:ef7eb2e8f9f7 1040 */
<> 144:ef7eb2e8f9f7 1041 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1044 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1047 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /**
<> 144:ef7eb2e8f9f7 1052 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1053 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1054 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1055 * @retval None
<> 144:ef7eb2e8f9f7 1056 */
<> 144:ef7eb2e8f9f7 1057 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1058 {
<> 144:ef7eb2e8f9f7 1059 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1060 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1063 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1064 */
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /**
<> 144:ef7eb2e8f9f7 1068 * @brief I2S error callbacks
<> 144:ef7eb2e8f9f7 1069 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1070 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1071 * @retval None
<> 144:ef7eb2e8f9f7 1072 */
<> 144:ef7eb2e8f9f7 1073 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1076 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1079 the HAL_I2S_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1080 */
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /**
<> 144:ef7eb2e8f9f7 1084 * @}
<> 144:ef7eb2e8f9f7 1085 */
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1088 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1089 *
<> 144:ef7eb2e8f9f7 1090 @verbatim
<> 144:ef7eb2e8f9f7 1091 ===============================================================================
<> 144:ef7eb2e8f9f7 1092 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1093 ===============================================================================
<> 144:ef7eb2e8f9f7 1094 [..]
<> 144:ef7eb2e8f9f7 1095 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1096 and the data flow.
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 @endverbatim
<> 144:ef7eb2e8f9f7 1099 * @{
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /**
<> 144:ef7eb2e8f9f7 1103 * @brief Return the I2S state
<> 144:ef7eb2e8f9f7 1104 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1105 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1106 * @retval HAL state
<> 144:ef7eb2e8f9f7 1107 */
<> 144:ef7eb2e8f9f7 1108 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 return hi2s->State;
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @brief Return the I2S error code
<> 144:ef7eb2e8f9f7 1115 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1116 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1117 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1118 */
<> 144:ef7eb2e8f9f7 1119 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1120 {
<> 144:ef7eb2e8f9f7 1121 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 /**
<> 144:ef7eb2e8f9f7 1124 * @}
<> 144:ef7eb2e8f9f7 1125 */
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /**
<> 144:ef7eb2e8f9f7 1128 * @}
<> 144:ef7eb2e8f9f7 1129 */
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 1132 * @{
<> 144:ef7eb2e8f9f7 1133 */
<> 144:ef7eb2e8f9f7 1134 /**
<> 144:ef7eb2e8f9f7 1135 * @brief DMA I2S transmit process complete callback
<> 144:ef7eb2e8f9f7 1136 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1137 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1138 * @retval None
<> 144:ef7eb2e8f9f7 1139 */
<> 144:ef7eb2e8f9f7 1140 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1147 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1150 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1151 }
<> 144:ef7eb2e8f9f7 1152 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /**
<> 144:ef7eb2e8f9f7 1156 * @brief DMA I2S transmit process half complete callback
<> 144:ef7eb2e8f9f7 1157 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1158 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1159 * @retval None
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1166 }
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /**
<> 144:ef7eb2e8f9f7 1169 * @brief DMA I2S receive process complete callback
<> 144:ef7eb2e8f9f7 1170 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1171 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1172 * @retval None
<> 144:ef7eb2e8f9f7 1173 */
<> 144:ef7eb2e8f9f7 1174 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1175 {
<> 144:ef7eb2e8f9f7 1176 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1181 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1182 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1183 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /**
<> 144:ef7eb2e8f9f7 1189 * @brief DMA I2S receive process half complete callback
<> 144:ef7eb2e8f9f7 1190 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1191 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1192 * @retval None
<> 144:ef7eb2e8f9f7 1193 */
<> 144:ef7eb2e8f9f7 1194 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /**
<> 144:ef7eb2e8f9f7 1202 * @brief DMA I2S communication error callback
<> 144:ef7eb2e8f9f7 1203 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1204 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1205 * @retval None
<> 144:ef7eb2e8f9f7 1206 */
<> 144:ef7eb2e8f9f7 1207 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1208 {
<> 144:ef7eb2e8f9f7 1209 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Disable Rx and Tx DMA Request */
<> 144:ef7eb2e8f9f7 1212 hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
<> 144:ef7eb2e8f9f7 1213 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1214 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1219 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1220 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1221 }
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /**
<> 144:ef7eb2e8f9f7 1224 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1225 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1226 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1227 * @retval None
<> 144:ef7eb2e8f9f7 1228 */
<> 144:ef7eb2e8f9f7 1229 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 /* Transmit data */
<> 144:ef7eb2e8f9f7 1232 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1233 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 if(hi2s->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1236 {
<> 144:ef7eb2e8f9f7 1237 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1238 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1241 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /**
<> 144:ef7eb2e8f9f7 1246 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1247 * @param hi2s: I2S handle
<> 144:ef7eb2e8f9f7 1248 * @retval None
<> 144:ef7eb2e8f9f7 1249 */
<> 144:ef7eb2e8f9f7 1250 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 /* Receive data */
<> 144:ef7eb2e8f9f7 1253 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1254 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 if(hi2s->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 1257 {
<> 144:ef7eb2e8f9f7 1258 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1259 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1262 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /**
<> 144:ef7eb2e8f9f7 1267 * @brief This function handles I2S Communication Timeout.
<> 144:ef7eb2e8f9f7 1268 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1269 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1270 * @param Flag: Flag checked
<> 144:ef7eb2e8f9f7 1271 * @param State: Value of the flag expected
<> 144:ef7eb2e8f9f7 1272 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 1273 * @retval HAL status
<> 144:ef7eb2e8f9f7 1274 */
<> 144:ef7eb2e8f9f7 1275 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1276 {
<> 144:ef7eb2e8f9f7 1277 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1280 if(State == RESET)
<> 144:ef7eb2e8f9f7 1281 {
<> 144:ef7eb2e8f9f7 1282 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1283 {
<> 144:ef7eb2e8f9f7 1284 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1285 {
<> 144:ef7eb2e8f9f7 1286 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1289 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1292 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299 else
<> 144:ef7eb2e8f9f7 1300 {
<> 144:ef7eb2e8f9f7 1301 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1302 {
<> 144:ef7eb2e8f9f7 1303 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1306 {
<> 144:ef7eb2e8f9f7 1307 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1308 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1311 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1314 }
<> 144:ef7eb2e8f9f7 1315 }
<> 144:ef7eb2e8f9f7 1316 }
<> 144:ef7eb2e8f9f7 1317 }
<> 144:ef7eb2e8f9f7 1318 return HAL_OK;
<> 144:ef7eb2e8f9f7 1319 }
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /**
<> 144:ef7eb2e8f9f7 1322 * @}
<> 144:ef7eb2e8f9f7 1323 */
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /**
<> 144:ef7eb2e8f9f7 1326 * @}
<> 144:ef7eb2e8f9f7 1327 */
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 /**
<> 144:ef7eb2e8f9f7 1330 * @}
<> 144:ef7eb2e8f9f7 1331 */
<> 144:ef7eb2e8f9f7 1332 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1333 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1334 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 1335 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/