Mymbed-dev - MBED-DEV only fro Nucleo STM32F303K8T6

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MBED-DEV only fro Nucleo STM32F303K8T6

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.h@151:acf04f8e7d03, 2016-11-19 (annotated)

Committer:: pravinautosys
Date:: Sat Nov 19 10:38:54 2016 +0000
Revision:: 151:acf04f8e7d03
Parent:: 149:156823d33999

MyMBED-DEVWithSTM32F303K8T6;

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User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_hrtim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.3.0
<>	144:ef7eb2e8f9f7	6	* @date 01-July-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of HRTIM HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F3xx_HAL_HRTIM_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F3xx_HAL_HRTIM_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	49	#include "stm32f3xx_hal_def.h"
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	52	* @{
<>	144:ef7eb2e8f9f7	53	*/
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/** @addtogroup HRTIM HRTIM
<>	144:ef7eb2e8f9f7	56	* @{
<>	144:ef7eb2e8f9f7	57	*/
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	60	/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
<>	144:ef7eb2e8f9f7	61	* @{
<>	144:ef7eb2e8f9f7	62	*/
<>	144:ef7eb2e8f9f7	63	/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
<>	144:ef7eb2e8f9f7	64	* @{
<>	144:ef7eb2e8f9f7	65	*/
<>	144:ef7eb2e8f9f7	66	#define MAX_HRTIM_TIMER 6
<>	144:ef7eb2e8f9f7	67	/**
<>	144:ef7eb2e8f9f7	68	* @}
<>	144:ef7eb2e8f9f7	69	*/
<>	144:ef7eb2e8f9f7	70	/**
<>	144:ef7eb2e8f9f7	71	* @}
<>	144:ef7eb2e8f9f7	72	*/
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
<>	144:ef7eb2e8f9f7	75	* @{
<>	144:ef7eb2e8f9f7	76	*/
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	/**
<>	144:ef7eb2e8f9f7	79	* @brief HRTIM Configuration Structure definition - Time base related parameters
<>	144:ef7eb2e8f9f7	80	*/
<>	144:ef7eb2e8f9f7	81	typedef struct
<>	144:ef7eb2e8f9f7	82	{
<>	144:ef7eb2e8f9f7	83	uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
<>	144:ef7eb2e8f9f7	84	This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
<>	144:ef7eb2e8f9f7	85	uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
<>	144:ef7eb2e8f9f7	86	The HRTIM instance can be configured to act as a slave (waiting for a trigger
<>	144:ef7eb2e8f9f7	87	to be synchronized) or a master (generating a synchronization signal) or both.
<>	144:ef7eb2e8f9f7	88	This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
<>	144:ef7eb2e8f9f7	89	uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
<>	144:ef7eb2e8f9f7	90	the HRTIM instance is configured as a slave).
<>	144:ef7eb2e8f9f7	91	This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
<>	144:ef7eb2e8f9f7	92	uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
<>	144:ef7eb2e8f9f7	93	(significant only when the HRTIM instance is configured as a master).
<>	144:ef7eb2e8f9f7	94	This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
<>	144:ef7eb2e8f9f7	95	uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
<>	144:ef7eb2e8f9f7	96	outputs (significant only when the HRTIM instance is configured as a master).
<>	144:ef7eb2e8f9f7	97	This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
<>	144:ef7eb2e8f9f7	98	} HRTIM_InitTypeDef;
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	/**
<>	144:ef7eb2e8f9f7	101	* @brief HAL State structures definition
<>	144:ef7eb2e8f9f7	102	*/
<>	144:ef7eb2e8f9f7	103	typedef enum
<>	144:ef7eb2e8f9f7	104	{
<>	144:ef7eb2e8f9f7	105	HAL_HRTIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
<>	144:ef7eb2e8f9f7	106	HAL_HRTIM_STATE_BUSY = 0x02, /!< an internal process is ongoing /
<>	144:ef7eb2e8f9f7	107	HAL_HRTIM_STATE_TIMEOUT = 0x06, /!< Timeout state /
<>	144:ef7eb2e8f9f7	108	HAL_HRTIM_STATE_ERROR = 0x07, /!< Error state /
<>	144:ef7eb2e8f9f7	109	} HAL_HRTIM_StateTypeDef;
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	/**
<>	144:ef7eb2e8f9f7	112	* @brief HRTIM Timer Structure definition
<>	144:ef7eb2e8f9f7	113	*/
<>	144:ef7eb2e8f9f7	114	typedef struct
<>	144:ef7eb2e8f9f7	115	{
<>	144:ef7eb2e8f9f7	116	uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
<>	144:ef7eb2e8f9f7	117	When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
<>	144:ef7eb2e8f9f7	118	When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
<>	144:ef7eb2e8f9f7	119	uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
<>	144:ef7eb2e8f9f7	120	When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
<>	144:ef7eb2e8f9f7	121	When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
<>	144:ef7eb2e8f9f7	122	uint32_t InterruptRequests; /!< Interrupts requests enabled for the timer. /
<>	144:ef7eb2e8f9f7	123	uint32_t DMARequests; /!< DMA requests enabled for the timer. /
<>	144:ef7eb2e8f9f7	124	uint32_t DMASrcAddress; /!< Address of the source address of the DMA transfer. /
<>	144:ef7eb2e8f9f7	125	uint32_t DMADstAddress; /!< Address of the destination address of the DMA transfer. /
<>	144:ef7eb2e8f9f7	126	uint32_t DMASize; /!< Size of the DMA transfer /
<>	144:ef7eb2e8f9f7	127	} HRTIM_TimerParamTypeDef;
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/**
<>	144:ef7eb2e8f9f7	130	* @brief HRTIM Handle Structure definition
<>	144:ef7eb2e8f9f7	131	*/
<>	144:ef7eb2e8f9f7	132	typedef struct __HRTIM_HandleTypeDef
<>	144:ef7eb2e8f9f7	133	{
<>	144:ef7eb2e8f9f7	134	HRTIM_TypeDef * Instance; /!< Register base address /
<>	144:ef7eb2e8f9f7	135
<>	144:ef7eb2e8f9f7	136	HRTIM_InitTypeDef Init; /!< HRTIM required parameters /
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /!< HRTIM timers - including the master - parameters /
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	__IO HAL_HRTIM_StateTypeDef State; /!< HRTIM communication state /
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	DMA_HandleTypeDef * hdmaMaster; /!< Master timer DMA handle parameters /
<>	144:ef7eb2e8f9f7	145	DMA_HandleTypeDef * hdmaTimerA; /!< Timer A DMA handle parameters /
<>	144:ef7eb2e8f9f7	146	DMA_HandleTypeDef * hdmaTimerB; /!< Timer B DMA handle parameters /
<>	144:ef7eb2e8f9f7	147	DMA_HandleTypeDef * hdmaTimerC; /!< Timer C DMA handle parameters /
<>	144:ef7eb2e8f9f7	148	DMA_HandleTypeDef * hdmaTimerD; /!< Timer D DMA handle parameters /
<>	144:ef7eb2e8f9f7	149	DMA_HandleTypeDef * hdmaTimerE; /!< Timer E DMA handle parameters /
<>	144:ef7eb2e8f9f7	150	} HRTIM_HandleTypeDef;
<>	144:ef7eb2e8f9f7	151
<>	144:ef7eb2e8f9f7	152	/**
<>	144:ef7eb2e8f9f7	153	* @brief Simple output compare mode configuration definition
<>	144:ef7eb2e8f9f7	154	*/
<>	144:ef7eb2e8f9f7	155	typedef struct {
<>	144:ef7eb2e8f9f7	156	uint32_t Period; /*!< Specifies the timer period.
<>	144:ef7eb2e8f9f7	157	The period value must be above 3 periods of the fHRTIM clock.
<>	144:ef7eb2e8f9f7	158	Maximum value is = 0xFFDF */
<>	144:ef7eb2e8f9f7	159	uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
<>	144:ef7eb2e8f9f7	160	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
<>	144:ef7eb2e8f9f7	161	uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
<>	144:ef7eb2e8f9f7	162	This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
<>	144:ef7eb2e8f9f7	163	uint32_t Mode; /*!< Specifies the counter operating mode.
<>	144:ef7eb2e8f9f7	164	This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
<>	144:ef7eb2e8f9f7	165	} HRTIM_TimeBaseCfgTypeDef;
<>	144:ef7eb2e8f9f7	166
<>	144:ef7eb2e8f9f7	167	/**
<>	144:ef7eb2e8f9f7	168	* @brief Simple output compare mode configuration definition
<>	144:ef7eb2e8f9f7	169	*/
<>	144:ef7eb2e8f9f7	170	typedef struct {
<>	144:ef7eb2e8f9f7	171	uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
<>	144:ef7eb2e8f9f7	172	This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
<>	144:ef7eb2e8f9f7	173	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
<>	144:ef7eb2e8f9f7	174	The compare value must be above or equal to 3 periods of the fHRTIM clock */
<>	144:ef7eb2e8f9f7	175	uint32_t Polarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	176	This parameter can be any value of @ref HRTIM_Output_Polarity */
<>	144:ef7eb2e8f9f7	177	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
<>	144:ef7eb2e8f9f7	178	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
<>	144:ef7eb2e8f9f7	179	} HRTIM_SimpleOCChannelCfgTypeDef;
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	/**
<>	144:ef7eb2e8f9f7	182	* @brief Simple PWM output mode configuration definition
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184	typedef struct {
<>	144:ef7eb2e8f9f7	185	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
<>	144:ef7eb2e8f9f7	186	The compare value must be above or equal to 3 periods of the fHRTIM clock */
<>	144:ef7eb2e8f9f7	187	uint32_t Polarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	188	This parameter can be any value of @ref HRTIM_Output_Polarity */
<>	144:ef7eb2e8f9f7	189	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
<>	144:ef7eb2e8f9f7	190	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
<>	144:ef7eb2e8f9f7	191	} HRTIM_SimplePWMChannelCfgTypeDef;
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	/**
<>	144:ef7eb2e8f9f7	194	* @brief Simple capture mode configuration definition
<>	144:ef7eb2e8f9f7	195	*/
<>	144:ef7eb2e8f9f7	196	typedef struct {
<>	144:ef7eb2e8f9f7	197	uint32_t Event; /*!< Specifies the external event triggering the capture.
<>	144:ef7eb2e8f9f7	198	This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
<>	144:ef7eb2e8f9f7	199	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
<>	144:ef7eb2e8f9f7	200	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
<>	144:ef7eb2e8f9f7	201	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
<>	144:ef7eb2e8f9f7	202	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
<>	144:ef7eb2e8f9f7	203	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
<>	144:ef7eb2e8f9f7	204	This parameter can be a value of @ref HRTIM_External_Event_Filter */
<>	144:ef7eb2e8f9f7	205	} HRTIM_SimpleCaptureChannelCfgTypeDef;
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/**
<>	144:ef7eb2e8f9f7	208	* @brief Simple One Pulse mode configuration definition
<>	144:ef7eb2e8f9f7	209	*/
<>	144:ef7eb2e8f9f7	210	typedef struct {
<>	144:ef7eb2e8f9f7	211	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
<>	144:ef7eb2e8f9f7	212	The compare value must be above or equal to 3 periods of the fHRTIM clock */
<>	144:ef7eb2e8f9f7	213	uint32_t OutputPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	214	This parameter can be any value of @ref HRTIM_Output_Polarity */
<>	144:ef7eb2e8f9f7	215	uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
<>	144:ef7eb2e8f9f7	216	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
<>	144:ef7eb2e8f9f7	217	uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
<>	144:ef7eb2e8f9f7	218	This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
<>	144:ef7eb2e8f9f7	219	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
<>	144:ef7eb2e8f9f7	220	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
<>	144:ef7eb2e8f9f7	221	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
<>	144:ef7eb2e8f9f7	222	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
<>	144:ef7eb2e8f9f7	223	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
<>	144:ef7eb2e8f9f7	224	This parameter can be a value of @ref HRTIM_External_Event_Filter */
<>	144:ef7eb2e8f9f7	225	} HRTIM_SimpleOnePulseChannelCfgTypeDef;
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/**
<>	144:ef7eb2e8f9f7	228	* @brief Timer configuration definition
<>	144:ef7eb2e8f9f7	229	*/
<>	144:ef7eb2e8f9f7	230	typedef struct {
<>	144:ef7eb2e8f9f7	231	uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	232	Specifies which interrupts requests must enabled for the timer.
<>	144:ef7eb2e8f9f7	233	This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
<>	144:ef7eb2e8f9f7	234	or @ref HRTIM_Timing_Unit_Interrupt_Enable */
<>	144:ef7eb2e8f9f7	235	uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	236	Specifies which DMA requests must be enabled for the timer.
<>	144:ef7eb2e8f9f7	237	This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
<>	144:ef7eb2e8f9f7	238	or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
<>	144:ef7eb2e8f9f7	239	uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	240	Specifies the address of the source address of the DMA transfer */
<>	144:ef7eb2e8f9f7	241	uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	242	Specifies the address of the destination address of the DMA transfer */
<>	144:ef7eb2e8f9f7	243	uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	244	Specifies the size of the DMA transfer */
<>	144:ef7eb2e8f9f7	245	uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	246	Specifies whether or not hald mode is enabled
<>	144:ef7eb2e8f9f7	247	This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
<>	144:ef7eb2e8f9f7	248	uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	249	Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
<>	144:ef7eb2e8f9f7	250	This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
<>	144:ef7eb2e8f9f7	251	uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	252	Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
<>	144:ef7eb2e8f9f7	253	This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
<>	144:ef7eb2e8f9f7	254	uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	255	Indicates whether or not the a DAC synchronization event is generated.
<>	144:ef7eb2e8f9f7	256	This parameter can be any value of @ref HRTIM_DAC_Synchronization */
<>	144:ef7eb2e8f9f7	257	uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	258	Specifies whether or not register preload is enabled.
<>	144:ef7eb2e8f9f7	259	This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
<>	144:ef7eb2e8f9f7	260	uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	261	Specifies how the update occurs with respect to a burst DMA transaction or
<>	144:ef7eb2e8f9f7	262	update enable inputs (Slave timers only).
<>	144:ef7eb2e8f9f7	263	This parameter can be any value of @ref HRTIM_Update_Gating */
<>	144:ef7eb2e8f9f7	264	uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	265	Specifies how the timer behaves during a burst mode operation.
<>	144:ef7eb2e8f9f7	266	This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
<>	144:ef7eb2e8f9f7	267	uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
<>	144:ef7eb2e8f9f7	268	Specifies whether or not registers update is triggered by the repetition event.
<>	144:ef7eb2e8f9f7	269	This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
<>	144:ef7eb2e8f9f7	270	uint32_t PushPull; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	271	Specifies whether or not the push-pull mode is enabled.
<>	144:ef7eb2e8f9f7	272	This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
<>	144:ef7eb2e8f9f7	273	uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	274	Specifies which fault channels are enabled for the timer.
<>	144:ef7eb2e8f9f7	275	This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
<>	144:ef7eb2e8f9f7	276	uint32_t FaultLock; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	277	Specifies whether or not fault enabling status is write protected.
<>	144:ef7eb2e8f9f7	278	This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
<>	144:ef7eb2e8f9f7	279	uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	280	Specifies whether or not dead-time insertion is enabled for the timer.
<>	144:ef7eb2e8f9f7	281	This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
<>	144:ef7eb2e8f9f7	282	uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	283	Specifies the delayed protection mode.
<>	144:ef7eb2e8f9f7	284	This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
<>	144:ef7eb2e8f9f7	285	uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	286	Specifies source(s) triggering the timer registers update.
<>	144:ef7eb2e8f9f7	287	This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
<>	144:ef7eb2e8f9f7	288	uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	289	Specifies source(s) triggering the timer counter reset.
<>	144:ef7eb2e8f9f7	290	This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
<>	144:ef7eb2e8f9f7	291	uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E.
<>	144:ef7eb2e8f9f7	292	Specifies whether or not registers update is triggered when the timer counter is reset.
<>	144:ef7eb2e8f9f7	293	This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
<>	144:ef7eb2e8f9f7	294	} HRTIM_TimerCfgTypeDef;
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296	/**
<>	144:ef7eb2e8f9f7	297	* @brief Compare unit configuration definition
<>	144:ef7eb2e8f9f7	298	*/
<>	144:ef7eb2e8f9f7	299	typedef struct {
<>	144:ef7eb2e8f9f7	300	uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
<>	144:ef7eb2e8f9f7	301	The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
<>	144:ef7eb2e8f9f7	302	The maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
<>	144:ef7eb2e8f9f7	303	uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
<>	144:ef7eb2e8f9f7	304	This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
<>	144:ef7eb2e8f9f7	305	uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
<>	144:ef7eb2e8f9f7	306	CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
<>	144:ef7eb2e8f9f7	307	} HRTIM_CompareCfgTypeDef;
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	/**
<>	144:ef7eb2e8f9f7	310	* @brief Capture unit configuration definition
<>	144:ef7eb2e8f9f7	311	*/
<>	144:ef7eb2e8f9f7	312	typedef struct {
<>	144:ef7eb2e8f9f7	313	uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
<>	144:ef7eb2e8f9f7	314	This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
<>	144:ef7eb2e8f9f7	315	} HRTIM_CaptureCfgTypeDef;
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/**
<>	144:ef7eb2e8f9f7	318	* @brief Output configuration definition
<>	144:ef7eb2e8f9f7	319	*/
<>	144:ef7eb2e8f9f7	320	typedef struct {
<>	144:ef7eb2e8f9f7	321	uint32_t Polarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	322	This parameter can be any value of @ref HRTIM_Output_Polarity */
<>	144:ef7eb2e8f9f7	323	uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
<>	144:ef7eb2e8f9f7	324	This parameter can be a combination of @ref HRTIM_Output_Set_Source */
<>	144:ef7eb2e8f9f7	325	uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
<>	144:ef7eb2e8f9f7	326	This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
<>	144:ef7eb2e8f9f7	327	uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
<>	144:ef7eb2e8f9f7	328	This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
<>	144:ef7eb2e8f9f7	329	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
<>	144:ef7eb2e8f9f7	330	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
<>	144:ef7eb2e8f9f7	331	uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
<>	144:ef7eb2e8f9f7	332	This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
<>	144:ef7eb2e8f9f7	333	uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
<>	144:ef7eb2e8f9f7	334	This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
<>	144:ef7eb2e8f9f7	335	uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
<>	144:ef7eb2e8f9f7	336	This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
<>	144:ef7eb2e8f9f7	337	} HRTIM_OutputCfgTypeDef;
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/**
<>	144:ef7eb2e8f9f7	340	* @brief External event filtering in timing units configuration definition
<>	144:ef7eb2e8f9f7	341	*/
<>	144:ef7eb2e8f9f7	342	typedef struct {
<>	144:ef7eb2e8f9f7	343	uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
<>	144:ef7eb2e8f9f7	344	This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
<>	144:ef7eb2e8f9f7	345	uint32_t Latch; /*!< Specifies whether or not the signal is latched.
<>	144:ef7eb2e8f9f7	346	This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
<>	144:ef7eb2e8f9f7	347	} HRTIM_TimerEventFilteringCfgTypeDef;
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/**
<>	144:ef7eb2e8f9f7	350	* @brief Dead time feature configuration definition
<>	144:ef7eb2e8f9f7	351	*/
<>	144:ef7eb2e8f9f7	352	typedef struct {
<>	144:ef7eb2e8f9f7	353	uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler.
<>	144:ef7eb2e8f9f7	354	This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
<>	144:ef7eb2e8f9f7	355	uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge.
<>	144:ef7eb2e8f9f7	356	This parameter can be a number between 0x0 and 0x1FF */
<>	144:ef7eb2e8f9f7	357	uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
<>	144:ef7eb2e8f9f7	358	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
<>	144:ef7eb2e8f9f7	359	uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
<>	144:ef7eb2e8f9f7	360	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
<>	144:ef7eb2e8f9f7	361	uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected.
<>	144:ef7eb2e8f9f7	362	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
<>	144:ef7eb2e8f9f7	363	uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge.
<>	144:ef7eb2e8f9f7	364	This parameter can be a number between 0x0 and 0x1FF */
<>	144:ef7eb2e8f9f7	365	uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
<>	144:ef7eb2e8f9f7	366	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
<>	144:ef7eb2e8f9f7	367	uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
<>	144:ef7eb2e8f9f7	368	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
<>	144:ef7eb2e8f9f7	369	uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected.
<>	144:ef7eb2e8f9f7	370	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
<>	144:ef7eb2e8f9f7	371	} HRTIM_DeadTimeCfgTypeDef ;
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/**
<>	144:ef7eb2e8f9f7	374	* @brief Chopper mode configuration definition
<>	144:ef7eb2e8f9f7	375	*/
<>	144:ef7eb2e8f9f7	376	typedef struct {
<>	144:ef7eb2e8f9f7	377	uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
<>	144:ef7eb2e8f9f7	378	This parameter can be a value of @ref HRTIM_Chopper_Frequency */
<>	144:ef7eb2e8f9f7	379	uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
<>	144:ef7eb2e8f9f7	380	This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
<>	144:ef7eb2e8f9f7	381	uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
<>	144:ef7eb2e8f9f7	382	This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
<>	144:ef7eb2e8f9f7	383	} HRTIM_ChopperModeCfgTypeDef;
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @brief External event channel configuration definition
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388	typedef struct {
<>	144:ef7eb2e8f9f7	389	uint32_t Source; /*!< Identifies the source of the external event.
<>	144:ef7eb2e8f9f7	390	This parameter can be a value of @ref HRTIM_External_Event_Sources */
<>	144:ef7eb2e8f9f7	391	uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
<>	144:ef7eb2e8f9f7	392	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
<>	144:ef7eb2e8f9f7	393	uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
<>	144:ef7eb2e8f9f7	394	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
<>	144:ef7eb2e8f9f7	395	uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
<>	144:ef7eb2e8f9f7	396	This parameter can be a value of @ref HRTIM_External_Event_Filter */
<>	144:ef7eb2e8f9f7	397	uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
<>	144:ef7eb2e8f9f7	398	This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
<>	144:ef7eb2e8f9f7	399	} HRTIM_EventCfgTypeDef;
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/**
<>	144:ef7eb2e8f9f7	402	* @brief Fault channel configuration definition
<>	144:ef7eb2e8f9f7	403	*/
<>	144:ef7eb2e8f9f7	404	typedef struct {
<>	144:ef7eb2e8f9f7	405	uint32_t Source; /*!< Identifies the source of the fault.
<>	144:ef7eb2e8f9f7	406	This parameter can be a value of @ref HRTIM_Fault_Sources */
<>	144:ef7eb2e8f9f7	407	uint32_t Polarity; /*!< Specifies the polarity of the fault event.
<>	144:ef7eb2e8f9f7	408	This parameter can be a value of @ref HRTIM_Fault_Polarity */
<>	144:ef7eb2e8f9f7	409	uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
<>	144:ef7eb2e8f9f7	410	This parameter can be a value of @ref HRTIM_Fault_Filter */
<>	144:ef7eb2e8f9f7	411	uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
<>	144:ef7eb2e8f9f7	412	This parameter can be a value of @ref HRTIM_Fault_Lock */
<>	144:ef7eb2e8f9f7	413	} HRTIM_FaultCfgTypeDef;
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	/**
<>	144:ef7eb2e8f9f7	416	* @brief Burst mode configuration definition
<>	144:ef7eb2e8f9f7	417	*/
<>	144:ef7eb2e8f9f7	418	typedef struct {
<>	144:ef7eb2e8f9f7	419	uint32_t Mode; /*!< Specifies the burst mode operating mode.
<>	144:ef7eb2e8f9f7	420	This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
<>	144:ef7eb2e8f9f7	421	uint32_t ClockSource; /*!< Specifies the burst mode clock source.
<>	144:ef7eb2e8f9f7	422	This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
<>	144:ef7eb2e8f9f7	423	uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
<>	144:ef7eb2e8f9f7	424	This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
<>	144:ef7eb2e8f9f7	425	uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
<>	144:ef7eb2e8f9f7	426	This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
<>	144:ef7eb2e8f9f7	427	uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
<>	144:ef7eb2e8f9f7	428	This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
<>	144:ef7eb2e8f9f7	429	uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
<>	144:ef7eb2e8f9f7	430	This parameter can be a number between 0x0 and 0xFFFF */
<>	144:ef7eb2e8f9f7	431	uint32_t Period; /*!< Specifies burst mode repetition period.
<>	144:ef7eb2e8f9f7	432	This parameter can be a number between 0x1 and 0xFFFF */
<>	144:ef7eb2e8f9f7	433	} HRTIM_BurstModeCfgTypeDef;
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	/**
<>	144:ef7eb2e8f9f7	436	* @brief ADC trigger configuration definition
<>	144:ef7eb2e8f9f7	437	*/
<>	144:ef7eb2e8f9f7	438	typedef struct {
<>	144:ef7eb2e8f9f7	439	uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
<>	144:ef7eb2e8f9f7	440	This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
<>	144:ef7eb2e8f9f7	441	uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
<>	144:ef7eb2e8f9f7	442	This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
<>	144:ef7eb2e8f9f7	443	} HRTIM_ADCTriggerCfgTypeDef;
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	/**
<>	144:ef7eb2e8f9f7	446	* @}
<>	144:ef7eb2e8f9f7	447	*/
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	450	/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
<>	144:ef7eb2e8f9f7	451	* @{
<>	144:ef7eb2e8f9f7	452	*/
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
<>	144:ef7eb2e8f9f7	455	* @{
<>	144:ef7eb2e8f9f7	456	* @brief Constants defining the timer indexes
<>	144:ef7eb2e8f9f7	457	*/
<>	144:ef7eb2e8f9f7	458	#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /!< Index used to access timer A registers /
<>	144:ef7eb2e8f9f7	459	#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /!< Index used to access timer B registers /
<>	144:ef7eb2e8f9f7	460	#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /!< Index used to access timer C registers /
<>	144:ef7eb2e8f9f7	461	#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /!< Index used to access timer D registers /
<>	144:ef7eb2e8f9f7	462	#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /!< Index used to access timer E registers /
<>	144:ef7eb2e8f9f7	463	#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /!< Index used to access master registers /
<>	144:ef7eb2e8f9f7	464	#define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFF /!< Index used to access HRTIM common registers /
<>	144:ef7eb2e8f9f7	465	/**
<>	144:ef7eb2e8f9f7	466	* @}
<>	144:ef7eb2e8f9f7	467	*/
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
<>	144:ef7eb2e8f9f7	470	* @{
<>	144:ef7eb2e8f9f7	471	* @brief Constants defining timer identifiers
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473	#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /!< Master identifier/
<>	144:ef7eb2e8f9f7	474	#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /!< Timer A identifier /
<>	144:ef7eb2e8f9f7	475	#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /!< Timer B identifier /
<>	144:ef7eb2e8f9f7	476	#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /!< Timer C identifier /
<>	144:ef7eb2e8f9f7	477	#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /!< Timer D identifier /
<>	144:ef7eb2e8f9f7	478	#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /!< Timer E identifier /
<>	144:ef7eb2e8f9f7	479	/**
<>	144:ef7eb2e8f9f7	480	* @}
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
<>	144:ef7eb2e8f9f7	484	* @{
<>	144:ef7eb2e8f9f7	485	* @brief Constants defining compare unit identifiers
<>	144:ef7eb2e8f9f7	486	*/
<>	144:ef7eb2e8f9f7	487	#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /!< Compare unit 1 identifier /
<>	144:ef7eb2e8f9f7	488	#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /!< Compare unit 2 identifier /
<>	144:ef7eb2e8f9f7	489	#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /!< Compare unit 3 identifier /
<>	144:ef7eb2e8f9f7	490	#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /!< Compare unit 4 identifier /
<>	144:ef7eb2e8f9f7	491	/**
<>	144:ef7eb2e8f9f7	492	* @}
<>	144:ef7eb2e8f9f7	493	*/
<>	144:ef7eb2e8f9f7	494
<>	144:ef7eb2e8f9f7	495	/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
<>	144:ef7eb2e8f9f7	496	* @{
<>	144:ef7eb2e8f9f7	497	* @brief Constants defining capture unit identifiers
<>	144:ef7eb2e8f9f7	498	*/
<>	144:ef7eb2e8f9f7	499	#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /!< Capture unit 1 identifier /
<>	144:ef7eb2e8f9f7	500	#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /!< Capture unit 2 identifier /
<>	144:ef7eb2e8f9f7	501	/**
<>	144:ef7eb2e8f9f7	502	* @}
<>	144:ef7eb2e8f9f7	503	*/
<>	144:ef7eb2e8f9f7	504
<>	144:ef7eb2e8f9f7	505	/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
<>	144:ef7eb2e8f9f7	506	* @{
<>	144:ef7eb2e8f9f7	507	* @brief Constants defining timer output identifiers
<>	144:ef7eb2e8f9f7	508	*/
<>	144:ef7eb2e8f9f7	509	#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /!< Timer A - Output 1 identifier /
<>	144:ef7eb2e8f9f7	510	#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /!< Timer A - Output 2 identifier /
<>	144:ef7eb2e8f9f7	511	#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /!< Timer B - Output 1 identifier /
<>	144:ef7eb2e8f9f7	512	#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /!< Timer B - Output 2 identifier /
<>	144:ef7eb2e8f9f7	513	#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /!< Timer C - Output 1 identifier /
<>	144:ef7eb2e8f9f7	514	#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /!< Timer C - Output 2 identifier /
<>	144:ef7eb2e8f9f7	515	#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /!< Timer D - Output 1 identifier /
<>	144:ef7eb2e8f9f7	516	#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /!< Timer D - Output 2 identifier /
<>	144:ef7eb2e8f9f7	517	#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /!< Timer E - Output 1 identifier /
<>	144:ef7eb2e8f9f7	518	#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /!< Timer E - Output 2 identifier /
<>	144:ef7eb2e8f9f7	519	/**
<>	144:ef7eb2e8f9f7	520	* @}
<>	144:ef7eb2e8f9f7	521	*/
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
<>	144:ef7eb2e8f9f7	524	* @{
<>	144:ef7eb2e8f9f7	525	* @brief Constants defining ADC triggers identifiers
<>	144:ef7eb2e8f9f7	526	*/
<>	144:ef7eb2e8f9f7	527	#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /!< ADC trigger 1 identifier /
<>	144:ef7eb2e8f9f7	528	#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /!< ADC trigger 2 identifier /
<>	144:ef7eb2e8f9f7	529	#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /!< ADC trigger 3 identifier /
<>	144:ef7eb2e8f9f7	530	#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /!< ADC trigger 4 identifier /
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
<>	144:ef7eb2e8f9f7	533	(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) \|\| \
<>	144:ef7eb2e8f9f7	534	((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) \|\| \
<>	144:ef7eb2e8f9f7	535	((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) \|\| \
<>	144:ef7eb2e8f9f7	536	((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
<>	144:ef7eb2e8f9f7	537	/**
<>	144:ef7eb2e8f9f7	538	* @}
<>	144:ef7eb2e8f9f7	539	*/
<>	144:ef7eb2e8f9f7	540
<>	144:ef7eb2e8f9f7	541	/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
<>	144:ef7eb2e8f9f7	542	* @{
<>	144:ef7eb2e8f9f7	543	* @brief Constants defining external event channel identifiers
<>	144:ef7eb2e8f9f7	544	*/
<>	144:ef7eb2e8f9f7	545	#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /!< Undefined event channel /
<>	144:ef7eb2e8f9f7	546	#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /!< External event channel 1 identifier /
<>	144:ef7eb2e8f9f7	547	#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /!< External event channel 2 identifier /
<>	144:ef7eb2e8f9f7	548	#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /!< External event channel 3 identifier /
<>	144:ef7eb2e8f9f7	549	#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /!< External event channel 4 identifier /
<>	144:ef7eb2e8f9f7	550	#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /!< External event channel 5 identifier /
<>	144:ef7eb2e8f9f7	551	#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /!< External event channel 6 identifier /
<>	144:ef7eb2e8f9f7	552	#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /!< External event channel 7 identifier /
<>	144:ef7eb2e8f9f7	553	#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /!< External event channel 8 identifier /
<>	144:ef7eb2e8f9f7	554	#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /!< External event channel 9 identifier /
<>	144:ef7eb2e8f9f7	555	#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /!< External event channel 10 identifier /
<>	144:ef7eb2e8f9f7	556	/**
<>	144:ef7eb2e8f9f7	557	* @}
<>	144:ef7eb2e8f9f7	558	*/
<>	144:ef7eb2e8f9f7	559
<>	144:ef7eb2e8f9f7	560	/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
<>	144:ef7eb2e8f9f7	561	* @{
<>	144:ef7eb2e8f9f7	562	* @brief Constants defining fault channel identifiers
<>	144:ef7eb2e8f9f7	563	*/
<>	144:ef7eb2e8f9f7	564	#define HRTIM_FAULT_1 ((uint32_t)0x01) /!< Fault channel 1 identifier /
<>	144:ef7eb2e8f9f7	565	#define HRTIM_FAULT_2 ((uint32_t)0x02) /!< Fault channel 2 identifier /
<>	144:ef7eb2e8f9f7	566	#define HRTIM_FAULT_3 ((uint32_t)0x04) /!< Fault channel 3 identifier /
<>	144:ef7eb2e8f9f7	567	#define HRTIM_FAULT_4 ((uint32_t)0x08) /!< Fault channel 4 identifier /
<>	144:ef7eb2e8f9f7	568	#define HRTIM_FAULT_5 ((uint32_t)0x10) /!< Fault channel 5 identifier /
<>	144:ef7eb2e8f9f7	569	/**
<>	144:ef7eb2e8f9f7	570	* @}
<>	144:ef7eb2e8f9f7	571	*/
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
<>	144:ef7eb2e8f9f7	575	* @{
<>	144:ef7eb2e8f9f7	576	* @brief Constants defining timer high-resolution clock prescaler ratio.
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578	#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	579	#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	580	#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	581	#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	582	#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	583	#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	584	#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	585	#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) /
<>	144:ef7eb2e8f9f7	586	/**
<>	144:ef7eb2e8f9f7	587	* @}
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589
<>	144:ef7eb2e8f9f7	590	/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
<>	144:ef7eb2e8f9f7	591	* @{
<>	144:ef7eb2e8f9f7	592	* @brief Constants defining timer counter operating mode.
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594	#define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008) /!< The timer operates in continuous (free-running) mode /
<>	144:ef7eb2e8f9f7	595	#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /!< The timer operates in non retriggerable single-shot mode /
<>	144:ef7eb2e8f9f7	596	#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /!< The timer operates in retriggerable single-shot mode /
<>	144:ef7eb2e8f9f7	597	/**
<>	144:ef7eb2e8f9f7	598	* @}
<>	144:ef7eb2e8f9f7	599	*/
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
<>	144:ef7eb2e8f9f7	602	* @{
<>	144:ef7eb2e8f9f7	603	* @brief Constants defining half mode enabling status.
<>	144:ef7eb2e8f9f7	604	*/
<>	144:ef7eb2e8f9f7	605	#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /!< Half mode is disabled /
<>	144:ef7eb2e8f9f7	606	#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /!< Half mode is enabled /
<>	144:ef7eb2e8f9f7	607	/**
<>	144:ef7eb2e8f9f7	608	* @}
<>	144:ef7eb2e8f9f7	609	*/
<>	144:ef7eb2e8f9f7	610
<>	144:ef7eb2e8f9f7	611	/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
<>	144:ef7eb2e8f9f7	612	* @{
<>	144:ef7eb2e8f9f7	613	* @brief Constants defining the timer behavior following the synchronization event
<>	144:ef7eb2e8f9f7	614	*/
<>	144:ef7eb2e8f9f7	615	#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /!< Synchronization input event has effect on the timer /
<>	144:ef7eb2e8f9f7	616	#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /!< Synchronization input event starts the timer /
<>	144:ef7eb2e8f9f7	617	/**
<>	144:ef7eb2e8f9f7	618	* @}
<>	144:ef7eb2e8f9f7	619	*/
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
<>	144:ef7eb2e8f9f7	622	* @{
<>	144:ef7eb2e8f9f7	623	* @brief Constants defining the timer behavior following the synchronization event
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625	#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /!< Synchronization input event has effect on the timer /
<>	144:ef7eb2e8f9f7	626	#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /!< Synchronization input event resets the timer /
<>	144:ef7eb2e8f9f7	627	/**
<>	144:ef7eb2e8f9f7	628	* @}
<>	144:ef7eb2e8f9f7	629	*/
<>	144:ef7eb2e8f9f7	630
<>	144:ef7eb2e8f9f7	631	/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
<>	144:ef7eb2e8f9f7	632	* @{
<>	144:ef7eb2e8f9f7	633	* @brief Constants defining on which output the DAC synchronization event is sent
<>	144:ef7eb2e8f9f7	634	*/
<>	144:ef7eb2e8f9f7	635	#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /!< No DAC synchronization event generated /
<>	144:ef7eb2e8f9f7	636	#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /!< DAC synchronization event generated on DACTrigOut1 output upon timer update /
<>	144:ef7eb2e8f9f7	637	#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /!< DAC synchronization event generated on DACTrigOut2 output upon timer update /
<>	144:ef7eb2e8f9f7	638	#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 \| HRTIM_MCR_DACSYNC_0) /!< DAC update generated on DACTrigOut3 output upon timer update /
<>	144:ef7eb2e8f9f7	639	/**
<>	144:ef7eb2e8f9f7	640	* @}
<>	144:ef7eb2e8f9f7	641	*/
<>	144:ef7eb2e8f9f7	642
<>	144:ef7eb2e8f9f7	643	/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
<>	144:ef7eb2e8f9f7	644	* @{
<>	144:ef7eb2e8f9f7	645	* @brief Constants defining whether a write access into a preloadable
<>	144:ef7eb2e8f9f7	646	* register is done into the active or the preload register.
<>	144:ef7eb2e8f9f7	647	*/
<>	144:ef7eb2e8f9f7	648	#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /!< Preload disabled: the write access is directly done into the active register /
<>	144:ef7eb2e8f9f7	649	#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /!< Preload enabled: the write access is done into the preload register /
<>	144:ef7eb2e8f9f7	650	/**
<>	144:ef7eb2e8f9f7	651	* @}
<>	144:ef7eb2e8f9f7	652	*/
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
<>	144:ef7eb2e8f9f7	655	* @{
<>	144:ef7eb2e8f9f7	656	* @brief Constants defining how the update occurs relatively to the burst DMA
<>	144:ef7eb2e8f9f7	657	* transaction and the external update request on update enable inputs 1 to 3.
<>	144:ef7eb2e8f9f7	658	*/
<>	144:ef7eb2e8f9f7	659	#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /!< Update done independently from the DMA burst transfer completion /
<>	144:ef7eb2e8f9f7	660	#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /!< Update done when the DMA burst transfer is completed /
<>	144:ef7eb2e8f9f7	661	#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /!< Update done on timer roll-over following a DMA burst transfer completion/
<>	144:ef7eb2e8f9f7	662	#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 /
<>	144:ef7eb2e8f9f7	663	#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 /
<>	144:ef7eb2e8f9f7	664	#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 /
<>	144:ef7eb2e8f9f7	665	#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 /
<>	144:ef7eb2e8f9f7	666	#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 /
<>	144:ef7eb2e8f9f7	667	#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 /
<>	144:ef7eb2e8f9f7	668	/**
<>	144:ef7eb2e8f9f7	669	* @}
<>	144:ef7eb2e8f9f7	670	*/
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
<>	144:ef7eb2e8f9f7	673	* @{
<>	144:ef7eb2e8f9f7	674	* @brief Constants defining how the timer behaves during a burst
<>	144:ef7eb2e8f9f7	675	mode operation.
<>	144:ef7eb2e8f9f7	676	*/
<>	144:ef7eb2e8f9f7	677	#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /!< Timer counter clock is maintained and the timer operates normally /
<>	144:ef7eb2e8f9f7	678	#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /!< Timer counter clock is stopped and the counter is reset /
<>	144:ef7eb2e8f9f7	679	/**
<>	144:ef7eb2e8f9f7	680	* @}
<>	144:ef7eb2e8f9f7	681	*/
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
<>	144:ef7eb2e8f9f7	684	* @{
<>	144:ef7eb2e8f9f7	685	* @brief Constants defining whether registers are updated when the timer
<>	144:ef7eb2e8f9f7	686	* repetition period is completed (either due to roll-over or
<>	144:ef7eb2e8f9f7	687	* reset events)
<>	144:ef7eb2e8f9f7	688	*/
<>	144:ef7eb2e8f9f7	689	#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /!< Update on repetition disabled /
<>	144:ef7eb2e8f9f7	690	#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /!< Update on repetition enabled /
<>	144:ef7eb2e8f9f7	691	/**
<>	144:ef7eb2e8f9f7	692	* @}
<>	144:ef7eb2e8f9f7	693	*/
<>	144:ef7eb2e8f9f7	694
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
<>	144:ef7eb2e8f9f7	697	* @{
<>	144:ef7eb2e8f9f7	698	* @brief Constants defining whether or not the puhs-pull mode is enabled for
<>	144:ef7eb2e8f9f7	699	* a timer.
<>	144:ef7eb2e8f9f7	700	*/
<>	144:ef7eb2e8f9f7	701	#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /!< Push-Pull mode disabled /
<>	144:ef7eb2e8f9f7	702	#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /!< Push-Pull mode enabled /
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @}
<>	144:ef7eb2e8f9f7	705	*/
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
<>	144:ef7eb2e8f9f7	708	* @{
<>	144:ef7eb2e8f9f7	709	* @brief Constants defining whether a faut channel is enabled for a timer
<>	144:ef7eb2e8f9f7	710	*/
<>	144:ef7eb2e8f9f7	711	#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /!< No fault enabled /
<>	144:ef7eb2e8f9f7	712	#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /!< Fault 1 enabled /
<>	144:ef7eb2e8f9f7	713	#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /!< Fault 2 enabled /
<>	144:ef7eb2e8f9f7	714	#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /!< Fault 3 enabled /
<>	144:ef7eb2e8f9f7	715	#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /!< Fault 4 enabled /
<>	144:ef7eb2e8f9f7	716	#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /!< Fault 5 enabled /
<>	144:ef7eb2e8f9f7	717	/**
<>	144:ef7eb2e8f9f7	718	* @}
<>	144:ef7eb2e8f9f7	719	*/
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
<>	144:ef7eb2e8f9f7	722	* @{
<>	144:ef7eb2e8f9f7	723	* @brief Constants defining whether or not fault enabling bits are write
<>	144:ef7eb2e8f9f7	724	* protected for a timer
<>	144:ef7eb2e8f9f7	725	*/
<>	144:ef7eb2e8f9f7	726	#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /!< Timer fault enabling bits are read/write /
<>	144:ef7eb2e8f9f7	727	#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /!< Timer fault enabling bits are read only /
<>	144:ef7eb2e8f9f7	728	/**
<>	144:ef7eb2e8f9f7	729	* @}
<>	144:ef7eb2e8f9f7	730	*/
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
<>	144:ef7eb2e8f9f7	733	* @{
<>	144:ef7eb2e8f9f7	734	* @brief Constants defining whether or not fault the dead time insertion
<>	144:ef7eb2e8f9f7	735	* feature is enabled for a timer
<>	144:ef7eb2e8f9f7	736	*/
<>	144:ef7eb2e8f9f7	737	#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /!< Output 1 and output 2 signals are independent /
<>	144:ef7eb2e8f9f7	738	#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /!< Deadtime is inserted between output 1 and output 2 /
<>	144:ef7eb2e8f9f7	739	/**
<>	144:ef7eb2e8f9f7	740	* @}
<>	144:ef7eb2e8f9f7	741	*/
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
<>	144:ef7eb2e8f9f7	744	* @{
<>	144:ef7eb2e8f9f7	745	* @brief Constants defining all possible delayed protection modes
<>	144:ef7eb2e8f9f7	746	* for a timer. Also definethe source and outputs on which the delayed
<>	144:ef7eb2e8f9f7	747	* protection schemes are applied
<>	144:ef7eb2e8f9f7	748	*/
<>	144:ef7eb2e8f9f7	749	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /!< No action /
<>	144:ef7eb2e8f9f7	750	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 delayed Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	751	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 2 delayed Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	752	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	753	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Balanced Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	754	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 delayed Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	755	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 2 delayed Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	756	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	757	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Balanced Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /!< No action /
<>	144:ef7eb2e8f9f7	760	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 delayed Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	761	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 2 delayed Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	762	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	763	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Balanced Idle on external Event 6 /
<>	144:ef7eb2e8f9f7	764	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 delayed Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	765	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 2 delayed Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	766	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	767	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Balanced Idle on external Event 7 /
<>	144:ef7eb2e8f9f7	768	/**
<>	144:ef7eb2e8f9f7	769	* @}
<>	144:ef7eb2e8f9f7	770	*/
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
<>	144:ef7eb2e8f9f7	773	* @{
<>	144:ef7eb2e8f9f7	774	* @brief Constants defining whether the registers update is done synchronously
<>	144:ef7eb2e8f9f7	775	* with any other timer or master update
<>	144:ef7eb2e8f9f7	776	*/
<>	144:ef7eb2e8f9f7	777	#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /!< Register update is disabled /
<>	144:ef7eb2e8f9f7	778	#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /!< Register update is triggered by the master timer update /
<>	144:ef7eb2e8f9f7	779	#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /!< Register update is triggered by the timer A update /
<>	144:ef7eb2e8f9f7	780	#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /!< Register update is triggered by the timer B update /
<>	144:ef7eb2e8f9f7	781	#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /!< Register update is triggered by the timer C update/
<>	144:ef7eb2e8f9f7	782	#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /!< Register update is triggered by the timer D update /
<>	144:ef7eb2e8f9f7	783	#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /!< Register update is triggered by the timer E update /
<>	144:ef7eb2e8f9f7	784	/**
<>	144:ef7eb2e8f9f7	785	* @}
<>	144:ef7eb2e8f9f7	786	*/
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
<>	144:ef7eb2e8f9f7	789	* @{
<>	144:ef7eb2e8f9f7	790	* @brief Constants defining the events that can be selected to trigger the reset
<>	144:ef7eb2e8f9f7	791	* of the timer counter
<>	144:ef7eb2e8f9f7	792	*/
<>	144:ef7eb2e8f9f7	793	#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /!< No counter reset trigger /
<>	144:ef7eb2e8f9f7	794	#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /!< The timer counter is reset upon update event /
<>	144:ef7eb2e8f9f7	795	#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /!< The timer counter is reset upon Timer Compare 2 event /
<>	144:ef7eb2e8f9f7	796	#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /!< The timer counter is reset upon Timer Compare 4 event /
<>	144:ef7eb2e8f9f7	797	#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /!< The timer counter is reset upon master timer period event /
<>	144:ef7eb2e8f9f7	798	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /!< The timer counter is reset upon master timer Compare 1 event /
<>	144:ef7eb2e8f9f7	799	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /!< The timer counter is reset upon master timer Compare 2 event /
<>	144:ef7eb2e8f9f7	800	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /!< The timer counter is reset upon master timer Compare 3 event /
<>	144:ef7eb2e8f9f7	801	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /!< The timer counter is reset upon master timer Compare 4 event /
<>	144:ef7eb2e8f9f7	802	#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /!< The timer counter is reset upon external event 1 /
<>	144:ef7eb2e8f9f7	803	#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /!< The timer counter is reset upon external event 2 /
<>	144:ef7eb2e8f9f7	804	#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /!< The timer counter is reset upon external event 3 /
<>	144:ef7eb2e8f9f7	805	#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /!< The timer counter is reset upon external event 4 /
<>	144:ef7eb2e8f9f7	806	#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /!< The timer counter is reset upon external event 5 /
<>	144:ef7eb2e8f9f7	807	#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /!< The timer counter is reset upon external event 6 /
<>	144:ef7eb2e8f9f7	808	#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /!< The timer counter is reset upon external event 7 /
<>	144:ef7eb2e8f9f7	809	#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /!< The timer counter is reset upon external event 8 /
<>	144:ef7eb2e8f9f7	810	#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /!< The timer counter is reset upon external event 9 /
<>	144:ef7eb2e8f9f7	811	#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /!< The timer counter is reset upon external event 10 /
<>	144:ef7eb2e8f9f7	812	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
<>	144:ef7eb2e8f9f7	813	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
<>	144:ef7eb2e8f9f7	814	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
<>	144:ef7eb2e8f9f7	815	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
<>	144:ef7eb2e8f9f7	816	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
<>	144:ef7eb2e8f9f7	817	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
<>	144:ef7eb2e8f9f7	818	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
<>	144:ef7eb2e8f9f7	819	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
<>	144:ef7eb2e8f9f7	820	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
<>	144:ef7eb2e8f9f7	821	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /!< The timer counter is reset upon other timer Compare 1 event /
<>	144:ef7eb2e8f9f7	822	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /!< The timer counter is reset upon other timer Compare 2 event /
<>	144:ef7eb2e8f9f7	823	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /!< The timer counter is reset upon other timer Compare 4 event /
<>	144:ef7eb2e8f9f7	824	/**
<>	144:ef7eb2e8f9f7	825	* @}
<>	144:ef7eb2e8f9f7	826	*/
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
<>	144:ef7eb2e8f9f7	829	* @{
<>	144:ef7eb2e8f9f7	830	* @brief Constants defining whether the register are updated upon Timerx
<>	144:ef7eb2e8f9f7	831	* counter reset or roll-over to 0 after reaching the period value
<>	144:ef7eb2e8f9f7	832	* in continuous mode
<>	144:ef7eb2e8f9f7	833	*/
<>	144:ef7eb2e8f9f7	834	#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /!< Update by timer x reset / roll-over disabled /
<>	144:ef7eb2e8f9f7	835	#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /!< Update by timer x reset / roll-over enabled /
<>	144:ef7eb2e8f9f7	836	/**
<>	144:ef7eb2e8f9f7	837	* @}
<>	144:ef7eb2e8f9f7	838	*/
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
<>	144:ef7eb2e8f9f7	841	* @{
<>	144:ef7eb2e8f9f7	842	* @brief Constants defining whether the compare register is behaving in
<>	144:ef7eb2e8f9f7	843	* regular mode (compare match issued as soon as counter equal compare),
<>	144:ef7eb2e8f9f7	844	* or in auto-delayed mode
<>	144:ef7eb2e8f9f7	845	*/
<>	144:ef7eb2e8f9f7	846	#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /!< standard compare mode /
<>	144:ef7eb2e8f9f7	847	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated only if a capture has occurred /
<>	144:ef7eb2e8f9f7	848	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) /
<>	144:ef7eb2e8f9f7	849	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 \| HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) /
<>	144:ef7eb2e8f9f7	850	/**
<>	144:ef7eb2e8f9f7	851	* @}
<>	144:ef7eb2e8f9f7	852	*/
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
<>	144:ef7eb2e8f9f7	855	* @{
<>	144:ef7eb2e8f9f7	856	* @brief Constants defining the behavior of the output signal when the timer
<>	144:ef7eb2e8f9f7	857	operates in basic output compare mode
<>	144:ef7eb2e8f9f7	858	*/
<>	144:ef7eb2e8f9f7	859	#define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /!< Output toggles when the timer counter reaches the compare value /
<>	144:ef7eb2e8f9f7	860	#define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /!< Output forced to active level when the timer counter reaches the compare value /
<>	144:ef7eb2e8f9f7	861	#define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /!< Output forced to inactive level when the timer counter reaches the compare value /
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
<>	144:ef7eb2e8f9f7	864	(((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) \|\| \
<>	144:ef7eb2e8f9f7	865	((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	866	((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
<>	144:ef7eb2e8f9f7	867	/**
<>	144:ef7eb2e8f9f7	868	* @}
<>	144:ef7eb2e8f9f7	869	*/
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
<>	144:ef7eb2e8f9f7	872	* @{
<>	144:ef7eb2e8f9f7	873	* @brief Constants defining the polarity of a timer output
<>	144:ef7eb2e8f9f7	874	*/
<>	144:ef7eb2e8f9f7	875	#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /!< Output is acitve HIGH /
<>	144:ef7eb2e8f9f7	876	#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /!< Output is active LOW /
<>	144:ef7eb2e8f9f7	877	/**
<>	144:ef7eb2e8f9f7	878	* @}
<>	144:ef7eb2e8f9f7	879	*/
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
<>	144:ef7eb2e8f9f7	882	* @{
<>	144:ef7eb2e8f9f7	883	* @brief Constants defining the events that can be selected to configure the
<>	144:ef7eb2e8f9f7	884	* set crossbar of a timer output
<>	144:ef7eb2e8f9f7	885	*/
<>	144:ef7eb2e8f9f7	886	#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /!< Reset the output set crossbar /
<>	144:ef7eb2e8f9f7	887	#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its active state /
<>	144:ef7eb2e8f9f7	888	#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /!< Timer period event forces the output to its active state /
<>	144:ef7eb2e8f9f7	889	#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /!< Timer compare 1 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	890	#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /!< Timer compare 2 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	891	#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /!< Timer compare 3 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	892	#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /!< Timer compare 4 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	893	#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /!< The master timer period event forces the output to its active state /
<>	144:ef7eb2e8f9f7	894	#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	895	#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	896	#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	897	#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its active state /
<>	144:ef7eb2e8f9f7	898	#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
<>	144:ef7eb2e8f9f7	899	#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
<>	144:ef7eb2e8f9f7	900	#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
<>	144:ef7eb2e8f9f7	901	#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
<>	144:ef7eb2e8f9f7	902	#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
<>	144:ef7eb2e8f9f7	903	#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
<>	144:ef7eb2e8f9f7	904	#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
<>	144:ef7eb2e8f9f7	905	#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
<>	144:ef7eb2e8f9f7	906	#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
<>	144:ef7eb2e8f9f7	907	#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /!< External event 1 forces the output to its active state /
<>	144:ef7eb2e8f9f7	908	#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /!< External event 2 forces the output to its active state /
<>	144:ef7eb2e8f9f7	909	#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /!< External event 3 forces the output to its active state /
<>	144:ef7eb2e8f9f7	910	#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /!< External event 4 forces the output to its active state /
<>	144:ef7eb2e8f9f7	911	#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /!< External event 5 forces the output to its active state /
<>	144:ef7eb2e8f9f7	912	#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /!< External event 6 forces the output to its active state /
<>	144:ef7eb2e8f9f7	913	#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /!< External event 7 forces the output to its active state /
<>	144:ef7eb2e8f9f7	914	#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /!< External event 8 forces the output to its active state /
<>	144:ef7eb2e8f9f7	915	#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /!< External event 9 forces the output to its active state /
<>	144:ef7eb2e8f9f7	916	#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /!< External event 10 forces the output to its active state /
<>	144:ef7eb2e8f9f7	917	#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /!< Timer register update event forces the output to its active state /
<>	144:ef7eb2e8f9f7	918	/**
<>	144:ef7eb2e8f9f7	919	* @}
<>	144:ef7eb2e8f9f7	920	*/
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
<>	144:ef7eb2e8f9f7	923	* @{
<>	144:ef7eb2e8f9f7	924	* @brief Constants defining the events that can be selected to configure the
<>	144:ef7eb2e8f9f7	925	* set crossbar of a timer output
<>	144:ef7eb2e8f9f7	926	*/
<>	144:ef7eb2e8f9f7	927	#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /!< Reset the output reset crossbar /
<>	144:ef7eb2e8f9f7	928	#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	929	#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /!< Timer period event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	930	#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /!< Timer compare 1 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	931	#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /!< Timer compare 2 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	932	#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /!< Timer compare 3 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	933	#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /!< Timer compare 4 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	934	#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /!< The master timer period event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	935	#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	936	#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	937	#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	938	#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	939	#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	940	#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	941	#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	942	#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	943	#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	944	#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	945	#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	946	#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	947	#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	948	#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /!< External event 1 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	949	#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /!< External event 2 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	950	#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /!< External event 3 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	951	#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /!< External event 4 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	952	#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /!< External event 5 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	953	#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /!< External event 6 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	954	#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /!< External event 7 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	955	#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /!< External event 8 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	956	#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /!< External event 9 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	957	#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /!< External event 10 forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	958	#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /!< Timer register update event forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	959	/**
<>	144:ef7eb2e8f9f7	960	* @}
<>	144:ef7eb2e8f9f7	961	*/
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
<>	144:ef7eb2e8f9f7	964	* @{
<>	144:ef7eb2e8f9f7	965	* @brief Constants defining whether or not the timer output transition to its
<>	144:ef7eb2e8f9f7	966	IDLE state when burst mode is entered
<>	144:ef7eb2e8f9f7	967	*/
<>	144:ef7eb2e8f9f7	968	#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /!< The output is not affected by the burst mode operation /
<>	144:ef7eb2e8f9f7	969	#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /!< The output is in idle state when requested by the burst mode controller /
<>	144:ef7eb2e8f9f7	970	/**
<>	144:ef7eb2e8f9f7	971	* @}
<>	144:ef7eb2e8f9f7	972	*/
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
<>	144:ef7eb2e8f9f7	975	* @{
<>	144:ef7eb2e8f9f7	976	* @brief Constants defining the output level when output is in IDLE state
<>	144:ef7eb2e8f9f7	977	*/
<>	144:ef7eb2e8f9f7	978	#define HRTIM_OUTPUTIDLELEVEL_INACTIVE (uint32_t)0x00000000 /!< Output at inactive level when in IDLE state /
<>	144:ef7eb2e8f9f7	979	#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /!< Output at active level when in IDLE state /
<>	144:ef7eb2e8f9f7	980	/**
<>	144:ef7eb2e8f9f7	981	* @}
<>	144:ef7eb2e8f9f7	982	*/
<>	144:ef7eb2e8f9f7	983
<>	144:ef7eb2e8f9f7	984	/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
<>	144:ef7eb2e8f9f7	985	* @{
<>	144:ef7eb2e8f9f7	986	* @brief Constants defining the output level when output is in FAULT state
<>	144:ef7eb2e8f9f7	987	*/
<>	144:ef7eb2e8f9f7	988	#define HRTIM_OUTPUTFAULTLEVEL_NONE (uint32_t)0x00000000 /!< The output is not affected by the fault input /
<>	144:ef7eb2e8f9f7	989	#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /!< Output at active level when in FAULT state /
<>	144:ef7eb2e8f9f7	990	#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /!< Output at inactive level when in FAULT state /
<>	144:ef7eb2e8f9f7	991	#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 \| HRTIM_OUTR_FAULT1_0) /!< Output is tri-stated when in FAULT state /
<>	144:ef7eb2e8f9f7	992	/**
<>	144:ef7eb2e8f9f7	993	* @}
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995
<>	144:ef7eb2e8f9f7	996	/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
<>	144:ef7eb2e8f9f7	997	* @{
<>	144:ef7eb2e8f9f7	998	* @brief Constants defining whether or not chopper mode is enabled for a timer
<>	144:ef7eb2e8f9f7	999	output
<>	144:ef7eb2e8f9f7	1000	*/
<>	144:ef7eb2e8f9f7	1001	#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /!< Output signal is not altered /
<>	144:ef7eb2e8f9f7	1002	#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /!< Output signal is chopped by a carrier signal /
<>	144:ef7eb2e8f9f7	1003	/**
<>	144:ef7eb2e8f9f7	1004	* @}
<>	144:ef7eb2e8f9f7	1005	*/
<>	144:ef7eb2e8f9f7	1006
<>	144:ef7eb2e8f9f7	1007	/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
<>	144:ef7eb2e8f9f7	1008	* @{
<>	144:ef7eb2e8f9f7	1009	* @brief Constants defining the idle mode entry is delayed by forcing a
<>	144:ef7eb2e8f9f7	1010	deadtime insertion before switching the outputs to their idle state
<>	144:ef7eb2e8f9f7	1011	*/
<>	144:ef7eb2e8f9f7	1012	#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /!< The programmed Idle state is applied immediately to the Output /
<>	144:ef7eb2e8f9f7	1013	#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /!< Deadtime is inserted on output before entering the idle mode /
<>	144:ef7eb2e8f9f7	1014	/**
<>	144:ef7eb2e8f9f7	1015	* @}
<>	144:ef7eb2e8f9f7	1016	*/
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
<>	144:ef7eb2e8f9f7	1019	* @{
<>	144:ef7eb2e8f9f7	1020	* @brief Constants defining the events that can be selected to trigger the
<>	144:ef7eb2e8f9f7	1021	* capture of the timing unit counter
<>	144:ef7eb2e8f9f7	1022	*/
<>	144:ef7eb2e8f9f7	1023	#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /!< Capture trigger is disabled /
<>	144:ef7eb2e8f9f7	1024	#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /!< The update event triggers the Capture /
<>	144:ef7eb2e8f9f7	1025	#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /!< The External event 1 triggers the Capture /
<>	144:ef7eb2e8f9f7	1026	#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /!< The External event 2 triggers the Capture /
<>	144:ef7eb2e8f9f7	1027	#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /!< The External event 3 triggers the Capture /
<>	144:ef7eb2e8f9f7	1028	#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /!< The External event 4 triggers the Capture /
<>	144:ef7eb2e8f9f7	1029	#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /!< The External event 5 triggers the Capture /
<>	144:ef7eb2e8f9f7	1030	#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /!< The External event 6 triggers the Capture /
<>	144:ef7eb2e8f9f7	1031	#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /!< The External event 7 triggers the Capture /
<>	144:ef7eb2e8f9f7	1032	#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /!< The External event 8 triggers the Capture /
<>	144:ef7eb2e8f9f7	1033	#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /!< The External event 9 triggers the Capture /
<>	144:ef7eb2e8f9f7	1034	#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /!< The External event 10 triggers the Capture /
<>	144:ef7eb2e8f9f7	1035	#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /!< Capture is triggered by TA1 output inactive to active transition /
<>	144:ef7eb2e8f9f7	1036	#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /!< Capture is triggered by TA1 output active to inactive transition /
<>	144:ef7eb2e8f9f7	1037	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /!< Timer A Compare 1 triggers Capture /
<>	144:ef7eb2e8f9f7	1038	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /!< Timer A Compare 2 triggers Capture /
<>	144:ef7eb2e8f9f7	1039	#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /!< Capture is triggered by TB1 output inactive to active transition /
<>	144:ef7eb2e8f9f7	1040	#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /!< Capture is triggered by TB1 output active to inactive transition /
<>	144:ef7eb2e8f9f7	1041	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /!< Timer B Compare 1 triggers Capture /
<>	144:ef7eb2e8f9f7	1042	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /!< Timer B Compare 2 triggers Capture /
<>	144:ef7eb2e8f9f7	1043	#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /!< Capture is triggered by TC1 output inactive to active transition /
<>	144:ef7eb2e8f9f7	1044	#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /!< Capture is triggered by TC1 output active to inactive transition /
<>	144:ef7eb2e8f9f7	1045	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /!< Timer C Compare 1 triggers Capture /
<>	144:ef7eb2e8f9f7	1046	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /!< Timer C Compare 2 triggers Capture /
<>	144:ef7eb2e8f9f7	1047	#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /!< Capture is triggered by TD1 output inactive to active transition /
<>	144:ef7eb2e8f9f7	1048	#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /!< Capture is triggered by TD1 output active to inactive transition /
<>	144:ef7eb2e8f9f7	1049	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /!< Timer D Compare 1 triggers Capture /
<>	144:ef7eb2e8f9f7	1050	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /!< Timer D Compare 2 triggers Capture /
<>	144:ef7eb2e8f9f7	1051	#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /!< Capture is triggered by TE1 output inactive to active transition /
<>	144:ef7eb2e8f9f7	1052	#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /!< Capture is triggered by TE1 output active to inactive transition /
<>	144:ef7eb2e8f9f7	1053	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /!< Timer E Compare 1 triggers Capture /
<>	144:ef7eb2e8f9f7	1054	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /!< Timer E Compare 2 triggers Capture /
<>	144:ef7eb2e8f9f7	1055	/**
<>	144:ef7eb2e8f9f7	1056	* @}
<>	144:ef7eb2e8f9f7	1057	*/
<>	144:ef7eb2e8f9f7	1058
<>	144:ef7eb2e8f9f7	1059	/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
<>	144:ef7eb2e8f9f7	1060	* @{
<>	144:ef7eb2e8f9f7	1061	* @brief Constants defining the event filtering apploed to external events
<>	144:ef7eb2e8f9f7	1062	* by a timer
<>	144:ef7eb2e8f9f7	1063	*/
<>	144:ef7eb2e8f9f7	1064	#define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
<>	144:ef7eb2e8f9f7	1065	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 1 /
<>	144:ef7eb2e8f9f7	1066	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from counter reset/roll-over to Compare 2 /
<>	144:ef7eb2e8f9f7	1067	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 3 /
<>	144:ef7eb2e8f9f7	1068	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from counter reset/roll-over to Compare 4 /
<>	144:ef7eb2e8f9f7	1069	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR1 source /
<>	144:ef7eb2e8f9f7	1070	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR2 source /
<>	144:ef7eb2e8f9f7	1071	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR3 source /
<>	144:ef7eb2e8f9f7	1072	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /!< Blanking from another timing unit: TIMFLTR4 source /
<>	144:ef7eb2e8f9f7	1073	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR5 source /
<>	144:ef7eb2e8f9f7	1074	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR6 source /
<>	144:ef7eb2e8f9f7	1075	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR7 source /
<>	144:ef7eb2e8f9f7	1076	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from another timing unit: TIMFLTR8 source /
<>	144:ef7eb2e8f9f7	1077	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from counter reset/roll-over to Compare 2 /
<>	144:ef7eb2e8f9f7	1078	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Windowing from counter reset/roll-over to Compare 3 /
<>	144:ef7eb2e8f9f7	1079	#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from another timing unit: TIMWIN source /
<>	144:ef7eb2e8f9f7	1080	/**
<>	144:ef7eb2e8f9f7	1081	* @}
<>	144:ef7eb2e8f9f7	1082	*/
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
<>	144:ef7eb2e8f9f7	1085	* @{
<>	144:ef7eb2e8f9f7	1086	* @brief Constants defining whether or not the external event is
<>	144:ef7eb2e8f9f7	1087	* memorized (latched) and generated as soon as the blanking period
<>	144:ef7eb2e8f9f7	1088	* is completed or the window ends
<>	144:ef7eb2e8f9f7	1089	*/
<>	144:ef7eb2e8f9f7	1090	#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /!< Event is ignored if it happens during a blank, or passed through during a window /
<>	144:ef7eb2e8f9f7	1091	#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /!< Event is latched and delayed till the end of the blanking or windowing period /
<>	144:ef7eb2e8f9f7	1092	/**
<>	144:ef7eb2e8f9f7	1093	* @}
<>	144:ef7eb2e8f9f7	1094	*/
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
<>	144:ef7eb2e8f9f7	1097	* @{
<>	144:ef7eb2e8f9f7	1098	* @brief Constants defining division ratio between the timer clock frequency
<>	144:ef7eb2e8f9f7	1099	* (fHRTIM) and the deadtime generator clock (fDTG)
<>	144:ef7eb2e8f9f7	1100	*/
<>	144:ef7eb2e8f9f7	1101	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000) /!< fDTG = fHRTIM 8 */
<>	144:ef7eb2e8f9f7	1102	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM 4 */
<>	144:ef7eb2e8f9f7	1103	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM 2 */
<>	144:ef7eb2e8f9f7	1104	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM /
<>	144:ef7eb2e8f9f7	1105	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /!< fDTG = fHRTIM / 2 /
<>	144:ef7eb2e8f9f7	1106	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 4 /
<>	144:ef7eb2e8f9f7	1107	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM / 8 /
<>	144:ef7eb2e8f9f7	1108	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 16 /
<>	144:ef7eb2e8f9f7	1109	/**
<>	144:ef7eb2e8f9f7	1110	* @}
<>	144:ef7eb2e8f9f7	1111	*/
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
<>	144:ef7eb2e8f9f7	1114	* @{
<>	144:ef7eb2e8f9f7	1115	* @brief Constants defining whether the deadtime is positive or negative
<>	144:ef7eb2e8f9f7	1116	* (overlapping signal) on rising edge
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118	#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /!< Positive deadtime on rising edge /
<>	144:ef7eb2e8f9f7	1119	#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /!< Negative deadtime on rising edge /
<>	144:ef7eb2e8f9f7	1120	/**
<>	144:ef7eb2e8f9f7	1121	* @}
<>	144:ef7eb2e8f9f7	1122	*/
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
<>	144:ef7eb2e8f9f7	1125	* @{
<>	144:ef7eb2e8f9f7	1126	* @brief Constants defining whether or not the deadtime (rising sign and
<>	144:ef7eb2e8f9f7	1127	* value) is write protected
<>	144:ef7eb2e8f9f7	1128	*/
<>	144:ef7eb2e8f9f7	1129	#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime rising value and sign is writeable /
<>	144:ef7eb2e8f9f7	1130	#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /!< Deadtime rising value and sign is read-only /
<>	144:ef7eb2e8f9f7	1131	/**
<>	144:ef7eb2e8f9f7	1132	* @}
<>	144:ef7eb2e8f9f7	1133	*/
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
<>	144:ef7eb2e8f9f7	1136	* @{
<>	144:ef7eb2e8f9f7	1137	* @brief Constants defining whether or not the deadtime rising sign is write
<>	144:ef7eb2e8f9f7	1138	* protected
<>	144:ef7eb2e8f9f7	1139	*/
<>	144:ef7eb2e8f9f7	1140	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime rising sign is writeable /
<>	144:ef7eb2e8f9f7	1141	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /!< Deadtime rising sign is read-only /
<>	144:ef7eb2e8f9f7	1142	/**
<>	144:ef7eb2e8f9f7	1143	* @}
<>	144:ef7eb2e8f9f7	1144	*/
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
<>	144:ef7eb2e8f9f7	1147	* @{
<>	144:ef7eb2e8f9f7	1148	* @brief Constants defining whether the deadtime is positive or negative
<>	144:ef7eb2e8f9f7	1149	* (overlapping signal) on falling edge
<>	144:ef7eb2e8f9f7	1150	*/
<>	144:ef7eb2e8f9f7	1151	#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /!< Positive deadtime on falling edge /
<>	144:ef7eb2e8f9f7	1152	#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /!< Negative deadtime on falling edge /
<>	144:ef7eb2e8f9f7	1153	/**
<>	144:ef7eb2e8f9f7	1154	* @}
<>	144:ef7eb2e8f9f7	1155	*/
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
<>	144:ef7eb2e8f9f7	1158	* @{
<>	144:ef7eb2e8f9f7	1159	* @brief Constants defining whether or not the deadtime (falling sign and
<>	144:ef7eb2e8f9f7	1160	* value) is write protected
<>	144:ef7eb2e8f9f7	1161	*/
<>	144:ef7eb2e8f9f7	1162	#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime falling value and sign is writeable /
<>	144:ef7eb2e8f9f7	1163	#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /!< Deadtime falling value and sign is read-only /
<>	144:ef7eb2e8f9f7	1164	/**
<>	144:ef7eb2e8f9f7	1165	* @}
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167
<>	144:ef7eb2e8f9f7	1168	/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
<>	144:ef7eb2e8f9f7	1169	* @{
<>	144:ef7eb2e8f9f7	1170	* @brief Constants defining whether or not the deadtime falling sign is write
<>	144:ef7eb2e8f9f7	1171	* protected
<>	144:ef7eb2e8f9f7	1172	*/
<>	144:ef7eb2e8f9f7	1173	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime falling sign is writeable /
<>	144:ef7eb2e8f9f7	1174	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /!< Deadtime falling sign is read-only /
<>	144:ef7eb2e8f9f7	1175	/**
<>	144:ef7eb2e8f9f7	1176	* @}
<>	144:ef7eb2e8f9f7	1177	*/
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
<>	144:ef7eb2e8f9f7	1180	* @{
<>	144:ef7eb2e8f9f7	1181	* @brief Constants defining the frequency of the generated high frequency carrier
<>	144:ef7eb2e8f9f7	1182	*/
<>	144:ef7eb2e8f9f7	1183	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000) /!< fCHPFRQ = fHRTIM / 16 /
<>	144:ef7eb2e8f9f7	1184	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 32 /
<>	144:ef7eb2e8f9f7	1185	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 48 /
<>	144:ef7eb2e8f9f7	1186	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 64 /
<>	144:ef7eb2e8f9f7	1187	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 80 /
<>	144:ef7eb2e8f9f7	1188	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 96 /
<>	144:ef7eb2e8f9f7	1189	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 112 /
<>	144:ef7eb2e8f9f7	1190	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 128 /
<>	144:ef7eb2e8f9f7	1191	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /!< fCHPFRQ = fHRTIM / 144 /
<>	144:ef7eb2e8f9f7	1192	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 160 /
<>	144:ef7eb2e8f9f7	1193	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 176 /
<>	144:ef7eb2e8f9f7	1194	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 192 /
<>	144:ef7eb2e8f9f7	1195	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 208 /
<>	144:ef7eb2e8f9f7	1196	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 224 /
<>	144:ef7eb2e8f9f7	1197	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 240 /
<>	144:ef7eb2e8f9f7	1198	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 256 /
<>	144:ef7eb2e8f9f7	1199	/**
<>	144:ef7eb2e8f9f7	1200	* @}
<>	144:ef7eb2e8f9f7	1201	*/
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
<>	144:ef7eb2e8f9f7	1204	* @{
<>	144:ef7eb2e8f9f7	1205	* @brief Constants defining the duty cycle of the generated high frequency carrier
<>	144:ef7eb2e8f9f7	1206	* Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
<>	144:ef7eb2e8f9f7	1207	*/
<>	144:ef7eb2e8f9f7	1208	#define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000) /!< Only 1st pulse is present /
<>	144:ef7eb2e8f9f7	1209	#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 12.5 % /
<>	144:ef7eb2e8f9f7	1210	#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /!< Duty cycle of the carrier signal is 25 % /
<>	144:ef7eb2e8f9f7	1211	#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 37.5 % /
<>	144:ef7eb2e8f9f7	1212	#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /!< Duty cycle of the carrier signal is 50 % /
<>	144:ef7eb2e8f9f7	1213	#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 62.5 % /
<>	144:ef7eb2e8f9f7	1214	#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1) /!< Duty cycle of the carrier signal is 75 % /
<>	144:ef7eb2e8f9f7	1215	#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 87.5 % /
<>	144:ef7eb2e8f9f7	1216	/**
<>	144:ef7eb2e8f9f7	1217	* @}
<>	144:ef7eb2e8f9f7	1218	*/
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
<>	144:ef7eb2e8f9f7	1221	* @{
<>	144:ef7eb2e8f9f7	1222	* @brief Constants defining the pulse width of the first pulse of the generated
<>	144:ef7eb2e8f9f7	1223	* high frequency carrier
<>	144:ef7eb2e8f9f7	1224	*/
<>	144:ef7eb2e8f9f7	1225	#define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000) /!< tSTPW = tHRTIM x 16 /
<>	144:ef7eb2e8f9f7	1226	#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 32 /
<>	144:ef7eb2e8f9f7	1227	#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 48 /
<>	144:ef7eb2e8f9f7	1228	#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 64 /
<>	144:ef7eb2e8f9f7	1229	#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 80 /
<>	144:ef7eb2e8f9f7	1230	#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 96 /
<>	144:ef7eb2e8f9f7	1231	#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 112 /
<>	144:ef7eb2e8f9f7	1232	#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 128 /
<>	144:ef7eb2e8f9f7	1233	#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /!< tSTPW = tHRTIM x 144 /
<>	144:ef7eb2e8f9f7	1234	#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 160 /
<>	144:ef7eb2e8f9f7	1235	#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 176 /
<>	144:ef7eb2e8f9f7	1236	#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 192 /
<>	144:ef7eb2e8f9f7	1237	#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 208 /
<>	144:ef7eb2e8f9f7	1238	#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 224 /
<>	144:ef7eb2e8f9f7	1239	#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 240 /
<>	144:ef7eb2e8f9f7	1240	#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 256 /
<>	144:ef7eb2e8f9f7	1241	/**
<>	144:ef7eb2e8f9f7	1242	* @}
<>	144:ef7eb2e8f9f7	1243	*/
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
<>	144:ef7eb2e8f9f7	1246	* @{
<>	144:ef7eb2e8f9f7	1247	* @brief Constants defining the options for synchronizing multiple HRTIM
<>	144:ef7eb2e8f9f7	1248	* instances, as a master unit (generating a synchronization signal)
<>	144:ef7eb2e8f9f7	1249	* or as a slave (waiting for a trigger to be synchronized)
<>	144:ef7eb2e8f9f7	1250	*/
<>	144:ef7eb2e8f9f7	1251	#define HRTIM_SYNCOPTION_NONE (uint32_t)0x00000000 /!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) /
<>	144:ef7eb2e8f9f7	1252	#define HRTIM_SYNCOPTION_MASTER (uint32_t)0x00000001 /!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)/
<>	144:ef7eb2e8f9f7	1253	#define HRTIM_SYNCOPTION_SLAVE (uint32_t)0x00000002 /!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) /
<>	144:ef7eb2e8f9f7	1254	/**
<>	144:ef7eb2e8f9f7	1255	* @}
<>	144:ef7eb2e8f9f7	1256	*/
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
<>	144:ef7eb2e8f9f7	1259	* @{
<>	144:ef7eb2e8f9f7	1260	* @brief Constants defining defining the synchronization input source
<>	144:ef7eb2e8f9f7	1261	*/
<>	144:ef7eb2e8f9f7	1262	#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /!< disabled. HRTIM is not synchronized and runs in standalone mode /
<>	144:ef7eb2e8f9f7	1263	#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /!< The HRTIM is synchronized with the on-chip timer /
<>	144:ef7eb2e8f9f7	1264	#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 \| HRTIM_MCR_SYNC_IN_0) /!< A positive pulse on SYNCIN input triggers the HRTIM /
<>	144:ef7eb2e8f9f7	1265	/**
<>	144:ef7eb2e8f9f7	1266	* @}
<>	144:ef7eb2e8f9f7	1267	*/
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
<>	144:ef7eb2e8f9f7	1270	* @{
<>	144:ef7eb2e8f9f7	1271	* @brief Constants defining the source and event to be sent on the
<>	144:ef7eb2e8f9f7	1272	* synchronization outputs
<>	144:ef7eb2e8f9f7	1273	*/
<>	144:ef7eb2e8f9f7	1274	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /!< A pulse is sent on the SYNCOUT output upon master timer start event /
<>	144:ef7eb2e8f9f7	1275	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event/
<>	144:ef7eb2e8f9f7	1276	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /!< A pulse is sent on the SYNCOUT output upon timer A start or reset events /
<>	144:ef7eb2e8f9f7	1277	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 \| HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event /
<>	144:ef7eb2e8f9f7	1278	/**
<>	144:ef7eb2e8f9f7	1279	* @}
<>	144:ef7eb2e8f9f7	1280	*/
<>	144:ef7eb2e8f9f7	1281
<>	144:ef7eb2e8f9f7	1282	/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
<>	144:ef7eb2e8f9f7	1283	* @{
<>	144:ef7eb2e8f9f7	1284	* @brief Constants defining the routing and conditioning of the synchronization output event
<>	144:ef7eb2e8f9f7	1285	*/
<>	144:ef7eb2e8f9f7	1286	#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /!< Synchronization output event is disabled /
<>	144:ef7eb2e8f9f7	1287	#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization /
<>	144:ef7eb2e8f9f7	1288	#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 \| HRTIM_MCR_SYNC_OUT_0) /!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization /
<>	144:ef7eb2e8f9f7	1289	/**
<>	144:ef7eb2e8f9f7	1290	* @}
<>	144:ef7eb2e8f9f7	1291	*/
<>	144:ef7eb2e8f9f7	1292
<>	144:ef7eb2e8f9f7	1293	/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
<>	144:ef7eb2e8f9f7	1294	* @{
<>	144:ef7eb2e8f9f7	1295	* @brief Constants defining available sources associated to external events
<>	144:ef7eb2e8f9f7	1296	*/
<>	144:ef7eb2e8f9f7	1297	#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /!< External event source 1 /
<>	144:ef7eb2e8f9f7	1298	#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /!< External event source 2 /
<>	144:ef7eb2e8f9f7	1299	#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /!< External event source 3 /
<>	144:ef7eb2e8f9f7	1300	#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 \| HRTIM_EECR1_EE1SRC_0) /!< External event source 4 /
<>	144:ef7eb2e8f9f7	1301	/**
<>	144:ef7eb2e8f9f7	1302	* @}
<>	144:ef7eb2e8f9f7	1303	*/
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
<>	144:ef7eb2e8f9f7	1306	* @{
<>	144:ef7eb2e8f9f7	1307	* @brief Constants defining the polarity of an external event
<>	144:ef7eb2e8f9f7	1308	*/
<>	144:ef7eb2e8f9f7	1309	#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /!< External event is active high /
<>	144:ef7eb2e8f9f7	1310	#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /!< External event is active low /
<>	144:ef7eb2e8f9f7	1311	/**
<>	144:ef7eb2e8f9f7	1312	* @}
<>	144:ef7eb2e8f9f7	1313	*/
<>	144:ef7eb2e8f9f7	1314
<>	144:ef7eb2e8f9f7	1315	/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
<>	144:ef7eb2e8f9f7	1316	* @{
<>	144:ef7eb2e8f9f7	1317	* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
<>	144:ef7eb2e8f9f7	1318	* of an external event
<>	144:ef7eb2e8f9f7	1319	*/
<>	144:ef7eb2e8f9f7	1320	#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /!< External event is active on level /
<>	144:ef7eb2e8f9f7	1321	#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising edge /
<>	144:ef7eb2e8f9f7	1322	#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /!< External event is active on Falling edge /
<>	144:ef7eb2e8f9f7	1323	#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 \| HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising and Falling edges /
<>	144:ef7eb2e8f9f7	1324	/**
<>	144:ef7eb2e8f9f7	1325	* @}
<>	144:ef7eb2e8f9f7	1326	*/
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328	/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
<>	144:ef7eb2e8f9f7	1329	* @{
<>	144:ef7eb2e8f9f7	1330	* @brief Constants defining whether or not an external event is programmed in
<>	144:ef7eb2e8f9f7	1331	fast mode
<>	144:ef7eb2e8f9f7	1332	*/
<>	144:ef7eb2e8f9f7	1333	#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /!< External Event is acting asynchronously on outputs (low latency mode) /
<>	144:ef7eb2e8f9f7	1334	#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /!< External Event is re-synchronized by the HRTIM logic before acting on outputs /
<>	144:ef7eb2e8f9f7	1335	/**
<>	144:ef7eb2e8f9f7	1336	* @}
<>	144:ef7eb2e8f9f7	1337	*/
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
<>	144:ef7eb2e8f9f7	1340	* @{
<>	144:ef7eb2e8f9f7	1341	* @brief Constants defining the frequency used to sample an external event 6
<>	144:ef7eb2e8f9f7	1342	* input and the length (N) of the digital filter applied
<>	144:ef7eb2e8f9f7	1343	*/
<>	144:ef7eb2e8f9f7	1344	#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /!< Filter disabled /
<>	144:ef7eb2e8f9f7	1345	#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=2 /
<>	144:ef7eb2e8f9f7	1346	#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fHRTIM, N=4 /
<>	144:ef7eb2e8f9f7	1347	#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=8 /
<>	144:ef7eb2e8f9f7	1348	#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/2, N=6 /
<>	144:ef7eb2e8f9f7	1349	#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/2, N=8 /
<>	144:ef7eb2e8f9f7	1350	#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/4, N=6 /
<>	144:ef7eb2e8f9f7	1351	#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/4, N=8 /
<>	144:ef7eb2e8f9f7	1352	#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /!< fSAMPLING= fEEVS/8, N=6 /
<>	144:ef7eb2e8f9f7	1353	#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/8, N=8 /
<>	144:ef7eb2e8f9f7	1354	#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/16, N=5 /
<>	144:ef7eb2e8f9f7	1355	#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/16, N=6 /
<>	144:ef7eb2e8f9f7	1356	#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/16, N=8 /
<>	144:ef7eb2e8f9f7	1357	#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32, N=5 /
<>	144:ef7eb2e8f9f7	1358	#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/32, N=6 /
<>	144:ef7eb2e8f9f7	1359	#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32, N=8 /
<>	144:ef7eb2e8f9f7	1360	/**
<>	144:ef7eb2e8f9f7	1361	* @}
<>	144:ef7eb2e8f9f7	1362	*/
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
<>	144:ef7eb2e8f9f7	1365	* @{
<>	144:ef7eb2e8f9f7	1366	* @brief Constants defining division ratio between the timer clock frequency
<>	144:ef7eb2e8f9f7	1367	* fHRTIM) and the external event signal sampling clock (fEEVS)
<>	144:ef7eb2e8f9f7	1368	* used by the digital filters
<>	144:ef7eb2e8f9f7	1369	*/
<>	144:ef7eb2e8f9f7	1370	#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fEEVS=fHRTIM /
<>	144:ef7eb2e8f9f7	1371	#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 2 /
<>	144:ef7eb2e8f9f7	1372	#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /!< fEEVS=fHRTIM / 4 /
<>	144:ef7eb2e8f9f7	1373	#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 \| HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 8 /
<>	144:ef7eb2e8f9f7	1374	/**
<>	144:ef7eb2e8f9f7	1375	* @}
<>	144:ef7eb2e8f9f7	1376	*/
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
<>	144:ef7eb2e8f9f7	1379	* @{
<>	144:ef7eb2e8f9f7	1380	* @brief Constants defining whether a faults is be triggered by any external
<>	144:ef7eb2e8f9f7	1381	* or internal fault source
<>	144:ef7eb2e8f9f7	1382	*/
<>	144:ef7eb2e8f9f7	1383	#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /!< Fault input is FLT input pin /
<>	144:ef7eb2e8f9f7	1384	#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /!< Fault input is FLT_Int signal (e.g. internal comparator) /
<>	144:ef7eb2e8f9f7	1385	/**
<>	144:ef7eb2e8f9f7	1386	* @}
<>	144:ef7eb2e8f9f7	1387	*/
<>	144:ef7eb2e8f9f7	1388
<>	144:ef7eb2e8f9f7	1389	/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
<>	144:ef7eb2e8f9f7	1390	* @{
<>	144:ef7eb2e8f9f7	1391	* @brief Constants defining the polarity of a fault event
<>	144:ef7eb2e8f9f7	1392	*/
<>	144:ef7eb2e8f9f7	1393	#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /!< Fault input is active low /
<>	144:ef7eb2e8f9f7	1394	#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /!< Fault input is active high /
<>	144:ef7eb2e8f9f7	1395	/**
<>	144:ef7eb2e8f9f7	1396	* @}
<>	144:ef7eb2e8f9f7	1397	*/
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
<>	144:ef7eb2e8f9f7	1400	* @{
<>	144:ef7eb2e8f9f7	1401	* @ brief Constants defining the frequency used to sample the fault input and
<>	144:ef7eb2e8f9f7	1402	* the length (N) of the digital filter applied
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404	#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /!< Filter disabled /
<>	144:ef7eb2e8f9f7	1405	#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=2 /
<>	144:ef7eb2e8f9f7	1406	#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fHRTIM, N=4 /
<>	144:ef7eb2e8f9f7	1407	#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=8 /
<>	144:ef7eb2e8f9f7	1408	#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/2, N=6 /
<>	144:ef7eb2e8f9f7	1409	#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/2, N=8 /
<>	144:ef7eb2e8f9f7	1410	#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/4, N=6 /
<>	144:ef7eb2e8f9f7	1411	#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/4, N=8 /
<>	144:ef7eb2e8f9f7	1412	#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /!< fSAMPLING= fFLTS/8, N=6 /
<>	144:ef7eb2e8f9f7	1413	#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/8, N=8 /
<>	144:ef7eb2e8f9f7	1414	#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/16, N=5 /
<>	144:ef7eb2e8f9f7	1415	#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/16, N=6 /
<>	144:ef7eb2e8f9f7	1416	#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/16, N=8 /
<>	144:ef7eb2e8f9f7	1417	#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=5 /
<>	144:ef7eb2e8f9f7	1418	#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/32, N=6 /
<>	144:ef7eb2e8f9f7	1419	#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=8 /
<>	144:ef7eb2e8f9f7	1420	/**
<>	144:ef7eb2e8f9f7	1421	* @}
<>	144:ef7eb2e8f9f7	1422	*/
<>	144:ef7eb2e8f9f7	1423
<>	144:ef7eb2e8f9f7	1424	/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
<>	144:ef7eb2e8f9f7	1425	* @{
<>	144:ef7eb2e8f9f7	1426	* @brief Constants defining whether or not the fault programming bits are
<>	144:ef7eb2e8f9f7	1427	write protected
<>	144:ef7eb2e8f9f7	1428	*/
<>	144:ef7eb2e8f9f7	1429	#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /!< Fault settings bits are read/write /
<>	144:ef7eb2e8f9f7	1430	#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /!< Fault settings bits are read only /
<>	144:ef7eb2e8f9f7	1431	/**
<>	144:ef7eb2e8f9f7	1432	* @}
<>	144:ef7eb2e8f9f7	1433	*/
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
<>	144:ef7eb2e8f9f7	1436	* @{
<>	144:ef7eb2e8f9f7	1437	* @brief Constants defining the division ratio between the timer clock
<>	144:ef7eb2e8f9f7	1438	* frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
<>	144:ef7eb2e8f9f7	1439	* by the digital filters.
<>	144:ef7eb2e8f9f7	1440	*/
<>	144:ef7eb2e8f9f7	1441	#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fFLTS=fHRTIM /
<>	144:ef7eb2e8f9f7	1442	#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 2 /
<>	144:ef7eb2e8f9f7	1443	#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /!< fFLTS=fHRTIM / 4 /
<>	144:ef7eb2e8f9f7	1444	#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 \| HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 8 /
<>	144:ef7eb2e8f9f7	1445	/**
<>	144:ef7eb2e8f9f7	1446	* @}
<>	144:ef7eb2e8f9f7	1447	*/
<>	144:ef7eb2e8f9f7	1448
<>	144:ef7eb2e8f9f7	1449	/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
<>	144:ef7eb2e8f9f7	1450	* @{
<>	144:ef7eb2e8f9f7	1451	* @brief Constants defining if the burst mode is entered once or if it is
<>	144:ef7eb2e8f9f7	1452	* continuously operating
<>	144:ef7eb2e8f9f7	1453	*/
<>	144:ef7eb2e8f9f7	1454	#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /!< Burst mode operates in single shot mode /
<>	144:ef7eb2e8f9f7	1455	#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /!< Burst mode operates in continuous mode /
<>	144:ef7eb2e8f9f7	1456	/**
<>	144:ef7eb2e8f9f7	1457	* @}
<>	144:ef7eb2e8f9f7	1458	*/
<>	144:ef7eb2e8f9f7	1459
<>	144:ef7eb2e8f9f7	1460	/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
<>	144:ef7eb2e8f9f7	1461	* @{
<>	144:ef7eb2e8f9f7	1462	* @brief Constants defining the clock source for the burst mode counter
<>	144:ef7eb2e8f9f7	1463	*/
<>	144:ef7eb2e8f9f7	1464	#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /!< Master timer counter reset/roll-over is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1465	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /!< Timer A counter reset/roll-over is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1466	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /!< Timer B counter reset/roll-over is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1467	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< Timer C counter reset/roll-over is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1468	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /!< Timer D counter reset/roll-over is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1469	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_0) /!< Timer E counter reset/roll-over is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1470	#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1) /!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock /
<>	144:ef7eb2e8f9f7	1471	#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock /
<>	144:ef7eb2e8f9f7	1472	#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock /
<>	144:ef7eb2e8f9f7	1473	#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 \| HRTIM_BMCR_BMCLK_1) /!< Prescaled fHRTIM clock is used as clock source for the burst mode counter /
<>	144:ef7eb2e8f9f7	1474	/**
<>	144:ef7eb2e8f9f7	1475	* @}
<>	144:ef7eb2e8f9f7	1476	*/
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478	/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
<>	144:ef7eb2e8f9f7	1479	* @{
<>	144:ef7eb2e8f9f7	1480	* @brief Constants defining the prescaling ratio of the fHRTIM clock
<>	144:ef7eb2e8f9f7	1481	* for the burst mode controller
<>	144:ef7eb2e8f9f7	1482	*/
<>	144:ef7eb2e8f9f7	1483	#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fBRST = fHRTIM /
<>	144:ef7eb2e8f9f7	1484	#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2 /
<>	144:ef7eb2e8f9f7	1485	#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/4 /
<>	144:ef7eb2e8f9f7	1486	#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8 /
<>	144:ef7eb2e8f9f7	1487	#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/16 /
<>	144:ef7eb2e8f9f7	1488	#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32 /
<>	144:ef7eb2e8f9f7	1489	#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/64 /
<>	144:ef7eb2e8f9f7	1490	#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/128 /
<>	144:ef7eb2e8f9f7	1491	#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /!< fBRST = fHRTIM/256 /
<>	144:ef7eb2e8f9f7	1492	#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/512 /
<>	144:ef7eb2e8f9f7	1493	#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/1024 /
<>	144:ef7eb2e8f9f7	1494	#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2048/
<>	144:ef7eb2e8f9f7	1495	#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/4096 /
<>	144:ef7eb2e8f9f7	1496	#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8192 /
<>	144:ef7eb2e8f9f7	1497	#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/16384 /
<>	144:ef7eb2e8f9f7	1498	#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32768 /
<>	144:ef7eb2e8f9f7	1499	/**
<>	144:ef7eb2e8f9f7	1500	* @}
<>	144:ef7eb2e8f9f7	1501	*/
<>	144:ef7eb2e8f9f7	1502
<>	144:ef7eb2e8f9f7	1503	/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
<>	144:ef7eb2e8f9f7	1504	* @{
<>	144:ef7eb2e8f9f7	1505	* @brief Constants defining whether or not burst mode registers preload
<>	144:ef7eb2e8f9f7	1506	mechanism is enabled, i.e. a write access into a preloadable register
<>	144:ef7eb2e8f9f7	1507	(HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
<>	144:ef7eb2e8f9f7	1508	*/
<>	144:ef7eb2e8f9f7	1509	#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /!< Preload disabled: the write access is directly done into active registers /
<>	144:ef7eb2e8f9f7	1510	#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /!< Preload enabled: the write access is done into preload registers /
<>	144:ef7eb2e8f9f7	1511	/**
<>	144:ef7eb2e8f9f7	1512	* @}
<>	144:ef7eb2e8f9f7	1513	*/
<>	144:ef7eb2e8f9f7	1514
<>	144:ef7eb2e8f9f7	1515	/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
<>	144:ef7eb2e8f9f7	1516	* @{
<>	144:ef7eb2e8f9f7	1517	* @brief Constants defining the events that can be used tor trig the burst
<>	144:ef7eb2e8f9f7	1518	* mode operation
<>	144:ef7eb2e8f9f7	1519	*/
<>	144:ef7eb2e8f9f7	1520	#define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 /!< No trigger /
<>	144:ef7eb2e8f9f7	1521	#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /!< Master reset /
<>	144:ef7eb2e8f9f7	1522	#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /!< Master repetition /
<>	144:ef7eb2e8f9f7	1523	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /!< Master compare 1 /
<>	144:ef7eb2e8f9f7	1524	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /!< Master compare 2 /
<>	144:ef7eb2e8f9f7	1525	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /!< Master compare 3 /
<>	144:ef7eb2e8f9f7	1526	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /!< Master compare 4 /
<>	144:ef7eb2e8f9f7	1527	#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /!< Timer A reset /
<>	144:ef7eb2e8f9f7	1528	#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /!< Timer A repetition /
<>	144:ef7eb2e8f9f7	1529	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /!< Timer A compare 1 /
<>	144:ef7eb2e8f9f7	1530	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /!< Timer A compare 2 /
<>	144:ef7eb2e8f9f7	1531	#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /!< Timer B reset /
<>	144:ef7eb2e8f9f7	1532	#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /!< Timer B repetition /
<>	144:ef7eb2e8f9f7	1533	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /!< Timer B compare 1 /
<>	144:ef7eb2e8f9f7	1534	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /!< Timer B compare 2 /
<>	144:ef7eb2e8f9f7	1535	#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /!< Timer C reset /
<>	144:ef7eb2e8f9f7	1536	#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /!< Timer C repetition /
<>	144:ef7eb2e8f9f7	1537	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /!< Timer C compare 1 /
<>	144:ef7eb2e8f9f7	1538	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /!< Timer C compare 2 /
<>	144:ef7eb2e8f9f7	1539	#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /!< Timer D reset /
<>	144:ef7eb2e8f9f7	1540	#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /!< Timer D repetition /
<>	144:ef7eb2e8f9f7	1541	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /!< Timer D compare 1 /
<>	144:ef7eb2e8f9f7	1542	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /!< Timer D compare 2 /
<>	144:ef7eb2e8f9f7	1543	#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /!< Timer E reset /
<>	144:ef7eb2e8f9f7	1544	#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /!< Timer E repetition /
<>	144:ef7eb2e8f9f7	1545	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /!< Timer E compare 1 /
<>	144:ef7eb2e8f9f7	1546	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /!< Timer E compare 2 /
<>	144:ef7eb2e8f9f7	1547	#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /!< Timer A period following External Event 7 /
<>	144:ef7eb2e8f9f7	1548	#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /!< Timer D period following External Event 8 /
<>	144:ef7eb2e8f9f7	1549	#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /!< External Event 7 (timer A filters applied) /
<>	144:ef7eb2e8f9f7	1550	#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /!< External Event 8 (timer D filters applied)/
<>	144:ef7eb2e8f9f7	1551	#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /!< On-chip Event /
<>	144:ef7eb2e8f9f7	1552	/**
<>	144:ef7eb2e8f9f7	1553	* @}
<>	144:ef7eb2e8f9f7	1554	*/
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
<>	144:ef7eb2e8f9f7	1557	* @{
<>	144:ef7eb2e8f9f7	1558	* @brief constants defining the source triggering the update of the
<>	144:ef7eb2e8f9f7	1559	HRTIM_ADCxR register (transfer from preload to active register).
<>	144:ef7eb2e8f9f7	1560	*/
<>	144:ef7eb2e8f9f7	1561	#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /!< Master timer /
<>	144:ef7eb2e8f9f7	1562	#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /!< Timer A /
<>	144:ef7eb2e8f9f7	1563	#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /!< Timer B /
<>	144:ef7eb2e8f9f7	1564	#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 \| HRTIM_CR1_ADC1USRC_0) /!< Timer C /
<>	144:ef7eb2e8f9f7	1565	#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /!< Timer D /
<>	144:ef7eb2e8f9f7	1566	#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 \| HRTIM_CR1_ADC1USRC_0) /!< Timer E /
<>	144:ef7eb2e8f9f7	1567	/**
<>	144:ef7eb2e8f9f7	1568	* @}
<>	144:ef7eb2e8f9f7	1569	*/
<>	144:ef7eb2e8f9f7	1570
<>	144:ef7eb2e8f9f7	1571	/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
<>	144:ef7eb2e8f9f7	1572	* @{
<>	144:ef7eb2e8f9f7	1573	* @brief constants defining the events triggering ADC conversion.
<>	144:ef7eb2e8f9f7	1574	* HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
<>	144:ef7eb2e8f9f7	1575	* HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
<>	144:ef7eb2e8f9f7	1576	*/
<>	144:ef7eb2e8f9f7	1577	#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /!< No ADC trigger event /
<>	144:ef7eb2e8f9f7	1578	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /!< ADC Trigger on master compare 1 /
<>	144:ef7eb2e8f9f7	1579	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /!< ADC Trigger on master compare 2 /
<>	144:ef7eb2e8f9f7	1580	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /!< ADC Trigger on master compare 3 /
<>	144:ef7eb2e8f9f7	1581	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /!< ADC Trigger on master compare 4 /
<>	144:ef7eb2e8f9f7	1582	#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /!< ADC Trigger on master period /
<>	144:ef7eb2e8f9f7	1583	#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /!< ADC Trigger on external event 1 /
<>	144:ef7eb2e8f9f7	1584	#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /!< ADC Trigger on external event 2 /
<>	144:ef7eb2e8f9f7	1585	#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /!< ADC Trigger on external event 3 /
<>	144:ef7eb2e8f9f7	1586	#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /!< ADC Trigger on external event 4 /
<>	144:ef7eb2e8f9f7	1587	#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /!< ADC Trigger on external event 5 /
<>	144:ef7eb2e8f9f7	1588	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /!< ADC Trigger on Timer A compare 2 /
<>	144:ef7eb2e8f9f7	1589	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /!< ADC Trigger on Timer A compare 3 /
<>	144:ef7eb2e8f9f7	1590	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /!< ADC Trigger on Timer A compare 4 /
<>	144:ef7eb2e8f9f7	1591	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /!< ADC Trigger on Timer A period /
<>	144:ef7eb2e8f9f7	1592	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /!< ADC Trigger on Timer A reset /
<>	144:ef7eb2e8f9f7	1593	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /!< ADC Trigger on Timer B compare 2 /
<>	144:ef7eb2e8f9f7	1594	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /!< ADC Trigger on Timer B compare 3 /
<>	144:ef7eb2e8f9f7	1595	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /!< ADC Trigger on Timer B compare 4 /
<>	144:ef7eb2e8f9f7	1596	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /!< ADC Trigger on Timer B period /
<>	144:ef7eb2e8f9f7	1597	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /!< ADC Trigger on Timer B reset /
<>	144:ef7eb2e8f9f7	1598	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /!< ADC Trigger on Timer C compare 2 /
<>	144:ef7eb2e8f9f7	1599	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /!< ADC Trigger on Timer C compare 3 /
<>	144:ef7eb2e8f9f7	1600	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /!< ADC Trigger on Timer C compare 4 /
<>	144:ef7eb2e8f9f7	1601	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /!< ADC Trigger on Timer C period /
<>	144:ef7eb2e8f9f7	1602	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /!< ADC Trigger on Timer D compare 2 /
<>	144:ef7eb2e8f9f7	1603	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /!< ADC Trigger on Timer D compare 3 /
<>	144:ef7eb2e8f9f7	1604	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /!< ADC Trigger on Timer D compare 4 /
<>	144:ef7eb2e8f9f7	1605	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /!< ADC Trigger on Timer D period /
<>	144:ef7eb2e8f9f7	1606	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /!< ADC Trigger on Timer E compare 2 /
<>	144:ef7eb2e8f9f7	1607	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /!< ADC Trigger on Timer E compare 3 /
<>	144:ef7eb2e8f9f7	1608	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /!< ADC Trigger on Timer E compare 4 /
<>	144:ef7eb2e8f9f7	1609	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /!< ADC Trigger on Timer E period /
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /!< No ADC trigger event /
<>	144:ef7eb2e8f9f7	1612	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /!< ADC Trigger on master compare 1 /
<>	144:ef7eb2e8f9f7	1613	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /!< ADC Trigger on master compare 2 /
<>	144:ef7eb2e8f9f7	1614	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /!< ADC Trigger on master compare 3 /
<>	144:ef7eb2e8f9f7	1615	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /!< ADC Trigger on master compare 4 /
<>	144:ef7eb2e8f9f7	1616	#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /!< ADC Trigger on master period /
<>	144:ef7eb2e8f9f7	1617	#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /!< ADC Trigger on external event 6 /
<>	144:ef7eb2e8f9f7	1618	#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /!< ADC Trigger on external event 7 /
<>	144:ef7eb2e8f9f7	1619	#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /!< ADC Trigger on external event 8 /
<>	144:ef7eb2e8f9f7	1620	#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /!< ADC Trigger on external event 9 /
<>	144:ef7eb2e8f9f7	1621	#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /!< ADC Trigger on external event 10 /
<>	144:ef7eb2e8f9f7	1622	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /!< ADC Trigger on Timer A compare 2 /
<>	144:ef7eb2e8f9f7	1623	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /!< ADC Trigger on Timer A compare 3 /
<>	144:ef7eb2e8f9f7	1624	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /!< ADC Trigger on Timer A compare 4 /
<>	144:ef7eb2e8f9f7	1625	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /!< ADC Trigger on Timer A period /
<>	144:ef7eb2e8f9f7	1626	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /!< ADC Trigger on Timer B compare 2 /
<>	144:ef7eb2e8f9f7	1627	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /!< ADC Trigger on Timer B compare 3 /
<>	144:ef7eb2e8f9f7	1628	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /!< ADC Trigger on Timer B compare 4 /
<>	144:ef7eb2e8f9f7	1629	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /!< ADC Trigger on Timer B period /
<>	144:ef7eb2e8f9f7	1630	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /!< ADC Trigger on Timer C compare 2 /
<>	144:ef7eb2e8f9f7	1631	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /!< ADC Trigger on Timer C compare 3 /
<>	144:ef7eb2e8f9f7	1632	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /!< ADC Trigger on Timer C compare 4 /
<>	144:ef7eb2e8f9f7	1633	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /!< ADC Trigger on Timer C period /
<>	144:ef7eb2e8f9f7	1634	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /!< ADC Trigger on Timer C reset /
<>	144:ef7eb2e8f9f7	1635	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /!< ADC Trigger on Timer D compare 2 /
<>	144:ef7eb2e8f9f7	1636	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /!< ADC Trigger on Timer D compare 3 /
<>	144:ef7eb2e8f9f7	1637	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /!< ADC Trigger on Timer D compare 4 /
<>	144:ef7eb2e8f9f7	1638	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /!< ADC Trigger on Timer D period /
<>	144:ef7eb2e8f9f7	1639	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /!< ADC Trigger on Timer D reset /
<>	144:ef7eb2e8f9f7	1640	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /!< ADC Trigger on Timer E compare 2 /
<>	144:ef7eb2e8f9f7	1641	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /!< ADC Trigger on Timer E compare 3 /
<>	144:ef7eb2e8f9f7	1642	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /!< ADC Trigger on Timer E compare 4 /
<>	144:ef7eb2e8f9f7	1643	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /!< ADC Trigger on Timer E reset /
<>	144:ef7eb2e8f9f7	1644
<>	144:ef7eb2e8f9f7	1645	/**
<>	144:ef7eb2e8f9f7	1646	* @}
<>	144:ef7eb2e8f9f7	1647	*/
<>	144:ef7eb2e8f9f7	1648
<>	144:ef7eb2e8f9f7	1649	/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
<>	144:ef7eb2e8f9f7	1650	* @{
<>	144:ef7eb2e8f9f7	1651	* @brief Constants defining the DLL calibration periods (in micro seconds)
<>	144:ef7eb2e8f9f7	1652	*/
<>	144:ef7eb2e8f9f7	1653	#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /!< Non periodic DLL calibration /
<>	144:ef7eb2e8f9f7	1654	#define HRTIM_CALIBRATIONRATE_7300 0x00000000U /!< Periodic DLL calibration: T = 1048576 tHRTIM (7.3 ms) */
<>	144:ef7eb2e8f9f7	1655	#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /!< Periodic DLL calibration: T = 131072 tHRTIM (910 ms) */
<>	144:ef7eb2e8f9f7	1656	#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /!< Periodic DLL calibration: T = 16384 tHRTIM (114 ms) */
<>	144:ef7eb2e8f9f7	1657	#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 \| HRTIM_DLLCR_CALRTE_0) /!< Periodic DLL calibration: T = 2048 tHRTIM (14 ms) */
<>	144:ef7eb2e8f9f7	1658	/**
<>	144:ef7eb2e8f9f7	1659	* @}
<>	144:ef7eb2e8f9f7	1660	*/
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
<>	144:ef7eb2e8f9f7	1663	* @{
<>	144:ef7eb2e8f9f7	1664	* @brief Constants defining the registers that can be written during a burst
<>	144:ef7eb2e8f9f7	1665	* DMA operation
<>	144:ef7eb2e8f9f7	1666	*/
<>	144:ef7eb2e8f9f7	1667	#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /!< No register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1668	#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /!< MCR or TIMxCR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1669	#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /!< MICR or TIMxICR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1670	#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /!< MDIER or TIMxDIER register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1671	#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /!< MCNTR or CNTxCR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1672	#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /!< MPER or PERxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1673	#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /!< MREPR or REPxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1674	#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /!< MCMP1R or CMP1xR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1675	#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /!< MCMP2R or CMP2xR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1676	#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /!< MCMP3R or CMP3xR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1677	#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /!< MCMP4R or CMP4xR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1678	#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /!< TDxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1679	#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /!< SET1R register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1680	#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /!< RST1R register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1681	#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /!< SET2R register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1682	#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /!< RST1R register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1683	#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /!< EEFxR1 register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1684	#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /!< EEFxR2 register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1685	#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /!< RSTxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1686	#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /!< CHPxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1687	#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /!< OUTxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1688	#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /!< FLTxR register is updated by Burst DMA accesses /
<>	144:ef7eb2e8f9f7	1689	/**
<>	144:ef7eb2e8f9f7	1690	* @}
<>	144:ef7eb2e8f9f7	1691	*/
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
<>	144:ef7eb2e8f9f7	1694	* @{
<>	144:ef7eb2e8f9f7	1695	* @brief Constants used to enable or disable the burst mode controller
<>	144:ef7eb2e8f9f7	1696	*/
<>	144:ef7eb2e8f9f7	1697	#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /!< Burst mode disabled /
<>	144:ef7eb2e8f9f7	1698	#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /!< Burst mode enabled /
<>	144:ef7eb2e8f9f7	1699	/**
<>	144:ef7eb2e8f9f7	1700	* @}
<>	144:ef7eb2e8f9f7	1701	*/
<>	144:ef7eb2e8f9f7	1702
<>	144:ef7eb2e8f9f7	1703	/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
<>	144:ef7eb2e8f9f7	1704	* @{
<>	144:ef7eb2e8f9f7	1705	* @brief Constants used to enable or disable a fault channel
<>	144:ef7eb2e8f9f7	1706	*/
<>	144:ef7eb2e8f9f7	1707	#define HRTIM_FAULTMODECTL_DISABLED (uint32_t)0x00000000 /!< Fault channel is disabled /
<>	144:ef7eb2e8f9f7	1708	#define HRTIM_FAULTMODECTL_ENABLED (uint32_t)0x00000001 /!< Fault channel is enabled /
<>	144:ef7eb2e8f9f7	1709
<>	144:ef7eb2e8f9f7	1710	#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
<>	144:ef7eb2e8f9f7	1711	(((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	1712	((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
<>	144:ef7eb2e8f9f7	1713	/**
<>	144:ef7eb2e8f9f7	1714	* @}
<>	144:ef7eb2e8f9f7	1715	*/
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
<>	144:ef7eb2e8f9f7	1718	* @{
<>	144:ef7eb2e8f9f7	1719	* @brief Constants used to force timer registers update
<>	144:ef7eb2e8f9f7	1720	*/
<>	144:ef7eb2e8f9f7	1721	#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /!< Forces an immediate transfer from the preload to the active register in the master timer /
<>	144:ef7eb2e8f9f7	1722	#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /!< Forces an immediate transfer from the preload to the active register in the timer A /
<>	144:ef7eb2e8f9f7	1723	#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /!< Forces an immediate transfer from the preload to the active register in the timer B /
<>	144:ef7eb2e8f9f7	1724	#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /!< Forces an immediate transfer from the preload to the active register in the timer C /
<>	144:ef7eb2e8f9f7	1725	#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /!< Forces an immediate transfer from the preload to the active register in the timer D /
<>	144:ef7eb2e8f9f7	1726	#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /!< Forces an immediate transfer from the preload to the active register in the timer E /
<>	144:ef7eb2e8f9f7	1727	/**
<>	144:ef7eb2e8f9f7	1728	* @}
<>	144:ef7eb2e8f9f7	1729	*/
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
<>	144:ef7eb2e8f9f7	1732	* @{
<>	144:ef7eb2e8f9f7	1733	* @brief Constants used to force timer counter reset
<>	144:ef7eb2e8f9f7	1734	*/
<>	144:ef7eb2e8f9f7	1735	#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /!< Resets the master timer counter /
<>	144:ef7eb2e8f9f7	1736	#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /!< Resets the timer A counter /
<>	144:ef7eb2e8f9f7	1737	#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /!< Resets the timer B counter /
<>	144:ef7eb2e8f9f7	1738	#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /!< Resets the timer C counter /
<>	144:ef7eb2e8f9f7	1739	#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /!< Resets the timer D counter /
<>	144:ef7eb2e8f9f7	1740	#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /!< Resets the timer E counter /
<>	144:ef7eb2e8f9f7	1741	/**
<>	144:ef7eb2e8f9f7	1742	* @}
<>	144:ef7eb2e8f9f7	1743	*/
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	/** @defgroup HRTIM_Output_Level HRTIM Output Level
<>	144:ef7eb2e8f9f7	1746	* @{
<>	144:ef7eb2e8f9f7	1747	* @brief Constants defining the level of a timer output
<>	144:ef7eb2e8f9f7	1748	*/
<>	144:ef7eb2e8f9f7	1749	#define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /!< Forces the output to its active state /
<>	144:ef7eb2e8f9f7	1750	#define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /!< Forces the output to its inactive state /
<>	144:ef7eb2e8f9f7	1751
<>	144:ef7eb2e8f9f7	1752	#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
<>	144:ef7eb2e8f9f7	1753	(((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	1754	((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
<>	144:ef7eb2e8f9f7	1755	/**
<>	144:ef7eb2e8f9f7	1756	* @}
<>	144:ef7eb2e8f9f7	1757	*/
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/** @defgroup HRTIM_Output_State HRTIM Output State
<>	144:ef7eb2e8f9f7	1760	* @{
<>	144:ef7eb2e8f9f7	1761	* @brief Constants defining the state of a timer output
<>	144:ef7eb2e8f9f7	1762	*/
<>	144:ef7eb2e8f9f7	1763	#define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
<>	144:ef7eb2e8f9f7	1764	inactive level as programmed in the crossbar unit */
<>	144:ef7eb2e8f9f7	1765	#define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
<>	144:ef7eb2e8f9f7	1766	outputs are disabled by software or during a burst mode operation */
<>	144:ef7eb2e8f9f7	1767	#define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
<>	144:ef7eb2e8f9f7	1768	FAULTx inputs */
<>	144:ef7eb2e8f9f7	1769	/**
<>	144:ef7eb2e8f9f7	1770	* @}
<>	144:ef7eb2e8f9f7	1771	*/
<>	144:ef7eb2e8f9f7	1772
<>	144:ef7eb2e8f9f7	1773	/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
<>	144:ef7eb2e8f9f7	1774	* @{
<>	144:ef7eb2e8f9f7	1775	* @brief Constants defining the operating state of the burst mode controller
<>	144:ef7eb2e8f9f7	1776	*/
<>	144:ef7eb2e8f9f7	1777	#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /!< Normal operation /
<>	144:ef7eb2e8f9f7	1778	#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /!< Burst operation on-going /
<>	144:ef7eb2e8f9f7	1779	/**
<>	144:ef7eb2e8f9f7	1780	* @}
<>	144:ef7eb2e8f9f7	1781	*/
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
<>	144:ef7eb2e8f9f7	1784	* @{
<>	144:ef7eb2e8f9f7	1785	* @brief Constants defining on which output the signal is currently applied
<>	144:ef7eb2e8f9f7	1786	* in push-pull mode
<>	144:ef7eb2e8f9f7	1787	*/
<>	144:ef7eb2e8f9f7	1788	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /!< Signal applied on output 1 and output 2 forced inactive /
<>	144:ef7eb2e8f9f7	1789	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /!< Signal applied on output 2 and output 1 forced inactive /
<>	144:ef7eb2e8f9f7	1790	/**
<>	144:ef7eb2e8f9f7	1791	* @}
<>	144:ef7eb2e8f9f7	1792	*/
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
<>	144:ef7eb2e8f9f7	1795	* @{
<>	144:ef7eb2e8f9f7	1796	* @brief Constants defining on which output the signal was applied, in
<>	144:ef7eb2e8f9f7	1797	* push-pull mode balanced fault mode or delayed idle mode, when the
<>	144:ef7eb2e8f9f7	1798	* protection was triggered
<>	144:ef7eb2e8f9f7	1799	*/
<>	144:ef7eb2e8f9f7	1800	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /!< Protection occurred when the output 1 was active and output 2 forced inactive /
<>	144:ef7eb2e8f9f7	1801	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /!< Protection occurred when the output 2 was active and output 1 forced inactive /
<>	144:ef7eb2e8f9f7	1802	/**
<>	144:ef7eb2e8f9f7	1803	* @}
<>	144:ef7eb2e8f9f7	1804	*/
<>	144:ef7eb2e8f9f7	1805
<>	144:ef7eb2e8f9f7	1806	/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
<>	144:ef7eb2e8f9f7	1807	* @{
<>	144:ef7eb2e8f9f7	1808	*/
<>	144:ef7eb2e8f9f7	1809	#define HRTIM_IT_NONE (uint32_t)0x00000000 /!< No interrupt enabled /
<>	144:ef7eb2e8f9f7	1810	#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /!< Fault 1 interrupt enable /
<>	144:ef7eb2e8f9f7	1811	#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /!< Fault 2 interrupt enable /
<>	144:ef7eb2e8f9f7	1812	#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /!< Fault 3 interrupt enable /
<>	144:ef7eb2e8f9f7	1813	#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /!< Fault 4 interrupt enable /
<>	144:ef7eb2e8f9f7	1814	#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /!< Fault 5 interrupt enable /
<>	144:ef7eb2e8f9f7	1815	#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /!< System Fault interrupt enable /
<>	144:ef7eb2e8f9f7	1816	#define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /!< DLL ready interrupt enable /
<>	144:ef7eb2e8f9f7	1817	#define HRTIM_IT_BMPER HRTIM_IER_BMPER /!< Burst mode period interrupt enable /
<>	144:ef7eb2e8f9f7	1818	/**
<>	144:ef7eb2e8f9f7	1819	* @}
<>	144:ef7eb2e8f9f7	1820	*/
<>	144:ef7eb2e8f9f7	1821
<>	144:ef7eb2e8f9f7	1822	/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
<>	144:ef7eb2e8f9f7	1823	* @{
<>	144:ef7eb2e8f9f7	1824	*/
<>	144:ef7eb2e8f9f7	1825	#define HRTIM_MASTER_IT_NONE (uint32_t)0x00000000 /!< No interrupt enabled /
<>	144:ef7eb2e8f9f7	1826	#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /!< Master compare 1 interrupt enable /
<>	144:ef7eb2e8f9f7	1827	#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /!< Master compare 2 interrupt enable /
<>	144:ef7eb2e8f9f7	1828	#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /!< Master compare 3 interrupt enable /
<>	144:ef7eb2e8f9f7	1829	#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /!< Master compare 4 interrupt enable /
<>	144:ef7eb2e8f9f7	1830	#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /!< Master Repetition interrupt enable /
<>	144:ef7eb2e8f9f7	1831	#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /!< Synchronization input interrupt enable /
<>	144:ef7eb2e8f9f7	1832	#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /!< Master update interrupt enable /
<>	144:ef7eb2e8f9f7	1833	/**
<>	144:ef7eb2e8f9f7	1834	* @}
<>	144:ef7eb2e8f9f7	1835	*/
<>	144:ef7eb2e8f9f7	1836
<>	144:ef7eb2e8f9f7	1837	/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
<>	144:ef7eb2e8f9f7	1838	* @{
<>	144:ef7eb2e8f9f7	1839	*/
<>	144:ef7eb2e8f9f7	1840	#define HRTIM_TIM_IT_NONE (uint32_t)0x00000000 /!< No interrupt enabled /
<>	144:ef7eb2e8f9f7	1841	#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /!< Timer compare 1 interrupt enable /
<>	144:ef7eb2e8f9f7	1842	#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /!< Timer compare 2 interrupt enable /
<>	144:ef7eb2e8f9f7	1843	#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /!< Timer compare 3 interrupt enable /
<>	144:ef7eb2e8f9f7	1844	#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /!< Timer compare 4 interrupt enable /
<>	144:ef7eb2e8f9f7	1845	#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /!< Timer repetition interrupt enable /
<>	144:ef7eb2e8f9f7	1846	#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /!< Timer update interrupt enable /
<>	144:ef7eb2e8f9f7	1847	#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /!< Timer capture 1 interrupt enable /
<>	144:ef7eb2e8f9f7	1848	#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /!< Timer capture 2 interrupt enable /
<>	144:ef7eb2e8f9f7	1849	#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /!< Timer output 1 set interrupt enable /
<>	144:ef7eb2e8f9f7	1850	#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /!< Timer output 1 reset interrupt enable /
<>	144:ef7eb2e8f9f7	1851	#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /!< Timer output 2 set interrupt enable /
<>	144:ef7eb2e8f9f7	1852	#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /!< Timer output 2 reset interrupt enable /
<>	144:ef7eb2e8f9f7	1853	#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /!< Timer reset interrupt enable /
<>	144:ef7eb2e8f9f7	1854	#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /!< Timer delay protection interrupt enable /
<>	144:ef7eb2e8f9f7	1855	/**
<>	144:ef7eb2e8f9f7	1856	* @}
<>	144:ef7eb2e8f9f7	1857	*/
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
<>	144:ef7eb2e8f9f7	1860	* @{
<>	144:ef7eb2e8f9f7	1861	*/
<>	144:ef7eb2e8f9f7	1862	#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /!< Fault 1 interrupt flag /
<>	144:ef7eb2e8f9f7	1863	#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /!< Fault 2 interrupt flag /
<>	144:ef7eb2e8f9f7	1864	#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /!< Fault 3 interrupt flag /
<>	144:ef7eb2e8f9f7	1865	#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /!< Fault 4 interrupt flag /
<>	144:ef7eb2e8f9f7	1866	#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /!< Fault 5 interrupt flag /
<>	144:ef7eb2e8f9f7	1867	#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /!< System Fault interrupt flag /
<>	144:ef7eb2e8f9f7	1868	#define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /!< DLL ready interrupt flag /
<>	144:ef7eb2e8f9f7	1869	#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /!< Burst mode period interrupt flag /
<>	144:ef7eb2e8f9f7	1870	/**
<>	144:ef7eb2e8f9f7	1871	* @}
<>	144:ef7eb2e8f9f7	1872	*/
<>	144:ef7eb2e8f9f7	1873
<>	144:ef7eb2e8f9f7	1874	/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
<>	144:ef7eb2e8f9f7	1875	* @{
<>	144:ef7eb2e8f9f7	1876	*/
<>	144:ef7eb2e8f9f7	1877	#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /!< Master compare 1 interrupt flag /
<>	144:ef7eb2e8f9f7	1878	#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /!< Master compare 2 interrupt flag /
<>	144:ef7eb2e8f9f7	1879	#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /!< Master compare 3 interrupt flag /
<>	144:ef7eb2e8f9f7	1880	#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /!< Master compare 4 interrupt flag /
<>	144:ef7eb2e8f9f7	1881	#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /!< Master Repetition interrupt flag /
<>	144:ef7eb2e8f9f7	1882	#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /!< Synchronization input interrupt flag /
<>	144:ef7eb2e8f9f7	1883	#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /!< Master update interrupt flag /
<>	144:ef7eb2e8f9f7	1884	/**
<>	144:ef7eb2e8f9f7	1885	* @}
<>	144:ef7eb2e8f9f7	1886	*/
<>	144:ef7eb2e8f9f7	1887
<>	144:ef7eb2e8f9f7	1888	/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
<>	144:ef7eb2e8f9f7	1889	* @{
<>	144:ef7eb2e8f9f7	1890	*/
<>	144:ef7eb2e8f9f7	1891	#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /!< Timer compare 1 interrupt flag /
<>	144:ef7eb2e8f9f7	1892	#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /!< Timer compare 2 interrupt flag /
<>	144:ef7eb2e8f9f7	1893	#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /!< Timer compare 3 interrupt flag /
<>	144:ef7eb2e8f9f7	1894	#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /!< Timer compare 4 interrupt flag /
<>	144:ef7eb2e8f9f7	1895	#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /!< Timer repetition interrupt flag /
<>	144:ef7eb2e8f9f7	1896	#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /!< Timer update interrupt flag /
<>	144:ef7eb2e8f9f7	1897	#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /!< Timer capture 1 interrupt flag /
<>	144:ef7eb2e8f9f7	1898	#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /!< Timer capture 2 interrupt flag /
<>	144:ef7eb2e8f9f7	1899	#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /!< Timer output 1 set interrupt flag /
<>	144:ef7eb2e8f9f7	1900	#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /!< Timer output 1 reset interrupt flag /
<>	144:ef7eb2e8f9f7	1901	#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /!< Timer output 2 set interrupt flag /
<>	144:ef7eb2e8f9f7	1902	#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /!< Timer output 2 reset interrupt flag /
<>	144:ef7eb2e8f9f7	1903	#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /!< Timer reset interrupt flag /
<>	144:ef7eb2e8f9f7	1904	#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /!< Timer delay protection interrupt flag /
<>	144:ef7eb2e8f9f7	1905	/**
<>	144:ef7eb2e8f9f7	1906	* @}
<>	144:ef7eb2e8f9f7	1907	*/
<>	144:ef7eb2e8f9f7	1908
<>	144:ef7eb2e8f9f7	1909	/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
<>	144:ef7eb2e8f9f7	1910	* @{
<>	144:ef7eb2e8f9f7	1911	*/
<>	144:ef7eb2e8f9f7	1912	#define HRTIM_MASTER_DMA_NONE (uint32_t)0x00000000 /!< No DMA request enable /
<>	144:ef7eb2e8f9f7	1913	#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /!< Master compare 1 DMA request enable /
<>	144:ef7eb2e8f9f7	1914	#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /!< Master compare 2 DMA request enable /
<>	144:ef7eb2e8f9f7	1915	#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /!< Master compare 3 DMA request enable /
<>	144:ef7eb2e8f9f7	1916	#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /!< Master compare 4 DMA request enable /
<>	144:ef7eb2e8f9f7	1917	#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /!< Master Repetition DMA request enable /
<>	144:ef7eb2e8f9f7	1918	#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /!< Synchronization input DMA request enable /
<>	144:ef7eb2e8f9f7	1919	#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /!< Master update DMA request enable /
<>	144:ef7eb2e8f9f7	1920	/**
<>	144:ef7eb2e8f9f7	1921	* @}
<>	144:ef7eb2e8f9f7	1922	*/
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924	/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
<>	144:ef7eb2e8f9f7	1925	* @{
<>	144:ef7eb2e8f9f7	1926	*/
<>	144:ef7eb2e8f9f7	1927	#define HRTIM_TIM_DMA_NONE (uint32_t)0x00000000 /!< No DMA request enable /
<>	144:ef7eb2e8f9f7	1928	#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /!< Timer compare 1 DMA request enable /
<>	144:ef7eb2e8f9f7	1929	#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /!< Timer compare 2 DMA request enable /
<>	144:ef7eb2e8f9f7	1930	#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /!< Timer compare 3 DMA request enable /
<>	144:ef7eb2e8f9f7	1931	#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /!< Timer compare 4 DMA request enable /
<>	144:ef7eb2e8f9f7	1932	#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /!< Timer repetition DMA request enable /
<>	144:ef7eb2e8f9f7	1933	#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /!< Timer update DMA request enable /
<>	144:ef7eb2e8f9f7	1934	#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /!< Timer capture 1 DMA request enable /
<>	144:ef7eb2e8f9f7	1935	#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /!< Timer capture 2 DMA request enable /
<>	144:ef7eb2e8f9f7	1936	#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /!< Timer output 1 set DMA request enable /
<>	144:ef7eb2e8f9f7	1937	#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /!< Timer output 1 reset DMA request enable /
<>	144:ef7eb2e8f9f7	1938	#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /!< Timer output 2 set DMA request enable /
<>	144:ef7eb2e8f9f7	1939	#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /!< Timer output 2 reset DMA request enable /
<>	144:ef7eb2e8f9f7	1940	#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /!< Timer reset DMA request enable /
<>	144:ef7eb2e8f9f7	1941	#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /!< Timer delay protection DMA request enable /
<>	144:ef7eb2e8f9f7	1942	/**
<>	144:ef7eb2e8f9f7	1943	* @}
<>	144:ef7eb2e8f9f7	1944	*/
<>	144:ef7eb2e8f9f7	1945
<>	144:ef7eb2e8f9f7	1946	/**
<>	144:ef7eb2e8f9f7	1947	* @}
<>	144:ef7eb2e8f9f7	1948	*/
<>	144:ef7eb2e8f9f7	1949
<>	144:ef7eb2e8f9f7	1950	/* Private macros --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1951	/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
<>	144:ef7eb2e8f9f7	1952	* @{
<>	144:ef7eb2e8f9f7	1953	*/
<>	144:ef7eb2e8f9f7	1954
<>	144:ef7eb2e8f9f7	1955	#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
<>	144:ef7eb2e8f9f7	1956	(((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) \|\| \
<>	144:ef7eb2e8f9f7	1957	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
<>	144:ef7eb2e8f9f7	1958	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
<>	144:ef7eb2e8f9f7	1959	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
<>	144:ef7eb2e8f9f7	1960	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
<>	144:ef7eb2e8f9f7	1961	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
<>	144:ef7eb2e8f9f7	1962
<>	144:ef7eb2e8f9f7	1963	#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
<>	144:ef7eb2e8f9f7	1964	(((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
<>	144:ef7eb2e8f9f7	1965	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
<>	144:ef7eb2e8f9f7	1966	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
<>	144:ef7eb2e8f9f7	1967	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
<>	144:ef7eb2e8f9f7	1968	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
<>	144:ef7eb2e8f9f7	1969
<>	144:ef7eb2e8f9f7	1970	#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000)
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
<>	144:ef7eb2e8f9f7	1973	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) \|\| \
<>	144:ef7eb2e8f9f7	1974	((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) \|\| \
<>	144:ef7eb2e8f9f7	1975	((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) \|\| \
<>	144:ef7eb2e8f9f7	1976	((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
<>	144:ef7eb2e8f9f7	1977
<>	144:ef7eb2e8f9f7	1978	#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
<>	144:ef7eb2e8f9f7	1979	(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) \|\| \
<>	144:ef7eb2e8f9f7	1980	((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000)
<>	144:ef7eb2e8f9f7	1983
<>	144:ef7eb2e8f9f7	1984	#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
<>	144:ef7eb2e8f9f7	1985	((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
<>	144:ef7eb2e8f9f7	1986	(((OUTPUT) == HRTIM_OUTPUT_TA1) \|\| \
<>	144:ef7eb2e8f9f7	1987	((OUTPUT) == HRTIM_OUTPUT_TA2))) \
<>	144:ef7eb2e8f9f7	1988	\|\| \
<>	144:ef7eb2e8f9f7	1989	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
<>	144:ef7eb2e8f9f7	1990	(((OUTPUT) == HRTIM_OUTPUT_TB1) \|\| \
<>	144:ef7eb2e8f9f7	1991	((OUTPUT) == HRTIM_OUTPUT_TB2))) \
<>	144:ef7eb2e8f9f7	1992	\|\| \
<>	144:ef7eb2e8f9f7	1993	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
<>	144:ef7eb2e8f9f7	1994	(((OUTPUT) == HRTIM_OUTPUT_TC1) \|\| \
<>	144:ef7eb2e8f9f7	1995	((OUTPUT) == HRTIM_OUTPUT_TC2))) \
<>	144:ef7eb2e8f9f7	1996	\|\| \
<>	144:ef7eb2e8f9f7	1997	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
<>	144:ef7eb2e8f9f7	1998	(((OUTPUT) == HRTIM_OUTPUT_TD1) \|\| \
<>	144:ef7eb2e8f9f7	1999	((OUTPUT) == HRTIM_OUTPUT_TD2))) \
<>	144:ef7eb2e8f9f7	2000	\|\| \
<>	144:ef7eb2e8f9f7	2001	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
<>	144:ef7eb2e8f9f7	2002	(((OUTPUT) == HRTIM_OUTPUT_TE1) \|\| \
<>	144:ef7eb2e8f9f7	2003	((OUTPUT) == HRTIM_OUTPUT_TE2))))
<>	144:ef7eb2e8f9f7	2004
<>	144:ef7eb2e8f9f7	2005	#define IS_HRTIM_EVENT(EVENT)\
<>	144:ef7eb2e8f9f7	2006	(((EVENT) == HRTIM_EVENT_1) \|\| \
<>	144:ef7eb2e8f9f7	2007	((EVENT) == HRTIM_EVENT_2) \|\| \
<>	144:ef7eb2e8f9f7	2008	((EVENT) == HRTIM_EVENT_3) \|\| \
<>	144:ef7eb2e8f9f7	2009	((EVENT) == HRTIM_EVENT_4) \|\| \
<>	144:ef7eb2e8f9f7	2010	((EVENT) == HRTIM_EVENT_5) \|\| \
<>	144:ef7eb2e8f9f7	2011	((EVENT) == HRTIM_EVENT_6) \|\| \
<>	144:ef7eb2e8f9f7	2012	((EVENT) == HRTIM_EVENT_7) \|\| \
<>	144:ef7eb2e8f9f7	2013	((EVENT) == HRTIM_EVENT_8) \|\| \
<>	144:ef7eb2e8f9f7	2014	((EVENT) == HRTIM_EVENT_9) \|\| \
<>	144:ef7eb2e8f9f7	2015	((EVENT) == HRTIM_EVENT_10))
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	#define IS_HRTIM_FAULT(FAULT)\
<>	144:ef7eb2e8f9f7	2018	(((FAULT) == HRTIM_FAULT_1) \|\| \
<>	144:ef7eb2e8f9f7	2019	((FAULT) == HRTIM_FAULT_2) \|\| \
<>	144:ef7eb2e8f9f7	2020	((FAULT) == HRTIM_FAULT_3) \|\| \
<>	144:ef7eb2e8f9f7	2021	((FAULT) == HRTIM_FAULT_4) \|\| \
<>	144:ef7eb2e8f9f7	2022	((FAULT) == HRTIM_FAULT_5))
<>	144:ef7eb2e8f9f7	2023
<>	144:ef7eb2e8f9f7	2024	#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
<>	144:ef7eb2e8f9f7	2025	(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) \|\| \
<>	144:ef7eb2e8f9f7	2026	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) \|\| \
<>	144:ef7eb2e8f9f7	2027	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) \|\| \
<>	144:ef7eb2e8f9f7	2028	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) \|\| \
<>	144:ef7eb2e8f9f7	2029	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) \|\| \
<>	144:ef7eb2e8f9f7	2030	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	2031	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2032	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
<>	144:ef7eb2e8f9f7	2033
<>	144:ef7eb2e8f9f7	2034	#define IS_HRTIM_MODE(MODE)\
<>	144:ef7eb2e8f9f7	2035	(((MODE) == HRTIM_MODE_CONTINUOUS) \|\| \
<>	144:ef7eb2e8f9f7	2036	((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
<>	144:ef7eb2e8f9f7	2037	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
<>	144:ef7eb2e8f9f7	2038
<>	144:ef7eb2e8f9f7	2039	#define IS_HRTIM_MODE_ONEPULSE(MODE)\
<>	144:ef7eb2e8f9f7	2040	(((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
<>	144:ef7eb2e8f9f7	2041	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
<>	144:ef7eb2e8f9f7	2042
<>	144:ef7eb2e8f9f7	2043
<>	144:ef7eb2e8f9f7	2044	#define IS_HRTIM_HALFMODE(HALFMODE)\
<>	144:ef7eb2e8f9f7	2045	(((HALFMODE) == HRTIM_HALFMODE_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2046	((HALFMODE) == HRTIM_HALFMODE_ENABLED))
<>	144:ef7eb2e8f9f7	2047
<>	144:ef7eb2e8f9f7	2048	#define IS_HRTIM_SYNCSTART(SYNCSTART)\
<>	144:ef7eb2e8f9f7	2049	(((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2050	((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052	#define IS_HRTIM_SYNCRESET(SYNCRESET)\
<>	144:ef7eb2e8f9f7	2053	(((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2054	((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
<>	144:ef7eb2e8f9f7	2055
<>	144:ef7eb2e8f9f7	2056	#define IS_HHRTIM_DACSYNC(DACSYNC)\
<>	144:ef7eb2e8f9f7	2057	(((DACSYNC) == HRTIM_DACSYNC_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2058	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) \|\| \
<>	144:ef7eb2e8f9f7	2059	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) \|\| \
<>	144:ef7eb2e8f9f7	2060	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
<>	144:ef7eb2e8f9f7	2061
<>	144:ef7eb2e8f9f7	2062	#define IS_HRTIM_PRELOAD(PRELOAD)\
<>	144:ef7eb2e8f9f7	2063	(((PRELOAD) == HRTIM_PRELOAD_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2064	((PRELOAD) == HRTIM_PRELOAD_ENABLED))
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
<>	144:ef7eb2e8f9f7	2067	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	2068	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
<>	144:ef7eb2e8f9f7	2069	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
<>	144:ef7eb2e8f9f7	2070
<>	144:ef7eb2e8f9f7	2071	#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
<>	144:ef7eb2e8f9f7	2072	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	2073	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
<>	144:ef7eb2e8f9f7	2074	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	2075	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) \|\| \
<>	144:ef7eb2e8f9f7	2076	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) \|\| \
<>	144:ef7eb2e8f9f7	2077	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) \|\| \
<>	144:ef7eb2e8f9f7	2078	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	2079	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	2080	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
<>	144:ef7eb2e8f9f7	2081
<>	144:ef7eb2e8f9f7	2082	#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
<>	144:ef7eb2e8f9f7	2083	(((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) \|\| \
<>	144:ef7eb2e8f9f7	2084	((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
<>	144:ef7eb2e8f9f7	2085
<>	144:ef7eb2e8f9f7	2086	#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
<>	144:ef7eb2e8f9f7	2087	(((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2088	((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
<>	144:ef7eb2e8f9f7	2089
<>	144:ef7eb2e8f9f7	2090	#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
<>	144:ef7eb2e8f9f7	2091	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2092	((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
<>	144:ef7eb2e8f9f7	2093
<>	144:ef7eb2e8f9f7	2094	#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000)
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096
<>	144:ef7eb2e8f9f7	2097	#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
<>	144:ef7eb2e8f9f7	2098	(((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) \|\| \
<>	144:ef7eb2e8f9f7	2099	((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
<>	144:ef7eb2e8f9f7	2102	((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
<>	144:ef7eb2e8f9f7	2103	((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2104	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
<>	144:ef7eb2e8f9f7	2105	\|\| \
<>	144:ef7eb2e8f9f7	2106	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
<>	144:ef7eb2e8f9f7	2107	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
<>	144:ef7eb2e8f9f7	2108
<>	144:ef7eb2e8f9f7	2109	#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
<>	144:ef7eb2e8f9f7	2110	((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2111	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) \|\| \
<>	144:ef7eb2e8f9f7	2112	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) \|\| \
<>	144:ef7eb2e8f9f7	2113	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) \|\| \
<>	144:ef7eb2e8f9f7	2114	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) \|\| \
<>	144:ef7eb2e8f9f7	2115	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) \|\| \
<>	144:ef7eb2e8f9f7	2116	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
<>	144:ef7eb2e8f9f7	2117	\|\| \
<>	144:ef7eb2e8f9f7	2118	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
<>	144:ef7eb2e8f9f7	2119	(((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) \|\| \
<>	144:ef7eb2e8f9f7	2120	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
<>	144:ef7eb2e8f9f7	2121
<>	144:ef7eb2e8f9f7	2122	#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000)
<>	144:ef7eb2e8f9f7	2123
<>	144:ef7eb2e8f9f7	2124	#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000)
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126
<>	144:ef7eb2e8f9f7	2127	#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
<>	144:ef7eb2e8f9f7	2128	(((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2129	((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
<>	144:ef7eb2e8f9f7	2130
<>	144:ef7eb2e8f9f7	2131	#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
<>	144:ef7eb2e8f9f7	2132	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
<>	144:ef7eb2e8f9f7	2133	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
<>	144:ef7eb2e8f9f7	2134	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2135	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
<>	144:ef7eb2e8f9f7	2136
<>	144:ef7eb2e8f9f7	2137	/* Auto delayed mode is only available for compare units 2 and 4 */
<>	144:ef7eb2e8f9f7	2138	#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
<>	144:ef7eb2e8f9f7	2139	((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
<>	144:ef7eb2e8f9f7	2140	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
<>	144:ef7eb2e8f9f7	2141	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
<>	144:ef7eb2e8f9f7	2142	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2143	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
<>	144:ef7eb2e8f9f7	2144	\|\| \
<>	144:ef7eb2e8f9f7	2145	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
<>	144:ef7eb2e8f9f7	2146	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
<>	144:ef7eb2e8f9f7	2147	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
<>	144:ef7eb2e8f9f7	2148	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2149	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
<>	144:ef7eb2e8f9f7	2150
<>	144:ef7eb2e8f9f7	2151	#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
<>	144:ef7eb2e8f9f7	2152	(((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	2153	((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
<>	144:ef7eb2e8f9f7	2154
<>	144:ef7eb2e8f9f7	2155	#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
<>	144:ef7eb2e8f9f7	2156	(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2157	((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) \|\| \
<>	144:ef7eb2e8f9f7	2158	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) \|\| \
<>	144:ef7eb2e8f9f7	2159	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2160	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) \|\| \
<>	144:ef7eb2e8f9f7	2161	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) \|\| \
<>	144:ef7eb2e8f9f7	2162	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) \|\| \
<>	144:ef7eb2e8f9f7	2163	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) \|\| \
<>	144:ef7eb2e8f9f7	2164	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2165	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) \|\| \
<>	144:ef7eb2e8f9f7	2166	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) \|\| \
<>	144:ef7eb2e8f9f7	2167	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) \|\| \
<>	144:ef7eb2e8f9f7	2168	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) \|\| \
<>	144:ef7eb2e8f9f7	2169	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) \|\| \
<>	144:ef7eb2e8f9f7	2170	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) \|\| \
<>	144:ef7eb2e8f9f7	2171	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) \|\| \
<>	144:ef7eb2e8f9f7	2172	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) \|\| \
<>	144:ef7eb2e8f9f7	2173	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) \|\| \
<>	144:ef7eb2e8f9f7	2174	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) \|\| \
<>	144:ef7eb2e8f9f7	2175	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) \|\| \
<>	144:ef7eb2e8f9f7	2176	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) \|\| \
<>	144:ef7eb2e8f9f7	2177	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) \|\| \
<>	144:ef7eb2e8f9f7	2178	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) \|\| \
<>	144:ef7eb2e8f9f7	2179	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) \|\| \
<>	144:ef7eb2e8f9f7	2180	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) \|\| \
<>	144:ef7eb2e8f9f7	2181	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) \|\| \
<>	144:ef7eb2e8f9f7	2182	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) \|\| \
<>	144:ef7eb2e8f9f7	2183	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) \|\| \
<>	144:ef7eb2e8f9f7	2184	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) \|\| \
<>	144:ef7eb2e8f9f7	2185	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) \|\| \
<>	144:ef7eb2e8f9f7	2186	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) \|\| \
<>	144:ef7eb2e8f9f7	2187	((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
<>	144:ef7eb2e8f9f7	2188
<>	144:ef7eb2e8f9f7	2189	#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
<>	144:ef7eb2e8f9f7	2190	(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2191	((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) \|\| \
<>	144:ef7eb2e8f9f7	2192	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) \|\| \
<>	144:ef7eb2e8f9f7	2193	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2194	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) \|\| \
<>	144:ef7eb2e8f9f7	2195	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) \|\| \
<>	144:ef7eb2e8f9f7	2196	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) \|\| \
<>	144:ef7eb2e8f9f7	2197	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) \|\| \
<>	144:ef7eb2e8f9f7	2198	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2199	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) \|\| \
<>	144:ef7eb2e8f9f7	2200	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) \|\| \
<>	144:ef7eb2e8f9f7	2201	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) \|\| \
<>	144:ef7eb2e8f9f7	2202	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) \|\| \
<>	144:ef7eb2e8f9f7	2203	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) \|\| \
<>	144:ef7eb2e8f9f7	2204	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) \|\| \
<>	144:ef7eb2e8f9f7	2205	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) \|\| \
<>	144:ef7eb2e8f9f7	2206	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) \|\| \
<>	144:ef7eb2e8f9f7	2207	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) \|\| \
<>	144:ef7eb2e8f9f7	2208	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) \|\| \
<>	144:ef7eb2e8f9f7	2209	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) \|\| \
<>	144:ef7eb2e8f9f7	2210	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) \|\| \
<>	144:ef7eb2e8f9f7	2211	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) \|\| \
<>	144:ef7eb2e8f9f7	2212	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) \|\| \
<>	144:ef7eb2e8f9f7	2213	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) \|\| \
<>	144:ef7eb2e8f9f7	2214	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) \|\| \
<>	144:ef7eb2e8f9f7	2215	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) \|\| \
<>	144:ef7eb2e8f9f7	2216	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) \|\| \
<>	144:ef7eb2e8f9f7	2217	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) \|\| \
<>	144:ef7eb2e8f9f7	2218	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) \|\| \
<>	144:ef7eb2e8f9f7	2219	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) \|\| \
<>	144:ef7eb2e8f9f7	2220	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) \|\| \
<>	144:ef7eb2e8f9f7	2221	((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
<>	144:ef7eb2e8f9f7	2222
<>	144:ef7eb2e8f9f7	2223	#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
<>	144:ef7eb2e8f9f7	2224	(((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2225	((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
<>	144:ef7eb2e8f9f7	2226
<>	144:ef7eb2e8f9f7	2227	#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
<>	144:ef7eb2e8f9f7	2228	(((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	2229	((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
<>	144:ef7eb2e8f9f7	2232	(((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2233	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	2234	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	2235	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
<>	144:ef7eb2e8f9f7	2236
<>	144:ef7eb2e8f9f7	2237	#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
<>	144:ef7eb2e8f9f7	2238	(((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2239	((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
<>	144:ef7eb2e8f9f7	2240
<>	144:ef7eb2e8f9f7	2241	#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
<>	144:ef7eb2e8f9f7	2242	(((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) \|\| \
<>	144:ef7eb2e8f9f7	2243	((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
<>	144:ef7eb2e8f9f7	2244
<>	144:ef7eb2e8f9f7	2245	#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
<>	144:ef7eb2e8f9f7	2246	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2247	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	2248	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) \|\| \
<>	144:ef7eb2e8f9f7	2249	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) \|\| \
<>	144:ef7eb2e8f9f7	2250	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) \|\| \
<>	144:ef7eb2e8f9f7	2251	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) \|\| \
<>	144:ef7eb2e8f9f7	2252	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) \|\| \
<>	144:ef7eb2e8f9f7	2253	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) \|\| \
<>	144:ef7eb2e8f9f7	2254	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) \|\| \
<>	144:ef7eb2e8f9f7	2255	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) \|\| \
<>	144:ef7eb2e8f9f7	2256	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) \|\| \
<>	144:ef7eb2e8f9f7	2257	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
<>	144:ef7eb2e8f9f7	2258	\|\| \
<>	144:ef7eb2e8f9f7	2259	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
<>	144:ef7eb2e8f9f7	2260	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2261	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2262	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2263	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2264	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2265	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2266	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2267	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2268	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2269	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2270	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2271	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2272	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2273	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2274	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2275	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
<>	144:ef7eb2e8f9f7	2276	\|\| \
<>	144:ef7eb2e8f9f7	2277	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
<>	144:ef7eb2e8f9f7	2278	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2279	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2280	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2281	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2282	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2283	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2284	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2285	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2286	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2287	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2288	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2289	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2290	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2291	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2292	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2293	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
<>	144:ef7eb2e8f9f7	2294	\|\| \
<>	144:ef7eb2e8f9f7	2295	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
<>	144:ef7eb2e8f9f7	2296	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2297	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2298	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2299	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2300	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2301	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2302	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2303	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2304	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2305	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2306	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2307	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2308	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2309	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2310	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2311	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
<>	144:ef7eb2e8f9f7	2312	\|\| \
<>	144:ef7eb2e8f9f7	2313	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
<>	144:ef7eb2e8f9f7	2314	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2315	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2316	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2317	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2318	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2319	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2320	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2321	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2322	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2323	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2324	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2325	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2326	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2327	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2328	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2329	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
<>	144:ef7eb2e8f9f7	2330	\|\| \
<>	144:ef7eb2e8f9f7	2331	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
<>	144:ef7eb2e8f9f7	2332	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2333	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2334	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2335	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2336	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2337	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2338	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2339	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2340	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2341	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2342	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2343	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2344	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
<>	144:ef7eb2e8f9f7	2345	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2346	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2347	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
<>	144:ef7eb2e8f9f7	2348
<>	144:ef7eb2e8f9f7	2349	#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
<>	144:ef7eb2e8f9f7	2350	(((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2351	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) \|\| \
<>	144:ef7eb2e8f9f7	2352	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) \|\| \
<>	144:ef7eb2e8f9f7	2353	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) \|\| \
<>	144:ef7eb2e8f9f7	2354	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) \|\| \
<>	144:ef7eb2e8f9f7	2355	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) \|\| \
<>	144:ef7eb2e8f9f7	2356	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) \|\| \
<>	144:ef7eb2e8f9f7	2357	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) \|\| \
<>	144:ef7eb2e8f9f7	2358	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) \|\| \
<>	144:ef7eb2e8f9f7	2359	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) \|\| \
<>	144:ef7eb2e8f9f7	2360	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) \|\| \
<>	144:ef7eb2e8f9f7	2361	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) \|\| \
<>	144:ef7eb2e8f9f7	2362	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) \|\| \
<>	144:ef7eb2e8f9f7	2363	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) \|\| \
<>	144:ef7eb2e8f9f7	2364	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) \|\| \
<>	144:ef7eb2e8f9f7	2365	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
<>	144:ef7eb2e8f9f7	2366
<>	144:ef7eb2e8f9f7	2367	#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
<>	144:ef7eb2e8f9f7	2368	(((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2369	((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
<>	144:ef7eb2e8f9f7	2372	(((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) \|\| \
<>	144:ef7eb2e8f9f7	2373	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) \|\| \
<>	144:ef7eb2e8f9f7	2374	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) \|\| \
<>	144:ef7eb2e8f9f7	2375	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	2376	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2377	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	2378	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	2379	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
<>	144:ef7eb2e8f9f7	2380
<>	144:ef7eb2e8f9f7	2381	#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
<>	144:ef7eb2e8f9f7	2382	(((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) \|\| \
<>	144:ef7eb2e8f9f7	2383	((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385	#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
<>	144:ef7eb2e8f9f7	2386	(((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) \|\| \
<>	144:ef7eb2e8f9f7	2387	((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
<>	144:ef7eb2e8f9f7	2388
<>	144:ef7eb2e8f9f7	2389	#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
<>	144:ef7eb2e8f9f7	2390	(((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) \|\| \
<>	144:ef7eb2e8f9f7	2391	((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
<>	144:ef7eb2e8f9f7	2394	(((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) \|\| \
<>	144:ef7eb2e8f9f7	2395	((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
<>	144:ef7eb2e8f9f7	2396
<>	144:ef7eb2e8f9f7	2397	#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
<>	144:ef7eb2e8f9f7	2398	(((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) \|\| \
<>	144:ef7eb2e8f9f7	2399	((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
<>	144:ef7eb2e8f9f7	2400
<>	144:ef7eb2e8f9f7	2401	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
<>	144:ef7eb2e8f9f7	2402	(((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) \|\| \
<>	144:ef7eb2e8f9f7	2403	((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
<>	144:ef7eb2e8f9f7	2404
<>	144:ef7eb2e8f9f7	2405	#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
<>	144:ef7eb2e8f9f7	2406	(((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) \|\| \
<>	144:ef7eb2e8f9f7	2407	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) \|\| \
<>	144:ef7eb2e8f9f7	2408	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) \|\| \
<>	144:ef7eb2e8f9f7	2409	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	2410	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) \|\| \
<>	144:ef7eb2e8f9f7	2411	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) \|\| \
<>	144:ef7eb2e8f9f7	2412	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) \|\| \
<>	144:ef7eb2e8f9f7	2413	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) \|\| \
<>	144:ef7eb2e8f9f7	2414	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) \|\| \
<>	144:ef7eb2e8f9f7	2415	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) \|\| \
<>	144:ef7eb2e8f9f7	2416	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) \|\| \
<>	144:ef7eb2e8f9f7	2417	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) \|\| \
<>	144:ef7eb2e8f9f7	2418	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) \|\| \
<>	144:ef7eb2e8f9f7	2419	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) \|\| \
<>	144:ef7eb2e8f9f7	2420	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) \|\| \
<>	144:ef7eb2e8f9f7	2421	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
<>	144:ef7eb2e8f9f7	2422
<>	144:ef7eb2e8f9f7	2423	#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
<>	144:ef7eb2e8f9f7	2424	(((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) \|\| \
<>	144:ef7eb2e8f9f7	2425	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) \|\| \
<>	144:ef7eb2e8f9f7	2426	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) \|\| \
<>	144:ef7eb2e8f9f7	2427	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) \|\| \
<>	144:ef7eb2e8f9f7	2428	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) \|\| \
<>	144:ef7eb2e8f9f7	2429	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) \|\| \
<>	144:ef7eb2e8f9f7	2430	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) \|\| \
<>	144:ef7eb2e8f9f7	2431	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
<>	144:ef7eb2e8f9f7	2432
<>	144:ef7eb2e8f9f7	2433	#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
<>	144:ef7eb2e8f9f7	2434	(((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) \|\| \
<>	144:ef7eb2e8f9f7	2435	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) \|\| \
<>	144:ef7eb2e8f9f7	2436	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) \|\| \
<>	144:ef7eb2e8f9f7	2437	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) \|\| \
<>	144:ef7eb2e8f9f7	2438	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) \|\| \
<>	144:ef7eb2e8f9f7	2439	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) \|\| \
<>	144:ef7eb2e8f9f7	2440	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) \|\| \
<>	144:ef7eb2e8f9f7	2441	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) \|\| \
<>	144:ef7eb2e8f9f7	2442	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) \|\| \
<>	144:ef7eb2e8f9f7	2443	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) \|\| \
<>	144:ef7eb2e8f9f7	2444	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) \|\| \
<>	144:ef7eb2e8f9f7	2445	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) \|\| \
<>	144:ef7eb2e8f9f7	2446	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) \|\| \
<>	144:ef7eb2e8f9f7	2447	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) \|\| \
<>	144:ef7eb2e8f9f7	2448	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) \|\| \
<>	144:ef7eb2e8f9f7	2449	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
<>	144:ef7eb2e8f9f7	2450
<>	144:ef7eb2e8f9f7	2451	#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
<>	144:ef7eb2e8f9f7	2452	(((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2453	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) \|\| \
<>	144:ef7eb2e8f9f7	2454	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
<>	144:ef7eb2e8f9f7	2455
<>	144:ef7eb2e8f9f7	2456	#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
<>	144:ef7eb2e8f9f7	2457	(((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) \|\| \
<>	144:ef7eb2e8f9f7	2458	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2459	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) \|\| \
<>	144:ef7eb2e8f9f7	2460	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
<>	144:ef7eb2e8f9f7	2461
<>	144:ef7eb2e8f9f7	2462	#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
<>	144:ef7eb2e8f9f7	2463	(((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2464	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) \|\| \
<>	144:ef7eb2e8f9f7	2465	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
<>	144:ef7eb2e8f9f7	2466
<>	144:ef7eb2e8f9f7	2467	#define IS_HRTIM_EVENTSRC(EVENTSRC)\
<>	144:ef7eb2e8f9f7	2468	(((EVENTSRC) == HRTIM_EVENTSRC_1) \|\| \
<>	144:ef7eb2e8f9f7	2469	((EVENTSRC) == HRTIM_EVENTSRC_2) \|\| \
<>	144:ef7eb2e8f9f7	2470	((EVENTSRC) == HRTIM_EVENTSRC_3) \|\| \
<>	144:ef7eb2e8f9f7	2471	((EVENTSRC) == HRTIM_EVENTSRC_4))
<>	144:ef7eb2e8f9f7	2472
<>	144:ef7eb2e8f9f7	2473	#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
<>	144:ef7eb2e8f9f7	2474	((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
<>	144:ef7eb2e8f9f7	2475	(((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	2476	((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
<>	144:ef7eb2e8f9f7	2477	\|\| \
<>	144:ef7eb2e8f9f7	2478	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
<>	144:ef7eb2e8f9f7	2479	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)\|\| \
<>	144:ef7eb2e8f9f7	2480	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
<>	144:ef7eb2e8f9f7	2481
<>	144:ef7eb2e8f9f7	2482	#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
<>	144:ef7eb2e8f9f7	2483	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) \|\| \
<>	144:ef7eb2e8f9f7	2484	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
<>	144:ef7eb2e8f9f7	2485	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) \|\| \
<>	144:ef7eb2e8f9f7	2486	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
<>	144:ef7eb2e8f9f7	2487
<>	144:ef7eb2e8f9f7	2488	#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
<>	144:ef7eb2e8f9f7	2489	(((((EVENT) == HRTIM_EVENT_1) \|\| \
<>	144:ef7eb2e8f9f7	2490	((EVENT) == HRTIM_EVENT_2) \|\| \
<>	144:ef7eb2e8f9f7	2491	((EVENT) == HRTIM_EVENT_3) \|\| \
<>	144:ef7eb2e8f9f7	2492	((EVENT) == HRTIM_EVENT_4) \|\| \
<>	144:ef7eb2e8f9f7	2493	((EVENT) == HRTIM_EVENT_5)) && \
<>	144:ef7eb2e8f9f7	2494	(((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	2495	((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
<>	144:ef7eb2e8f9f7	2496	\|\| \
<>	144:ef7eb2e8f9f7	2497	(((EVENT) == HRTIM_EVENT_6) \|\| \
<>	144:ef7eb2e8f9f7	2498	((EVENT) == HRTIM_EVENT_7) \|\| \
<>	144:ef7eb2e8f9f7	2499	((EVENT) == HRTIM_EVENT_8) \|\| \
<>	144:ef7eb2e8f9f7	2500	((EVENT) == HRTIM_EVENT_9) \|\| \
<>	144:ef7eb2e8f9f7	2501	((EVENT) == HRTIM_EVENT_10)))
<>	144:ef7eb2e8f9f7	2502
<>	144:ef7eb2e8f9f7	2503
<>	144:ef7eb2e8f9f7	2504	#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
<>	144:ef7eb2e8f9f7	2505	((((EVENT) == HRTIM_EVENT_1) \|\| \
<>	144:ef7eb2e8f9f7	2506	((EVENT) == HRTIM_EVENT_2) \|\| \
<>	144:ef7eb2e8f9f7	2507	((EVENT) == HRTIM_EVENT_3) \|\| \
<>	144:ef7eb2e8f9f7	2508	((EVENT) == HRTIM_EVENT_4) \|\| \
<>	144:ef7eb2e8f9f7	2509	((EVENT) == HRTIM_EVENT_5)) \
<>	144:ef7eb2e8f9f7	2510	\|\| \
<>	144:ef7eb2e8f9f7	2511	((((EVENT) == HRTIM_EVENT_6) \|\| \
<>	144:ef7eb2e8f9f7	2512	((EVENT) == HRTIM_EVENT_7) \|\| \
<>	144:ef7eb2e8f9f7	2513	((EVENT) == HRTIM_EVENT_8) \|\| \
<>	144:ef7eb2e8f9f7	2514	((EVENT) == HRTIM_EVENT_9) \|\| \
<>	144:ef7eb2e8f9f7	2515	((EVENT) == HRTIM_EVENT_10)) && \
<>	144:ef7eb2e8f9f7	2516	(((FILTER) == HRTIM_EVENTFILTER_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2517	((FILTER) == HRTIM_EVENTFILTER_1) \|\| \
<>	144:ef7eb2e8f9f7	2518	((FILTER) == HRTIM_EVENTFILTER_2) \|\| \
<>	144:ef7eb2e8f9f7	2519	((FILTER) == HRTIM_EVENTFILTER_3) \|\| \
<>	144:ef7eb2e8f9f7	2520	((FILTER) == HRTIM_EVENTFILTER_4) \|\| \
<>	144:ef7eb2e8f9f7	2521	((FILTER) == HRTIM_EVENTFILTER_5) \|\| \
<>	144:ef7eb2e8f9f7	2522	((FILTER) == HRTIM_EVENTFILTER_6) \|\| \
<>	144:ef7eb2e8f9f7	2523	((FILTER) == HRTIM_EVENTFILTER_7) \|\| \
<>	144:ef7eb2e8f9f7	2524	((FILTER) == HRTIM_EVENTFILTER_8) \|\| \
<>	144:ef7eb2e8f9f7	2525	((FILTER) == HRTIM_EVENTFILTER_9) \|\| \
<>	144:ef7eb2e8f9f7	2526	((FILTER) == HRTIM_EVENTFILTER_10) \|\| \
<>	144:ef7eb2e8f9f7	2527	((FILTER) == HRTIM_EVENTFILTER_11) \|\| \
<>	144:ef7eb2e8f9f7	2528	((FILTER) == HRTIM_EVENTFILTER_12) \|\| \
<>	144:ef7eb2e8f9f7	2529	((FILTER) == HRTIM_EVENTFILTER_13) \|\| \
<>	144:ef7eb2e8f9f7	2530	((FILTER) == HRTIM_EVENTFILTER_14) \|\| \
<>	144:ef7eb2e8f9f7	2531	((FILTER) == HRTIM_EVENTFILTER_15))))
<>	144:ef7eb2e8f9f7	2532
<>	144:ef7eb2e8f9f7	2533	#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
<>	144:ef7eb2e8f9f7	2534	(((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	2535	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2536	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	2537	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	2538	#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
<>	144:ef7eb2e8f9f7	2539	(((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) \|\| \
<>	144:ef7eb2e8f9f7	2540	((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
<>	144:ef7eb2e8f9f7	2541
<>	144:ef7eb2e8f9f7	2542	#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
<>	144:ef7eb2e8f9f7	2543	(((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) \|\| \
<>	144:ef7eb2e8f9f7	2544	((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
<>	144:ef7eb2e8f9f7	2545
<>	144:ef7eb2e8f9f7	2546	#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
<>	144:ef7eb2e8f9f7	2547	(((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2548	((FAULTFILTER) == HRTIM_FAULTFILTER_1) \|\| \
<>	144:ef7eb2e8f9f7	2549	((FAULTFILTER) == HRTIM_FAULTFILTER_2) \|\| \
<>	144:ef7eb2e8f9f7	2550	((FAULTFILTER) == HRTIM_FAULTFILTER_3) \|\| \
<>	144:ef7eb2e8f9f7	2551	((FAULTFILTER) == HRTIM_FAULTFILTER_4) \|\| \
<>	144:ef7eb2e8f9f7	2552	((FAULTFILTER) == HRTIM_FAULTFILTER_5) \|\| \
<>	144:ef7eb2e8f9f7	2553	((FAULTFILTER) == HRTIM_FAULTFILTER_6) \|\| \
<>	144:ef7eb2e8f9f7	2554	((FAULTFILTER) == HRTIM_FAULTFILTER_7) \|\| \
<>	144:ef7eb2e8f9f7	2555	((FAULTFILTER) == HRTIM_FAULTFILTER_8) \|\| \
<>	144:ef7eb2e8f9f7	2556	((FAULTFILTER) == HRTIM_FAULTFILTER_9) \|\| \
<>	144:ef7eb2e8f9f7	2557	((FAULTFILTER) == HRTIM_FAULTFILTER_10) \|\| \
<>	144:ef7eb2e8f9f7	2558	((FAULTFILTER) == HRTIM_FAULTFILTER_11) \|\| \
<>	144:ef7eb2e8f9f7	2559	((FAULTFILTER) == HRTIM_FAULTFILTER_12) \|\| \
<>	144:ef7eb2e8f9f7	2560	((FAULTFILTER) == HRTIM_FAULTFILTER_13) \|\| \
<>	144:ef7eb2e8f9f7	2561	((FAULTFILTER) == HRTIM_FAULTFILTER_14) \|\| \
<>	144:ef7eb2e8f9f7	2562	((FAULTFILTER) == HRTIM_FAULTFILTER_15))
<>	144:ef7eb2e8f9f7	2563
<>	144:ef7eb2e8f9f7	2564	#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
<>	144:ef7eb2e8f9f7	2565	(((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) \|\| \
<>	144:ef7eb2e8f9f7	2566	((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
<>	144:ef7eb2e8f9f7	2567
<>	144:ef7eb2e8f9f7	2568	#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
<>	144:ef7eb2e8f9f7	2569	(((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	2570	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2571	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	2572	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	2573
<>	144:ef7eb2e8f9f7	2574	#define IS_HRTIM_BURSTMODE(BURSTMODE)\
<>	144:ef7eb2e8f9f7	2575	(((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) \|\| \
<>	144:ef7eb2e8f9f7	2576	((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
<>	144:ef7eb2e8f9f7	2577
<>	144:ef7eb2e8f9f7	2578	#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
<>	144:ef7eb2e8f9f7	2579	(((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) \|\| \
<>	144:ef7eb2e8f9f7	2580	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) \|\| \
<>	144:ef7eb2e8f9f7	2581	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) \|\| \
<>	144:ef7eb2e8f9f7	2582	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) \|\| \
<>	144:ef7eb2e8f9f7	2583	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) \|\| \
<>	144:ef7eb2e8f9f7	2584	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) \|\| \
<>	144:ef7eb2e8f9f7	2585	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) \|\| \
<>	144:ef7eb2e8f9f7	2586	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) \|\| \
<>	144:ef7eb2e8f9f7	2587	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	2588	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
<>	144:ef7eb2e8f9f7	2589
<>	144:ef7eb2e8f9f7	2590	#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
<>	144:ef7eb2e8f9f7	2591	(((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	2592	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2593	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	2594	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	2595	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) \|\| \
<>	144:ef7eb2e8f9f7	2596	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) \|\| \
<>	144:ef7eb2e8f9f7	2597	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	2598	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) \|\| \
<>	144:ef7eb2e8f9f7	2599	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) \|\| \
<>	144:ef7eb2e8f9f7	2600	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) \|\| \
<>	144:ef7eb2e8f9f7	2601	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) \|\| \
<>	144:ef7eb2e8f9f7	2602	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) \|\| \
<>	144:ef7eb2e8f9f7	2603	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) \|\| \
<>	144:ef7eb2e8f9f7	2604	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) \|\| \
<>	144:ef7eb2e8f9f7	2605	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) \|\| \
<>	144:ef7eb2e8f9f7	2606	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
<>	144:ef7eb2e8f9f7	2607
<>	144:ef7eb2e8f9f7	2608	#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
<>	144:ef7eb2e8f9f7	2609	(((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2610	((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
<>	144:ef7eb2e8f9f7	2611
<>	144:ef7eb2e8f9f7	2612	#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
<>	144:ef7eb2e8f9f7	2613	(((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) \|\| \
<>	144:ef7eb2e8f9f7	2614	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2615	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) \|\| \
<>	144:ef7eb2e8f9f7	2616	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2617	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2618	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) \|\| \
<>	144:ef7eb2e8f9f7	2619	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) \|\| \
<>	144:ef7eb2e8f9f7	2620	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2621	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) \|\| \
<>	144:ef7eb2e8f9f7	2622	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2623	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2624	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2625	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) \|\| \
<>	144:ef7eb2e8f9f7	2626	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2627	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2628	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2629	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) \|\| \
<>	144:ef7eb2e8f9f7	2630	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2631	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2632	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2633	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) \|\| \
<>	144:ef7eb2e8f9f7	2634	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2635	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2636	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) \|\| \
<>	144:ef7eb2e8f9f7	2637	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) \|\| \
<>	144:ef7eb2e8f9f7	2638	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) \|\| \
<>	144:ef7eb2e8f9f7	2639	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) \|\| \
<>	144:ef7eb2e8f9f7	2640	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) \|\| \
<>	144:ef7eb2e8f9f7	2641	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) \|\| \
<>	144:ef7eb2e8f9f7	2642	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) \|\| \
<>	144:ef7eb2e8f9f7	2643	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) \|\| \
<>	144:ef7eb2e8f9f7	2644	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
<>	144:ef7eb2e8f9f7	2645
<>	144:ef7eb2e8f9f7	2646	#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
<>	144:ef7eb2e8f9f7	2647	(((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) \|\| \
<>	144:ef7eb2e8f9f7	2648	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) \|\| \
<>	144:ef7eb2e8f9f7	2649	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) \|\| \
<>	144:ef7eb2e8f9f7	2650	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) \|\| \
<>	144:ef7eb2e8f9f7	2651	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) \|\| \
<>	144:ef7eb2e8f9f7	2652	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
<>	144:ef7eb2e8f9f7	2653
<>	144:ef7eb2e8f9f7	2654	#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
<>	144:ef7eb2e8f9f7	2655	(((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) \|\| \
<>	144:ef7eb2e8f9f7	2656	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) \|\| \
<>	144:ef7eb2e8f9f7	2657	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) \|\| \
<>	144:ef7eb2e8f9f7	2658	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) \|\| \
<>	144:ef7eb2e8f9f7	2659	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
<>	144:ef7eb2e8f9f7	2660
<>	144:ef7eb2e8f9f7	2661	#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
<>	144:ef7eb2e8f9f7	2662	((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000)) \
<>	144:ef7eb2e8f9f7	2663	\|\| \
<>	144:ef7eb2e8f9f7	2664	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
<>	144:ef7eb2e8f9f7	2665	\|\| \
<>	144:ef7eb2e8f9f7	2666	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
<>	144:ef7eb2e8f9f7	2667	\|\| \
<>	144:ef7eb2e8f9f7	2668	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
<>	144:ef7eb2e8f9f7	2669	\|\| \
<>	144:ef7eb2e8f9f7	2670	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
<>	144:ef7eb2e8f9f7	2671	\|\| \
<>	144:ef7eb2e8f9f7	2672	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)))
<>	144:ef7eb2e8f9f7	2673
<>	144:ef7eb2e8f9f7	2674	#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
<>	144:ef7eb2e8f9f7	2675	(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	2676	((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
<>	144:ef7eb2e8f9f7	2677
<>	144:ef7eb2e8f9f7	2678	#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000)
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680	#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000)
<>	144:ef7eb2e8f9f7	2681
<>	144:ef7eb2e8f9f7	2682	#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000)
<>	144:ef7eb2e8f9f7	2683
<>	144:ef7eb2e8f9f7	2684
<>	144:ef7eb2e8f9f7	2685	#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000)
<>	144:ef7eb2e8f9f7	2686
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000)
<>	144:ef7eb2e8f9f7	2689
<>	144:ef7eb2e8f9f7	2690
<>	144:ef7eb2e8f9f7	2691	#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000)
<>	144:ef7eb2e8f9f7	2692
<>	144:ef7eb2e8f9f7	2693	#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000)
<>	144:ef7eb2e8f9f7	2694	/**
<>	144:ef7eb2e8f9f7	2695	* @}
<>	144:ef7eb2e8f9f7	2696	*/
<>	144:ef7eb2e8f9f7	2697
<>	144:ef7eb2e8f9f7	2698	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2699	/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
<>	144:ef7eb2e8f9f7	2700	* @{
<>	144:ef7eb2e8f9f7	2701	*/
<>	144:ef7eb2e8f9f7	2702
<>	144:ef7eb2e8f9f7	2703	/** @brief Reset HRTIM handle state
<>	144:ef7eb2e8f9f7	2704	* @param __HANDLE__: HRTIM handle.
<>	144:ef7eb2e8f9f7	2705	* @retval None
<>	144:ef7eb2e8f9f7	2706	*/
<>	144:ef7eb2e8f9f7	2707	#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	2708
<>	144:ef7eb2e8f9f7	2709	/** @brief Enables or disables the timer counter(s)
<>	144:ef7eb2e8f9f7	2710	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2711	* @param __TIMERS__: timers to enable/disable
<>	144:ef7eb2e8f9f7	2712	* This parameter can be any combinations of the following values:
<>	144:ef7eb2e8f9f7	2713	* @arg HRTIM_TIMERID_MASTER: Master timer identifier
<>	144:ef7eb2e8f9f7	2714	* @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
<>	144:ef7eb2e8f9f7	2715	* @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
<>	144:ef7eb2e8f9f7	2716	* @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
<>	144:ef7eb2e8f9f7	2717	* @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
<>	144:ef7eb2e8f9f7	2718	* @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
<>	144:ef7eb2e8f9f7	2719	* @retval None
<>	144:ef7eb2e8f9f7	2720	*/
<>	144:ef7eb2e8f9f7	2721	#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR \|= (__TIMERS__))
<>	144:ef7eb2e8f9f7	2722
<>	144:ef7eb2e8f9f7	2723	/* The counter of a timing unit is disabled only if all the timer outputs */
<>	144:ef7eb2e8f9f7	2724	/* are disabled and no capture is configured */
<>	144:ef7eb2e8f9f7	2725	#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN \| HRTIM_OENR_TA1OEN)
<>	144:ef7eb2e8f9f7	2726	#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN \| HRTIM_OENR_TB1OEN)
<>	144:ef7eb2e8f9f7	2727	#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN \| HRTIM_OENR_TC1OEN)
<>	144:ef7eb2e8f9f7	2728	#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN \| HRTIM_OENR_TD1OEN)
<>	144:ef7eb2e8f9f7	2729	#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN \| HRTIM_OENR_TE1OEN)
<>	144:ef7eb2e8f9f7	2730	#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
<>	144:ef7eb2e8f9f7	2731	do {\
<>	144:ef7eb2e8f9f7	2732	if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
<>	144:ef7eb2e8f9f7	2733	{\
<>	144:ef7eb2e8f9f7	2734	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
<>	144:ef7eb2e8f9f7	2735	}\
<>	144:ef7eb2e8f9f7	2736	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
<>	144:ef7eb2e8f9f7	2737	{\
<>	144:ef7eb2e8f9f7	2738	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
<>	144:ef7eb2e8f9f7	2739	{\
<>	144:ef7eb2e8f9f7	2740	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
<>	144:ef7eb2e8f9f7	2741	}\
<>	144:ef7eb2e8f9f7	2742	}\
<>	144:ef7eb2e8f9f7	2743	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
<>	144:ef7eb2e8f9f7	2744	{\
<>	144:ef7eb2e8f9f7	2745	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
<>	144:ef7eb2e8f9f7	2746	{\
<>	144:ef7eb2e8f9f7	2747	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
<>	144:ef7eb2e8f9f7	2748	}\
<>	144:ef7eb2e8f9f7	2749	}\
<>	144:ef7eb2e8f9f7	2750	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
<>	144:ef7eb2e8f9f7	2751	{\
<>	144:ef7eb2e8f9f7	2752	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
<>	144:ef7eb2e8f9f7	2753	{\
<>	144:ef7eb2e8f9f7	2754	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
<>	144:ef7eb2e8f9f7	2755	}\
<>	144:ef7eb2e8f9f7	2756	}\
<>	144:ef7eb2e8f9f7	2757	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
<>	144:ef7eb2e8f9f7	2758	{\
<>	144:ef7eb2e8f9f7	2759	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
<>	144:ef7eb2e8f9f7	2760	{\
<>	144:ef7eb2e8f9f7	2761	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
<>	144:ef7eb2e8f9f7	2762	}\
<>	144:ef7eb2e8f9f7	2763	}\
<>	144:ef7eb2e8f9f7	2764	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
<>	144:ef7eb2e8f9f7	2765	{\
<>	144:ef7eb2e8f9f7	2766	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
<>	144:ef7eb2e8f9f7	2767	{\
<>	144:ef7eb2e8f9f7	2768	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
<>	144:ef7eb2e8f9f7	2769	}\
<>	144:ef7eb2e8f9f7	2770	}\
<>	144:ef7eb2e8f9f7	2771	} while(0)
<>	144:ef7eb2e8f9f7	2772
<>	144:ef7eb2e8f9f7	2773	/** @brief Enables or disables the specified HRTIM common interrupts.
<>	144:ef7eb2e8f9f7	2774	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2775	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<>	144:ef7eb2e8f9f7	2776	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2777	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
<>	144:ef7eb2e8f9f7	2778	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
<>	144:ef7eb2e8f9f7	2779	* @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
<>	144:ef7eb2e8f9f7	2780	* @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
<>	144:ef7eb2e8f9f7	2781	* @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
<>	144:ef7eb2e8f9f7	2782	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
<>	144:ef7eb2e8f9f7	2783	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
<>	144:ef7eb2e8f9f7	2784	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
<>	144:ef7eb2e8f9f7	2785	* @retval None
<>	144:ef7eb2e8f9f7	2786	*/
<>	144:ef7eb2e8f9f7	2787	#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2788	#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2789
<>	144:ef7eb2e8f9f7	2790	/** @brief Enables or disables the specified HRTIM Master timer interrupts.
<>	144:ef7eb2e8f9f7	2791	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2792	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<>	144:ef7eb2e8f9f7	2793	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2794	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
<>	144:ef7eb2e8f9f7	2795	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
<>	144:ef7eb2e8f9f7	2796	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
<>	144:ef7eb2e8f9f7	2797	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
<>	144:ef7eb2e8f9f7	2798	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
<>	144:ef7eb2e8f9f7	2799	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
<>	144:ef7eb2e8f9f7	2800	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
<>	144:ef7eb2e8f9f7	2801	* @retval None
<>	144:ef7eb2e8f9f7	2802	*/
<>	144:ef7eb2e8f9f7	2803	#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2804	#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2805
<>	144:ef7eb2e8f9f7	2806	/** @brief Enables or disables the specified HRTIM Timerx interrupts.
<>	144:ef7eb2e8f9f7	2807	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2808	* @param __TIMER__: specified the timing unit (Timer A to E)
<>	144:ef7eb2e8f9f7	2809	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<>	144:ef7eb2e8f9f7	2810	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2811	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
<>	144:ef7eb2e8f9f7	2812	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
<>	144:ef7eb2e8f9f7	2813	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
<>	144:ef7eb2e8f9f7	2814	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
<>	144:ef7eb2e8f9f7	2815	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
<>	144:ef7eb2e8f9f7	2816	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
<>	144:ef7eb2e8f9f7	2817	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
<>	144:ef7eb2e8f9f7	2818	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
<>	144:ef7eb2e8f9f7	2819	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
<>	144:ef7eb2e8f9f7	2820	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
<>	144:ef7eb2e8f9f7	2821	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
<>	144:ef7eb2e8f9f7	2822	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
<>	144:ef7eb2e8f9f7	2823	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
<>	144:ef7eb2e8f9f7	2824	* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
<>	144:ef7eb2e8f9f7	2825	* @retval None
<>	144:ef7eb2e8f9f7	2826	*/
<>	144:ef7eb2e8f9f7	2827	#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2828	#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2829
<>	144:ef7eb2e8f9f7	2830	/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	2831	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2832	* @param __INTERRUPT__: specifies the interrupt source to check.
<>	144:ef7eb2e8f9f7	2833	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2834	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
<>	144:ef7eb2e8f9f7	2835	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
<>	144:ef7eb2e8f9f7	2836	* @arg HRTIM_IT_FLT3: Fault 3 enable
<>	144:ef7eb2e8f9f7	2837	* @arg HRTIM_IT_FLT4: Fault 4 enable
<>	144:ef7eb2e8f9f7	2838	* @arg HRTIM_IT_FLT5: Fault 5 enable
<>	144:ef7eb2e8f9f7	2839	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
<>	144:ef7eb2e8f9f7	2840	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
<>	144:ef7eb2e8f9f7	2841	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
<>	144:ef7eb2e8f9f7	2842	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	2843	*/
<>	144:ef7eb2e8f9f7	2844	#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	144:ef7eb2e8f9f7	2845
<>	144:ef7eb2e8f9f7	2846	/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	2847	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2848	* @param __INTERRUPT__: specifies the interrupt source to check.
<>	144:ef7eb2e8f9f7	2849	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2850	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
<>	144:ef7eb2e8f9f7	2851	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
<>	144:ef7eb2e8f9f7	2852	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
<>	144:ef7eb2e8f9f7	2853	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
<>	144:ef7eb2e8f9f7	2854	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
<>	144:ef7eb2e8f9f7	2855	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
<>	144:ef7eb2e8f9f7	2856	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
<>	144:ef7eb2e8f9f7	2857	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	2858	*/
<>	144:ef7eb2e8f9f7	2859	#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	144:ef7eb2e8f9f7	2860
<>	144:ef7eb2e8f9f7	2861	/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	2862	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2863	* @param __TIMER__: specified the timing unit (Timer A to E)
<>	144:ef7eb2e8f9f7	2864	* @param __INTERRUPT__: specifies the interrupt source to check.
<>	144:ef7eb2e8f9f7	2865	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2866	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
<>	144:ef7eb2e8f9f7	2867	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
<>	144:ef7eb2e8f9f7	2868	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
<>	144:ef7eb2e8f9f7	2869	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
<>	144:ef7eb2e8f9f7	2870	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
<>	144:ef7eb2e8f9f7	2871	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
<>	144:ef7eb2e8f9f7	2872	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
<>	144:ef7eb2e8f9f7	2873	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
<>	144:ef7eb2e8f9f7	2874	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
<>	144:ef7eb2e8f9f7	2875	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
<>	144:ef7eb2e8f9f7	2876	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
<>	144:ef7eb2e8f9f7	2877	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
<>	144:ef7eb2e8f9f7	2878	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
<>	144:ef7eb2e8f9f7	2879	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
<>	144:ef7eb2e8f9f7	2880	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
<>	144:ef7eb2e8f9f7	2881	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
<>	144:ef7eb2e8f9f7	2882	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
<>	144:ef7eb2e8f9f7	2883	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
<>	144:ef7eb2e8f9f7	2884	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
<>	144:ef7eb2e8f9f7	2885	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
<>	144:ef7eb2e8f9f7	2886	* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
<>	144:ef7eb2e8f9f7	2887	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	2888	*/
<>	144:ef7eb2e8f9f7	2889	#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	144:ef7eb2e8f9f7	2890
<>	144:ef7eb2e8f9f7	2891	/** @brief Clears the specified HRTIM common pending flag.
<>	144:ef7eb2e8f9f7	2892	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2893	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	2894	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2895	* @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
<>	144:ef7eb2e8f9f7	2896	* @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
<>	144:ef7eb2e8f9f7	2897	* @arg HRTIM_IT_FLT3: Fault 3 clear flag
<>	144:ef7eb2e8f9f7	2898	* @arg HRTIM_IT_FLT4: Fault 4 clear flag
<>	144:ef7eb2e8f9f7	2899	* @arg HRTIM_IT_FLT5: Fault 5 clear flag
<>	144:ef7eb2e8f9f7	2900	* @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
<>	144:ef7eb2e8f9f7	2901	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
<>	144:ef7eb2e8f9f7	2902	* @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
<>	144:ef7eb2e8f9f7	2903	* @retval None
<>	144:ef7eb2e8f9f7	2904	*/
<>	144:ef7eb2e8f9f7	2905	#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2906
<>	144:ef7eb2e8f9f7	2907	/** @brief Clears the specified HRTIM Master pending flag.
<>	144:ef7eb2e8f9f7	2908	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2909	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	2910	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2911	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
<>	144:ef7eb2e8f9f7	2912	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
<>	144:ef7eb2e8f9f7	2913	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
<>	144:ef7eb2e8f9f7	2914	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
<>	144:ef7eb2e8f9f7	2915	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
<>	144:ef7eb2e8f9f7	2916	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
<>	144:ef7eb2e8f9f7	2917	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
<>	144:ef7eb2e8f9f7	2918	* @retval None
<>	144:ef7eb2e8f9f7	2919	*/
<>	144:ef7eb2e8f9f7	2920	#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2921
<>	144:ef7eb2e8f9f7	2922	/** @brief Clears the specified HRTIM Timerx pending flag.
<>	144:ef7eb2e8f9f7	2923	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2924	* @param __TIMER__: specified the timing unit (Timer A to E)
<>	144:ef7eb2e8f9f7	2925	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	2926	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2927	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
<>	144:ef7eb2e8f9f7	2928	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
<>	144:ef7eb2e8f9f7	2929	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
<>	144:ef7eb2e8f9f7	2930	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
<>	144:ef7eb2e8f9f7	2931	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
<>	144:ef7eb2e8f9f7	2932	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
<>	144:ef7eb2e8f9f7	2933	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
<>	144:ef7eb2e8f9f7	2934	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
<>	144:ef7eb2e8f9f7	2935	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
<>	144:ef7eb2e8f9f7	2936	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
<>	144:ef7eb2e8f9f7	2937	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
<>	144:ef7eb2e8f9f7	2938	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
<>	144:ef7eb2e8f9f7	2939	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
<>	144:ef7eb2e8f9f7	2940	* @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
<>	144:ef7eb2e8f9f7	2941	* @retval None
<>	144:ef7eb2e8f9f7	2942	*/
<>	144:ef7eb2e8f9f7	2943	#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2944
<>	144:ef7eb2e8f9f7	2945	/* DMA HANDLING */
<>	144:ef7eb2e8f9f7	2946	/** @brief Enables or disables the specified HRTIM common interrupts.
<>	144:ef7eb2e8f9f7	2947	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2948	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<>	144:ef7eb2e8f9f7	2949	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2950	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
<>	144:ef7eb2e8f9f7	2951	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
<>	144:ef7eb2e8f9f7	2952	* @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
<>	144:ef7eb2e8f9f7	2953	* @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
<>	144:ef7eb2e8f9f7	2954	* @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
<>	144:ef7eb2e8f9f7	2955	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
<>	144:ef7eb2e8f9f7	2956	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
<>	144:ef7eb2e8f9f7	2957	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
<>	144:ef7eb2e8f9f7	2958	* @retval None
<>	144:ef7eb2e8f9f7	2959	*/
<>	144:ef7eb2e8f9f7	2960	#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2961	#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2962
<>	144:ef7eb2e8f9f7	2963	/** @brief Enables or disables the specified HRTIM Master timer DMA requets.
<>	144:ef7eb2e8f9f7	2964	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2965	* @param __DMA__: specifies the DMA request to enable or disable.
<>	144:ef7eb2e8f9f7	2966	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2967	* @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
<>	144:ef7eb2e8f9f7	2968	* @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
<>	144:ef7eb2e8f9f7	2969	* @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
<>	144:ef7eb2e8f9f7	2970	* @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
<>	144:ef7eb2e8f9f7	2971	* @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
<>	144:ef7eb2e8f9f7	2972	* @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
<>	144:ef7eb2e8f9f7	2973	* @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
<>	144:ef7eb2e8f9f7	2974	* @retval None
<>	144:ef7eb2e8f9f7	2975	*/
<>	144:ef7eb2e8f9f7	2976	#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \|= (__DMA__))
<>	144:ef7eb2e8f9f7	2977	#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
<>	144:ef7eb2e8f9f7	2978
<>	144:ef7eb2e8f9f7	2979	/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
<>	144:ef7eb2e8f9f7	2980	* @param __HANDLE__: specifies the HRTIM Handle.
<>	144:ef7eb2e8f9f7	2981	* @param __TIMER__: specified the timing unit (Timer A to E)
<>	144:ef7eb2e8f9f7	2982	* @param __DMA__: specifies the DMA request to enable or disable.
<>	144:ef7eb2e8f9f7	2983	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2984	* @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
<>	144:ef7eb2e8f9f7	2985	* @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
<>	144:ef7eb2e8f9f7	2986	* @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
<>	144:ef7eb2e8f9f7	2987	* @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
<>	144:ef7eb2e8f9f7	2988	* @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
<>	144:ef7eb2e8f9f7	2989	* @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
<>	144:ef7eb2e8f9f7	2990	* @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
<>	144:ef7eb2e8f9f7	2991	* @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
<>	144:ef7eb2e8f9f7	2992	* @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
<>	144:ef7eb2e8f9f7	2993	* @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
<>	144:ef7eb2e8f9f7	2994	* @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
<>	144:ef7eb2e8f9f7	2995	* @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
<>	144:ef7eb2e8f9f7	2996	* @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
<>	144:ef7eb2e8f9f7	2997	* @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
<>	144:ef7eb2e8f9f7	2998	* @retval None
<>	144:ef7eb2e8f9f7	2999	*/
<>	144:ef7eb2e8f9f7	3000	#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER \|= (__DMA__))
<>	144:ef7eb2e8f9f7	3001	#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
<>	144:ef7eb2e8f9f7	3002
<>	144:ef7eb2e8f9f7	3003	#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	3004	#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	3005
<>	144:ef7eb2e8f9f7	3006	#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	3007	#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	3008
<>	144:ef7eb2e8f9f7	3009	#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	3010	#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	3011
<>	144:ef7eb2e8f9f7	3012	/** @brief Sets the HRTIM timer Counter Register value on runtime
<>	144:ef7eb2e8f9f7	3013	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3014	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3015	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3016	* @arg 0x5 for master timer
<>	144:ef7eb2e8f9f7	3017	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3018	* @param __COUNTER__: specifies the Counter Register new value.
<>	144:ef7eb2e8f9f7	3019	* @retval None
<>	144:ef7eb2e8f9f7	3020	*/
<>	144:ef7eb2e8f9f7	3021	#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
<>	144:ef7eb2e8f9f7	3022	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
<>	144:ef7eb2e8f9f7	3023	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
<>	144:ef7eb2e8f9f7	3024
<>	144:ef7eb2e8f9f7	3025	/** @brief Gets the HRTIM timer Counter Register value on runtime
<>	144:ef7eb2e8f9f7	3026	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3027	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3028	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3029	* @arg 0x5 for master timer
<>	144:ef7eb2e8f9f7	3030	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3031	* @retval HRTIM timer Counter Register value
<>	144:ef7eb2e8f9f7	3032	*/
<>	144:ef7eb2e8f9f7	3033	#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
<>	144:ef7eb2e8f9f7	3034	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
<>	144:ef7eb2e8f9f7	3035	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
<>	144:ef7eb2e8f9f7	3036
<>	144:ef7eb2e8f9f7	3037	/** @brief Sets the HRTIM timer Period value on runtime
<>	144:ef7eb2e8f9f7	3038	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3039	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3040	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3041	* @arg 0x5 for master timer
<>	144:ef7eb2e8f9f7	3042	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3043	* @param __PERIOD__: specifies the Period Register new value.
<>	144:ef7eb2e8f9f7	3044	* @retval None
<>	144:ef7eb2e8f9f7	3045	*/
<>	144:ef7eb2e8f9f7	3046	#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
<>	144:ef7eb2e8f9f7	3047	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
<>	144:ef7eb2e8f9f7	3048	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
<>	144:ef7eb2e8f9f7	3049
<>	144:ef7eb2e8f9f7	3050	/** @brief Gets the HRTIM timer Period Register value on runtime
<>	144:ef7eb2e8f9f7	3051	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3052	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3053	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3054	* @arg 0x5 for master timer
<>	144:ef7eb2e8f9f7	3055	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3056	* @retval timer Period Register
<>	144:ef7eb2e8f9f7	3057	*/
<>	144:ef7eb2e8f9f7	3058	#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
<>	144:ef7eb2e8f9f7	3059	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
<>	144:ef7eb2e8f9f7	3060	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
<>	144:ef7eb2e8f9f7	3061
<>	144:ef7eb2e8f9f7	3062	/** @brief Sets the HRTIM timer clock prescaler value on runtime
<>	144:ef7eb2e8f9f7	3063	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3064	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3065	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3066	* @arg 0x5 for master timer
<>	144:ef7eb2e8f9f7	3067	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3068	* @param __PRESCALER__: specifies the clock prescaler new value.
<>	144:ef7eb2e8f9f7	3069	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3070	* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3071	* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3072	* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3073	* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3074	* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3075	* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3076	* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3077	* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
<>	144:ef7eb2e8f9f7	3078	* @retval None
<>	144:ef7eb2e8f9f7	3079	*/
<>	144:ef7eb2e8f9f7	3080	#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
<>	144:ef7eb2e8f9f7	3081	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR \|= (__PRESCALER__)) :\
<>	144:ef7eb2e8f9f7	3082	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR \|= (__PRESCALER__)))
<>	144:ef7eb2e8f9f7	3083
<>	144:ef7eb2e8f9f7	3084	/** @brief Gets the HRTIM timer clock prescaler value on runtime
<>	144:ef7eb2e8f9f7	3085	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3086	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3087	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3088	* @arg 0x5 for master timer
<>	144:ef7eb2e8f9f7	3089	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3090	* @retval timer clock prescaler value
<>	144:ef7eb2e8f9f7	3091	*/
<>	144:ef7eb2e8f9f7	3092	#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
<>	144:ef7eb2e8f9f7	3093	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
<>	144:ef7eb2e8f9f7	3094	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
<>	144:ef7eb2e8f9f7	3095
<>	144:ef7eb2e8f9f7	3096	/** @brief Sets the HRTIM timer Compare Register value on runtime
<>	144:ef7eb2e8f9f7	3097	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3098	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3099	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3100	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3101	* @param __COMPAREUNIT__: timer compare unit
<>	144:ef7eb2e8f9f7	3102	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3103	* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
<>	144:ef7eb2e8f9f7	3104	* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
<>	144:ef7eb2e8f9f7	3105	* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
<>	144:ef7eb2e8f9f7	3106	* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
<>	144:ef7eb2e8f9f7	3107	* @param __COMPARE__: specifies the Compare new value.
<>	144:ef7eb2e8f9f7	3108	* @retval None
<>	144:ef7eb2e8f9f7	3109	*/
<>	144:ef7eb2e8f9f7	3110	#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
<>	144:ef7eb2e8f9f7	3111	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
<>	144:ef7eb2e8f9f7	3112	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	3113	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	3114	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	3115	((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
<>	144:ef7eb2e8f9f7	3116	: \
<>	144:ef7eb2e8f9f7	3117	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	3118	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	3119	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
<>	144:ef7eb2e8f9f7	3120	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
<>	144:ef7eb2e8f9f7	3121
<>	144:ef7eb2e8f9f7	3122	/** @brief Gets the HRTIM timer Compare Register value on runtime
<>	144:ef7eb2e8f9f7	3123	* @param __HANDLE__: HRTIM Handle.
<>	144:ef7eb2e8f9f7	3124	* @param __TIMER__: HRTIM timer
<>	144:ef7eb2e8f9f7	3125	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3126	* @arg 0x0 to 0x4 for timers A to E
<>	144:ef7eb2e8f9f7	3127	* @param __COMPAREUNIT__: timer compare unit
<>	144:ef7eb2e8f9f7	3128	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3129	* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
<>	144:ef7eb2e8f9f7	3130	* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
<>	144:ef7eb2e8f9f7	3131	* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
<>	144:ef7eb2e8f9f7	3132	* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
<>	144:ef7eb2e8f9f7	3133	* @retval Compare value
<>	144:ef7eb2e8f9f7	3134	*/
<>	144:ef7eb2e8f9f7	3135	#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
<>	144:ef7eb2e8f9f7	3136	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
<>	144:ef7eb2e8f9f7	3137	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
<>	144:ef7eb2e8f9f7	3138	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
<>	144:ef7eb2e8f9f7	3139	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
<>	144:ef7eb2e8f9f7	3140	((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
<>	144:ef7eb2e8f9f7	3141	: \
<>	144:ef7eb2e8f9f7	3142	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
<>	144:ef7eb2e8f9f7	3143	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
<>	144:ef7eb2e8f9f7	3144	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
<>	144:ef7eb2e8f9f7	3145	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
<>	144:ef7eb2e8f9f7	3146
<>	144:ef7eb2e8f9f7	3147	/**
<>	144:ef7eb2e8f9f7	3148	* @}
<>	144:ef7eb2e8f9f7	3149	*/
<>	144:ef7eb2e8f9f7	3150
<>	144:ef7eb2e8f9f7	3151	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3152	/** @addtogroup HRTIM_Exported_Functions
<>	144:ef7eb2e8f9f7	3153	* @{
<>	144:ef7eb2e8f9f7	3154	*/
<>	144:ef7eb2e8f9f7	3155
<>	144:ef7eb2e8f9f7	3156	/** @addtogroup HRTIM_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	3157	* @{
<>	144:ef7eb2e8f9f7	3158	*/
<>	144:ef7eb2e8f9f7	3159
<>	144:ef7eb2e8f9f7	3160	/* Initialization and Configuration functions ********************************/
<>	144:ef7eb2e8f9f7	3161	HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3162
<>	144:ef7eb2e8f9f7	3163	HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3164
<>	144:ef7eb2e8f9f7	3165	void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3166
<>	144:ef7eb2e8f9f7	3167	void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3168
<>	144:ef7eb2e8f9f7	3169	HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3170	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3171	HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
<>	144:ef7eb2e8f9f7	3172
<>	144:ef7eb2e8f9f7	3173	HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3174	uint32_t CalibrationRate);
<>	144:ef7eb2e8f9f7	3175
<>	144:ef7eb2e8f9f7	3176	HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3177	uint32_t CalibrationRate);
<>	144:ef7eb2e8f9f7	3178
<>	144:ef7eb2e8f9f7	3179	HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3180	uint32_t Timeout);
<>	144:ef7eb2e8f9f7	3181
<>	144:ef7eb2e8f9f7	3182	/**
<>	144:ef7eb2e8f9f7	3183	* @}
<>	144:ef7eb2e8f9f7	3184	*/
<>	144:ef7eb2e8f9f7	3185
<>	144:ef7eb2e8f9f7	3186	/** @addtogroup HRTIM_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	3187	* @{
<>	144:ef7eb2e8f9f7	3188	*/
<>	144:ef7eb2e8f9f7	3189
<>	144:ef7eb2e8f9f7	3190	/* Simple time base related functions *****************************************/
<>	144:ef7eb2e8f9f7	3191	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3192	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3193
<>	144:ef7eb2e8f9f7	3194	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3195	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3196
<>	144:ef7eb2e8f9f7	3197	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3198	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3199
<>	144:ef7eb2e8f9f7	3200	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3201	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3202
<>	144:ef7eb2e8f9f7	3203	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3204	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3205	uint32_t SrcAddr,
<>	144:ef7eb2e8f9f7	3206	uint32_t DestAddr,
<>	144:ef7eb2e8f9f7	3207	uint32_t Length);
<>	144:ef7eb2e8f9f7	3208
<>	144:ef7eb2e8f9f7	3209	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3210	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3211
<>	144:ef7eb2e8f9f7	3212	/**
<>	144:ef7eb2e8f9f7	3213	* @}
<>	144:ef7eb2e8f9f7	3214	*/
<>	144:ef7eb2e8f9f7	3215
<>	144:ef7eb2e8f9f7	3216	/** @addtogroup HRTIM_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	3217	* @{
<>	144:ef7eb2e8f9f7	3218	*/
<>	144:ef7eb2e8f9f7	3219	/* Simple output compare related functions ************************************/
<>	144:ef7eb2e8f9f7	3220	HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3221	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3222	uint32_t OCChannel,
<>	144:ef7eb2e8f9f7	3223	HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
<>	144:ef7eb2e8f9f7	3224
<>	144:ef7eb2e8f9f7	3225	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3226	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3227	uint32_t OCChannel);
<>	144:ef7eb2e8f9f7	3228
<>	144:ef7eb2e8f9f7	3229	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3230	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3231	uint32_t OCChannel);
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3234	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3235	uint32_t OCChannel);
<>	144:ef7eb2e8f9f7	3236
<>	144:ef7eb2e8f9f7	3237	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3238	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3239	uint32_t OCChannel);
<>	144:ef7eb2e8f9f7	3240
<>	144:ef7eb2e8f9f7	3241	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3242	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3243	uint32_t OCChannel,
<>	144:ef7eb2e8f9f7	3244	uint32_t SrcAddr,
<>	144:ef7eb2e8f9f7	3245	uint32_t DestAddr,
<>	144:ef7eb2e8f9f7	3246	uint32_t Length);
<>	144:ef7eb2e8f9f7	3247
<>	144:ef7eb2e8f9f7	3248	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3249	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3250	uint32_t OCChannel);
<>	144:ef7eb2e8f9f7	3251
<>	144:ef7eb2e8f9f7	3252	/**
<>	144:ef7eb2e8f9f7	3253	* @}
<>	144:ef7eb2e8f9f7	3254	*/
<>	144:ef7eb2e8f9f7	3255
<>	144:ef7eb2e8f9f7	3256	/** @addtogroup HRTIM_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	3257	* @{
<>	144:ef7eb2e8f9f7	3258	*/
<>	144:ef7eb2e8f9f7	3259	/* Simple PWM output related functions ****************************************/
<>	144:ef7eb2e8f9f7	3260	HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3261	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3262	uint32_t PWMChannel,
<>	144:ef7eb2e8f9f7	3263	HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
<>	144:ef7eb2e8f9f7	3264
<>	144:ef7eb2e8f9f7	3265	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3266	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3267	uint32_t PWMChannel);
<>	144:ef7eb2e8f9f7	3268
<>	144:ef7eb2e8f9f7	3269	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3270	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3271	uint32_t PWMChannel);
<>	144:ef7eb2e8f9f7	3272
<>	144:ef7eb2e8f9f7	3273	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3274	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3275	uint32_t PWMChannel);
<>	144:ef7eb2e8f9f7	3276
<>	144:ef7eb2e8f9f7	3277	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3278	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3279	uint32_t PWMChannel);
<>	144:ef7eb2e8f9f7	3280
<>	144:ef7eb2e8f9f7	3281	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3282	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3283	uint32_t PWMChannel,
<>	144:ef7eb2e8f9f7	3284	uint32_t SrcAddr,
<>	144:ef7eb2e8f9f7	3285	uint32_t DestAddr,
<>	144:ef7eb2e8f9f7	3286	uint32_t Length);
<>	144:ef7eb2e8f9f7	3287
<>	144:ef7eb2e8f9f7	3288	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3289	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3290	uint32_t PWMChannel);
<>	144:ef7eb2e8f9f7	3291
<>	144:ef7eb2e8f9f7	3292	/**
<>	144:ef7eb2e8f9f7	3293	* @}
<>	144:ef7eb2e8f9f7	3294	*/
<>	144:ef7eb2e8f9f7	3295
<>	144:ef7eb2e8f9f7	3296	/** @addtogroup HRTIM_Exported_Functions_Group5
<>	144:ef7eb2e8f9f7	3297	* @{
<>	144:ef7eb2e8f9f7	3298	*/
<>	144:ef7eb2e8f9f7	3299	/* Simple capture related functions *******************************************/
<>	144:ef7eb2e8f9f7	3300	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3301	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3302	uint32_t CaptureChannel,
<>	144:ef7eb2e8f9f7	3303	HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
<>	144:ef7eb2e8f9f7	3304
<>	144:ef7eb2e8f9f7	3305	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3306	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3307	uint32_t CaptureChannel);
<>	144:ef7eb2e8f9f7	3308
<>	144:ef7eb2e8f9f7	3309	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3310	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3311	uint32_t CaptureChannel);
<>	144:ef7eb2e8f9f7	3312
<>	144:ef7eb2e8f9f7	3313	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3314	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3315	uint32_t CaptureChannel);
<>	144:ef7eb2e8f9f7	3316
<>	144:ef7eb2e8f9f7	3317	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3318	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3319	uint32_t CaptureChannel);
<>	144:ef7eb2e8f9f7	3320
<>	144:ef7eb2e8f9f7	3321	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3322	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3323	uint32_t CaptureChannel,
<>	144:ef7eb2e8f9f7	3324	uint32_t SrcAddr,
<>	144:ef7eb2e8f9f7	3325	uint32_t DestAddr,
<>	144:ef7eb2e8f9f7	3326	uint32_t Length);
<>	144:ef7eb2e8f9f7	3327
<>	144:ef7eb2e8f9f7	3328	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3329	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3330	uint32_t CaptureChannel);
<>	144:ef7eb2e8f9f7	3331
<>	144:ef7eb2e8f9f7	3332	/**
<>	144:ef7eb2e8f9f7	3333	* @}
<>	144:ef7eb2e8f9f7	3334	*/
<>	144:ef7eb2e8f9f7	3335
<>	144:ef7eb2e8f9f7	3336	/** @addtogroup HRTIM_Exported_Functions_Group6
<>	144:ef7eb2e8f9f7	3337	* @{
<>	144:ef7eb2e8f9f7	3338	*/
<>	144:ef7eb2e8f9f7	3339	/* Simple one pulse related functions *****************************************/
<>	144:ef7eb2e8f9f7	3340	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3341	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3342	uint32_t OnePulseChannel,
<>	144:ef7eb2e8f9f7	3343	HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
<>	144:ef7eb2e8f9f7	3344
<>	144:ef7eb2e8f9f7	3345	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3346	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3347	uint32_t OnePulseChannel);
<>	144:ef7eb2e8f9f7	3348
<>	144:ef7eb2e8f9f7	3349	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3350	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3351	uint32_t OnePulseChannel);
<>	144:ef7eb2e8f9f7	3352
<>	144:ef7eb2e8f9f7	3353	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3354	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3355	uint32_t OnePulseChannel);
<>	144:ef7eb2e8f9f7	3356
<>	144:ef7eb2e8f9f7	3357	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3358	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3359	uint32_t OnePulseChannel);
<>	144:ef7eb2e8f9f7	3360
<>	144:ef7eb2e8f9f7	3361	/**
<>	144:ef7eb2e8f9f7	3362	* @}
<>	144:ef7eb2e8f9f7	3363	*/
<>	144:ef7eb2e8f9f7	3364
<>	144:ef7eb2e8f9f7	3365	/** @addtogroup HRTIM_Exported_Functions_Group7
<>	144:ef7eb2e8f9f7	3366	* @{
<>	144:ef7eb2e8f9f7	3367	*/
<>	144:ef7eb2e8f9f7	3368	HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3369	HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
<>	144:ef7eb2e8f9f7	3370
<>	144:ef7eb2e8f9f7	3371	HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3372	uint32_t Event,
<>	144:ef7eb2e8f9f7	3373	HRTIM_EventCfgTypeDef* pEventCfg);
<>	144:ef7eb2e8f9f7	3374
<>	144:ef7eb2e8f9f7	3375	HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3376	uint32_t Prescaler);
<>	144:ef7eb2e8f9f7	3377
<>	144:ef7eb2e8f9f7	3378	HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3379	uint32_t Fault,
<>	144:ef7eb2e8f9f7	3380	HRTIM_FaultCfgTypeDef* pFaultCfg);
<>	144:ef7eb2e8f9f7	3381
<>	144:ef7eb2e8f9f7	3382	HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3383	uint32_t Prescaler);
<>	144:ef7eb2e8f9f7	3384
<>	144:ef7eb2e8f9f7	3385	void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
<>	144:ef7eb2e8f9f7	3386	uint32_t Faults,
<>	144:ef7eb2e8f9f7	3387	uint32_t Enable);
<>	144:ef7eb2e8f9f7	3388
<>	144:ef7eb2e8f9f7	3389	HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3390	uint32_t ADCTrigger,
<>	144:ef7eb2e8f9f7	3391	HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
<>	144:ef7eb2e8f9f7	3392
<>	144:ef7eb2e8f9f7	3393	/**
<>	144:ef7eb2e8f9f7	3394	* @}
<>	144:ef7eb2e8f9f7	3395	*/
<>	144:ef7eb2e8f9f7	3396
<>	144:ef7eb2e8f9f7	3397	/** @addtogroup HRTIM_Exported_Functions_Group8
<>	144:ef7eb2e8f9f7	3398	* @{
<>	144:ef7eb2e8f9f7	3399	*/
<>	144:ef7eb2e8f9f7	3400	/* Waveform related functions *************************************************/
<>	144:ef7eb2e8f9f7	3401	HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3402	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3403	HRTIM_TimerCfgTypeDef * pTimerCfg);
<>	144:ef7eb2e8f9f7	3404
<>	144:ef7eb2e8f9f7	3405	HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3406	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3407	uint32_t CompareUnit,
<>	144:ef7eb2e8f9f7	3408	HRTIM_CompareCfgTypeDef* pCompareCfg);
<>	144:ef7eb2e8f9f7	3409
<>	144:ef7eb2e8f9f7	3410	HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3411	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3412	uint32_t CaptureUnit,
<>	144:ef7eb2e8f9f7	3413	HRTIM_CaptureCfgTypeDef* pCaptureCfg);
<>	144:ef7eb2e8f9f7	3414
<>	144:ef7eb2e8f9f7	3415	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3416	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3417	uint32_t Output,
<>	144:ef7eb2e8f9f7	3418	HRTIM_OutputCfgTypeDef * pOutputCfg);
<>	144:ef7eb2e8f9f7	3419
<>	144:ef7eb2e8f9f7	3420	HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3421	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3422	uint32_t Output,
<>	144:ef7eb2e8f9f7	3423	uint32_t OutputLevel);
<>	144:ef7eb2e8f9f7	3424
<>	144:ef7eb2e8f9f7	3425	HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3426	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3427	uint32_t Event,
<>	144:ef7eb2e8f9f7	3428	HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
<>	144:ef7eb2e8f9f7	3429
<>	144:ef7eb2e8f9f7	3430	HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3431	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3432	HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
<>	144:ef7eb2e8f9f7	3433
<>	144:ef7eb2e8f9f7	3434	HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3435	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3436	HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
<>	144:ef7eb2e8f9f7	3437
<>	144:ef7eb2e8f9f7	3438	HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3439	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3440	uint32_t RegistersToUpdate);
<>	144:ef7eb2e8f9f7	3441
<>	144:ef7eb2e8f9f7	3442
<>	144:ef7eb2e8f9f7	3443	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3444	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3445
<>	144:ef7eb2e8f9f7	3446	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3447	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3448
<>	144:ef7eb2e8f9f7	3449
<>	144:ef7eb2e8f9f7	3450	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3451	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3452
<>	144:ef7eb2e8f9f7	3453	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3454	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3455
<>	144:ef7eb2e8f9f7	3456
<>	144:ef7eb2e8f9f7	3457	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3458	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3459
<>	144:ef7eb2e8f9f7	3460	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3461	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3462
<>	144:ef7eb2e8f9f7	3463	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3464	uint32_t OutputsToStart);
<>	144:ef7eb2e8f9f7	3465
<>	144:ef7eb2e8f9f7	3466	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3467	uint32_t OutputsToStop);
<>	144:ef7eb2e8f9f7	3468
<>	144:ef7eb2e8f9f7	3469	HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3470	uint32_t Enable);
<>	144:ef7eb2e8f9f7	3471
<>	144:ef7eb2e8f9f7	3472	HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3473
<>	144:ef7eb2e8f9f7	3474	HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3475	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3476	uint32_t CaptureUnit);
<>	144:ef7eb2e8f9f7	3477
<>	144:ef7eb2e8f9f7	3478	HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3479	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3480
<>	144:ef7eb2e8f9f7	3481	HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3482	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3483
<>	144:ef7eb2e8f9f7	3484	HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3485	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3486	uint32_t BurstBufferAddress,
<>	144:ef7eb2e8f9f7	3487	uint32_t BurstBufferLength);
<>	144:ef7eb2e8f9f7	3488
<>	144:ef7eb2e8f9f7	3489	HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3490	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3491
<>	144:ef7eb2e8f9f7	3492	HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3493	uint32_t Timers);
<>	144:ef7eb2e8f9f7	3494
<>	144:ef7eb2e8f9f7	3495	/**
<>	144:ef7eb2e8f9f7	3496	* @}
<>	144:ef7eb2e8f9f7	3497	*/
<>	144:ef7eb2e8f9f7	3498
<>	144:ef7eb2e8f9f7	3499	/** @addtogroup HRTIM_Exported_Functions_Group9
<>	144:ef7eb2e8f9f7	3500	* @{
<>	144:ef7eb2e8f9f7	3501	*/
<>	144:ef7eb2e8f9f7	3502	/* HRTIM peripheral state functions */
<>	144:ef7eb2e8f9f7	3503	HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
<>	144:ef7eb2e8f9f7	3504
<>	144:ef7eb2e8f9f7	3505	uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3506	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3507	uint32_t CaptureUnit);
<>	144:ef7eb2e8f9f7	3508
<>	144:ef7eb2e8f9f7	3509	uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3510	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3511	uint32_t Output);
<>	144:ef7eb2e8f9f7	3512
<>	144:ef7eb2e8f9f7	3513	uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
<>	144:ef7eb2e8f9f7	3514	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3515	uint32_t Output);
<>	144:ef7eb2e8f9f7	3516
<>	144:ef7eb2e8f9f7	3517	uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3518	uint32_t TimerIdx,
<>	144:ef7eb2e8f9f7	3519	uint32_t Output);
<>	144:ef7eb2e8f9f7	3520
<>	144:ef7eb2e8f9f7	3521	uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3522
<>	144:ef7eb2e8f9f7	3523	uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3524	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3525
<>	144:ef7eb2e8f9f7	3526	uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3527	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3528
<>	144:ef7eb2e8f9f7	3529	/**
<>	144:ef7eb2e8f9f7	3530	* @}
<>	144:ef7eb2e8f9f7	3531	*/
<>	144:ef7eb2e8f9f7	3532
<>	144:ef7eb2e8f9f7	3533	/** @addtogroup HRTIM_Exported_Functions_Group10
<>	144:ef7eb2e8f9f7	3534	* @{
<>	144:ef7eb2e8f9f7	3535	*/
<>	144:ef7eb2e8f9f7	3536	/* IRQ handler */
<>	144:ef7eb2e8f9f7	3537	void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3538	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3539
<>	144:ef7eb2e8f9f7	3540	/* HRTIM events related callback functions */
<>	144:ef7eb2e8f9f7	3541	void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3542	void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3543	void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3544	void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3545	void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3546	void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3547	void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3548	void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3549	void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3550
<>	144:ef7eb2e8f9f7	3551	/* Timer events related callback functions */
<>	144:ef7eb2e8f9f7	3552	void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3553	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3554	void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3555	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3556	void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3557	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3558	void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3559	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3560	void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3561	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3562	void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3563	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3564	void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3565	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3566	void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3567	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3568	void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3569	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3570	void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3571	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3572	void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3573	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3574	void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3575	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3576	void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3577	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3578	void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3579	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3580	void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
<>	144:ef7eb2e8f9f7	3581	uint32_t TimerIdx);
<>	144:ef7eb2e8f9f7	3582	void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
<>	144:ef7eb2e8f9f7	3583
<>	144:ef7eb2e8f9f7	3584	/**
<>	144:ef7eb2e8f9f7	3585	* @}
<>	144:ef7eb2e8f9f7	3586	*/
<>	144:ef7eb2e8f9f7	3587
<>	144:ef7eb2e8f9f7	3588	/**
<>	144:ef7eb2e8f9f7	3589	* @}
<>	144:ef7eb2e8f9f7	3590	*/
<>	144:ef7eb2e8f9f7	3591
<>	144:ef7eb2e8f9f7	3592	/**
<>	144:ef7eb2e8f9f7	3593	* @}
<>	144:ef7eb2e8f9f7	3594	*/
<>	144:ef7eb2e8f9f7	3595
<>	144:ef7eb2e8f9f7	3596	/**
<>	144:ef7eb2e8f9f7	3597	* @}
<>	144:ef7eb2e8f9f7	3598	*/
<>	144:ef7eb2e8f9f7	3599
<>	144:ef7eb2e8f9f7	3600	#endif /* defined(STM32F334x8) */
<>	144:ef7eb2e8f9f7	3601
<>	144:ef7eb2e8f9f7	3602	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	3603	}
<>	144:ef7eb2e8f9f7	3604	#endif
<>	144:ef7eb2e8f9f7	3605
<>	144:ef7eb2e8f9f7	3606	#endif /* __STM32F3xx_HAL_HRTIM_H */
<>	144:ef7eb2e8f9f7	3607
<>	144:ef7eb2e8f9f7	3608	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	19 Nov 2016
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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.h@151:acf04f8e7d03, 2016-11-19 (annotated)

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