pravin sarode / Mymbed-dev

MBED-DEV only fro Nucleo STM32F303K8T6

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.h@151:acf04f8e7d03, 2016-11-19 (annotated)

Committer:
pravinautosys
Date:
Sat Nov 19 10:38:54 2016 +0000
Revision:
151:acf04f8e7d03
Parent:
149:156823d33999 
MyMBED-DEVWithSTM32F303K8T6;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_flash_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of Flash HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F3xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F3xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f3xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup FLASHEx_Private_Constants
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7CC)
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @}
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /** @addtogroup FLASHEx_Private_Macros
<> 144:ef7eb2e8f9f7 68 * @{
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
<> 144:ef7eb2e8f9f7 71 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 76 ((VALUE) == OB_WRPSTATE_ENABLE))
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
<> 144:ef7eb2e8f9f7 81 ((LEVEL) == OB_RDP_LEVEL_1))/*||\
<> 144:ef7eb2e8f9f7 82 ((LEVEL) == OB_RDP_LEVEL_2))*/
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
<> 144:ef7eb2e8f9f7 98 #define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
<> 144:ef7eb2e8f9f7 99 ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
<> 144:ef7eb2e8f9f7 100 #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
<> 144:ef7eb2e8f9f7 105 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 106 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
<> 144:ef7eb2e8f9f7 107 ((ADDRESS) <= 0x0803FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
<> 144:ef7eb2e8f9f7 108 ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
<> 144:ef7eb2e8f9f7 109 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 110 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 113 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFF))
<> 144:ef7eb2e8f9f7 114 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
<> 144:ef7eb2e8f9f7 117 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 118 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
<> 144:ef7eb2e8f9f7 119 ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
<> 144:ef7eb2e8f9f7 120 ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF))))
<> 144:ef7eb2e8f9f7 121 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 122 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
<> 144:ef7eb2e8f9f7 125 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 126 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
<> 144:ef7eb2e8f9f7 127 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
<> 144:ef7eb2e8f9f7 128 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
<> 144:ef7eb2e8f9f7 129 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 130 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 133 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF)
<> 144:ef7eb2e8f9f7 134 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
<> 144:ef7eb2e8f9f7 137 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 138 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
<> 144:ef7eb2e8f9f7 139 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
<> 144:ef7eb2e8f9f7 140 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)))
<> 144:ef7eb2e8f9f7 141 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 142 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 typedef struct
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
<> 144:ef7eb2e8f9f7 158 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
<> 144:ef7eb2e8f9f7 161 This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
<> 144:ef7eb2e8f9f7 164 This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief FLASH Options bytes program structure definition
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 typedef struct
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
<> 144:ef7eb2e8f9f7 174 This parameter can be a value of @ref FLASHEx_OB_Type */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
<> 144:ef7eb2e8f9f7 177 This parameter can be a value of @ref FLASHEx_OB_WRP_State */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
<> 144:ef7eb2e8f9f7 180 This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
<> 144:ef7eb2e8f9f7 183 This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
<> 144:ef7eb2e8f9f7 186 IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
<> 144:ef7eb2e8f9f7 187 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
<> 144:ef7eb2e8f9f7 188 @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
<> 144:ef7eb2e8f9f7 189 @ref FLASHEx_OB_RAM_Parity_Check_Enable.
<> 144:ef7eb2e8f9f7 190 @if STM32F373xC
<> 144:ef7eb2e8f9f7 191 And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
<> 144:ef7eb2e8f9f7 192 @endif
<> 144:ef7eb2e8f9f7 193 @if STM32F378xx
<> 144:ef7eb2e8f9f7 194 And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
<> 144:ef7eb2e8f9f7 195 @endif
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
<> 144:ef7eb2e8f9f7 199 This parameter can be a value of @ref FLASHEx_OB_Data_Address */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
<> 144:ef7eb2e8f9f7 202 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 203 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 209 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup FLASHEx_Page_Size FLASHEx Page Size
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define FLASH_PAGE_SIZE 0x800
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
<> 144:ef7eb2e8f9f7 225 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /** @defgroup FLASHEx_OB_Type Option Bytes Type
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
<> 144:ef7eb2e8f9f7 239 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
<> 144:ef7eb2e8f9f7 240 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
<> 144:ef7eb2e8f9f7 241 #define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
<> 144:ef7eb2e8f9f7 251 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
<> 144:ef7eb2e8f9f7 261 #define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
<> 144:ef7eb2e8f9f7 262 #define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
<> 144:ef7eb2e8f9f7 263 #define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
<> 144:ef7eb2e8f9f7 264 #define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
<> 144:ef7eb2e8f9f7 265 #define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
<> 144:ef7eb2e8f9f7 266 #define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
<> 144:ef7eb2e8f9f7 267 #define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
<> 144:ef7eb2e8f9f7 268 #define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
<> 144:ef7eb2e8f9f7 269 #define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
<> 144:ef7eb2e8f9f7 270 #define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
<> 144:ef7eb2e8f9f7 271 #define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
<> 144:ef7eb2e8f9f7 272 #define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
<> 144:ef7eb2e8f9f7 273 #define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
<> 144:ef7eb2e8f9f7 274 #define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
<> 144:ef7eb2e8f9f7 275 #define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
<> 144:ef7eb2e8f9f7 278 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 279 #define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
<> 144:ef7eb2e8f9f7 280 #define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
<> 144:ef7eb2e8f9f7 281 #define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
<> 144:ef7eb2e8f9f7 282 #define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
<> 144:ef7eb2e8f9f7 283 #define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
<> 144:ef7eb2e8f9f7 284 #define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
<> 144:ef7eb2e8f9f7 285 #define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
<> 144:ef7eb2e8f9f7 286 #define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
<> 144:ef7eb2e8f9f7 287 #define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
<> 144:ef7eb2e8f9f7 288 #define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
<> 144:ef7eb2e8f9f7 289 #define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
<> 144:ef7eb2e8f9f7 290 #define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
<> 144:ef7eb2e8f9f7 291 #define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
<> 144:ef7eb2e8f9f7 292 #define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
<> 144:ef7eb2e8f9f7 293 #define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
<> 144:ef7eb2e8f9f7 294 #define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000U) /* Write protection of page 62 to 127 */
<> 144:ef7eb2e8f9f7 295 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 296 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 299 #define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
<> 144:ef7eb2e8f9f7 300 #define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
<> 144:ef7eb2e8f9f7 301 #define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
<> 144:ef7eb2e8f9f7 302 #define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
<> 144:ef7eb2e8f9f7 303 #define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
<> 144:ef7eb2e8f9f7 304 #define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
<> 144:ef7eb2e8f9f7 305 #define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
<> 144:ef7eb2e8f9f7 306 #define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
<> 144:ef7eb2e8f9f7 307 #define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
<> 144:ef7eb2e8f9f7 308 #define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
<> 144:ef7eb2e8f9f7 309 #define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
<> 144:ef7eb2e8f9f7 310 #define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
<> 144:ef7eb2e8f9f7 311 #define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
<> 144:ef7eb2e8f9f7 312 #define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
<> 144:ef7eb2e8f9f7 313 #define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
<> 144:ef7eb2e8f9f7 314 #define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000U) /* Write protection of page 62 to 255 */
<> 144:ef7eb2e8f9f7 315 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 #define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FFU)
<> 144:ef7eb2e8f9f7 318 #define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00U)
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
<> 144:ef7eb2e8f9f7 321 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 322 #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000U)
<> 144:ef7eb2e8f9f7 323 #define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000U)
<> 144:ef7eb2e8f9f7 324 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 325 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 328 #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000U)
<> 144:ef7eb2e8f9f7 329 #define OB_WRP_PAGES48TO255MASK ((uint32_t)0xFF000000U)
<> 144:ef7eb2e8f9f7 330 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
<> 144:ef7eb2e8f9f7 333 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 334 #define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000U)
<> 144:ef7eb2e8f9f7 335 #define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000U)
<> 144:ef7eb2e8f9f7 336 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 337 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
<> 144:ef7eb2e8f9f7 340 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
<> 144:ef7eb2e8f9f7 341 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 342 #define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< Write protection of all pages */
<> 144:ef7eb2e8f9f7 343 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 344 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 345 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
<> 144:ef7eb2e8f9f7 348 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 349 #define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */
<> 144:ef7eb2e8f9f7 350 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 351 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
<> 144:ef7eb2e8f9f7 358 * @{
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 #define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
<> 144:ef7eb2e8f9f7 361 #define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
<> 144:ef7eb2e8f9f7 362 #define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
<> 144:ef7eb2e8f9f7 363 it's no more possible to go back to level 1 or 0 */
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @}
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
<> 144:ef7eb2e8f9f7 369 * @{
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
<> 144:ef7eb2e8f9f7 372 #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 381 #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @}
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
<> 144:ef7eb2e8f9f7 387 * @{
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389 #define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 390 #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
<> 144:ef7eb2e8f9f7 396 * @{
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 #define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
<> 144:ef7eb2e8f9f7 399 #define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
<> 144:ef7eb2e8f9f7 405 * @{
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 #define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
<> 144:ef7eb2e8f9f7 408 #define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
<> 144:ef7eb2e8f9f7 409 /**
<> 144:ef7eb2e8f9f7 410 * @}
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
<> 144:ef7eb2e8f9f7 414 * @{
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 #define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity check enable set */
<> 144:ef7eb2e8f9f7 417 #define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity check enable reset */
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 #if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
<> 144:ef7eb2e8f9f7 424 /** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR OB SDADC12 VDD MONITOR
<> 144:ef7eb2e8f9f7 425 * @{
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00) /*!< SDADC VDD Monitor reset */
<> 144:ef7eb2e8f9f7 428 #define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80) /*!< SDADC VDD Monitor set */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /**
<> 144:ef7eb2e8f9f7 431 * @}
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
<> 144:ef7eb2e8f9f7 436 * @{
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 #define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
<> 144:ef7eb2e8f9f7 439 #define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @}
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /**
<> 144:ef7eb2e8f9f7 449 * @}
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 453 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 454 * @{
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 458 * @{
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 461 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 144:ef7eb2e8f9f7 462 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 469 * @{
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 472 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 474 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 475 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @}
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @}
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /**
<> 144:ef7eb2e8f9f7 486 * @}
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @}
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 #endif
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 #endif /* __STM32F3xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 500