Mymbed-dev - MBED-DEV only fro Nucleo STM32F303K8T6

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MBED-DEV only fro Nucleo STM32F303K8T6

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sdadc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.c@144:ef7eb2e8f9f7

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_sdadc.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.3.0
<>	144:ef7eb2e8f9f7	6	* @date 01-July-2016
<>	144:ef7eb2e8f9f7	7	* @brief This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	8	* functionalities of the Sigma-Delta Analog to Digital Converter
<>	144:ef7eb2e8f9f7	9	* (SDADC) peripherals:
<>	144:ef7eb2e8f9f7	10	* + Initialization and Configuration
<>	144:ef7eb2e8f9f7	11	* + Regular Channels Configuration
<>	144:ef7eb2e8f9f7	12	* + Injected channels Configuration
<>	144:ef7eb2e8f9f7	13	* + Power saving
<>	144:ef7eb2e8f9f7	14	* + Regular/Injected Channels DMA Configuration
<>	144:ef7eb2e8f9f7	15	* + Interrupts and flags management
<>	144:ef7eb2e8f9f7	16	@verbatim
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	##### SDADC specific features #####
<>	144:ef7eb2e8f9f7	19	==============================================================================
<>	144:ef7eb2e8f9f7	20	[..]
<>	144:ef7eb2e8f9f7	21	(#) 16-bit sigma delta architecture.
<>	144:ef7eb2e8f9f7	22	(#) Self calibration.
<>	144:ef7eb2e8f9f7	23	(#) Interrupt generation at the end of calibration, regular/injected conversion
<>	144:ef7eb2e8f9f7	24	and in case of overrun events.
<>	144:ef7eb2e8f9f7	25	(#) Single and continuous conversion modes.
<>	144:ef7eb2e8f9f7	26	(#) External trigger option with configurable polarity for injected conversion.
<>	144:ef7eb2e8f9f7	27	(#) Multi mode (synchronized another SDADC with SDADC1).
<>	144:ef7eb2e8f9f7	28	(#) DMA request generation during regular or injected channel conversion.
<>	144:ef7eb2e8f9f7	29
<>	144:ef7eb2e8f9f7	30	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	31	==============================================================================
<>	144:ef7eb2e8f9f7	32	[..]
<>	144:ef7eb2e8f9f7	33	* Initialization *
<>	144:ef7eb2e8f9f7	34	======================
<>	144:ef7eb2e8f9f7	35	[..]
<>	144:ef7eb2e8f9f7	36	(#) As prerequisite, fill in the HAL_SDADC_MspInit() :
<>	144:ef7eb2e8f9f7	37	(++) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	38	(++) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
<>	144:ef7eb2e8f9f7	39	(++) Enable power on SDADC with HAL_PWREx_EnableSDADC().
<>	144:ef7eb2e8f9f7	40	(++) Enable the clocks for the SDADC GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	41	(++) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
<>	144:ef7eb2e8f9f7	42	(++) If interrupt mode is used, enable and configure SDADC global
<>	144:ef7eb2e8f9f7	43	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<>	144:ef7eb2e8f9f7	44	(++) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
<>	144:ef7eb2e8f9f7	45	with SDADC handle using __HAL_LINKDMA.
<>	144:ef7eb2e8f9f7	46	(#) Configure the SDADC low power mode, fast conversion mode, slow clock
<>	144:ef7eb2e8f9f7	47	mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
<>	144:ef7eb2e8f9f7	48	Note: Common reference voltage. is common to all SDADC instances.
<>	144:ef7eb2e8f9f7	49	(#) Prepare channel configurations (input mode, common mode, gain and
<>	144:ef7eb2e8f9f7	50	offset) using HAL_SDADC_PrepareChannelConfig and associate channel
<>	144:ef7eb2e8f9f7	51	with one configuration using HAL_SDADC_AssociateChannelConfig.
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	* Calibration *
<>	144:ef7eb2e8f9f7	54	============================================
<>	144:ef7eb2e8f9f7	55	[..]
<>	144:ef7eb2e8f9f7	56	(#) Start calibration using HAL_SDADC_StartCalibration or
<>	144:ef7eb2e8f9f7	57	HAL_SDADC_CalibrationStart_IT.
<>	144:ef7eb2e8f9f7	58	(#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
<>	144:ef7eb2e8f9f7	59	calibration.
<>	144:ef7eb2e8f9f7	60	(#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
<>	144:ef7eb2e8f9f7	61	the end of calibration.
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	* Regular channel conversion *
<>	144:ef7eb2e8f9f7	64	============================================
<>	144:ef7eb2e8f9f7	65	[..]
<>	144:ef7eb2e8f9f7	66	(#) Select trigger for regular conversion using
<>	144:ef7eb2e8f9f7	67	HAL_SDADC_SelectRegularTrigger.
<>	144:ef7eb2e8f9f7	68	(#) Select regular channel and enable/disable continuous mode using
<>	144:ef7eb2e8f9f7	69	HAL_SDADC_ConfigChannel.
<>	144:ef7eb2e8f9f7	70	(#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
<>	144:ef7eb2e8f9f7	71	or HAL_SDADC_Start_DMA.
<>	144:ef7eb2e8f9f7	72	(#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
<>	144:ef7eb2e8f9f7	73	regular conversion.
<>	144:ef7eb2e8f9f7	74	(#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
<>	144:ef7eb2e8f9f7	75	end of regular conversion.
<>	144:ef7eb2e8f9f7	76	(#) Get value of regular conversion using HAL_SDADC_GetValue.
<>	144:ef7eb2e8f9f7	77	(#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
<>	144:ef7eb2e8f9f7	78	HAL_SDADC_ConvCpltCallback will be called respectively at the half
<>	144:ef7eb2e8f9f7	79	transfer and at the transfer complete.
<>	144:ef7eb2e8f9f7	80	(#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
<>	144:ef7eb2e8f9f7	81	or HAL_SDADC_Stop_DMA.
<>	144:ef7eb2e8f9f7	82
<>	144:ef7eb2e8f9f7	83	* Injected channels conversion *
<>	144:ef7eb2e8f9f7	84	============================================
<>	144:ef7eb2e8f9f7	85	[..]
<>	144:ef7eb2e8f9f7	86	(#) Enable/disable delay on injected conversion using
<>	144:ef7eb2e8f9f7	87	HAL_SDADC_SelectInjectedDelay.
<>	144:ef7eb2e8f9f7	88	(#) If external trigger is used for injected conversion, configure this
<>	144:ef7eb2e8f9f7	89	trigger using HAL_SDADC_SelectInjectedExtTrigger.
<>	144:ef7eb2e8f9f7	90	(#) Select trigger for injected conversion using
<>	144:ef7eb2e8f9f7	91	HAL_SDADC_SelectInjectedTrigger.
<>	144:ef7eb2e8f9f7	92	(#) Select injected channels and enable/disable continuous mode using
<>	144:ef7eb2e8f9f7	93	HAL_SDADC_InjectedConfigChannel.
<>	144:ef7eb2e8f9f7	94	(#) Start injected conversion using HAL_SDADC_InjectedStart,
<>	144:ef7eb2e8f9f7	95	HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
<>	144:ef7eb2e8f9f7	96	(#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
<>	144:ef7eb2e8f9f7	97	end of injected conversion.
<>	144:ef7eb2e8f9f7	98	(#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
<>	144:ef7eb2e8f9f7	99	at the end of injected conversion.
<>	144:ef7eb2e8f9f7	100	(#) Get value of injected conversion and corresponding channel using
<>	144:ef7eb2e8f9f7	101	HAL_SDADC_InjectedGetValue.
<>	144:ef7eb2e8f9f7	102	(#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
<>	144:ef7eb2e8f9f7	103	HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
<>	144:ef7eb2e8f9f7	104	half transfer and at the transfer complete.
<>	144:ef7eb2e8f9f7	105	(#) Stop injected conversion using HAL_SDADC_InjectedStop,
<>	144:ef7eb2e8f9f7	106	HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	* Multi mode regular channels conversions *
<>	144:ef7eb2e8f9f7	109	======================================================
<>	144:ef7eb2e8f9f7	110	[..]
<>	144:ef7eb2e8f9f7	111	(#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
<>	144:ef7eb2e8f9f7	112	HAL_SDADC_MultiModeConfigChannel.
<>	144:ef7eb2e8f9f7	113	(#) Select software trigger for SDADC1 and synchronized trigger for
<>	144:ef7eb2e8f9f7	114	SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
<>	144:ef7eb2e8f9f7	115	(#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
<>	144:ef7eb2e8f9f7	116	HAL_SDADC_ConfigChannel.
<>	144:ef7eb2e8f9f7	117	(#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
<>	144:ef7eb2e8f9f7	118	(#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
<>	144:ef7eb2e8f9f7	119	HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
<>	144:ef7eb2e8f9f7	120	(#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
<>	144:ef7eb2e8f9f7	121	regular conversion for SDADC1.
<>	144:ef7eb2e8f9f7	122	(#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
<>	144:ef7eb2e8f9f7	123	end of regular conversion for SDADC1.
<>	144:ef7eb2e8f9f7	124	(#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
<>	144:ef7eb2e8f9f7	125	(#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
<>	144:ef7eb2e8f9f7	126	HAL_SDADC_ConvCpltCallback will be called respectively at the half
<>	144:ef7eb2e8f9f7	127	transfer and at the transfer complete for SDADC1.
<>	144:ef7eb2e8f9f7	128	(#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
<>	144:ef7eb2e8f9f7	129	or HAL_SDADC_MultiModeStop_DMA for SDADC1.
<>	144:ef7eb2e8f9f7	130	(#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	* Multi mode injected channels conversions *
<>	144:ef7eb2e8f9f7	133	======================================================
<>	144:ef7eb2e8f9f7	134	[..]
<>	144:ef7eb2e8f9f7	135	(#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
<>	144:ef7eb2e8f9f7	136	HAL_SDADC_InjectedMultiModeConfigChannel.
<>	144:ef7eb2e8f9f7	137	(#) Select software or external trigger for SDADC1 and synchronized
<>	144:ef7eb2e8f9f7	138	trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
<>	144:ef7eb2e8f9f7	139	(#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
<>	144:ef7eb2e8f9f7	140	HAL_SDADC_InjectedConfigChannel.
<>	144:ef7eb2e8f9f7	141	(#) Start injected conversion for SDADC2 (or SDADC3) with
<>	144:ef7eb2e8f9f7	142	HAL_SDADC_InjectedStart.
<>	144:ef7eb2e8f9f7	143	(#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
<>	144:ef7eb2e8f9f7	144	HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
<>	144:ef7eb2e8f9f7	145	(#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
<>	144:ef7eb2e8f9f7	146	the end of injected conversion for SDADC1.
<>	144:ef7eb2e8f9f7	147	(#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
<>	144:ef7eb2e8f9f7	148	at the end of injected conversion for SDADC1.
<>	144:ef7eb2e8f9f7	149	(#) Get value of injected conversions using
<>	144:ef7eb2e8f9f7	150	HAL_SDADC_InjectedMultiModeGetValue.
<>	144:ef7eb2e8f9f7	151	(#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
<>	144:ef7eb2e8f9f7	152	HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
<>	144:ef7eb2e8f9f7	153	half transfer and at the transfer complete for SDADC1.
<>	144:ef7eb2e8f9f7	154	(#) Stop injected conversion using HAL_SDADC_InjectedStop,
<>	144:ef7eb2e8f9f7	155	HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
<>	144:ef7eb2e8f9f7	156	for SDADC1.
<>	144:ef7eb2e8f9f7	157	(#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
<>	144:ef7eb2e8f9f7	158	(or SDADC3).
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	@endverbatim
<>	144:ef7eb2e8f9f7	161	******************************************************************************
<>	144:ef7eb2e8f9f7	162	* @attention
<>	144:ef7eb2e8f9f7	163	*
<>	144:ef7eb2e8f9f7	164	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	165	*
<>	144:ef7eb2e8f9f7	166	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	167	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	168	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	169	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	170	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	171	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	172	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	173	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	174	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	175	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	176	*
<>	144:ef7eb2e8f9f7	177	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	178	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	179	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	180	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	181	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	182	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	183	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	184	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	185	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	186	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	187	*
<>	144:ef7eb2e8f9f7	188	******************************************************************************
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	192	#include "stm32f3xx_hal.h"
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	195	* @{
<>	144:ef7eb2e8f9f7	196	*/
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	#ifdef HAL_SDADC_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	199	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	200	/** @defgroup SDADC SDADC
<>	144:ef7eb2e8f9f7	201	* @brief SDADC HAL driver modules
<>	144:ef7eb2e8f9f7	202	* @{
<>	144:ef7eb2e8f9f7	203	*/
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	206	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	207	/** @defgroup SDADC_Private_Define SDADC Private Define
<>	144:ef7eb2e8f9f7	208	* @{
<>	144:ef7eb2e8f9f7	209	*/
<>	144:ef7eb2e8f9f7	210	#define SDADC_TIMEOUT 200
<>	144:ef7eb2e8f9f7	211	#define SDADC_CONFREG_OFFSET 0x00000020
<>	144:ef7eb2e8f9f7	212	#define SDADC_JDATAR_CH_OFFSET 24
<>	144:ef7eb2e8f9f7	213	#define SDADC_MSB_MASK 0xFFFF0000U
<>	144:ef7eb2e8f9f7	214	#define SDADC_LSB_MASK 0x0000FFFFU
<>	144:ef7eb2e8f9f7	215	/**
<>	144:ef7eb2e8f9f7	216	* @}
<>	144:ef7eb2e8f9f7	217	*/
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	220	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	221	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	222	/** @defgroup SDADC_Private_Functions SDADC Private Functions
<>	144:ef7eb2e8f9f7	223	* @{
<>	144:ef7eb2e8f9f7	224	*/
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc);
<>	144:ef7eb2e8f9f7	227	static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc);
<>	144:ef7eb2e8f9f7	228	static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels);
<>	144:ef7eb2e8f9f7	229	static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc);
<>	144:ef7eb2e8f9f7	230	static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc);
<>	144:ef7eb2e8f9f7	231	static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc);
<>	144:ef7eb2e8f9f7	232	static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc);
<>	144:ef7eb2e8f9f7	233	static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	234	static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	235	static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	236	static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	237	static void SDADC_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	238	/**
<>	144:ef7eb2e8f9f7	239	* @}
<>	144:ef7eb2e8f9f7	240	*/
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244	/** @defgroup SDADC_Exported_Functions SDADC Exported Functions
<>	144:ef7eb2e8f9f7	245	* @{
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	/** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	249	* @brief Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	250	*
<>	144:ef7eb2e8f9f7	251	@verbatim
<>	144:ef7eb2e8f9f7	252	===============================================================================
<>	144:ef7eb2e8f9f7	253	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	254	===============================================================================
<>	144:ef7eb2e8f9f7	255	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	256	(+) Initialize the SDADC.
<>	144:ef7eb2e8f9f7	257	(+) De-initialize the SDADC.
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	@endverbatim
<>	144:ef7eb2e8f9f7	260	* @{
<>	144:ef7eb2e8f9f7	261	*/
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	/**
<>	144:ef7eb2e8f9f7	264	* @brief Initializes the SDADC according to the specified
<>	144:ef7eb2e8f9f7	265	* parameters in the SDADC_InitTypeDef structure.
<>	144:ef7eb2e8f9f7	266	* @note If multiple SDADC are used, please configure first SDADC1 to set
<>	144:ef7eb2e8f9f7	267	* the common reference voltage.
<>	144:ef7eb2e8f9f7	268	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	269	* @retval HAL status.
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271	HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	272	{
<>	144:ef7eb2e8f9f7	273	/* Check parameters */
<>	144:ef7eb2e8f9f7	274	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	275	assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
<>	144:ef7eb2e8f9f7	276	assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
<>	144:ef7eb2e8f9f7	277	assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
<>	144:ef7eb2e8f9f7	278	assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* Check SDADC handle */
<>	144:ef7eb2e8f9f7	281	if(hsdadc == NULL)
<>	144:ef7eb2e8f9f7	282	{
<>	144:ef7eb2e8f9f7	283	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	284	}
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/* Initialize SDADC variables with default values */
<>	144:ef7eb2e8f9f7	287	hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
<>	144:ef7eb2e8f9f7	288	hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
<>	144:ef7eb2e8f9f7	289	hsdadc->InjectedChannelsNbr = 1;
<>	144:ef7eb2e8f9f7	290	hsdadc->InjConvRemaining = 1;
<>	144:ef7eb2e8f9f7	291	hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER;
<>	144:ef7eb2e8f9f7	292	hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER;
<>	144:ef7eb2e8f9f7	293	hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE;
<>	144:ef7eb2e8f9f7	294	hsdadc->RegularMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
<>	144:ef7eb2e8f9f7	295	hsdadc->InjectedMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
<>	144:ef7eb2e8f9f7	296	hsdadc->ErrorCode = SDADC_ERROR_NONE;
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	/* Call MSP init function */
<>	144:ef7eb2e8f9f7	299	HAL_SDADC_MspInit(hsdadc);
<>	144:ef7eb2e8f9f7	300
<>	144:ef7eb2e8f9f7	301	/* Set idle low power and slow clock modes */
<>	144:ef7eb2e8f9f7	302	hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI\|SDADC_CR1_PDI\|SDADC_CR1_SLOWCK);
<>	144:ef7eb2e8f9f7	303	hsdadc->Instance->CR1 \|= (hsdadc->Init.IdleLowPowerMode \| \
<>	144:ef7eb2e8f9f7	304	hsdadc->Init.SlowClockMode);
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	/* Set fast conversion mode */
<>	144:ef7eb2e8f9f7	307	hsdadc->Instance->CR2 &= ~(SDADC_CR2_FAST);
<>	144:ef7eb2e8f9f7	308	hsdadc->Instance->CR2 \|= hsdadc->Init.FastConversionMode;
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/* Set reference voltage common to all SDADC instances */
<>	144:ef7eb2e8f9f7	311	/* Update this parameter only if needed to avoid unnecessary settling time */
<>	144:ef7eb2e8f9f7	312	if((SDADC1->CR1 & SDADC_CR1_REFV) != hsdadc->Init.ReferenceVoltage)
<>	144:ef7eb2e8f9f7	313	{
<>	144:ef7eb2e8f9f7	314	/* Voltage reference bits are common to all SADC instances but are */
<>	144:ef7eb2e8f9f7	315	/* present in SDADC1 register. */
<>	144:ef7eb2e8f9f7	316	SDADC1->CR1 &= ~(SDADC_CR1_REFV);
<>	144:ef7eb2e8f9f7	317	SDADC1->CR1 \|= hsdadc->Init.ReferenceVoltage;
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/* Wait at least 2ms before setting ADON */
<>	144:ef7eb2e8f9f7	320	HAL_Delay(2);
<>	144:ef7eb2e8f9f7	321	}
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	/* Enable SDADC */
<>	144:ef7eb2e8f9f7	324	hsdadc->Instance->CR2 \|= SDADC_CR2_ADON;
<>	144:ef7eb2e8f9f7	325
<>	144:ef7eb2e8f9f7	326	/* Wait end of stabilization */
<>	144:ef7eb2e8f9f7	327	while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0)
<>	144:ef7eb2e8f9f7	328	{
<>	144:ef7eb2e8f9f7	329	}
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/* Set SDADC to ready state */
<>	144:ef7eb2e8f9f7	332	hsdadc->State = HAL_SDADC_STATE_READY;
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	/* Return HAL status */
<>	144:ef7eb2e8f9f7	335	return HAL_OK;
<>	144:ef7eb2e8f9f7	336	}
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/**
<>	144:ef7eb2e8f9f7	339	* @brief De-initializes the SDADC.
<>	144:ef7eb2e8f9f7	340	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	341	* @retval HAL status.
<>	144:ef7eb2e8f9f7	342	*/
<>	144:ef7eb2e8f9f7	343	HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	344	{
<>	144:ef7eb2e8f9f7	345	/* Check parameters */
<>	144:ef7eb2e8f9f7	346	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/* Check SDADC handle */
<>	144:ef7eb2e8f9f7	349	if(hsdadc == NULL)
<>	144:ef7eb2e8f9f7	350	{
<>	144:ef7eb2e8f9f7	351	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	352	}
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Disable the SDADC */
<>	144:ef7eb2e8f9f7	355	hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/* Reset all registers */
<>	144:ef7eb2e8f9f7	358	hsdadc->Instance->CR1 = 0x00000000;
<>	144:ef7eb2e8f9f7	359	hsdadc->Instance->CR2 = 0x00000000;
<>	144:ef7eb2e8f9f7	360	hsdadc->Instance->JCHGR = 0x00000001;
<>	144:ef7eb2e8f9f7	361	hsdadc->Instance->CONF0R = 0x00000000;
<>	144:ef7eb2e8f9f7	362	hsdadc->Instance->CONF1R = 0x00000000;
<>	144:ef7eb2e8f9f7	363	hsdadc->Instance->CONF2R = 0x00000000;
<>	144:ef7eb2e8f9f7	364	hsdadc->Instance->CONFCHR1 = 0x00000000;
<>	144:ef7eb2e8f9f7	365	hsdadc->Instance->CONFCHR2 = 0x00000000;
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/* Call MSP deinit function */
<>	144:ef7eb2e8f9f7	368	HAL_SDADC_MspDeInit(hsdadc);
<>	144:ef7eb2e8f9f7	369
<>	144:ef7eb2e8f9f7	370	/* Set SDADC in reset state */
<>	144:ef7eb2e8f9f7	371	hsdadc->State = HAL_SDADC_STATE_RESET;
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/* Return function status */
<>	144:ef7eb2e8f9f7	374	return HAL_OK;
<>	144:ef7eb2e8f9f7	375	}
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	/**
<>	144:ef7eb2e8f9f7	378	* @brief Initializes the SDADC MSP.
<>	144:ef7eb2e8f9f7	379	* @param hsdadc: SDADC handle
<>	144:ef7eb2e8f9f7	380	* @retval None
<>	144:ef7eb2e8f9f7	381	*/
<>	144:ef7eb2e8f9f7	382	__weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	383	{
<>	144:ef7eb2e8f9f7	384	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	385	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	388	the HAL_SDADC_MspInit could be implemented in the user file.
<>	144:ef7eb2e8f9f7	389	*/
<>	144:ef7eb2e8f9f7	390	}
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	/**
<>	144:ef7eb2e8f9f7	393	* @brief De-initializes the SDADC MSP.
<>	144:ef7eb2e8f9f7	394	* @param hsdadc: SDADC handle
<>	144:ef7eb2e8f9f7	395	* @retval None
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397	__weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	398	{
<>	144:ef7eb2e8f9f7	399	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	400	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	403	the HAL_SDADC_MspDeInit could be implemented in the user file.
<>	144:ef7eb2e8f9f7	404	*/
<>	144:ef7eb2e8f9f7	405	}
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/**
<>	144:ef7eb2e8f9f7	408	* @}
<>	144:ef7eb2e8f9f7	409	*/
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	/** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
<>	144:ef7eb2e8f9f7	412	* @brief Peripheral control functions
<>	144:ef7eb2e8f9f7	413	*
<>	144:ef7eb2e8f9f7	414	@verbatim
<>	144:ef7eb2e8f9f7	415	===============================================================================
<>	144:ef7eb2e8f9f7	416	##### Peripheral control functions #####
<>	144:ef7eb2e8f9f7	417	===============================================================================
<>	144:ef7eb2e8f9f7	418	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	419	(+) Program one of the three different configurations for channels.
<>	144:ef7eb2e8f9f7	420	(+) Associate channel to one of configurations.
<>	144:ef7eb2e8f9f7	421	(+) Select regular and injected channels.
<>	144:ef7eb2e8f9f7	422	(+) Enable/disable continuous mode for regular and injected conversions.
<>	144:ef7eb2e8f9f7	423	(+) Select regular and injected triggers.
<>	144:ef7eb2e8f9f7	424	(+) Select and configure injected external trigger.
<>	144:ef7eb2e8f9f7	425	(+) Enable/disable delay addition for injected conversions.
<>	144:ef7eb2e8f9f7	426	(+) Configure multimode.
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	@endverbatim
<>	144:ef7eb2e8f9f7	429	* @{
<>	144:ef7eb2e8f9f7	430	*/
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/**
<>	144:ef7eb2e8f9f7	433	* @brief This function allows the user to set parameters for a configuration.
<>	144:ef7eb2e8f9f7	434	* Parameters are input mode, common mode, gain and offset.
<>	144:ef7eb2e8f9f7	435	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	436	* (neither calibration nor regular or injected conversion ongoing)
<>	144:ef7eb2e8f9f7	437	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	438	* @param ConfIndex: Index of configuration to modify.
<>	144:ef7eb2e8f9f7	439	* This parameter can be a value of @ref SDADC_ConfIndex.
<>	144:ef7eb2e8f9f7	440	* @param ConfParamStruct: Parameters to apply for this configuration.
<>	144:ef7eb2e8f9f7	441	* @retval HAL status
<>	144:ef7eb2e8f9f7	442	*/
<>	144:ef7eb2e8f9f7	443	HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	444	uint32_t ConfIndex,
<>	144:ef7eb2e8f9f7	445	SDADC_ConfParamTypeDef* ConfParamStruct)
<>	144:ef7eb2e8f9f7	446	{
<>	144:ef7eb2e8f9f7	447	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	448	uint32_t tmp = 0;
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/* Check parameters */
<>	144:ef7eb2e8f9f7	451	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	452	assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
<>	144:ef7eb2e8f9f7	453	assert_param(ConfParamStruct != NULL);
<>	144:ef7eb2e8f9f7	454	assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode));
<>	144:ef7eb2e8f9f7	455	assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain));
<>	144:ef7eb2e8f9f7	456	assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode));
<>	144:ef7eb2e8f9f7	457	assert_param(IS_SDADC_OFFSET_VALUE(ConfParamStruct->Offset));
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/* Check SDADC state is ready */
<>	144:ef7eb2e8f9f7	460	if(hsdadc->State != HAL_SDADC_STATE_READY)
<>	144:ef7eb2e8f9f7	461	{
<>	144:ef7eb2e8f9f7	462	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	463	}
<>	144:ef7eb2e8f9f7	464	else
<>	144:ef7eb2e8f9f7	465	{
<>	144:ef7eb2e8f9f7	466	/* Enter init mode */
<>	144:ef7eb2e8f9f7	467	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	468	{
<>	144:ef7eb2e8f9f7	469	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	470	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	471	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	472	}
<>	144:ef7eb2e8f9f7	473	else
<>	144:ef7eb2e8f9f7	474	{
<>	144:ef7eb2e8f9f7	475	/* Program configuration register with parameters */
<>	144:ef7eb2e8f9f7	476	tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
<>	144:ef7eb2e8f9f7	477	SDADC_CONFREG_OFFSET + \
<>	144:ef7eb2e8f9f7	478	(uint32_t)(ConfIndex << 2));
<>	144:ef7eb2e8f9f7	479	(__IO uint32_t ) (tmp) = (uint32_t) (ConfParamStruct->InputMode \| \
<>	144:ef7eb2e8f9f7	480	ConfParamStruct->Gain \| \
<>	144:ef7eb2e8f9f7	481	ConfParamStruct->CommonMode \| \
<>	144:ef7eb2e8f9f7	482	ConfParamStruct->Offset);
<>	144:ef7eb2e8f9f7	483	/* Exit init mode */
<>	144:ef7eb2e8f9f7	484	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	485	}
<>	144:ef7eb2e8f9f7	486	}
<>	144:ef7eb2e8f9f7	487	/* Return function status */
<>	144:ef7eb2e8f9f7	488	return status;
<>	144:ef7eb2e8f9f7	489	}
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	/**
<>	144:ef7eb2e8f9f7	492	* @brief This function allows the user to associate a channel with one of the
<>	144:ef7eb2e8f9f7	493	* available configurations.
<>	144:ef7eb2e8f9f7	494	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	495	* (neither calibration nor regular or injected conversion ongoing)
<>	144:ef7eb2e8f9f7	496	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	497	* @param Channel: Channel to associate with configuration.
<>	144:ef7eb2e8f9f7	498	* This parameter can be a value of @ref SDADC_Channel_Selection.
<>	144:ef7eb2e8f9f7	499	* @param ConfIndex: Index of configuration to associate with channel.
<>	144:ef7eb2e8f9f7	500	* This parameter can be a value of @ref SDADC_ConfIndex.
<>	144:ef7eb2e8f9f7	501	* @retval HAL status
<>	144:ef7eb2e8f9f7	502	*/
<>	144:ef7eb2e8f9f7	503	HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	504	uint32_t Channel,
<>	144:ef7eb2e8f9f7	505	uint32_t ConfIndex)
<>	144:ef7eb2e8f9f7	506	{
<>	144:ef7eb2e8f9f7	507	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	508	uint32_t channelnum = 0;
<>	144:ef7eb2e8f9f7	509
<>	144:ef7eb2e8f9f7	510	/* Check parameters */
<>	144:ef7eb2e8f9f7	511	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	512	assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
<>	144:ef7eb2e8f9f7	513	assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
<>	144:ef7eb2e8f9f7	514
<>	144:ef7eb2e8f9f7	515	/* Check SDADC state is ready */
<>	144:ef7eb2e8f9f7	516	if(hsdadc->State != HAL_SDADC_STATE_READY)
<>	144:ef7eb2e8f9f7	517	{
<>	144:ef7eb2e8f9f7	518	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	519	}
<>	144:ef7eb2e8f9f7	520	else
<>	144:ef7eb2e8f9f7	521	{
<>	144:ef7eb2e8f9f7	522	/* Enter init mode */
<>	144:ef7eb2e8f9f7	523	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	524	{
<>	144:ef7eb2e8f9f7	525	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	526	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	527	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	528	}
<>	144:ef7eb2e8f9f7	529	else
<>	144:ef7eb2e8f9f7	530	{
<>	144:ef7eb2e8f9f7	531	/* Program channel configuration register according parameters */
<>	144:ef7eb2e8f9f7	532	if(Channel != SDADC_CHANNEL_8)
<>	144:ef7eb2e8f9f7	533	{
<>	144:ef7eb2e8f9f7	534	/* Get channel number */
<>	144:ef7eb2e8f9f7	535	channelnum = (uint32_t)(Channel>>16);
<>	144:ef7eb2e8f9f7	536
<>	144:ef7eb2e8f9f7	537	/* Set the channel configuration */
<>	144:ef7eb2e8f9f7	538	hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2));
<>	144:ef7eb2e8f9f7	539	hsdadc->Instance->CONFCHR1 \|= (uint32_t) (ConfIndex << (channelnum << 2));
<>	144:ef7eb2e8f9f7	540	}
<>	144:ef7eb2e8f9f7	541	else
<>	144:ef7eb2e8f9f7	542	{
<>	144:ef7eb2e8f9f7	543	hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
<>	144:ef7eb2e8f9f7	544	}
<>	144:ef7eb2e8f9f7	545	/* Exit init mode */
<>	144:ef7eb2e8f9f7	546	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	547	}
<>	144:ef7eb2e8f9f7	548	}
<>	144:ef7eb2e8f9f7	549	/* Return function status */
<>	144:ef7eb2e8f9f7	550	return status;
<>	144:ef7eb2e8f9f7	551	}
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/**
<>	144:ef7eb2e8f9f7	554	* @brief This function allows to select channel for regular conversion and
<>	144:ef7eb2e8f9f7	555	* to enable/disable continuous mode for regular conversion.
<>	144:ef7eb2e8f9f7	556	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	557	* @param Channel: Channel for regular conversion.
<>	144:ef7eb2e8f9f7	558	* This parameter can be a value of @ref SDADC_Channel_Selection.
<>	144:ef7eb2e8f9f7	559	* @param ContinuousMode: Enable/disable continuous mode for regular conversion.
<>	144:ef7eb2e8f9f7	560	* This parameter can be a value of @ref SDADC_ContinuousMode.
<>	144:ef7eb2e8f9f7	561	* @retval HAL status
<>	144:ef7eb2e8f9f7	562	*/
<>	144:ef7eb2e8f9f7	563	HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	564	uint32_t Channel,
<>	144:ef7eb2e8f9f7	565	uint32_t ContinuousMode)
<>	144:ef7eb2e8f9f7	566	{
<>	144:ef7eb2e8f9f7	567	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/* Check parameters */
<>	144:ef7eb2e8f9f7	570	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	571	assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
<>	144:ef7eb2e8f9f7	572	assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	575	if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
<>	144:ef7eb2e8f9f7	576	{
<>	144:ef7eb2e8f9f7	577	/* Set RCH[3:0] and RCONT bits in SDADC_CR2 */
<>	144:ef7eb2e8f9f7	578	hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH \| SDADC_CR2_RCONT);
<>	144:ef7eb2e8f9f7	579	if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
<>	144:ef7eb2e8f9f7	580	{
<>	144:ef7eb2e8f9f7	581	hsdadc->Instance->CR2 \|= (uint32_t) ((Channel & SDADC_MSB_MASK) \| SDADC_CR2_RCONT);
<>	144:ef7eb2e8f9f7	582	}
<>	144:ef7eb2e8f9f7	583	else
<>	144:ef7eb2e8f9f7	584	{
<>	144:ef7eb2e8f9f7	585	hsdadc->Instance->CR2 \|= (uint32_t) ((Channel & SDADC_MSB_MASK));
<>	144:ef7eb2e8f9f7	586	}
<>	144:ef7eb2e8f9f7	587	/* Store continuous mode information */
<>	144:ef7eb2e8f9f7	588	hsdadc->RegularContMode = ContinuousMode;
<>	144:ef7eb2e8f9f7	589	}
<>	144:ef7eb2e8f9f7	590	else
<>	144:ef7eb2e8f9f7	591	{
<>	144:ef7eb2e8f9f7	592	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	593	}
<>	144:ef7eb2e8f9f7	594	/* Return function status */
<>	144:ef7eb2e8f9f7	595	return status;
<>	144:ef7eb2e8f9f7	596	}
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	/**
<>	144:ef7eb2e8f9f7	599	* @brief This function allows to select channels for injected conversion and
<>	144:ef7eb2e8f9f7	600	* to enable/disable continuous mode for injected conversion.
<>	144:ef7eb2e8f9f7	601	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	602	* @param Channel: Channels for injected conversion.
<>	144:ef7eb2e8f9f7	603	* This parameter can be a values combination of @ref SDADC_Channel_Selection.
<>	144:ef7eb2e8f9f7	604	* @param ContinuousMode: Enable/disable continuous mode for injected conversion.
<>	144:ef7eb2e8f9f7	605	* This parameter can be a value of @ref SDADC_ContinuousMode.
<>	144:ef7eb2e8f9f7	606	* @retval HAL status
<>	144:ef7eb2e8f9f7	607	*/
<>	144:ef7eb2e8f9f7	608	HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	609	uint32_t Channel,
<>	144:ef7eb2e8f9f7	610	uint32_t ContinuousMode)
<>	144:ef7eb2e8f9f7	611	{
<>	144:ef7eb2e8f9f7	612	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	/* Check parameters */
<>	144:ef7eb2e8f9f7	615	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	616	assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
<>	144:ef7eb2e8f9f7	617	assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
<>	144:ef7eb2e8f9f7	618
<>	144:ef7eb2e8f9f7	619	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	620	if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
<>	144:ef7eb2e8f9f7	621	{
<>	144:ef7eb2e8f9f7	622	/* Set JCHG[8:0] bits in SDADC_JCHG */
<>	144:ef7eb2e8f9f7	623	hsdadc->Instance->JCHGR = (uint32_t) (Channel & SDADC_LSB_MASK);
<>	144:ef7eb2e8f9f7	624	/* Set or clear JCONT bit in SDADC_CR2 */
<>	144:ef7eb2e8f9f7	625	if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
<>	144:ef7eb2e8f9f7	626	{
<>	144:ef7eb2e8f9f7	627	hsdadc->Instance->CR2 \|= SDADC_CR2_JCONT;
<>	144:ef7eb2e8f9f7	628	}
<>	144:ef7eb2e8f9f7	629	else
<>	144:ef7eb2e8f9f7	630	{
<>	144:ef7eb2e8f9f7	631	hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
<>	144:ef7eb2e8f9f7	632	}
<>	144:ef7eb2e8f9f7	633	/* Store continuous mode information */
<>	144:ef7eb2e8f9f7	634	hsdadc->InjectedContMode = ContinuousMode;
<>	144:ef7eb2e8f9f7	635	/* Store number of injected channels */
<>	144:ef7eb2e8f9f7	636	hsdadc->InjectedChannelsNbr = SDADC_GetInjChannelsNbr(Channel);
<>	144:ef7eb2e8f9f7	637	}
<>	144:ef7eb2e8f9f7	638	else
<>	144:ef7eb2e8f9f7	639	{
<>	144:ef7eb2e8f9f7	640	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	641	}
<>	144:ef7eb2e8f9f7	642	/* Return function status */
<>	144:ef7eb2e8f9f7	643	return status;
<>	144:ef7eb2e8f9f7	644	}
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	/**
<>	144:ef7eb2e8f9f7	647	* @brief This function allows to select trigger for regular conversions.
<>	144:ef7eb2e8f9f7	648	* @note This function should not be called if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	649	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	650	* @param Trigger: Trigger for regular conversions.
<>	144:ef7eb2e8f9f7	651	* This parameter can be one of the following value :
<>	144:ef7eb2e8f9f7	652	* @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
<>	144:ef7eb2e8f9f7	653	* @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
<>	144:ef7eb2e8f9f7	654	* @retval HAL status
<>	144:ef7eb2e8f9f7	655	*/
<>	144:ef7eb2e8f9f7	656	HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
<>	144:ef7eb2e8f9f7	657	{
<>	144:ef7eb2e8f9f7	658	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	659
<>	144:ef7eb2e8f9f7	660	/* Check parameters */
<>	144:ef7eb2e8f9f7	661	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	662	assert_param(IS_SDADC_REGULAR_TRIGGER(Trigger));
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	/* Check parameters compatibility */
<>	144:ef7eb2e8f9f7	665	if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
<>	144:ef7eb2e8f9f7	666	{
<>	144:ef7eb2e8f9f7	667	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	668	}
<>	144:ef7eb2e8f9f7	669	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	670	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	671	(hsdadc->State == HAL_SDADC_STATE_CALIB) \|\| \
<>	144:ef7eb2e8f9f7	672	(hsdadc->State == HAL_SDADC_STATE_INJ))
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	/* Store regular trigger information */
<>	144:ef7eb2e8f9f7	675	hsdadc->RegularTrigger = Trigger;
<>	144:ef7eb2e8f9f7	676	}
<>	144:ef7eb2e8f9f7	677	else
<>	144:ef7eb2e8f9f7	678	{
<>	144:ef7eb2e8f9f7	679	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	680	}
<>	144:ef7eb2e8f9f7	681	/* Return function status */
<>	144:ef7eb2e8f9f7	682	return status;
<>	144:ef7eb2e8f9f7	683	}
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	/**
<>	144:ef7eb2e8f9f7	686	* @brief This function allows to select trigger for injected conversions.
<>	144:ef7eb2e8f9f7	687	* @note This function should not be called if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	688	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	689	* @param Trigger: Trigger for injected conversions.
<>	144:ef7eb2e8f9f7	690	* This parameter can be one of the following value :
<>	144:ef7eb2e8f9f7	691	* @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
<>	144:ef7eb2e8f9f7	692	* @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
<>	144:ef7eb2e8f9f7	693	* @arg SDADC_EXTERNAL_TRIGGER : External trigger.
<>	144:ef7eb2e8f9f7	694	* @retval HAL status
<>	144:ef7eb2e8f9f7	695	*/
<>	144:ef7eb2e8f9f7	696	HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
<>	144:ef7eb2e8f9f7	697	{
<>	144:ef7eb2e8f9f7	698	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	/* Check parameters */
<>	144:ef7eb2e8f9f7	701	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	702	assert_param(IS_SDADC_INJECTED_TRIGGER(Trigger));
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	/* Check parameters compatibility */
<>	144:ef7eb2e8f9f7	705	if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
<>	144:ef7eb2e8f9f7	706	{
<>	144:ef7eb2e8f9f7	707	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	708	}
<>	144:ef7eb2e8f9f7	709	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	710	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	711	(hsdadc->State == HAL_SDADC_STATE_CALIB) \|\| \
<>	144:ef7eb2e8f9f7	712	(hsdadc->State == HAL_SDADC_STATE_REG))
<>	144:ef7eb2e8f9f7	713	{
<>	144:ef7eb2e8f9f7	714	/* Store regular trigger information */
<>	144:ef7eb2e8f9f7	715	hsdadc->InjectedTrigger = Trigger;
<>	144:ef7eb2e8f9f7	716	}
<>	144:ef7eb2e8f9f7	717	else
<>	144:ef7eb2e8f9f7	718	{
<>	144:ef7eb2e8f9f7	719	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	720	}
<>	144:ef7eb2e8f9f7	721	/* Return function status */
<>	144:ef7eb2e8f9f7	722	return status;
<>	144:ef7eb2e8f9f7	723	}
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	/**
<>	144:ef7eb2e8f9f7	726	* @brief This function allows to select and configure injected external trigger.
<>	144:ef7eb2e8f9f7	727	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	728	* (neither calibration nor regular or injected conversion ongoing)
<>	144:ef7eb2e8f9f7	729	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	730	* @param InjectedExtTrigger: External trigger for injected conversions.
<>	144:ef7eb2e8f9f7	731	* This parameter can be a value of @ref SDADC_InjectedExtTrigger.
<>	144:ef7eb2e8f9f7	732	* @param ExtTriggerEdge: Edge of external injected trigger.
<>	144:ef7eb2e8f9f7	733	* This parameter can be a value of @ref SDADC_ExtTriggerEdge.
<>	144:ef7eb2e8f9f7	734	* @retval HAL status
<>	144:ef7eb2e8f9f7	735	*/
<>	144:ef7eb2e8f9f7	736	HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	737	uint32_t InjectedExtTrigger,
<>	144:ef7eb2e8f9f7	738	uint32_t ExtTriggerEdge)
<>	144:ef7eb2e8f9f7	739	{
<>	144:ef7eb2e8f9f7	740	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	/* Check parameters */
<>	144:ef7eb2e8f9f7	743	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	744	assert_param(IS_SDADC_EXT_INJEC_TRIG(InjectedExtTrigger));
<>	144:ef7eb2e8f9f7	745	assert_param(IS_SDADC_EXT_TRIG_EDGE(ExtTriggerEdge));
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	748	if(hsdadc->State == HAL_SDADC_STATE_READY)
<>	144:ef7eb2e8f9f7	749	{
<>	144:ef7eb2e8f9f7	750	/* Enter init mode */
<>	144:ef7eb2e8f9f7	751	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	752	{
<>	144:ef7eb2e8f9f7	753	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	754	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	755	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	756	}
<>	144:ef7eb2e8f9f7	757	else
<>	144:ef7eb2e8f9f7	758	{
<>	144:ef7eb2e8f9f7	759	/* Set JEXTSEL[2:0] bits in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	760	hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTSEL);
<>	144:ef7eb2e8f9f7	761	hsdadc->Instance->CR2 \|= InjectedExtTrigger;
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	/* Store external trigger edge information */
<>	144:ef7eb2e8f9f7	764	hsdadc->ExtTriggerEdge = ExtTriggerEdge;
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/* Exit init mode */
<>	144:ef7eb2e8f9f7	767	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	768	}
<>	144:ef7eb2e8f9f7	769	}
<>	144:ef7eb2e8f9f7	770	else
<>	144:ef7eb2e8f9f7	771	{
<>	144:ef7eb2e8f9f7	772	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	773	}
<>	144:ef7eb2e8f9f7	774	/* Return function status */
<>	144:ef7eb2e8f9f7	775	return status;
<>	144:ef7eb2e8f9f7	776	}
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	/**
<>	144:ef7eb2e8f9f7	779	* @brief This function allows to enable/disable delay addition for injected conversions.
<>	144:ef7eb2e8f9f7	780	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	781	* (neither calibration nor regular or injected conversion ongoing)
<>	144:ef7eb2e8f9f7	782	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	783	* @param InjectedDelay: Enable/disable delay for injected conversions.
<>	144:ef7eb2e8f9f7	784	* This parameter can be a value of @ref SDADC_InjectedDelay.
<>	144:ef7eb2e8f9f7	785	* @retval HAL status
<>	144:ef7eb2e8f9f7	786	*/
<>	144:ef7eb2e8f9f7	787	HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	788	uint32_t InjectedDelay)
<>	144:ef7eb2e8f9f7	789	{
<>	144:ef7eb2e8f9f7	790	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/* Check parameters */
<>	144:ef7eb2e8f9f7	793	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	794	assert_param(IS_SDADC_INJECTED_DELAY(InjectedDelay));
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	797	if(hsdadc->State == HAL_SDADC_STATE_READY)
<>	144:ef7eb2e8f9f7	798	{
<>	144:ef7eb2e8f9f7	799	/* Enter init mode */
<>	144:ef7eb2e8f9f7	800	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	801	{
<>	144:ef7eb2e8f9f7	802	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	803	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	804	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	805	}
<>	144:ef7eb2e8f9f7	806	else
<>	144:ef7eb2e8f9f7	807	{
<>	144:ef7eb2e8f9f7	808	/* Set JDS bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	809	hsdadc->Instance->CR2 &= ~(SDADC_CR2_JDS);
<>	144:ef7eb2e8f9f7	810	hsdadc->Instance->CR2 \|= InjectedDelay;
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/* Exit init mode */
<>	144:ef7eb2e8f9f7	813	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816	else
<>	144:ef7eb2e8f9f7	817	{
<>	144:ef7eb2e8f9f7	818	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	819	}
<>	144:ef7eb2e8f9f7	820	/* Return function status */
<>	144:ef7eb2e8f9f7	821	return status;
<>	144:ef7eb2e8f9f7	822	}
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/**
<>	144:ef7eb2e8f9f7	825	* @brief This function allows to configure multimode for regular conversions.
<>	144:ef7eb2e8f9f7	826	* @note This function should not be called if regular conversion is ongoing
<>	144:ef7eb2e8f9f7	827	* and should be could only for SDADC1.
<>	144:ef7eb2e8f9f7	828	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	829	* @param MultimodeType: Type of multimode for regular conversions.
<>	144:ef7eb2e8f9f7	830	* This parameter can be a value of @ref SDADC_MultimodeType.
<>	144:ef7eb2e8f9f7	831	* @retval HAL status
<>	144:ef7eb2e8f9f7	832	*/
<>	144:ef7eb2e8f9f7	833	HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
<>	144:ef7eb2e8f9f7	834	uint32_t MultimodeType)
<>	144:ef7eb2e8f9f7	835	{
<>	144:ef7eb2e8f9f7	836	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Check parameters */
<>	144:ef7eb2e8f9f7	839	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	840	assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842	/* Check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	843	if(hsdadc->Instance != SDADC1)
<>	144:ef7eb2e8f9f7	844	{
<>	144:ef7eb2e8f9f7	845	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	846	}
<>	144:ef7eb2e8f9f7	847	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	848	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	849	(hsdadc->State == HAL_SDADC_STATE_CALIB) \|\| \
<>	144:ef7eb2e8f9f7	850	(hsdadc->State == HAL_SDADC_STATE_INJ))
<>	144:ef7eb2e8f9f7	851	{
<>	144:ef7eb2e8f9f7	852	/* Store regular trigger information */
<>	144:ef7eb2e8f9f7	853	hsdadc->RegularMultimode = MultimodeType;
<>	144:ef7eb2e8f9f7	854	}
<>	144:ef7eb2e8f9f7	855	else
<>	144:ef7eb2e8f9f7	856	{
<>	144:ef7eb2e8f9f7	857	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	858	}
<>	144:ef7eb2e8f9f7	859	/* Return function status */
<>	144:ef7eb2e8f9f7	860	return status;
<>	144:ef7eb2e8f9f7	861	}
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	/**
<>	144:ef7eb2e8f9f7	864	* @brief This function allows to configure multimode for injected conversions.
<>	144:ef7eb2e8f9f7	865	* @note This function should not be called if injected conversion is ongoing
<>	144:ef7eb2e8f9f7	866	* and should be could only for SDADC1.
<>	144:ef7eb2e8f9f7	867	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	868	* @param MultimodeType: Type of multimode for injected conversions.
<>	144:ef7eb2e8f9f7	869	* This parameter can be a value of @ref SDADC_MultimodeType.
<>	144:ef7eb2e8f9f7	870	* @retval HAL status
<>	144:ef7eb2e8f9f7	871	*/
<>	144:ef7eb2e8f9f7	872	HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
<>	144:ef7eb2e8f9f7	873	uint32_t MultimodeType)
<>	144:ef7eb2e8f9f7	874	{
<>	144:ef7eb2e8f9f7	875	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	876
<>	144:ef7eb2e8f9f7	877	/* Check parameters */
<>	144:ef7eb2e8f9f7	878	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	879	assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	882	if(hsdadc->Instance != SDADC1)
<>	144:ef7eb2e8f9f7	883	{
<>	144:ef7eb2e8f9f7	884	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	887	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	888	(hsdadc->State == HAL_SDADC_STATE_CALIB) \|\| \
<>	144:ef7eb2e8f9f7	889	(hsdadc->State == HAL_SDADC_STATE_REG))
<>	144:ef7eb2e8f9f7	890	{
<>	144:ef7eb2e8f9f7	891	/* Store regular trigger information */
<>	144:ef7eb2e8f9f7	892	hsdadc->InjectedMultimode = MultimodeType;
<>	144:ef7eb2e8f9f7	893	}
<>	144:ef7eb2e8f9f7	894	else
<>	144:ef7eb2e8f9f7	895	{
<>	144:ef7eb2e8f9f7	896	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	897	}
<>	144:ef7eb2e8f9f7	898	/* Return function status */
<>	144:ef7eb2e8f9f7	899	return status;
<>	144:ef7eb2e8f9f7	900	}
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/**
<>	144:ef7eb2e8f9f7	903	* @}
<>	144:ef7eb2e8f9f7	904	*/
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
<>	144:ef7eb2e8f9f7	907	* @brief IO operation Control functions
<>	144:ef7eb2e8f9f7	908	*
<>	144:ef7eb2e8f9f7	909	@verbatim
<>	144:ef7eb2e8f9f7	910	===============================================================================
<>	144:ef7eb2e8f9f7	911	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	912	===============================================================================
<>	144:ef7eb2e8f9f7	913	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	914	(+) Start calibration.
<>	144:ef7eb2e8f9f7	915	(+) Poll for the end of calibration.
<>	144:ef7eb2e8f9f7	916	(+) Start calibration and enable interrupt.
<>	144:ef7eb2e8f9f7	917	(+) Start conversion of regular/injected channel.
<>	144:ef7eb2e8f9f7	918	(+) Poll for the end of regular/injected conversion.
<>	144:ef7eb2e8f9f7	919	(+) Stop conversion of regular/injected channel.
<>	144:ef7eb2e8f9f7	920	(+) Start conversion of regular/injected channel and enable interrupt.
<>	144:ef7eb2e8f9f7	921	(+) Stop conversion of regular/injected channel and disable interrupt.
<>	144:ef7eb2e8f9f7	922	(+) Start conversion of regular/injected channel and enable DMA transfer.
<>	144:ef7eb2e8f9f7	923	(+) Stop conversion of regular/injected channel and disable DMA transfer.
<>	144:ef7eb2e8f9f7	924	(+) Start multimode and enable DMA transfer for regular/injected conversion.
<>	144:ef7eb2e8f9f7	925	(+) Stop multimode and disable DMA transfer for regular/injected conversion..
<>	144:ef7eb2e8f9f7	926	(+) Get result of regular channel conversion.
<>	144:ef7eb2e8f9f7	927	(+) Get result of injected channel conversion.
<>	144:ef7eb2e8f9f7	928	(+) Get result of multimode conversion.
<>	144:ef7eb2e8f9f7	929	(+) Handle SDADC interrupt request.
<>	144:ef7eb2e8f9f7	930	(+) Callbacks for calibration and regular/injected conversions.
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	@endverbatim
<>	144:ef7eb2e8f9f7	933	* @{
<>	144:ef7eb2e8f9f7	934	*/
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	/**
<>	144:ef7eb2e8f9f7	937	* @brief This function allows to start calibration in polling mode.
<>	144:ef7eb2e8f9f7	938	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	939	* (neither calibration nor regular or injected conversion ongoing).
<>	144:ef7eb2e8f9f7	940	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	941	* @param CalibrationSequence: Calibration sequence.
<>	144:ef7eb2e8f9f7	942	* This parameter can be a value of @ref SDADC_CalibrationSequence.
<>	144:ef7eb2e8f9f7	943	* @retval HAL status
<>	144:ef7eb2e8f9f7	944	*/
<>	144:ef7eb2e8f9f7	945	HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	946	uint32_t CalibrationSequence)
<>	144:ef7eb2e8f9f7	947	{
<>	144:ef7eb2e8f9f7	948	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/* Check parameters */
<>	144:ef7eb2e8f9f7	951	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	952	assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	955	if(hsdadc->State == HAL_SDADC_STATE_READY)
<>	144:ef7eb2e8f9f7	956	{
<>	144:ef7eb2e8f9f7	957	/* Enter init mode */
<>	144:ef7eb2e8f9f7	958	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	959	{
<>	144:ef7eb2e8f9f7	960	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	961	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	962	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	963	}
<>	144:ef7eb2e8f9f7	964	else
<>	144:ef7eb2e8f9f7	965	{
<>	144:ef7eb2e8f9f7	966	/* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	967	hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
<>	144:ef7eb2e8f9f7	968	hsdadc->Instance->CR2 \|= CalibrationSequence;
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/* Exit init mode */
<>	144:ef7eb2e8f9f7	971	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	972
<>	144:ef7eb2e8f9f7	973	/* Set STARTCALIB in SDADC_CR2 */
<>	144:ef7eb2e8f9f7	974	hsdadc->Instance->CR2 \|= SDADC_CR2_STARTCALIB;
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/* Set SDADC in calibration state */
<>	144:ef7eb2e8f9f7	977	hsdadc->State = HAL_SDADC_STATE_CALIB;
<>	144:ef7eb2e8f9f7	978	}
<>	144:ef7eb2e8f9f7	979	}
<>	144:ef7eb2e8f9f7	980	else
<>	144:ef7eb2e8f9f7	981	{
<>	144:ef7eb2e8f9f7	982	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	983	}
<>	144:ef7eb2e8f9f7	984	/* Return function status */
<>	144:ef7eb2e8f9f7	985	return status;
<>	144:ef7eb2e8f9f7	986	}
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/**
<>	144:ef7eb2e8f9f7	989	* @brief This function allows to poll for the end of calibration.
<>	144:ef7eb2e8f9f7	990	* @note This function should be called only if calibration is ongoing.
<>	144:ef7eb2e8f9f7	991	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	992	* @param Timeout: Timeout value in milliseconds.
<>	144:ef7eb2e8f9f7	993	* @retval HAL status
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995	HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	996	{
<>	144:ef7eb2e8f9f7	997	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/* Check parameters */
<>	144:ef7eb2e8f9f7	1000	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1003	if(hsdadc->State != HAL_SDADC_STATE_CALIB)
<>	144:ef7eb2e8f9f7	1004	{
<>	144:ef7eb2e8f9f7	1005	/* Return error status */
<>	144:ef7eb2e8f9f7	1006	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1007	}
<>	144:ef7eb2e8f9f7	1008	else
<>	144:ef7eb2e8f9f7	1009	{
<>	144:ef7eb2e8f9f7	1010	/* Get timeout */
<>	144:ef7eb2e8f9f7	1011	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/* Wait EOCALF bit in SDADC_ISR register */
<>	144:ef7eb2e8f9f7	1014	while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	/* Check the Timeout */
<>	144:ef7eb2e8f9f7	1017	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1018	{
<>	144:ef7eb2e8f9f7	1019	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1020	{
<>	144:ef7eb2e8f9f7	1021	/* Return timeout status */
<>	144:ef7eb2e8f9f7	1022	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1023	}
<>	144:ef7eb2e8f9f7	1024	}
<>	144:ef7eb2e8f9f7	1025	}
<>	144:ef7eb2e8f9f7	1026	/* Set CLREOCALF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	1027	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLREOCALF;
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* Set SDADC in ready state */
<>	144:ef7eb2e8f9f7	1030	hsdadc->State = HAL_SDADC_STATE_READY;
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* Return function status */
<>	144:ef7eb2e8f9f7	1033	return HAL_OK;
<>	144:ef7eb2e8f9f7	1034	}
<>	144:ef7eb2e8f9f7	1035	}
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/**
<>	144:ef7eb2e8f9f7	1038	* @brief This function allows to start calibration in interrupt mode.
<>	144:ef7eb2e8f9f7	1039	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1040	* (neither calibration nor regular or injected conversion ongoing).
<>	144:ef7eb2e8f9f7	1041	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1042	* @param CalibrationSequence: Calibration sequence.
<>	144:ef7eb2e8f9f7	1043	* This parameter can be a value of @ref SDADC_CalibrationSequence.
<>	144:ef7eb2e8f9f7	1044	* @retval HAL status
<>	144:ef7eb2e8f9f7	1045	*/
<>	144:ef7eb2e8f9f7	1046	HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
<>	144:ef7eb2e8f9f7	1047	uint32_t CalibrationSequence)
<>	144:ef7eb2e8f9f7	1048	{
<>	144:ef7eb2e8f9f7	1049	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/* Check parameters */
<>	144:ef7eb2e8f9f7	1052	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1053	assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1056	if(hsdadc->State == HAL_SDADC_STATE_READY)
<>	144:ef7eb2e8f9f7	1057	{
<>	144:ef7eb2e8f9f7	1058	/* Enter init mode */
<>	144:ef7eb2e8f9f7	1059	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	1060	{
<>	144:ef7eb2e8f9f7	1061	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1062	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1063	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1064	}
<>	144:ef7eb2e8f9f7	1065	else
<>	144:ef7eb2e8f9f7	1066	{
<>	144:ef7eb2e8f9f7	1067	/* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	1068	hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
<>	144:ef7eb2e8f9f7	1069	hsdadc->Instance->CR2 \|= CalibrationSequence;
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	/* Exit init mode */
<>	144:ef7eb2e8f9f7	1072	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	/* Set EOCALIE bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1075	hsdadc->Instance->CR1 \|= SDADC_CR1_EOCALIE;
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	/* Set STARTCALIB in SDADC_CR2 */
<>	144:ef7eb2e8f9f7	1078	hsdadc->Instance->CR2 \|= SDADC_CR2_STARTCALIB;
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/* Set SDADC in calibration state */
<>	144:ef7eb2e8f9f7	1081	hsdadc->State = HAL_SDADC_STATE_CALIB;
<>	144:ef7eb2e8f9f7	1082	}
<>	144:ef7eb2e8f9f7	1083	}
<>	144:ef7eb2e8f9f7	1084	else
<>	144:ef7eb2e8f9f7	1085	{
<>	144:ef7eb2e8f9f7	1086	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1087	}
<>	144:ef7eb2e8f9f7	1088	/* Return function status */
<>	144:ef7eb2e8f9f7	1089	return status;
<>	144:ef7eb2e8f9f7	1090	}
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/**
<>	144:ef7eb2e8f9f7	1093	* @brief This function allows to start regular conversion in polling mode.
<>	144:ef7eb2e8f9f7	1094	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1095	* or if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1096	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1097	* @retval HAL status
<>	144:ef7eb2e8f9f7	1098	*/
<>	144:ef7eb2e8f9f7	1099	HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1100	{
<>	144:ef7eb2e8f9f7	1101	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/* Check parameters */
<>	144:ef7eb2e8f9f7	1104	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1107	if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1108	(hsdadc->State == HAL_SDADC_STATE_INJ))
<>	144:ef7eb2e8f9f7	1109	{
<>	144:ef7eb2e8f9f7	1110	/* Start regular conversion */
<>	144:ef7eb2e8f9f7	1111	status = SDADC_RegConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1112	}
<>	144:ef7eb2e8f9f7	1113	else
<>	144:ef7eb2e8f9f7	1114	{
<>	144:ef7eb2e8f9f7	1115	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1116	}
<>	144:ef7eb2e8f9f7	1117	/* Return function status */
<>	144:ef7eb2e8f9f7	1118	return status;
<>	144:ef7eb2e8f9f7	1119	}
<>	144:ef7eb2e8f9f7	1120
<>	144:ef7eb2e8f9f7	1121	/**
<>	144:ef7eb2e8f9f7	1122	* @brief This function allows to poll for the end of regular conversion.
<>	144:ef7eb2e8f9f7	1123	* @note This function should be called only if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1124	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1125	* @param Timeout: Timeout value in milliseconds.
<>	144:ef7eb2e8f9f7	1126	* @retval HAL status
<>	144:ef7eb2e8f9f7	1127	*/
<>	144:ef7eb2e8f9f7	1128	HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1129	{
<>	144:ef7eb2e8f9f7	1130	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	/* Check parameters */
<>	144:ef7eb2e8f9f7	1133	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1136	if((hsdadc->State != HAL_SDADC_STATE_REG) && \
<>	144:ef7eb2e8f9f7	1137	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1138	{
<>	144:ef7eb2e8f9f7	1139	/* Return error status */
<>	144:ef7eb2e8f9f7	1140	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1141	}
<>	144:ef7eb2e8f9f7	1142	else
<>	144:ef7eb2e8f9f7	1143	{
<>	144:ef7eb2e8f9f7	1144	/* Get timeout */
<>	144:ef7eb2e8f9f7	1145	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147	/* Wait REOCF bit in SDADC_ISR register */
<>	144:ef7eb2e8f9f7	1148	while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
<>	144:ef7eb2e8f9f7	1149	{
<>	144:ef7eb2e8f9f7	1150	/* Check the Timeout */
<>	144:ef7eb2e8f9f7	1151	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1152	{
<>	144:ef7eb2e8f9f7	1153	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1154	{
<>	144:ef7eb2e8f9f7	1155	/* Return timeout status */
<>	144:ef7eb2e8f9f7	1156	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1157	}
<>	144:ef7eb2e8f9f7	1158	}
<>	144:ef7eb2e8f9f7	1159	}
<>	144:ef7eb2e8f9f7	1160	/* Check if overrun occurs */
<>	144:ef7eb2e8f9f7	1161	if((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)
<>	144:ef7eb2e8f9f7	1162	{
<>	144:ef7eb2e8f9f7	1163	/* Update error code and call error callback */
<>	144:ef7eb2e8f9f7	1164	hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
<>	144:ef7eb2e8f9f7	1165	HAL_SDADC_ErrorCallback(hsdadc);
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/* Set CLRROVRF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	1168	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLRROVRF;
<>	144:ef7eb2e8f9f7	1169	}
<>	144:ef7eb2e8f9f7	1170	/* Update SDADC state only if not continuous conversion and SW trigger */
<>	144:ef7eb2e8f9f7	1171	if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1172	(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
<>	144:ef7eb2e8f9f7	1173	{
<>	144:ef7eb2e8f9f7	1174	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
<>	144:ef7eb2e8f9f7	1175	HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
<>	144:ef7eb2e8f9f7	1176	}
<>	144:ef7eb2e8f9f7	1177	/* Return function status */
<>	144:ef7eb2e8f9f7	1178	return HAL_OK;
<>	144:ef7eb2e8f9f7	1179	}
<>	144:ef7eb2e8f9f7	1180	}
<>	144:ef7eb2e8f9f7	1181
<>	144:ef7eb2e8f9f7	1182	/**
<>	144:ef7eb2e8f9f7	1183	* @brief This function allows to stop regular conversion in polling mode.
<>	144:ef7eb2e8f9f7	1184	* @note This function should be called only if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1185	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1186	* @retval HAL status
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188	HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1189	{
<>	144:ef7eb2e8f9f7	1190	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	/* Check parameters */
<>	144:ef7eb2e8f9f7	1193	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1196	if((hsdadc->State != HAL_SDADC_STATE_REG) && \
<>	144:ef7eb2e8f9f7	1197	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1198	{
<>	144:ef7eb2e8f9f7	1199	/* Return error status */
<>	144:ef7eb2e8f9f7	1200	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1201	}
<>	144:ef7eb2e8f9f7	1202	else
<>	144:ef7eb2e8f9f7	1203	{
<>	144:ef7eb2e8f9f7	1204	/* Stop regular conversion */
<>	144:ef7eb2e8f9f7	1205	status = SDADC_RegConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207	/* Return function status */
<>	144:ef7eb2e8f9f7	1208	return status;
<>	144:ef7eb2e8f9f7	1209	}
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/**
<>	144:ef7eb2e8f9f7	1212	* @brief This function allows to start regular conversion in interrupt mode.
<>	144:ef7eb2e8f9f7	1213	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1214	* or if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1215	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1216	* @retval HAL status
<>	144:ef7eb2e8f9f7	1217	*/
<>	144:ef7eb2e8f9f7	1218	HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1219	{
<>	144:ef7eb2e8f9f7	1220	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1221
<>	144:ef7eb2e8f9f7	1222	/* Check parameters */
<>	144:ef7eb2e8f9f7	1223	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1224
<>	144:ef7eb2e8f9f7	1225	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1226	if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1227	(hsdadc->State == HAL_SDADC_STATE_INJ))
<>	144:ef7eb2e8f9f7	1228	{
<>	144:ef7eb2e8f9f7	1229	/* Set REOCIE and ROVRIE bits in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1230	hsdadc->Instance->CR1 \|= (uint32_t) (SDADC_CR1_REOCIE \| SDADC_CR1_ROVRIE);
<>	144:ef7eb2e8f9f7	1231
<>	144:ef7eb2e8f9f7	1232	/* Start regular conversion */
<>	144:ef7eb2e8f9f7	1233	status = SDADC_RegConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1234	}
<>	144:ef7eb2e8f9f7	1235	else
<>	144:ef7eb2e8f9f7	1236	{
<>	144:ef7eb2e8f9f7	1237	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1238	}
<>	144:ef7eb2e8f9f7	1239	/* Return function status */
<>	144:ef7eb2e8f9f7	1240	return status;
<>	144:ef7eb2e8f9f7	1241	}
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/**
<>	144:ef7eb2e8f9f7	1244	* @brief This function allows to stop regular conversion in interrupt mode.
<>	144:ef7eb2e8f9f7	1245	* @note This function should be called only if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1246	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1247	* @retval HAL status
<>	144:ef7eb2e8f9f7	1248	*/
<>	144:ef7eb2e8f9f7	1249	HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1250	{
<>	144:ef7eb2e8f9f7	1251	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Check parameters */
<>	144:ef7eb2e8f9f7	1254	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1257	if((hsdadc->State != HAL_SDADC_STATE_REG) && \
<>	144:ef7eb2e8f9f7	1258	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1259	{
<>	144:ef7eb2e8f9f7	1260	/* Return error status */
<>	144:ef7eb2e8f9f7	1261	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1262	}
<>	144:ef7eb2e8f9f7	1263	else
<>	144:ef7eb2e8f9f7	1264	{
<>	144:ef7eb2e8f9f7	1265	/* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1266	hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_REOCIE \| SDADC_CR1_ROVRIE);
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	/* Stop regular conversion */
<>	144:ef7eb2e8f9f7	1269	status = SDADC_RegConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1270	}
<>	144:ef7eb2e8f9f7	1271	/* Return function status */
<>	144:ef7eb2e8f9f7	1272	return status;
<>	144:ef7eb2e8f9f7	1273	}
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/**
<>	144:ef7eb2e8f9f7	1276	* @brief This function allows to start regular conversion in DMA mode.
<>	144:ef7eb2e8f9f7	1277	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1278	* or if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1279	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1280	* @param pData: The destination buffer address.
<>	144:ef7eb2e8f9f7	1281	* @param Length: The length of data to be transferred from SDADC peripheral to memory.
<>	144:ef7eb2e8f9f7	1282	* @retval HAL status
<>	144:ef7eb2e8f9f7	1283	*/
<>	144:ef7eb2e8f9f7	1284	HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef hsdadc, uint32_t pData,
<>	144:ef7eb2e8f9f7	1285	uint32_t Length)
<>	144:ef7eb2e8f9f7	1286	{
<>	144:ef7eb2e8f9f7	1287	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1288
<>	144:ef7eb2e8f9f7	1289	/* Check parameters */
<>	144:ef7eb2e8f9f7	1290	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1291	assert_param(pData != NULL);
<>	144:ef7eb2e8f9f7	1292	assert_param(Length != 0);
<>	144:ef7eb2e8f9f7	1293
<>	144:ef7eb2e8f9f7	1294	/* Check that DMA is not enabled for injected conversion */
<>	144:ef7eb2e8f9f7	1295	if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
<>	144:ef7eb2e8f9f7	1296	{
<>	144:ef7eb2e8f9f7	1297	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1298	}
<>	144:ef7eb2e8f9f7	1299	/* Check parameters compatibility */
<>	144:ef7eb2e8f9f7	1300	else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1301	(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1302	(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
<>	144:ef7eb2e8f9f7	1303	(Length != 1))
<>	144:ef7eb2e8f9f7	1304	{
<>	144:ef7eb2e8f9f7	1305	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1306	}
<>	144:ef7eb2e8f9f7	1307	else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1308	(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1309	(hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
<>	144:ef7eb2e8f9f7	1310	{
<>	144:ef7eb2e8f9f7	1311	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1312	}
<>	144:ef7eb2e8f9f7	1313	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1314	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1315	(hsdadc->State == HAL_SDADC_STATE_INJ))
<>	144:ef7eb2e8f9f7	1316	{
<>	144:ef7eb2e8f9f7	1317	/* Set callbacks on DMA handler */
<>	144:ef7eb2e8f9f7	1318	hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
<>	144:ef7eb2e8f9f7	1319	hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
<>	144:ef7eb2e8f9f7	1320	if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
<>	144:ef7eb2e8f9f7	1321	{
<>	144:ef7eb2e8f9f7	1322	hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
<>	144:ef7eb2e8f9f7	1323	}
<>	144:ef7eb2e8f9f7	1324
<>	144:ef7eb2e8f9f7	1325	/* Set RDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1326	hsdadc->Instance->CR1 \|= SDADC_CR1_RDMAEN;
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328	/* Start DMA in interrupt mode */
<>	144:ef7eb2e8f9f7	1329	if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATAR, \
<>	144:ef7eb2e8f9f7	1330	(uint32_t) pData, Length) != HAL_OK)
<>	144:ef7eb2e8f9f7	1331	{
<>	144:ef7eb2e8f9f7	1332	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1333	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1334	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1335	}
<>	144:ef7eb2e8f9f7	1336	else
<>	144:ef7eb2e8f9f7	1337	{
<>	144:ef7eb2e8f9f7	1338	/* Start regular conversion */
<>	144:ef7eb2e8f9f7	1339	status = SDADC_RegConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1340	}
<>	144:ef7eb2e8f9f7	1341	}
<>	144:ef7eb2e8f9f7	1342	else
<>	144:ef7eb2e8f9f7	1343	{
<>	144:ef7eb2e8f9f7	1344	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1345	}
<>	144:ef7eb2e8f9f7	1346	/* Return function status */
<>	144:ef7eb2e8f9f7	1347	return status;
<>	144:ef7eb2e8f9f7	1348	}
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/**
<>	144:ef7eb2e8f9f7	1351	* @brief This function allows to stop regular conversion in DMA mode.
<>	144:ef7eb2e8f9f7	1352	* @note This function should be called only if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1353	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1354	* @retval HAL status
<>	144:ef7eb2e8f9f7	1355	*/
<>	144:ef7eb2e8f9f7	1356	HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1357	{
<>	144:ef7eb2e8f9f7	1358	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1359
<>	144:ef7eb2e8f9f7	1360	/* Check parameters */
<>	144:ef7eb2e8f9f7	1361	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1362
<>	144:ef7eb2e8f9f7	1363	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1364	if((hsdadc->State != HAL_SDADC_STATE_REG) && \
<>	144:ef7eb2e8f9f7	1365	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1366	{
<>	144:ef7eb2e8f9f7	1367	/* Return error status */
<>	144:ef7eb2e8f9f7	1368	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1369	}
<>	144:ef7eb2e8f9f7	1370	else
<>	144:ef7eb2e8f9f7	1371	{
<>	144:ef7eb2e8f9f7	1372	/* Clear RDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1373	hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	/* Stop current DMA transfer */
<>	144:ef7eb2e8f9f7	1376	if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
<>	144:ef7eb2e8f9f7	1377	{
<>	144:ef7eb2e8f9f7	1378	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1379	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1380	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1381	}
<>	144:ef7eb2e8f9f7	1382	else
<>	144:ef7eb2e8f9f7	1383	{
<>	144:ef7eb2e8f9f7	1384	/* Stop regular conversion */
<>	144:ef7eb2e8f9f7	1385	status = SDADC_RegConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1386	}
<>	144:ef7eb2e8f9f7	1387	}
<>	144:ef7eb2e8f9f7	1388	/* Return function status */
<>	144:ef7eb2e8f9f7	1389	return status;
<>	144:ef7eb2e8f9f7	1390	}
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	/**
<>	144:ef7eb2e8f9f7	1393	* @brief This function allows to get regular conversion value.
<>	144:ef7eb2e8f9f7	1394	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1395	* @retval Regular conversion value
<>	144:ef7eb2e8f9f7	1396	*/
<>	144:ef7eb2e8f9f7	1397	uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1398	{
<>	144:ef7eb2e8f9f7	1399	/* Check parameters */
<>	144:ef7eb2e8f9f7	1400	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	/* Return regular conversion value */
<>	144:ef7eb2e8f9f7	1403	return hsdadc->Instance->RDATAR;
<>	144:ef7eb2e8f9f7	1404	}
<>	144:ef7eb2e8f9f7	1405
<>	144:ef7eb2e8f9f7	1406	/**
<>	144:ef7eb2e8f9f7	1407	* @brief This function allows to start injected conversion in polling mode.
<>	144:ef7eb2e8f9f7	1408	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1409	* or if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1410	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1411	* @retval HAL status
<>	144:ef7eb2e8f9f7	1412	*/
<>	144:ef7eb2e8f9f7	1413	HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1414	{
<>	144:ef7eb2e8f9f7	1415	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/* Check parameters */
<>	144:ef7eb2e8f9f7	1418	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1419
<>	144:ef7eb2e8f9f7	1420	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1421	if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1422	(hsdadc->State == HAL_SDADC_STATE_REG))
<>	144:ef7eb2e8f9f7	1423	{
<>	144:ef7eb2e8f9f7	1424	/* Start injected conversion */
<>	144:ef7eb2e8f9f7	1425	status = SDADC_InjConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1426	}
<>	144:ef7eb2e8f9f7	1427	else
<>	144:ef7eb2e8f9f7	1428	{
<>	144:ef7eb2e8f9f7	1429	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1430	}
<>	144:ef7eb2e8f9f7	1431	/* Return function status */
<>	144:ef7eb2e8f9f7	1432	return status;
<>	144:ef7eb2e8f9f7	1433	}
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/**
<>	144:ef7eb2e8f9f7	1436	* @brief This function allows to poll for the end of injected conversion.
<>	144:ef7eb2e8f9f7	1437	* @note This function should be called only if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1438	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1439	* @param Timeout: Timeout value in milliseconds.
<>	144:ef7eb2e8f9f7	1440	* @retval HAL status
<>	144:ef7eb2e8f9f7	1441	*/
<>	144:ef7eb2e8f9f7	1442	HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
<>	144:ef7eb2e8f9f7	1443	uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1444	{
<>	144:ef7eb2e8f9f7	1445	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Check parameters */
<>	144:ef7eb2e8f9f7	1448	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1451	if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
<>	144:ef7eb2e8f9f7	1452	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1453	{
<>	144:ef7eb2e8f9f7	1454	/* Return error status */
<>	144:ef7eb2e8f9f7	1455	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1456	}
<>	144:ef7eb2e8f9f7	1457	else
<>	144:ef7eb2e8f9f7	1458	{
<>	144:ef7eb2e8f9f7	1459	/* Get timeout */
<>	144:ef7eb2e8f9f7	1460	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/* Wait JEOCF bit in SDADC_ISR register */
<>	144:ef7eb2e8f9f7	1463	while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
<>	144:ef7eb2e8f9f7	1464	{
<>	144:ef7eb2e8f9f7	1465	/* Check the Timeout */
<>	144:ef7eb2e8f9f7	1466	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1467	{
<>	144:ef7eb2e8f9f7	1468	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1469	{
<>	144:ef7eb2e8f9f7	1470	/* Return timeout status */
<>	144:ef7eb2e8f9f7	1471	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1472	}
<>	144:ef7eb2e8f9f7	1473	}
<>	144:ef7eb2e8f9f7	1474	}
<>	144:ef7eb2e8f9f7	1475	/* Check if overrun occurs */
<>	144:ef7eb2e8f9f7	1476	if((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)
<>	144:ef7eb2e8f9f7	1477	{
<>	144:ef7eb2e8f9f7	1478	/* Update error code and call error callback */
<>	144:ef7eb2e8f9f7	1479	hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
<>	144:ef7eb2e8f9f7	1480	HAL_SDADC_ErrorCallback(hsdadc);
<>	144:ef7eb2e8f9f7	1481
<>	144:ef7eb2e8f9f7	1482	/* Set CLRJOVRF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	1483	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLRJOVRF;
<>	144:ef7eb2e8f9f7	1484	}
<>	144:ef7eb2e8f9f7	1485	/* Update remaining injected conversions */
<>	144:ef7eb2e8f9f7	1486	hsdadc->InjConvRemaining--;
<>	144:ef7eb2e8f9f7	1487	if(hsdadc->InjConvRemaining == 0)
<>	144:ef7eb2e8f9f7	1488	{
<>	144:ef7eb2e8f9f7	1489	/* end of injected sequence, reset the value */
<>	144:ef7eb2e8f9f7	1490	hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
<>	144:ef7eb2e8f9f7	1491	}
<>	144:ef7eb2e8f9f7	1492
<>	144:ef7eb2e8f9f7	1493	/* Update SDADC state only if not continuous conversion, SW trigger */
<>	144:ef7eb2e8f9f7	1494	/* and end of injected sequence */
<>	144:ef7eb2e8f9f7	1495	if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1496	(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1497	(hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
<>	144:ef7eb2e8f9f7	1498	{
<>	144:ef7eb2e8f9f7	1499	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
<>	144:ef7eb2e8f9f7	1500	HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
<>	144:ef7eb2e8f9f7	1501	}
<>	144:ef7eb2e8f9f7	1502	/* Return function status */
<>	144:ef7eb2e8f9f7	1503	return HAL_OK;
<>	144:ef7eb2e8f9f7	1504	}
<>	144:ef7eb2e8f9f7	1505	}
<>	144:ef7eb2e8f9f7	1506
<>	144:ef7eb2e8f9f7	1507	/**
<>	144:ef7eb2e8f9f7	1508	* @brief This function allows to stop injected conversion in polling mode.
<>	144:ef7eb2e8f9f7	1509	* @note This function should be called only if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1510	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1511	* @retval HAL status
<>	144:ef7eb2e8f9f7	1512	*/
<>	144:ef7eb2e8f9f7	1513	HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1514	{
<>	144:ef7eb2e8f9f7	1515	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1516
<>	144:ef7eb2e8f9f7	1517	/* Check parameters */
<>	144:ef7eb2e8f9f7	1518	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1519
<>	144:ef7eb2e8f9f7	1520	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1521	if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
<>	144:ef7eb2e8f9f7	1522	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1523	{
<>	144:ef7eb2e8f9f7	1524	/* Return error status */
<>	144:ef7eb2e8f9f7	1525	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1526	}
<>	144:ef7eb2e8f9f7	1527	else
<>	144:ef7eb2e8f9f7	1528	{
<>	144:ef7eb2e8f9f7	1529	/* Stop injected conversion */
<>	144:ef7eb2e8f9f7	1530	status = SDADC_InjConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1531	}
<>	144:ef7eb2e8f9f7	1532	/* Return function status */
<>	144:ef7eb2e8f9f7	1533	return status;
<>	144:ef7eb2e8f9f7	1534	}
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/**
<>	144:ef7eb2e8f9f7	1537	* @brief This function allows to start injected conversion in interrupt mode.
<>	144:ef7eb2e8f9f7	1538	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1539	* or if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1540	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1541	* @retval HAL status
<>	144:ef7eb2e8f9f7	1542	*/
<>	144:ef7eb2e8f9f7	1543	HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1544	{
<>	144:ef7eb2e8f9f7	1545	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1546
<>	144:ef7eb2e8f9f7	1547	/* Check parameters */
<>	144:ef7eb2e8f9f7	1548	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1551	if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1552	(hsdadc->State == HAL_SDADC_STATE_REG))
<>	144:ef7eb2e8f9f7	1553	{
<>	144:ef7eb2e8f9f7	1554	/* Set JEOCIE and JOVRIE bits in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1555	hsdadc->Instance->CR1 \|= (uint32_t) (SDADC_CR1_JEOCIE \| SDADC_CR1_JOVRIE);
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	/* Start injected conversion */
<>	144:ef7eb2e8f9f7	1558	status = SDADC_InjConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1559	}
<>	144:ef7eb2e8f9f7	1560	else
<>	144:ef7eb2e8f9f7	1561	{
<>	144:ef7eb2e8f9f7	1562	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1563	}
<>	144:ef7eb2e8f9f7	1564	/* Return function status */
<>	144:ef7eb2e8f9f7	1565	return status;
<>	144:ef7eb2e8f9f7	1566	}
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	/**
<>	144:ef7eb2e8f9f7	1569	* @brief This function allows to stop injected conversion in interrupt mode.
<>	144:ef7eb2e8f9f7	1570	* @note This function should be called only if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1571	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1572	* @retval HAL status
<>	144:ef7eb2e8f9f7	1573	*/
<>	144:ef7eb2e8f9f7	1574	HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1575	{
<>	144:ef7eb2e8f9f7	1576	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/* Check parameters */
<>	144:ef7eb2e8f9f7	1579	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1582	if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
<>	144:ef7eb2e8f9f7	1583	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1584	{
<>	144:ef7eb2e8f9f7	1585	/* Return error status */
<>	144:ef7eb2e8f9f7	1586	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1587	}
<>	144:ef7eb2e8f9f7	1588	else
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	/* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1591	hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_JEOCIE \| SDADC_CR1_JOVRIE);
<>	144:ef7eb2e8f9f7	1592
<>	144:ef7eb2e8f9f7	1593	/* Stop injected conversion */
<>	144:ef7eb2e8f9f7	1594	status = SDADC_InjConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1595	}
<>	144:ef7eb2e8f9f7	1596	/* Return function status */
<>	144:ef7eb2e8f9f7	1597	return status;
<>	144:ef7eb2e8f9f7	1598	}
<>	144:ef7eb2e8f9f7	1599
<>	144:ef7eb2e8f9f7	1600	/**
<>	144:ef7eb2e8f9f7	1601	* @brief This function allows to start injected conversion in DMA mode.
<>	144:ef7eb2e8f9f7	1602	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1603	* or if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1604	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1605	* @param pData: The destination buffer address.
<>	144:ef7eb2e8f9f7	1606	* @param Length: The length of data to be transferred from SDADC peripheral to memory.
<>	144:ef7eb2e8f9f7	1607	* @retval HAL status
<>	144:ef7eb2e8f9f7	1608	*/
<>	144:ef7eb2e8f9f7	1609	HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef hsdadc, uint32_t pData,
<>	144:ef7eb2e8f9f7	1610	uint32_t Length)
<>	144:ef7eb2e8f9f7	1611	{
<>	144:ef7eb2e8f9f7	1612	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* Check parameters */
<>	144:ef7eb2e8f9f7	1615	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1616	assert_param(pData != NULL);
<>	144:ef7eb2e8f9f7	1617	assert_param(Length != 0);
<>	144:ef7eb2e8f9f7	1618
<>	144:ef7eb2e8f9f7	1619	/* Check that DMA is not enabled for regular conversion */
<>	144:ef7eb2e8f9f7	1620	if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
<>	144:ef7eb2e8f9f7	1621	{
<>	144:ef7eb2e8f9f7	1622	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1623	}
<>	144:ef7eb2e8f9f7	1624	/* Check parameters compatibility */
<>	144:ef7eb2e8f9f7	1625	else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1626	(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1627	(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
<>	144:ef7eb2e8f9f7	1628	(Length > hsdadc->InjectedChannelsNbr))
<>	144:ef7eb2e8f9f7	1629	{
<>	144:ef7eb2e8f9f7	1630	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1631	}
<>	144:ef7eb2e8f9f7	1632	else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1633	(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1634	(hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
<>	144:ef7eb2e8f9f7	1635	{
<>	144:ef7eb2e8f9f7	1636	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1637	}
<>	144:ef7eb2e8f9f7	1638	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1639	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1640	(hsdadc->State == HAL_SDADC_STATE_REG))
<>	144:ef7eb2e8f9f7	1641	{
<>	144:ef7eb2e8f9f7	1642	/* Set callbacks on DMA handler */
<>	144:ef7eb2e8f9f7	1643	hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
<>	144:ef7eb2e8f9f7	1644	hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
<>	144:ef7eb2e8f9f7	1645	if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
<>	144:ef7eb2e8f9f7	1646	{
<>	144:ef7eb2e8f9f7	1647	hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
<>	144:ef7eb2e8f9f7	1648	}
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	/* Set JDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1651	hsdadc->Instance->CR1 \|= SDADC_CR1_JDMAEN;
<>	144:ef7eb2e8f9f7	1652
<>	144:ef7eb2e8f9f7	1653	/* Start DMA in interrupt mode */
<>	144:ef7eb2e8f9f7	1654	if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATAR, \
<>	144:ef7eb2e8f9f7	1655	(uint32_t) pData, Length) != HAL_OK)
<>	144:ef7eb2e8f9f7	1656	{
<>	144:ef7eb2e8f9f7	1657	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1658	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1659	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1660	}
<>	144:ef7eb2e8f9f7	1661	else
<>	144:ef7eb2e8f9f7	1662	{
<>	144:ef7eb2e8f9f7	1663	/* Start injected conversion */
<>	144:ef7eb2e8f9f7	1664	status = SDADC_InjConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1665	}
<>	144:ef7eb2e8f9f7	1666	}
<>	144:ef7eb2e8f9f7	1667	else
<>	144:ef7eb2e8f9f7	1668	{
<>	144:ef7eb2e8f9f7	1669	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1670	}
<>	144:ef7eb2e8f9f7	1671	/* Return function status */
<>	144:ef7eb2e8f9f7	1672	return status;
<>	144:ef7eb2e8f9f7	1673	}
<>	144:ef7eb2e8f9f7	1674
<>	144:ef7eb2e8f9f7	1675	/**
<>	144:ef7eb2e8f9f7	1676	* @brief This function allows to stop injected conversion in DMA mode.
<>	144:ef7eb2e8f9f7	1677	* @note This function should be called only if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1678	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1679	* @retval HAL status
<>	144:ef7eb2e8f9f7	1680	*/
<>	144:ef7eb2e8f9f7	1681	HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
<>	144:ef7eb2e8f9f7	1682	{
<>	144:ef7eb2e8f9f7	1683	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1684
<>	144:ef7eb2e8f9f7	1685	/* Check parameters */
<>	144:ef7eb2e8f9f7	1686	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1687
<>	144:ef7eb2e8f9f7	1688	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1689	if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
<>	144:ef7eb2e8f9f7	1690	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1691	{
<>	144:ef7eb2e8f9f7	1692	/* Return error status */
<>	144:ef7eb2e8f9f7	1693	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1694	}
<>	144:ef7eb2e8f9f7	1695	else
<>	144:ef7eb2e8f9f7	1696	{
<>	144:ef7eb2e8f9f7	1697	/* Clear JDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1698	hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
<>	144:ef7eb2e8f9f7	1699
<>	144:ef7eb2e8f9f7	1700	/* Stop current DMA transfer */
<>	144:ef7eb2e8f9f7	1701	if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
<>	144:ef7eb2e8f9f7	1702	{
<>	144:ef7eb2e8f9f7	1703	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1704	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1705	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1706	}
<>	144:ef7eb2e8f9f7	1707	else
<>	144:ef7eb2e8f9f7	1708	{
<>	144:ef7eb2e8f9f7	1709	/* Stop injected conversion */
<>	144:ef7eb2e8f9f7	1710	status = SDADC_InjConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712	}
<>	144:ef7eb2e8f9f7	1713	/* Return function status */
<>	144:ef7eb2e8f9f7	1714	return status;
<>	144:ef7eb2e8f9f7	1715	}
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/**
<>	144:ef7eb2e8f9f7	1718	* @brief This function allows to get injected conversion value.
<>	144:ef7eb2e8f9f7	1719	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1720	* @param Channel: Corresponding channel of injected conversion.
<>	144:ef7eb2e8f9f7	1721	* @retval Injected conversion value
<>	144:ef7eb2e8f9f7	1722	*/
<>	144:ef7eb2e8f9f7	1723	uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef hsdadc, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1724	{
<>	144:ef7eb2e8f9f7	1725	uint32_t value = 0;
<>	144:ef7eb2e8f9f7	1726
<>	144:ef7eb2e8f9f7	1727	/* Check parameters */
<>	144:ef7eb2e8f9f7	1728	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1729	assert_param(Channel != NULL);
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	/* Read SDADC_JDATAR register and extract channel and conversion value */
<>	144:ef7eb2e8f9f7	1732	value = hsdadc->Instance->JDATAR;
<>	144:ef7eb2e8f9f7	1733	*Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
<>	144:ef7eb2e8f9f7	1734	value &= SDADC_JDATAR_JDATA;
<>	144:ef7eb2e8f9f7	1735
<>	144:ef7eb2e8f9f7	1736	/* Return injected conversion value */
<>	144:ef7eb2e8f9f7	1737	return value;
<>	144:ef7eb2e8f9f7	1738	}
<>	144:ef7eb2e8f9f7	1739
<>	144:ef7eb2e8f9f7	1740	/**
<>	144:ef7eb2e8f9f7	1741	* @brief This function allows to start multimode regular conversions in DMA mode.
<>	144:ef7eb2e8f9f7	1742	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1743	* or if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1744	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1745	* @param pData: The destination buffer address.
<>	144:ef7eb2e8f9f7	1746	* @param Length: The length of data to be transferred from SDADC peripheral to memory.
<>	144:ef7eb2e8f9f7	1747	* @retval HAL status
<>	144:ef7eb2e8f9f7	1748	*/
<>	144:ef7eb2e8f9f7	1749	HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
<>	144:ef7eb2e8f9f7	1750	uint32_t Length)
<>	144:ef7eb2e8f9f7	1751	{
<>	144:ef7eb2e8f9f7	1752	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	/* Check parameters */
<>	144:ef7eb2e8f9f7	1755	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1756	assert_param(pData != NULL);
<>	144:ef7eb2e8f9f7	1757	assert_param(Length != 0);
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/* Check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	1760	if(hsdadc->Instance != SDADC1)
<>	144:ef7eb2e8f9f7	1761	{
<>	144:ef7eb2e8f9f7	1762	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1763	}
<>	144:ef7eb2e8f9f7	1764	/* Check that DMA is not enabled for injected conversion */
<>	144:ef7eb2e8f9f7	1765	else if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
<>	144:ef7eb2e8f9f7	1766	{
<>	144:ef7eb2e8f9f7	1767	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1768	}
<>	144:ef7eb2e8f9f7	1769	/* Check parameters compatibility */
<>	144:ef7eb2e8f9f7	1770	else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1771	(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1772	(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
<>	144:ef7eb2e8f9f7	1773	(Length != 1))
<>	144:ef7eb2e8f9f7	1774	{
<>	144:ef7eb2e8f9f7	1775	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777	else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1778	(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1779	(hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
<>	144:ef7eb2e8f9f7	1780	{
<>	144:ef7eb2e8f9f7	1781	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1782	}
<>	144:ef7eb2e8f9f7	1783	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1784	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1785	(hsdadc->State == HAL_SDADC_STATE_INJ))
<>	144:ef7eb2e8f9f7	1786	{
<>	144:ef7eb2e8f9f7	1787	/* Set callbacks on DMA handler */
<>	144:ef7eb2e8f9f7	1788	hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
<>	144:ef7eb2e8f9f7	1789	hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
<>	144:ef7eb2e8f9f7	1790	if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
<>	144:ef7eb2e8f9f7	1791	{
<>	144:ef7eb2e8f9f7	1792	hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
<>	144:ef7eb2e8f9f7	1793	}
<>	144:ef7eb2e8f9f7	1794	/* Set RDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1795	hsdadc->Instance->CR1 \|= SDADC_CR1_RDMAEN;
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797	/* Start DMA in interrupt mode */
<>	144:ef7eb2e8f9f7	1798	if(hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
<>	144:ef7eb2e8f9f7	1799	{
<>	144:ef7eb2e8f9f7	1800	status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA12R, \
<>	144:ef7eb2e8f9f7	1801	(uint32_t) pData, Length);
<>	144:ef7eb2e8f9f7	1802	}
<>	144:ef7eb2e8f9f7	1803	else
<>	144:ef7eb2e8f9f7	1804	{
<>	144:ef7eb2e8f9f7	1805	status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA13R, \
<>	144:ef7eb2e8f9f7	1806	(uint32_t) pData, Length);
<>	144:ef7eb2e8f9f7	1807	}
<>	144:ef7eb2e8f9f7	1808	if(status != HAL_OK)
<>	144:ef7eb2e8f9f7	1809	{
<>	144:ef7eb2e8f9f7	1810	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1811	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1812	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1813	}
<>	144:ef7eb2e8f9f7	1814	else
<>	144:ef7eb2e8f9f7	1815	{
<>	144:ef7eb2e8f9f7	1816	/* Start regular conversion */
<>	144:ef7eb2e8f9f7	1817	status = SDADC_RegConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1818	}
<>	144:ef7eb2e8f9f7	1819	}
<>	144:ef7eb2e8f9f7	1820	else
<>	144:ef7eb2e8f9f7	1821	{
<>	144:ef7eb2e8f9f7	1822	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1823	}
<>	144:ef7eb2e8f9f7	1824	/* Return function status */
<>	144:ef7eb2e8f9f7	1825	return status;
<>	144:ef7eb2e8f9f7	1826	}
<>	144:ef7eb2e8f9f7	1827
<>	144:ef7eb2e8f9f7	1828	/**
<>	144:ef7eb2e8f9f7	1829	* @brief This function allows to stop multimode regular conversions in DMA mode.
<>	144:ef7eb2e8f9f7	1830	* @note This function should be called only if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1831	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1832	* @retval HAL status
<>	144:ef7eb2e8f9f7	1833	*/
<>	144:ef7eb2e8f9f7	1834	HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	1835	{
<>	144:ef7eb2e8f9f7	1836	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1837
<>	144:ef7eb2e8f9f7	1838	/* Check parameters */
<>	144:ef7eb2e8f9f7	1839	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1840
<>	144:ef7eb2e8f9f7	1841	/* Check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	1842	if(hsdadc->Instance != SDADC1)
<>	144:ef7eb2e8f9f7	1843	{
<>	144:ef7eb2e8f9f7	1844	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1845	}
<>	144:ef7eb2e8f9f7	1846	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1847	else if((hsdadc->State != HAL_SDADC_STATE_REG) && \
<>	144:ef7eb2e8f9f7	1848	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	1849	{
<>	144:ef7eb2e8f9f7	1850	/* Return error status */
<>	144:ef7eb2e8f9f7	1851	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1852	}
<>	144:ef7eb2e8f9f7	1853	else
<>	144:ef7eb2e8f9f7	1854	{
<>	144:ef7eb2e8f9f7	1855	/* Clear RDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1856	hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
<>	144:ef7eb2e8f9f7	1857
<>	144:ef7eb2e8f9f7	1858	/* Stop current DMA transfer */
<>	144:ef7eb2e8f9f7	1859	if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
<>	144:ef7eb2e8f9f7	1860	{
<>	144:ef7eb2e8f9f7	1861	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1862	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1863	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1864	}
<>	144:ef7eb2e8f9f7	1865	else
<>	144:ef7eb2e8f9f7	1866	{
<>	144:ef7eb2e8f9f7	1867	/* Stop regular conversion */
<>	144:ef7eb2e8f9f7	1868	status = SDADC_RegConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	1869	}
<>	144:ef7eb2e8f9f7	1870	}
<>	144:ef7eb2e8f9f7	1871	/* Return function status */
<>	144:ef7eb2e8f9f7	1872	return status;
<>	144:ef7eb2e8f9f7	1873	}
<>	144:ef7eb2e8f9f7	1874
<>	144:ef7eb2e8f9f7	1875	/**
<>	144:ef7eb2e8f9f7	1876	* @brief This function allows to get multimode regular conversion value.
<>	144:ef7eb2e8f9f7	1877	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1878	* @retval Multimode regular conversion value
<>	144:ef7eb2e8f9f7	1879	*/
<>	144:ef7eb2e8f9f7	1880	uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	1881	{
<>	144:ef7eb2e8f9f7	1882	uint32_t value = 0;
<>	144:ef7eb2e8f9f7	1883
<>	144:ef7eb2e8f9f7	1884	/* Check parameters and check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	1885	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1886	assert_param(hsdadc->Instance == SDADC1);
<>	144:ef7eb2e8f9f7	1887
<>	144:ef7eb2e8f9f7	1888	/* read multimode regular value */
<>	144:ef7eb2e8f9f7	1889	value = (hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
<>	144:ef7eb2e8f9f7	1890	hsdadc->Instance->RDATA12R : hsdadc->Instance->RDATA13R;
<>	144:ef7eb2e8f9f7	1891
<>	144:ef7eb2e8f9f7	1892	/* Return multimode regular conversions value */
<>	144:ef7eb2e8f9f7	1893	return value;
<>	144:ef7eb2e8f9f7	1894	}
<>	144:ef7eb2e8f9f7	1895
<>	144:ef7eb2e8f9f7	1896	/**
<>	144:ef7eb2e8f9f7	1897	* @brief This function allows to start multimode injected conversions in DMA mode.
<>	144:ef7eb2e8f9f7	1898	* @note This function should be called only when SDADC instance is in idle state
<>	144:ef7eb2e8f9f7	1899	* or if regular conversion is ongoing.
<>	144:ef7eb2e8f9f7	1900	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1901	* @param pData: The destination buffer address.
<>	144:ef7eb2e8f9f7	1902	* @param Length: The length of data to be transferred from SDADC peripheral to memory.
<>	144:ef7eb2e8f9f7	1903	* @retval HAL status
<>	144:ef7eb2e8f9f7	1904	*/
<>	144:ef7eb2e8f9f7	1905	HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
<>	144:ef7eb2e8f9f7	1906	uint32_t* pData, uint32_t Length)
<>	144:ef7eb2e8f9f7	1907	{
<>	144:ef7eb2e8f9f7	1908	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1909
<>	144:ef7eb2e8f9f7	1910	/* Check parameters */
<>	144:ef7eb2e8f9f7	1911	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1912	assert_param(pData != NULL);
<>	144:ef7eb2e8f9f7	1913	assert_param(Length != 0);
<>	144:ef7eb2e8f9f7	1914
<>	144:ef7eb2e8f9f7	1915	/* Check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	1916	if(hsdadc->Instance != SDADC1)
<>	144:ef7eb2e8f9f7	1917	{
<>	144:ef7eb2e8f9f7	1918	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1919	}
<>	144:ef7eb2e8f9f7	1920	/* Check that DMA is not enabled for regular conversion */
<>	144:ef7eb2e8f9f7	1921	else if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
<>	144:ef7eb2e8f9f7	1922	{
<>	144:ef7eb2e8f9f7	1923	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1924	}
<>	144:ef7eb2e8f9f7	1925	/* Check parameters compatibility */
<>	144:ef7eb2e8f9f7	1926	else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1927	(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1928	(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
<>	144:ef7eb2e8f9f7	1929	(Length > (hsdadc->InjectedChannelsNbr << 1)))
<>	144:ef7eb2e8f9f7	1930	{
<>	144:ef7eb2e8f9f7	1931	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1932	}
<>	144:ef7eb2e8f9f7	1933	else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	1934	(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	1935	(hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
<>	144:ef7eb2e8f9f7	1936	{
<>	144:ef7eb2e8f9f7	1937	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1938	}
<>	144:ef7eb2e8f9f7	1939	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	1940	else if((hsdadc->State == HAL_SDADC_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1941	(hsdadc->State == HAL_SDADC_STATE_REG))
<>	144:ef7eb2e8f9f7	1942	{
<>	144:ef7eb2e8f9f7	1943	/* Set callbacks on DMA handler */
<>	144:ef7eb2e8f9f7	1944	hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
<>	144:ef7eb2e8f9f7	1945	hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
<>	144:ef7eb2e8f9f7	1946	if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
<>	144:ef7eb2e8f9f7	1947	{
<>	144:ef7eb2e8f9f7	1948	hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
<>	144:ef7eb2e8f9f7	1949	}
<>	144:ef7eb2e8f9f7	1950	/* Set JDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	1951	hsdadc->Instance->CR1 \|= SDADC_CR1_JDMAEN;
<>	144:ef7eb2e8f9f7	1952
<>	144:ef7eb2e8f9f7	1953	/* Start DMA in interrupt mode */
<>	144:ef7eb2e8f9f7	1954	if(hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
<>	144:ef7eb2e8f9f7	1955	{
<>	144:ef7eb2e8f9f7	1956	status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA12R, \
<>	144:ef7eb2e8f9f7	1957	(uint32_t) pData, Length);
<>	144:ef7eb2e8f9f7	1958	}
<>	144:ef7eb2e8f9f7	1959	else
<>	144:ef7eb2e8f9f7	1960	{
<>	144:ef7eb2e8f9f7	1961	status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA13R, \
<>	144:ef7eb2e8f9f7	1962	(uint32_t) pData, Length);
<>	144:ef7eb2e8f9f7	1963	}
<>	144:ef7eb2e8f9f7	1964	if(status != HAL_OK)
<>	144:ef7eb2e8f9f7	1965	{
<>	144:ef7eb2e8f9f7	1966	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	1967	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	1968	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1969	}
<>	144:ef7eb2e8f9f7	1970	else
<>	144:ef7eb2e8f9f7	1971	{
<>	144:ef7eb2e8f9f7	1972	/* Start injected conversion */
<>	144:ef7eb2e8f9f7	1973	status = SDADC_InjConvStart(hsdadc);
<>	144:ef7eb2e8f9f7	1974	}
<>	144:ef7eb2e8f9f7	1975	}
<>	144:ef7eb2e8f9f7	1976	else
<>	144:ef7eb2e8f9f7	1977	{
<>	144:ef7eb2e8f9f7	1978	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1979	}
<>	144:ef7eb2e8f9f7	1980	/* Return function status */
<>	144:ef7eb2e8f9f7	1981	return status;
<>	144:ef7eb2e8f9f7	1982	}
<>	144:ef7eb2e8f9f7	1983
<>	144:ef7eb2e8f9f7	1984	/**
<>	144:ef7eb2e8f9f7	1985	* @brief This function allows to stop multimode injected conversions in DMA mode.
<>	144:ef7eb2e8f9f7	1986	* @note This function should be called only if injected conversion is ongoing.
<>	144:ef7eb2e8f9f7	1987	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	1988	* @retval HAL status
<>	144:ef7eb2e8f9f7	1989	*/
<>	144:ef7eb2e8f9f7	1990	HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	1991	{
<>	144:ef7eb2e8f9f7	1992	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	/* Check parameters */
<>	144:ef7eb2e8f9f7	1995	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	1996
<>	144:ef7eb2e8f9f7	1997	/* Check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	1998	if(hsdadc->Instance != SDADC1)
<>	144:ef7eb2e8f9f7	1999	{
<>	144:ef7eb2e8f9f7	2000	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2001	}
<>	144:ef7eb2e8f9f7	2002	/* Check SDADC state */
<>	144:ef7eb2e8f9f7	2003	else if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
<>	144:ef7eb2e8f9f7	2004	(hsdadc->State != HAL_SDADC_STATE_REG_INJ))
<>	144:ef7eb2e8f9f7	2005	{
<>	144:ef7eb2e8f9f7	2006	/* Return error status */
<>	144:ef7eb2e8f9f7	2007	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2008	}
<>	144:ef7eb2e8f9f7	2009	else
<>	144:ef7eb2e8f9f7	2010	{
<>	144:ef7eb2e8f9f7	2011	/* Clear JDMAEN bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2012	hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	/* Stop current DMA transfer */
<>	144:ef7eb2e8f9f7	2015	if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
<>	144:ef7eb2e8f9f7	2016	{
<>	144:ef7eb2e8f9f7	2017	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	2018	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2019	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2020	}
<>	144:ef7eb2e8f9f7	2021	else
<>	144:ef7eb2e8f9f7	2022	{
<>	144:ef7eb2e8f9f7	2023	/* Stop injected conversion */
<>	144:ef7eb2e8f9f7	2024	status = SDADC_InjConvStop(hsdadc);
<>	144:ef7eb2e8f9f7	2025	}
<>	144:ef7eb2e8f9f7	2026	}
<>	144:ef7eb2e8f9f7	2027	/* Return function status */
<>	144:ef7eb2e8f9f7	2028	return status;
<>	144:ef7eb2e8f9f7	2029	}
<>	144:ef7eb2e8f9f7	2030
<>	144:ef7eb2e8f9f7	2031	/**
<>	144:ef7eb2e8f9f7	2032	* @brief This function allows to get multimode injected conversion value.
<>	144:ef7eb2e8f9f7	2033	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2034	* @retval Multimode injected conversion value
<>	144:ef7eb2e8f9f7	2035	*/
<>	144:ef7eb2e8f9f7	2036	uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2037	{
<>	144:ef7eb2e8f9f7	2038	uint32_t value = 0;
<>	144:ef7eb2e8f9f7	2039
<>	144:ef7eb2e8f9f7	2040	/* Check parameters and check instance is SDADC1 */
<>	144:ef7eb2e8f9f7	2041	assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
<>	144:ef7eb2e8f9f7	2042	assert_param(hsdadc->Instance == SDADC1);
<>	144:ef7eb2e8f9f7	2043
<>	144:ef7eb2e8f9f7	2044	/* read multimode injected value */
<>	144:ef7eb2e8f9f7	2045	value = (hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
<>	144:ef7eb2e8f9f7	2046	hsdadc->Instance->JDATA12R : hsdadc->Instance->JDATA13R;
<>	144:ef7eb2e8f9f7	2047
<>	144:ef7eb2e8f9f7	2048	/* Return multimode injected conversions value */
<>	144:ef7eb2e8f9f7	2049	return value;
<>	144:ef7eb2e8f9f7	2050	}
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052	/**
<>	144:ef7eb2e8f9f7	2053	* @brief This function handles the SDADC interrupts.
<>	144:ef7eb2e8f9f7	2054	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2055	* @retval None
<>	144:ef7eb2e8f9f7	2056	*/
<>	144:ef7eb2e8f9f7	2057	void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2058	{
<>	144:ef7eb2e8f9f7	2059	/* Check if end of regular conversion */
<>	144:ef7eb2e8f9f7	2060	if(((hsdadc->Instance->ISR & SDADC_ISR_REOCF) == SDADC_ISR_REOCF) && \
<>	144:ef7eb2e8f9f7	2061	((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE))
<>	144:ef7eb2e8f9f7	2062	{
<>	144:ef7eb2e8f9f7	2063	/* Call regular conversion complete callback */
<>	144:ef7eb2e8f9f7	2064	HAL_SDADC_ConvCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	/* End of conversion if mode is not continuous and software trigger */
<>	144:ef7eb2e8f9f7	2067	if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	2068	(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
<>	144:ef7eb2e8f9f7	2069	{
<>	144:ef7eb2e8f9f7	2070	/* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2071	hsdadc->Instance->CR1 &= ~(SDADC_CR1_REOCIE \| SDADC_CR1_ROVRIE);
<>	144:ef7eb2e8f9f7	2072
<>	144:ef7eb2e8f9f7	2073	/* Update SDADC state */
<>	144:ef7eb2e8f9f7	2074	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
<>	144:ef7eb2e8f9f7	2075	HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
<>	144:ef7eb2e8f9f7	2076	}
<>	144:ef7eb2e8f9f7	2077	}
<>	144:ef7eb2e8f9f7	2078	/* Check if end of injected conversion */
<>	144:ef7eb2e8f9f7	2079	else if(((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF) && \
<>	144:ef7eb2e8f9f7	2080	((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE))
<>	144:ef7eb2e8f9f7	2081	{
<>	144:ef7eb2e8f9f7	2082	/* Call injected conversion complete callback */
<>	144:ef7eb2e8f9f7	2083	HAL_SDADC_InjectedConvCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2084
<>	144:ef7eb2e8f9f7	2085	/* Update remaining injected conversions */
<>	144:ef7eb2e8f9f7	2086	hsdadc->InjConvRemaining--;
<>	144:ef7eb2e8f9f7	2087	if(hsdadc->InjConvRemaining ==0)
<>	144:ef7eb2e8f9f7	2088	{
<>	144:ef7eb2e8f9f7	2089	/* end of injected sequence, reset the value */
<>	144:ef7eb2e8f9f7	2090	hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
<>	144:ef7eb2e8f9f7	2091	}
<>	144:ef7eb2e8f9f7	2092	/* End of conversion if mode is not continuous, software trigger */
<>	144:ef7eb2e8f9f7	2093	/* and end of injected sequence */
<>	144:ef7eb2e8f9f7	2094	if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
<>	144:ef7eb2e8f9f7	2095	(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
<>	144:ef7eb2e8f9f7	2096	(hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
<>	144:ef7eb2e8f9f7	2097	{
<>	144:ef7eb2e8f9f7	2098	/* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2099	hsdadc->Instance->CR1 &= ~(SDADC_CR1_JEOCIE \| SDADC_CR1_JOVRIE);
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	/* Update SDADC state */
<>	144:ef7eb2e8f9f7	2102	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
<>	144:ef7eb2e8f9f7	2103	HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
<>	144:ef7eb2e8f9f7	2104	}
<>	144:ef7eb2e8f9f7	2105	}
<>	144:ef7eb2e8f9f7	2106	/* Check if end of calibration */
<>	144:ef7eb2e8f9f7	2107	else if(((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF) && \
<>	144:ef7eb2e8f9f7	2108	((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE))
<>	144:ef7eb2e8f9f7	2109	{
<>	144:ef7eb2e8f9f7	2110	/* Clear EOCALIE bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2111	hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE);
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	/* Set CLREOCALF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	2114	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLREOCALF;
<>	144:ef7eb2e8f9f7	2115
<>	144:ef7eb2e8f9f7	2116	/* Call calibration callback */
<>	144:ef7eb2e8f9f7	2117	HAL_SDADC_CalibrationCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2118
<>	144:ef7eb2e8f9f7	2119	/* Update SDADC state */
<>	144:ef7eb2e8f9f7	2120	hsdadc->State = HAL_SDADC_STATE_READY;
<>	144:ef7eb2e8f9f7	2121	}
<>	144:ef7eb2e8f9f7	2122	/* Check if overrun occurs during regular conversion */
<>	144:ef7eb2e8f9f7	2123	else if(((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF) && \
<>	144:ef7eb2e8f9f7	2124	((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE))
<>	144:ef7eb2e8f9f7	2125	{
<>	144:ef7eb2e8f9f7	2126	/* Set CLRROVRF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	2127	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLRROVRF;
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	/* Update error code */
<>	144:ef7eb2e8f9f7	2130	hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	/* Call error callback */
<>	144:ef7eb2e8f9f7	2133	HAL_SDADC_ErrorCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2134	}
<>	144:ef7eb2e8f9f7	2135	/* Check if overrun occurs during injected conversion */
<>	144:ef7eb2e8f9f7	2136	else if(((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF) && \
<>	144:ef7eb2e8f9f7	2137	((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE))
<>	144:ef7eb2e8f9f7	2138	{
<>	144:ef7eb2e8f9f7	2139	/* Set CLRJOVRF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	2140	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLRJOVRF;
<>	144:ef7eb2e8f9f7	2141
<>	144:ef7eb2e8f9f7	2142	/* Update error code */
<>	144:ef7eb2e8f9f7	2143	hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
<>	144:ef7eb2e8f9f7	2144
<>	144:ef7eb2e8f9f7	2145	/* Call error callback */
<>	144:ef7eb2e8f9f7	2146	HAL_SDADC_ErrorCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2147	}
<>	144:ef7eb2e8f9f7	2148	else
<>	144:ef7eb2e8f9f7	2149	{
<>	144:ef7eb2e8f9f7	2150	/* No additional IRQ source */
<>	144:ef7eb2e8f9f7	2151	}
<>	144:ef7eb2e8f9f7	2152
<>	144:ef7eb2e8f9f7	2153	return;
<>	144:ef7eb2e8f9f7	2154	}
<>	144:ef7eb2e8f9f7	2155
<>	144:ef7eb2e8f9f7	2156	/**
<>	144:ef7eb2e8f9f7	2157	* @brief Calibration complete callback.
<>	144:ef7eb2e8f9f7	2158	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2159	* @retval None
<>	144:ef7eb2e8f9f7	2160	*/
<>	144:ef7eb2e8f9f7	2161	__weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2162	{
<>	144:ef7eb2e8f9f7	2163	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2164	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	2165
<>	144:ef7eb2e8f9f7	2166	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2167	the HAL_SDADC_CalibrationCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2168	*/
<>	144:ef7eb2e8f9f7	2169	}
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	/**
<>	144:ef7eb2e8f9f7	2172	* @brief Half regular conversion complete callback.
<>	144:ef7eb2e8f9f7	2173	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2174	* @retval None
<>	144:ef7eb2e8f9f7	2175	*/
<>	144:ef7eb2e8f9f7	2176	__weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2177	{
<>	144:ef7eb2e8f9f7	2178	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2179	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	2180
<>	144:ef7eb2e8f9f7	2181	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2182	the HAL_SDADC_ConvHalfCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2183	*/
<>	144:ef7eb2e8f9f7	2184	}
<>	144:ef7eb2e8f9f7	2185
<>	144:ef7eb2e8f9f7	2186	/**
<>	144:ef7eb2e8f9f7	2187	* @brief Regular conversion complete callback.
<>	144:ef7eb2e8f9f7	2188	* @note In interrupt mode, user has to read conversion value in this function
<>	144:ef7eb2e8f9f7	2189	using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
<>	144:ef7eb2e8f9f7	2190	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2191	* @retval None
<>	144:ef7eb2e8f9f7	2192	*/
<>	144:ef7eb2e8f9f7	2193	__weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2194	{
<>	144:ef7eb2e8f9f7	2195	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2196	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	2197
<>	144:ef7eb2e8f9f7	2198	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2199	the HAL_SDADC_ConvCpltCallback could be implemented in the user file.
<>	144:ef7eb2e8f9f7	2200	*/
<>	144:ef7eb2e8f9f7	2201	}
<>	144:ef7eb2e8f9f7	2202
<>	144:ef7eb2e8f9f7	2203	/**
<>	144:ef7eb2e8f9f7	2204	* @brief Half injected conversion complete callback.
<>	144:ef7eb2e8f9f7	2205	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2206	* @retval None
<>	144:ef7eb2e8f9f7	2207	*/
<>	144:ef7eb2e8f9f7	2208	__weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2209	{
<>	144:ef7eb2e8f9f7	2210	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2211	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	2212
<>	144:ef7eb2e8f9f7	2213	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2214	the HAL_SDADC_InjectedConvHalfCpltCallback could be implemented in the user file.
<>	144:ef7eb2e8f9f7	2215	*/
<>	144:ef7eb2e8f9f7	2216	}
<>	144:ef7eb2e8f9f7	2217
<>	144:ef7eb2e8f9f7	2218	/**
<>	144:ef7eb2e8f9f7	2219	* @brief Injected conversion complete callback.
<>	144:ef7eb2e8f9f7	2220	* @note In interrupt mode, user has to read conversion value in this function
<>	144:ef7eb2e8f9f7	2221	using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
<>	144:ef7eb2e8f9f7	2222	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2223	* @retval None
<>	144:ef7eb2e8f9f7	2224	*/
<>	144:ef7eb2e8f9f7	2225	__weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2226	{
<>	144:ef7eb2e8f9f7	2227	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2228	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	2229
<>	144:ef7eb2e8f9f7	2230	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2231	the HAL_SDADC_InjectedConvCpltCallback could be implemented in the user file.
<>	144:ef7eb2e8f9f7	2232	*/
<>	144:ef7eb2e8f9f7	2233	}
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235	/**
<>	144:ef7eb2e8f9f7	2236	* @brief Error callback.
<>	144:ef7eb2e8f9f7	2237	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2238	* @retval None
<>	144:ef7eb2e8f9f7	2239	*/
<>	144:ef7eb2e8f9f7	2240	__weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2241	{
<>	144:ef7eb2e8f9f7	2242	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2243	UNUSED(hsdadc);
<>	144:ef7eb2e8f9f7	2244
<>	144:ef7eb2e8f9f7	2245	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2246	the HAL_SDADC_ErrorCallback could be implemented in the user file.
<>	144:ef7eb2e8f9f7	2247	*/
<>	144:ef7eb2e8f9f7	2248	}
<>	144:ef7eb2e8f9f7	2249
<>	144:ef7eb2e8f9f7	2250	/**
<>	144:ef7eb2e8f9f7	2251	* @brief DMA half transfer complete callback for regular conversion.
<>	144:ef7eb2e8f9f7	2252	* @param hdma : DMA handle.
<>	144:ef7eb2e8f9f7	2253	* @retval None
<>	144:ef7eb2e8f9f7	2254	*/
<>	144:ef7eb2e8f9f7	2255	static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2256	{
<>	144:ef7eb2e8f9f7	2257	/* Get SDADC handle */
<>	144:ef7eb2e8f9f7	2258	SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef) ((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2259
<>	144:ef7eb2e8f9f7	2260	/* Call regular half conversion complete callback */
<>	144:ef7eb2e8f9f7	2261	HAL_SDADC_ConvHalfCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2262	}
<>	144:ef7eb2e8f9f7	2263
<>	144:ef7eb2e8f9f7	2264	/**
<>	144:ef7eb2e8f9f7	2265	* @brief DMA transfer complete callback for regular conversion.
<>	144:ef7eb2e8f9f7	2266	* @param hdma : DMA handle.
<>	144:ef7eb2e8f9f7	2267	* @retval None
<>	144:ef7eb2e8f9f7	2268	*/
<>	144:ef7eb2e8f9f7	2269	static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2270	{
<>	144:ef7eb2e8f9f7	2271	/* Get SDADC handle */
<>	144:ef7eb2e8f9f7	2272	SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef) ((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	/* Call regular conversion complete callback */
<>	144:ef7eb2e8f9f7	2275	HAL_SDADC_ConvCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2276	}
<>	144:ef7eb2e8f9f7	2277
<>	144:ef7eb2e8f9f7	2278	/**
<>	144:ef7eb2e8f9f7	2279	* @brief DMA half transfer complete callback for injected conversion.
<>	144:ef7eb2e8f9f7	2280	* @param hdma : DMA handle.
<>	144:ef7eb2e8f9f7	2281	* @retval None
<>	144:ef7eb2e8f9f7	2282	*/
<>	144:ef7eb2e8f9f7	2283	static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2284	{
<>	144:ef7eb2e8f9f7	2285	/* Get SDADC handle */
<>	144:ef7eb2e8f9f7	2286	SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef) ((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2287
<>	144:ef7eb2e8f9f7	2288	/* Call injected half conversion complete callback */
<>	144:ef7eb2e8f9f7	2289	HAL_SDADC_InjectedConvHalfCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2290	}
<>	144:ef7eb2e8f9f7	2291
<>	144:ef7eb2e8f9f7	2292	/**
<>	144:ef7eb2e8f9f7	2293	* @brief DMA transfer complete callback for injected conversion.
<>	144:ef7eb2e8f9f7	2294	* @param hdma : DMA handle.
<>	144:ef7eb2e8f9f7	2295	* @retval None
<>	144:ef7eb2e8f9f7	2296	*/
<>	144:ef7eb2e8f9f7	2297	static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2298	{
<>	144:ef7eb2e8f9f7	2299	/* Get SDADC handle */
<>	144:ef7eb2e8f9f7	2300	SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef) ((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2301
<>	144:ef7eb2e8f9f7	2302	/* Call injected conversion complete callback */
<>	144:ef7eb2e8f9f7	2303	HAL_SDADC_InjectedConvCpltCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2304	}
<>	144:ef7eb2e8f9f7	2305
<>	144:ef7eb2e8f9f7	2306	/**
<>	144:ef7eb2e8f9f7	2307	* @brief DMA error callback.
<>	144:ef7eb2e8f9f7	2308	* @param hdma : DMA handle.
<>	144:ef7eb2e8f9f7	2309	* @retval None
<>	144:ef7eb2e8f9f7	2310	*/
<>	144:ef7eb2e8f9f7	2311	static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2312	{
<>	144:ef7eb2e8f9f7	2313	/* Get SDADC handle */
<>	144:ef7eb2e8f9f7	2314	SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef) ((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	/* Update error code */
<>	144:ef7eb2e8f9f7	2317	hsdadc->ErrorCode = SDADC_ERROR_DMA;
<>	144:ef7eb2e8f9f7	2318
<>	144:ef7eb2e8f9f7	2319	/* Call error callback */
<>	144:ef7eb2e8f9f7	2320	HAL_SDADC_ErrorCallback(hsdadc);
<>	144:ef7eb2e8f9f7	2321	}
<>	144:ef7eb2e8f9f7	2322
<>	144:ef7eb2e8f9f7	2323	/**
<>	144:ef7eb2e8f9f7	2324	* @}
<>	144:ef7eb2e8f9f7	2325	*/
<>	144:ef7eb2e8f9f7	2326
<>	144:ef7eb2e8f9f7	2327	/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	2328	* @brief SDADC Peripheral State functions
<>	144:ef7eb2e8f9f7	2329	*
<>	144:ef7eb2e8f9f7	2330	@verbatim
<>	144:ef7eb2e8f9f7	2331	===============================================================================
<>	144:ef7eb2e8f9f7	2332	##### ADC Peripheral State functions #####
<>	144:ef7eb2e8f9f7	2333	===============================================================================
<>	144:ef7eb2e8f9f7	2334	[..] This subsection provides functions allowing to
<>	144:ef7eb2e8f9f7	2335	(+) Get the SDADC state
<>	144:ef7eb2e8f9f7	2336	(+) Get the SDADC Error
<>	144:ef7eb2e8f9f7	2337
<>	144:ef7eb2e8f9f7	2338	@endverbatim
<>	144:ef7eb2e8f9f7	2339	* @{
<>	144:ef7eb2e8f9f7	2340	*/
<>	144:ef7eb2e8f9f7	2341
<>	144:ef7eb2e8f9f7	2342	/**
<>	144:ef7eb2e8f9f7	2343	* @brief This function allows to get the current SDADC state.
<>	144:ef7eb2e8f9f7	2344	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2345	* @retval SDADC state.
<>	144:ef7eb2e8f9f7	2346	*/
<>	144:ef7eb2e8f9f7	2347	HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2348	{
<>	144:ef7eb2e8f9f7	2349	return hsdadc->State;
<>	144:ef7eb2e8f9f7	2350	}
<>	144:ef7eb2e8f9f7	2351
<>	144:ef7eb2e8f9f7	2352	/**
<>	144:ef7eb2e8f9f7	2353	* @brief This function allows to get the current SDADC error code.
<>	144:ef7eb2e8f9f7	2354	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2355	* @retval SDADC error code.
<>	144:ef7eb2e8f9f7	2356	*/
<>	144:ef7eb2e8f9f7	2357	uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2358	{
<>	144:ef7eb2e8f9f7	2359	return hsdadc->ErrorCode;
<>	144:ef7eb2e8f9f7	2360	}
<>	144:ef7eb2e8f9f7	2361
<>	144:ef7eb2e8f9f7	2362	/**
<>	144:ef7eb2e8f9f7	2363	* @}
<>	144:ef7eb2e8f9f7	2364	*/
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/** @addtogroup SDADC_Private_Functions SDADC Private Functions
<>	144:ef7eb2e8f9f7	2367	* @{
<>	144:ef7eb2e8f9f7	2368	*/
<>	144:ef7eb2e8f9f7	2369
<>	144:ef7eb2e8f9f7	2370	/**
<>	144:ef7eb2e8f9f7	2371	* @brief This function allows to enter in init mode for SDADC instance.
<>	144:ef7eb2e8f9f7	2372	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2373	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2374	*/
<>	144:ef7eb2e8f9f7	2375	static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2376	{
<>	144:ef7eb2e8f9f7	2377	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2378
<>	144:ef7eb2e8f9f7	2379	/* Set INIT bit on SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2380	hsdadc->Instance->CR1 \|= SDADC_CR1_INIT;
<>	144:ef7eb2e8f9f7	2381
<>	144:ef7eb2e8f9f7	2382	/* Wait INITRDY bit on SDADC_ISR */
<>	144:ef7eb2e8f9f7	2383	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2384	while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
<>	144:ef7eb2e8f9f7	2385	{
<>	144:ef7eb2e8f9f7	2386	if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
<>	144:ef7eb2e8f9f7	2387	{
<>	144:ef7eb2e8f9f7	2388	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2389	}
<>	144:ef7eb2e8f9f7	2390	}
<>	144:ef7eb2e8f9f7	2391
<>	144:ef7eb2e8f9f7	2392	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2393	return HAL_OK;
<>	144:ef7eb2e8f9f7	2394	}
<>	144:ef7eb2e8f9f7	2395
<>	144:ef7eb2e8f9f7	2396	/**
<>	144:ef7eb2e8f9f7	2397	* @brief This function allows to exit from init mode for SDADC instance.
<>	144:ef7eb2e8f9f7	2398	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2399	* @retval None.
<>	144:ef7eb2e8f9f7	2400	*/
<>	144:ef7eb2e8f9f7	2401	static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2402	{
<>	144:ef7eb2e8f9f7	2403	/* Reset INIT bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2404	hsdadc->Instance->CR1 &= ~(SDADC_CR1_INIT);
<>	144:ef7eb2e8f9f7	2405	}
<>	144:ef7eb2e8f9f7	2406
<>	144:ef7eb2e8f9f7	2407	/**
<>	144:ef7eb2e8f9f7	2408	* @brief This function allows to get the number of injected channels.
<>	144:ef7eb2e8f9f7	2409	* @param Channels : bitfield of injected channels.
<>	144:ef7eb2e8f9f7	2410	* @retval Number of injected channels.
<>	144:ef7eb2e8f9f7	2411	*/
<>	144:ef7eb2e8f9f7	2412	static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
<>	144:ef7eb2e8f9f7	2413	{
<>	144:ef7eb2e8f9f7	2414	uint32_t nbChannels = 0;
<>	144:ef7eb2e8f9f7	2415	uint32_t tmp,i;
<>	144:ef7eb2e8f9f7	2416
<>	144:ef7eb2e8f9f7	2417	/* Get the number of channels from bitfield */
<>	144:ef7eb2e8f9f7	2418	tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
<>	144:ef7eb2e8f9f7	2419	for(i = 0 ; i < 9 ; i++)
<>	144:ef7eb2e8f9f7	2420	{
<>	144:ef7eb2e8f9f7	2421	if((tmp & (uint32_t)0x00000001) != 0)
<>	144:ef7eb2e8f9f7	2422	{
<>	144:ef7eb2e8f9f7	2423	nbChannels++;
<>	144:ef7eb2e8f9f7	2424	}
<>	144:ef7eb2e8f9f7	2425	tmp = (uint32_t) (tmp >> 1);
<>	144:ef7eb2e8f9f7	2426	}
<>	144:ef7eb2e8f9f7	2427	return nbChannels;
<>	144:ef7eb2e8f9f7	2428	}
<>	144:ef7eb2e8f9f7	2429
<>	144:ef7eb2e8f9f7	2430	/**
<>	144:ef7eb2e8f9f7	2431	* @brief This function allows to really start regular conversion.
<>	144:ef7eb2e8f9f7	2432	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2433	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2434	*/
<>	144:ef7eb2e8f9f7	2435	static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2436	{
<>	144:ef7eb2e8f9f7	2437	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	2438
<>	144:ef7eb2e8f9f7	2439	/* Check regular trigger */
<>	144:ef7eb2e8f9f7	2440	if(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER)
<>	144:ef7eb2e8f9f7	2441	{
<>	144:ef7eb2e8f9f7	2442	/* Set RSWSTART bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2443	hsdadc->Instance->CR2 \|= SDADC_CR2_RSWSTART;
<>	144:ef7eb2e8f9f7	2444	}
<>	144:ef7eb2e8f9f7	2445	else /* synchronuous trigger */
<>	144:ef7eb2e8f9f7	2446	{
<>	144:ef7eb2e8f9f7	2447	/* Enter init mode */
<>	144:ef7eb2e8f9f7	2448	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	2449	{
<>	144:ef7eb2e8f9f7	2450	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	2451	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2452	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2453	}
<>	144:ef7eb2e8f9f7	2454	else
<>	144:ef7eb2e8f9f7	2455	{
<>	144:ef7eb2e8f9f7	2456	/* Set RSYNC bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2457	hsdadc->Instance->CR1 \|= SDADC_CR1_RSYNC;
<>	144:ef7eb2e8f9f7	2458
<>	144:ef7eb2e8f9f7	2459	/* Exit init mode */
<>	144:ef7eb2e8f9f7	2460	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	2461	}
<>	144:ef7eb2e8f9f7	2462	}
<>	144:ef7eb2e8f9f7	2463	/* Update SDADC state only if status is OK */
<>	144:ef7eb2e8f9f7	2464	if(status == HAL_OK)
<>	144:ef7eb2e8f9f7	2465	{
<>	144:ef7eb2e8f9f7	2466	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
<>	144:ef7eb2e8f9f7	2467	HAL_SDADC_STATE_REG : HAL_SDADC_STATE_REG_INJ;
<>	144:ef7eb2e8f9f7	2468	}
<>	144:ef7eb2e8f9f7	2469	/* Return function status */
<>	144:ef7eb2e8f9f7	2470	return status;
<>	144:ef7eb2e8f9f7	2471	}
<>	144:ef7eb2e8f9f7	2472
<>	144:ef7eb2e8f9f7	2473	/**
<>	144:ef7eb2e8f9f7	2474	* @brief This function allows to really stop regular conversion.
<>	144:ef7eb2e8f9f7	2475	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2476	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2477	*/
<>	144:ef7eb2e8f9f7	2478	static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2479	{
<>	144:ef7eb2e8f9f7	2480	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	2481	__IO uint32_t dummy_read_for_register_reset;
<>	144:ef7eb2e8f9f7	2482
<>	144:ef7eb2e8f9f7	2483	/* Check continuous mode */
<>	144:ef7eb2e8f9f7	2484	if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
<>	144:ef7eb2e8f9f7	2485	{
<>	144:ef7eb2e8f9f7	2486	/* Clear REOCF by reading SDADC_RDATAR register */
<>	144:ef7eb2e8f9f7	2487	dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
<>	144:ef7eb2e8f9f7	2488	UNUSED(dummy_read_for_register_reset);
<>	144:ef7eb2e8f9f7	2489
<>	144:ef7eb2e8f9f7	2490	/* Clear RCONT bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2491	hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
<>	144:ef7eb2e8f9f7	2492	}
<>	144:ef7eb2e8f9f7	2493	/* Wait for the end of regular conversion */
<>	144:ef7eb2e8f9f7	2494	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2495	while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0)
<>	144:ef7eb2e8f9f7	2496	{
<>	144:ef7eb2e8f9f7	2497	if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
<>	144:ef7eb2e8f9f7	2498	{
<>	144:ef7eb2e8f9f7	2499	/* Set SDADC in error state and return timeout status */
<>	144:ef7eb2e8f9f7	2500	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2501	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2502	}
<>	144:ef7eb2e8f9f7	2503	}
<>	144:ef7eb2e8f9f7	2504	/* Check if trigger is synchronuous */
<>	144:ef7eb2e8f9f7	2505	if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
<>	144:ef7eb2e8f9f7	2506	{
<>	144:ef7eb2e8f9f7	2507	/* Enter init mode */
<>	144:ef7eb2e8f9f7	2508	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	2509	{
<>	144:ef7eb2e8f9f7	2510	/* Set SDADC in error state and return timeout status */
<>	144:ef7eb2e8f9f7	2511	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2512	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2513	}
<>	144:ef7eb2e8f9f7	2514	else
<>	144:ef7eb2e8f9f7	2515	{
<>	144:ef7eb2e8f9f7	2516	/* Clear RSYNC bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2517	hsdadc->Instance->CR1 &= ~(SDADC_CR1_RSYNC);
<>	144:ef7eb2e8f9f7	2518
<>	144:ef7eb2e8f9f7	2519	/* Exit init mode */
<>	144:ef7eb2e8f9f7	2520	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	2521	}
<>	144:ef7eb2e8f9f7	2522	}
<>	144:ef7eb2e8f9f7	2523	/* Check if continuous mode */
<>	144:ef7eb2e8f9f7	2524	if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
<>	144:ef7eb2e8f9f7	2525	{
<>	144:ef7eb2e8f9f7	2526	/* Restore RCONT bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2527	hsdadc->Instance->CR2 \|= SDADC_CR2_RCONT;
<>	144:ef7eb2e8f9f7	2528	}
<>	144:ef7eb2e8f9f7	2529	/* Clear REOCF by reading SDADC_RDATAR register */
<>	144:ef7eb2e8f9f7	2530	dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
<>	144:ef7eb2e8f9f7	2531	UNUSED(dummy_read_for_register_reset);
<>	144:ef7eb2e8f9f7	2532
<>	144:ef7eb2e8f9f7	2533	/* Set CLRROVRF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	2534	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLRROVRF;
<>	144:ef7eb2e8f9f7	2535
<>	144:ef7eb2e8f9f7	2536	/* Update SDADC state */
<>	144:ef7eb2e8f9f7	2537	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
<>	144:ef7eb2e8f9f7	2538	HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
<>	144:ef7eb2e8f9f7	2539
<>	144:ef7eb2e8f9f7	2540	/* Return function status */
<>	144:ef7eb2e8f9f7	2541	return HAL_OK;
<>	144:ef7eb2e8f9f7	2542	}
<>	144:ef7eb2e8f9f7	2543
<>	144:ef7eb2e8f9f7	2544	/**
<>	144:ef7eb2e8f9f7	2545	* @brief This function allows to really start injected conversion.
<>	144:ef7eb2e8f9f7	2546	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2547	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2548	*/
<>	144:ef7eb2e8f9f7	2549	static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2550	{
<>	144:ef7eb2e8f9f7	2551	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	2552
<>	144:ef7eb2e8f9f7	2553	/* Initialize number of injected conversions remaining */
<>	144:ef7eb2e8f9f7	2554	hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
<>	144:ef7eb2e8f9f7	2555
<>	144:ef7eb2e8f9f7	2556	/* Check injected trigger */
<>	144:ef7eb2e8f9f7	2557	if(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER)
<>	144:ef7eb2e8f9f7	2558	{
<>	144:ef7eb2e8f9f7	2559	/* Set JSWSTART bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2560	hsdadc->Instance->CR2 \|= SDADC_CR2_JSWSTART;
<>	144:ef7eb2e8f9f7	2561	}
<>	144:ef7eb2e8f9f7	2562	else /* external or synchronuous trigger */
<>	144:ef7eb2e8f9f7	2563	{
<>	144:ef7eb2e8f9f7	2564	/* Enter init mode */
<>	144:ef7eb2e8f9f7	2565	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	2566	{
<>	144:ef7eb2e8f9f7	2567	/* Set SDADC in error state */
<>	144:ef7eb2e8f9f7	2568	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2569	status = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2570	}
<>	144:ef7eb2e8f9f7	2571	else
<>	144:ef7eb2e8f9f7	2572	{
<>	144:ef7eb2e8f9f7	2573	if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
<>	144:ef7eb2e8f9f7	2574	{
<>	144:ef7eb2e8f9f7	2575	/* Set JSYNC bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2576	hsdadc->Instance->CR1 \|= SDADC_CR1_JSYNC;
<>	144:ef7eb2e8f9f7	2577	}
<>	144:ef7eb2e8f9f7	2578	else /* external trigger */
<>	144:ef7eb2e8f9f7	2579	{
<>	144:ef7eb2e8f9f7	2580	/* Set JEXTEN[1:0] bits in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2581	hsdadc->Instance->CR2 \|= hsdadc->ExtTriggerEdge;
<>	144:ef7eb2e8f9f7	2582	}
<>	144:ef7eb2e8f9f7	2583	/* Exit init mode */
<>	144:ef7eb2e8f9f7	2584	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	2585	}
<>	144:ef7eb2e8f9f7	2586	}
<>	144:ef7eb2e8f9f7	2587	/* Update SDADC state only if status is OK */
<>	144:ef7eb2e8f9f7	2588	if(status == HAL_OK)
<>	144:ef7eb2e8f9f7	2589	{
<>	144:ef7eb2e8f9f7	2590	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
<>	144:ef7eb2e8f9f7	2591	HAL_SDADC_STATE_INJ : HAL_SDADC_STATE_REG_INJ;
<>	144:ef7eb2e8f9f7	2592	}
<>	144:ef7eb2e8f9f7	2593	/* Return function status */
<>	144:ef7eb2e8f9f7	2594	return status;
<>	144:ef7eb2e8f9f7	2595	}
<>	144:ef7eb2e8f9f7	2596
<>	144:ef7eb2e8f9f7	2597	/**
<>	144:ef7eb2e8f9f7	2598	* @brief This function allows to really stop injected conversion.
<>	144:ef7eb2e8f9f7	2599	* @param hsdadc: SDADC handle.
<>	144:ef7eb2e8f9f7	2600	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2601	*/
<>	144:ef7eb2e8f9f7	2602	static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
<>	144:ef7eb2e8f9f7	2603	{
<>	144:ef7eb2e8f9f7	2604	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	2605	__IO uint32_t dummy_read_for_register_reset;
<>	144:ef7eb2e8f9f7	2606
<>	144:ef7eb2e8f9f7	2607	/* Check continuous mode */
<>	144:ef7eb2e8f9f7	2608	if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
<>	144:ef7eb2e8f9f7	2609	{
<>	144:ef7eb2e8f9f7	2610	/* Clear JEOCF by reading SDADC_JDATAR register */
<>	144:ef7eb2e8f9f7	2611	dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
<>	144:ef7eb2e8f9f7	2612	UNUSED(dummy_read_for_register_reset);
<>	144:ef7eb2e8f9f7	2613
<>	144:ef7eb2e8f9f7	2614	/* Clear JCONT bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2615	hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
<>	144:ef7eb2e8f9f7	2616	}
<>	144:ef7eb2e8f9f7	2617	/* Wait for the end of injected conversion */
<>	144:ef7eb2e8f9f7	2618	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2619	while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0)
<>	144:ef7eb2e8f9f7	2620	{
<>	144:ef7eb2e8f9f7	2621	if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
<>	144:ef7eb2e8f9f7	2622	{
<>	144:ef7eb2e8f9f7	2623	/* Set SDADC in error state and return timeout status */
<>	144:ef7eb2e8f9f7	2624	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2625	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2626	}
<>	144:ef7eb2e8f9f7	2627	}
<>	144:ef7eb2e8f9f7	2628	/* Check if trigger is not software */
<>	144:ef7eb2e8f9f7	2629	if(hsdadc->InjectedTrigger != SDADC_SOFTWARE_TRIGGER)
<>	144:ef7eb2e8f9f7	2630	{
<>	144:ef7eb2e8f9f7	2631	/* Enter init mode */
<>	144:ef7eb2e8f9f7	2632	if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
<>	144:ef7eb2e8f9f7	2633	{
<>	144:ef7eb2e8f9f7	2634	/* Set SDADC in error state and return timeout status */
<>	144:ef7eb2e8f9f7	2635	hsdadc->State = HAL_SDADC_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2636	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2637	}
<>	144:ef7eb2e8f9f7	2638	else
<>	144:ef7eb2e8f9f7	2639	{
<>	144:ef7eb2e8f9f7	2640	/* Check if trigger is synchronuous */
<>	144:ef7eb2e8f9f7	2641	if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
<>	144:ef7eb2e8f9f7	2642	{
<>	144:ef7eb2e8f9f7	2643	/* Clear JSYNC bit in SDADC_CR1 register */
<>	144:ef7eb2e8f9f7	2644	hsdadc->Instance->CR1 &= ~(SDADC_CR1_JSYNC);
<>	144:ef7eb2e8f9f7	2645	}
<>	144:ef7eb2e8f9f7	2646	else /* external trigger */
<>	144:ef7eb2e8f9f7	2647	{
<>	144:ef7eb2e8f9f7	2648	/* Clear JEXTEN[1:0] bits in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2649	hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTEN);
<>	144:ef7eb2e8f9f7	2650	}
<>	144:ef7eb2e8f9f7	2651	/* Exit init mode */
<>	144:ef7eb2e8f9f7	2652	SDADC_ExitInitMode(hsdadc);
<>	144:ef7eb2e8f9f7	2653	}
<>	144:ef7eb2e8f9f7	2654	}
<>	144:ef7eb2e8f9f7	2655	/* Check if continuous mode */
<>	144:ef7eb2e8f9f7	2656	if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
<>	144:ef7eb2e8f9f7	2657	{
<>	144:ef7eb2e8f9f7	2658	/* Restore JCONT bit in SDADC_CR2 register */
<>	144:ef7eb2e8f9f7	2659	hsdadc->Instance->CR2 \|= SDADC_CR2_JCONT;
<>	144:ef7eb2e8f9f7	2660	}
<>	144:ef7eb2e8f9f7	2661	/* Clear JEOCF by reading SDADC_JDATAR register */
<>	144:ef7eb2e8f9f7	2662	dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
<>	144:ef7eb2e8f9f7	2663	UNUSED(dummy_read_for_register_reset);
<>	144:ef7eb2e8f9f7	2664
<>	144:ef7eb2e8f9f7	2665	/* Set CLRJOVRF bit in SDADC_CLRISR register */
<>	144:ef7eb2e8f9f7	2666	hsdadc->Instance->CLRISR \|= SDADC_ISR_CLRJOVRF;
<>	144:ef7eb2e8f9f7	2667
<>	144:ef7eb2e8f9f7	2668	/* Update SDADC state */
<>	144:ef7eb2e8f9f7	2669	hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
<>	144:ef7eb2e8f9f7	2670	HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
<>	144:ef7eb2e8f9f7	2671
<>	144:ef7eb2e8f9f7	2672	/* Return function status */
<>	144:ef7eb2e8f9f7	2673	return HAL_OK;
<>	144:ef7eb2e8f9f7	2674	}
<>	144:ef7eb2e8f9f7	2675
<>	144:ef7eb2e8f9f7	2676	/**
<>	144:ef7eb2e8f9f7	2677	* @}
<>	144:ef7eb2e8f9f7	2678	*/
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680	/**
<>	144:ef7eb2e8f9f7	2681	* @}
<>	144:ef7eb2e8f9f7	2682	*/
<>	144:ef7eb2e8f9f7	2683
<>	144:ef7eb2e8f9f7	2684	/**
<>	144:ef7eb2e8f9f7	2685	* @}
<>	144:ef7eb2e8f9f7	2686	*/
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	#endif /* defined(STM32F373xC) \|\| defined(STM32F378xx) */
<>	144:ef7eb2e8f9f7	2689	#endif /* HAL_SDADC_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2690	/**
<>	144:ef7eb2e8f9f7	2691	* @}
<>	144:ef7eb2e8f9f7	2692	*/
<>	144:ef7eb2e8f9f7	2693
<>	144:ef7eb2e8f9f7	2694	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	19 Nov 2016
Imports:	0
Forks:	0
Commits:	152
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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sdadc.c@149:156823d33999, 2016-10-28 (annotated)

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