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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c@167:e84263d55307, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:46:44 2017 +0100
- Revision:
- 167:e84263d55307
- Child:
- 182:a56a73fd2a6f
This updates the lib to the mbed lib v 145
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 167:e84263d55307 | 1 | /** |
| AnnaBridge | 167:e84263d55307 | 2 | ****************************************************************************** |
| AnnaBridge | 167:e84263d55307 | 3 | * @file stm32f4xx_ll_utils.c |
| AnnaBridge | 167:e84263d55307 | 4 | * @author MCD Application Team |
| AnnaBridge | 167:e84263d55307 | 5 | * @version V1.7.1 |
| AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
| AnnaBridge | 167:e84263d55307 | 7 | * @brief UTILS LL module driver. |
| AnnaBridge | 167:e84263d55307 | 8 | ****************************************************************************** |
| AnnaBridge | 167:e84263d55307 | 9 | * @attention |
| AnnaBridge | 167:e84263d55307 | 10 | * |
| AnnaBridge | 167:e84263d55307 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 167:e84263d55307 | 12 | * |
| AnnaBridge | 167:e84263d55307 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 167:e84263d55307 | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 167:e84263d55307 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 167:e84263d55307 | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 167:e84263d55307 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 167:e84263d55307 | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 167:e84263d55307 | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 167:e84263d55307 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 167:e84263d55307 | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 167:e84263d55307 | 22 | * without specific prior written permission. |
| AnnaBridge | 167:e84263d55307 | 23 | * |
| AnnaBridge | 167:e84263d55307 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 167:e84263d55307 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 167:e84263d55307 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 167:e84263d55307 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 167:e84263d55307 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 167:e84263d55307 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 167:e84263d55307 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 167:e84263d55307 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 167:e84263d55307 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 167:e84263d55307 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 167:e84263d55307 | 34 | * |
| AnnaBridge | 167:e84263d55307 | 35 | ****************************************************************************** |
| AnnaBridge | 167:e84263d55307 | 36 | */ |
| AnnaBridge | 167:e84263d55307 | 37 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 38 | #include "stm32f4xx_ll_utils.h" |
| AnnaBridge | 167:e84263d55307 | 39 | #include "stm32f4xx_ll_rcc.h" |
| AnnaBridge | 167:e84263d55307 | 40 | #include "stm32f4xx_ll_system.h" |
| AnnaBridge | 167:e84263d55307 | 41 | #include "stm32f4xx_ll_pwr.h" |
| AnnaBridge | 167:e84263d55307 | 42 | |
| AnnaBridge | 167:e84263d55307 | 43 | /** @addtogroup STM32F4xx_LL_Driver |
| AnnaBridge | 167:e84263d55307 | 44 | * @{ |
| AnnaBridge | 167:e84263d55307 | 45 | */ |
| AnnaBridge | 167:e84263d55307 | 46 | |
| AnnaBridge | 167:e84263d55307 | 47 | /** @addtogroup UTILS_LL |
| AnnaBridge | 167:e84263d55307 | 48 | * @{ |
| AnnaBridge | 167:e84263d55307 | 49 | */ |
| AnnaBridge | 167:e84263d55307 | 50 | |
| AnnaBridge | 167:e84263d55307 | 51 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 52 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 53 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 54 | /** @addtogroup UTILS_LL_Private_Constants |
| AnnaBridge | 167:e84263d55307 | 55 | * @{ |
| AnnaBridge | 167:e84263d55307 | 56 | */ |
| AnnaBridge | 167:e84263d55307 | 57 | #if defined(RCC_MAX_FREQUENCY_SCALE1) |
| AnnaBridge | 167:e84263d55307 | 58 | #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 59 | #endif /*RCC_MAX_FREQUENCY_SCALE1 */ |
| AnnaBridge | 167:e84263d55307 | 60 | #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 61 | #if defined(RCC_MAX_FREQUENCY_SCALE3) |
| AnnaBridge | 167:e84263d55307 | 62 | #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 63 | #endif /* MAX_FREQUENCY_SCALE3 */ |
| AnnaBridge | 167:e84263d55307 | 64 | |
| AnnaBridge | 167:e84263d55307 | 65 | /* Defines used for PLL range */ |
| AnnaBridge | 167:e84263d55307 | 66 | #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 67 | #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 68 | #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 69 | #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 70 | |
| AnnaBridge | 167:e84263d55307 | 71 | /* Defines used for HSE range */ |
| AnnaBridge | 167:e84263d55307 | 72 | #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 73 | #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 74 | |
| AnnaBridge | 167:e84263d55307 | 75 | /* Defines used for FLASH latency according to HCLK Frequency */ |
| AnnaBridge | 167:e84263d55307 | 76 | #if defined(FLASH_SCALE1_LATENCY1_FREQ) |
| AnnaBridge | 167:e84263d55307 | 77 | #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 78 | #endif |
| AnnaBridge | 167:e84263d55307 | 79 | #if defined(FLASH_SCALE1_LATENCY2_FREQ) |
| AnnaBridge | 167:e84263d55307 | 80 | #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 81 | #endif |
| AnnaBridge | 167:e84263d55307 | 82 | #if defined(FLASH_SCALE1_LATENCY3_FREQ) |
| AnnaBridge | 167:e84263d55307 | 83 | #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 84 | #endif |
| AnnaBridge | 167:e84263d55307 | 85 | #if defined(FLASH_SCALE1_LATENCY4_FREQ) |
| AnnaBridge | 167:e84263d55307 | 86 | #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 87 | #endif |
| AnnaBridge | 167:e84263d55307 | 88 | #if defined(FLASH_SCALE1_LATENCY5_FREQ) |
| AnnaBridge | 167:e84263d55307 | 89 | #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 90 | #endif |
| AnnaBridge | 167:e84263d55307 | 91 | #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 92 | #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 93 | #if defined(FLASH_SCALE2_LATENCY3_FREQ) |
| AnnaBridge | 167:e84263d55307 | 94 | #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 95 | #endif |
| AnnaBridge | 167:e84263d55307 | 96 | #if defined(FLASH_SCALE2_LATENCY4_FREQ) |
| AnnaBridge | 167:e84263d55307 | 97 | #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 98 | #endif |
| AnnaBridge | 167:e84263d55307 | 99 | #if defined(FLASH_SCALE2_LATENCY5_FREQ) |
| AnnaBridge | 167:e84263d55307 | 100 | #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 101 | #endif |
| AnnaBridge | 167:e84263d55307 | 102 | #if defined(FLASH_SCALE3_LATENCY1_FREQ) |
| AnnaBridge | 167:e84263d55307 | 103 | #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 104 | #endif |
| AnnaBridge | 167:e84263d55307 | 105 | #if defined(FLASH_SCALE3_LATENCY2_FREQ) |
| AnnaBridge | 167:e84263d55307 | 106 | #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 107 | #endif |
| AnnaBridge | 167:e84263d55307 | 108 | #if defined(FLASH_SCALE3_LATENCY3_FREQ) |
| AnnaBridge | 167:e84263d55307 | 109 | #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 110 | #endif |
| AnnaBridge | 167:e84263d55307 | 111 | #if defined(FLASH_SCALE3_LATENCY4_FREQ) |
| AnnaBridge | 167:e84263d55307 | 112 | #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 113 | #endif |
| AnnaBridge | 167:e84263d55307 | 114 | #if defined(FLASH_SCALE3_LATENCY5_FREQ) |
| AnnaBridge | 167:e84263d55307 | 115 | #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 116 | #endif |
| AnnaBridge | 167:e84263d55307 | 117 | /** |
| AnnaBridge | 167:e84263d55307 | 118 | * @} |
| AnnaBridge | 167:e84263d55307 | 119 | */ |
| AnnaBridge | 167:e84263d55307 | 120 | |
| AnnaBridge | 167:e84263d55307 | 121 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 122 | /** @addtogroup UTILS_LL_Private_Macros |
| AnnaBridge | 167:e84263d55307 | 123 | * @{ |
| AnnaBridge | 167:e84263d55307 | 124 | */ |
| AnnaBridge | 167:e84263d55307 | 125 | #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ |
| AnnaBridge | 167:e84263d55307 | 126 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ |
| AnnaBridge | 167:e84263d55307 | 127 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ |
| AnnaBridge | 167:e84263d55307 | 128 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ |
| AnnaBridge | 167:e84263d55307 | 129 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ |
| AnnaBridge | 167:e84263d55307 | 130 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ |
| AnnaBridge | 167:e84263d55307 | 131 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ |
| AnnaBridge | 167:e84263d55307 | 132 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ |
| AnnaBridge | 167:e84263d55307 | 133 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) |
| AnnaBridge | 167:e84263d55307 | 134 | |
| AnnaBridge | 167:e84263d55307 | 135 | #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ |
| AnnaBridge | 167:e84263d55307 | 136 | || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ |
| AnnaBridge | 167:e84263d55307 | 137 | || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ |
| AnnaBridge | 167:e84263d55307 | 138 | || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ |
| AnnaBridge | 167:e84263d55307 | 139 | || ((__VALUE__) == LL_RCC_APB1_DIV_16)) |
| AnnaBridge | 167:e84263d55307 | 140 | |
| AnnaBridge | 167:e84263d55307 | 141 | #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ |
| AnnaBridge | 167:e84263d55307 | 142 | || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ |
| AnnaBridge | 167:e84263d55307 | 143 | || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ |
| AnnaBridge | 167:e84263d55307 | 144 | || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ |
| AnnaBridge | 167:e84263d55307 | 145 | || ((__VALUE__) == LL_RCC_APB2_DIV_16)) |
| AnnaBridge | 167:e84263d55307 | 146 | |
| AnnaBridge | 167:e84263d55307 | 147 | #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \ |
| AnnaBridge | 167:e84263d55307 | 148 | || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ |
| AnnaBridge | 167:e84263d55307 | 149 | || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ |
| AnnaBridge | 167:e84263d55307 | 150 | || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ |
| AnnaBridge | 167:e84263d55307 | 151 | || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ |
| AnnaBridge | 167:e84263d55307 | 152 | || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ |
| AnnaBridge | 167:e84263d55307 | 153 | || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ |
| AnnaBridge | 167:e84263d55307 | 154 | || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ |
| AnnaBridge | 167:e84263d55307 | 155 | || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ |
| AnnaBridge | 167:e84263d55307 | 156 | || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ |
| AnnaBridge | 167:e84263d55307 | 157 | || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ |
| AnnaBridge | 167:e84263d55307 | 158 | || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ |
| AnnaBridge | 167:e84263d55307 | 159 | || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ |
| AnnaBridge | 167:e84263d55307 | 160 | || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ |
| AnnaBridge | 167:e84263d55307 | 161 | || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \ |
| AnnaBridge | 167:e84263d55307 | 162 | || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \ |
| AnnaBridge | 167:e84263d55307 | 163 | || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \ |
| AnnaBridge | 167:e84263d55307 | 164 | || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \ |
| AnnaBridge | 167:e84263d55307 | 165 | || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \ |
| AnnaBridge | 167:e84263d55307 | 166 | || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \ |
| AnnaBridge | 167:e84263d55307 | 167 | || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \ |
| AnnaBridge | 167:e84263d55307 | 168 | || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \ |
| AnnaBridge | 167:e84263d55307 | 169 | || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \ |
| AnnaBridge | 167:e84263d55307 | 170 | || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \ |
| AnnaBridge | 167:e84263d55307 | 171 | || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \ |
| AnnaBridge | 167:e84263d55307 | 172 | || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \ |
| AnnaBridge | 167:e84263d55307 | 173 | || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \ |
| AnnaBridge | 167:e84263d55307 | 174 | || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \ |
| AnnaBridge | 167:e84263d55307 | 175 | || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \ |
| AnnaBridge | 167:e84263d55307 | 176 | || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \ |
| AnnaBridge | 167:e84263d55307 | 177 | || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \ |
| AnnaBridge | 167:e84263d55307 | 178 | || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \ |
| AnnaBridge | 167:e84263d55307 | 179 | || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \ |
| AnnaBridge | 167:e84263d55307 | 180 | || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \ |
| AnnaBridge | 167:e84263d55307 | 181 | || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \ |
| AnnaBridge | 167:e84263d55307 | 182 | || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \ |
| AnnaBridge | 167:e84263d55307 | 183 | || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \ |
| AnnaBridge | 167:e84263d55307 | 184 | || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \ |
| AnnaBridge | 167:e84263d55307 | 185 | || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \ |
| AnnaBridge | 167:e84263d55307 | 186 | || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \ |
| AnnaBridge | 167:e84263d55307 | 187 | || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \ |
| AnnaBridge | 167:e84263d55307 | 188 | || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \ |
| AnnaBridge | 167:e84263d55307 | 189 | || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \ |
| AnnaBridge | 167:e84263d55307 | 190 | || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \ |
| AnnaBridge | 167:e84263d55307 | 191 | || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \ |
| AnnaBridge | 167:e84263d55307 | 192 | || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \ |
| AnnaBridge | 167:e84263d55307 | 193 | || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \ |
| AnnaBridge | 167:e84263d55307 | 194 | || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \ |
| AnnaBridge | 167:e84263d55307 | 195 | || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \ |
| AnnaBridge | 167:e84263d55307 | 196 | || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \ |
| AnnaBridge | 167:e84263d55307 | 197 | || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \ |
| AnnaBridge | 167:e84263d55307 | 198 | || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \ |
| AnnaBridge | 167:e84263d55307 | 199 | || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \ |
| AnnaBridge | 167:e84263d55307 | 200 | || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \ |
| AnnaBridge | 167:e84263d55307 | 201 | || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \ |
| AnnaBridge | 167:e84263d55307 | 202 | || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \ |
| AnnaBridge | 167:e84263d55307 | 203 | || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \ |
| AnnaBridge | 167:e84263d55307 | 204 | || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \ |
| AnnaBridge | 167:e84263d55307 | 205 | || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \ |
| AnnaBridge | 167:e84263d55307 | 206 | || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \ |
| AnnaBridge | 167:e84263d55307 | 207 | || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \ |
| AnnaBridge | 167:e84263d55307 | 208 | || ((__VALUE__) == LL_RCC_PLLM_DIV_63)) |
| AnnaBridge | 167:e84263d55307 | 209 | |
| AnnaBridge | 167:e84263d55307 | 210 | #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE)) |
| AnnaBridge | 167:e84263d55307 | 211 | |
| AnnaBridge | 167:e84263d55307 | 212 | #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \ |
| AnnaBridge | 167:e84263d55307 | 213 | || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \ |
| AnnaBridge | 167:e84263d55307 | 214 | || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \ |
| AnnaBridge | 167:e84263d55307 | 215 | || ((__VALUE__) == LL_RCC_PLLP_DIV_8)) |
| AnnaBridge | 167:e84263d55307 | 216 | |
| AnnaBridge | 167:e84263d55307 | 217 | #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) |
| AnnaBridge | 167:e84263d55307 | 218 | |
| AnnaBridge | 167:e84263d55307 | 219 | #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) |
| AnnaBridge | 167:e84263d55307 | 220 | |
| AnnaBridge | 167:e84263d55307 | 221 | #if !defined(RCC_MAX_FREQUENCY_SCALE1) |
| AnnaBridge | 167:e84263d55307 | 222 | #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ |
| AnnaBridge | 167:e84263d55307 | 223 | ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) |
| AnnaBridge | 167:e84263d55307 | 224 | |
| AnnaBridge | 167:e84263d55307 | 225 | #elif defined(RCC_MAX_FREQUENCY_SCALE3) |
| AnnaBridge | 167:e84263d55307 | 226 | #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ |
| AnnaBridge | 167:e84263d55307 | 227 | (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ |
| AnnaBridge | 167:e84263d55307 | 228 | ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) |
| AnnaBridge | 167:e84263d55307 | 229 | |
| AnnaBridge | 167:e84263d55307 | 230 | #else |
| AnnaBridge | 167:e84263d55307 | 231 | #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ |
| AnnaBridge | 167:e84263d55307 | 232 | ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) |
| AnnaBridge | 167:e84263d55307 | 233 | |
| AnnaBridge | 167:e84263d55307 | 234 | #endif /* RCC_MAX_FREQUENCY_SCALE1*/ |
| AnnaBridge | 167:e84263d55307 | 235 | #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ |
| AnnaBridge | 167:e84263d55307 | 236 | || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) |
| AnnaBridge | 167:e84263d55307 | 237 | |
| AnnaBridge | 167:e84263d55307 | 238 | #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) |
| AnnaBridge | 167:e84263d55307 | 239 | /** |
| AnnaBridge | 167:e84263d55307 | 240 | * @} |
| AnnaBridge | 167:e84263d55307 | 241 | */ |
| AnnaBridge | 167:e84263d55307 | 242 | /* Private function prototypes -----------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 243 | /** @defgroup UTILS_LL_Private_Functions UTILS Private functions |
| AnnaBridge | 167:e84263d55307 | 244 | * @{ |
| AnnaBridge | 167:e84263d55307 | 245 | */ |
| AnnaBridge | 167:e84263d55307 | 246 | static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, |
| AnnaBridge | 167:e84263d55307 | 247 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); |
| AnnaBridge | 167:e84263d55307 | 248 | static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); |
| AnnaBridge | 167:e84263d55307 | 249 | static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); |
| AnnaBridge | 167:e84263d55307 | 250 | static ErrorStatus UTILS_PLL_IsBusy(void); |
| AnnaBridge | 167:e84263d55307 | 251 | /** |
| AnnaBridge | 167:e84263d55307 | 252 | * @} |
| AnnaBridge | 167:e84263d55307 | 253 | */ |
| AnnaBridge | 167:e84263d55307 | 254 | |
| AnnaBridge | 167:e84263d55307 | 255 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 256 | /** @addtogroup UTILS_LL_Exported_Functions |
| AnnaBridge | 167:e84263d55307 | 257 | * @{ |
| AnnaBridge | 167:e84263d55307 | 258 | */ |
| AnnaBridge | 167:e84263d55307 | 259 | |
| AnnaBridge | 167:e84263d55307 | 260 | /** @addtogroup UTILS_LL_EF_DELAY |
| AnnaBridge | 167:e84263d55307 | 261 | * @{ |
| AnnaBridge | 167:e84263d55307 | 262 | */ |
| AnnaBridge | 167:e84263d55307 | 263 | |
| AnnaBridge | 167:e84263d55307 | 264 | /** |
| AnnaBridge | 167:e84263d55307 | 265 | * @brief This function configures the Cortex-M SysTick source to have 1ms time base. |
| AnnaBridge | 167:e84263d55307 | 266 | * @note When a RTOS is used, it is recommended to avoid changing the Systick |
| AnnaBridge | 167:e84263d55307 | 267 | * configuration by calling this function, for a delay use rather osDelay RTOS service. |
| AnnaBridge | 167:e84263d55307 | 268 | * @param HCLKFrequency HCLK frequency in Hz |
| AnnaBridge | 167:e84263d55307 | 269 | * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq |
| AnnaBridge | 167:e84263d55307 | 270 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 271 | */ |
| AnnaBridge | 167:e84263d55307 | 272 | void LL_Init1msTick(uint32_t HCLKFrequency) |
| AnnaBridge | 167:e84263d55307 | 273 | { |
| AnnaBridge | 167:e84263d55307 | 274 | /* Use frequency provided in argument */ |
| AnnaBridge | 167:e84263d55307 | 275 | LL_InitTick(HCLKFrequency, 1000U); |
| AnnaBridge | 167:e84263d55307 | 276 | } |
| AnnaBridge | 167:e84263d55307 | 277 | |
| AnnaBridge | 167:e84263d55307 | 278 | /** |
| AnnaBridge | 167:e84263d55307 | 279 | * @brief This function provides accurate delay (in milliseconds) based |
| AnnaBridge | 167:e84263d55307 | 280 | * on SysTick counter flag |
| AnnaBridge | 167:e84263d55307 | 281 | * @note When a RTOS is used, it is recommended to avoid using blocking delay |
| AnnaBridge | 167:e84263d55307 | 282 | * and use rather osDelay service. |
| AnnaBridge | 167:e84263d55307 | 283 | * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which |
| AnnaBridge | 167:e84263d55307 | 284 | * will configure Systick to 1ms |
| AnnaBridge | 167:e84263d55307 | 285 | * @param Delay specifies the delay time length, in milliseconds. |
| AnnaBridge | 167:e84263d55307 | 286 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 287 | */ |
| AnnaBridge | 167:e84263d55307 | 288 | void LL_mDelay(uint32_t Delay) |
| AnnaBridge | 167:e84263d55307 | 289 | { |
| AnnaBridge | 167:e84263d55307 | 290 | __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ |
| AnnaBridge | 167:e84263d55307 | 291 | /* Add this code to indicate that local variable is not used */ |
| AnnaBridge | 167:e84263d55307 | 292 | ((void)tmp); |
| AnnaBridge | 167:e84263d55307 | 293 | |
| AnnaBridge | 167:e84263d55307 | 294 | /* Add a period to guaranty minimum wait */ |
| AnnaBridge | 167:e84263d55307 | 295 | if(Delay < LL_MAX_DELAY) |
| AnnaBridge | 167:e84263d55307 | 296 | { |
| AnnaBridge | 167:e84263d55307 | 297 | Delay++; |
| AnnaBridge | 167:e84263d55307 | 298 | } |
| AnnaBridge | 167:e84263d55307 | 299 | |
| AnnaBridge | 167:e84263d55307 | 300 | while (Delay) |
| AnnaBridge | 167:e84263d55307 | 301 | { |
| AnnaBridge | 167:e84263d55307 | 302 | if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) |
| AnnaBridge | 167:e84263d55307 | 303 | { |
| AnnaBridge | 167:e84263d55307 | 304 | Delay--; |
| AnnaBridge | 167:e84263d55307 | 305 | } |
| AnnaBridge | 167:e84263d55307 | 306 | } |
| AnnaBridge | 167:e84263d55307 | 307 | } |
| AnnaBridge | 167:e84263d55307 | 308 | |
| AnnaBridge | 167:e84263d55307 | 309 | /** |
| AnnaBridge | 167:e84263d55307 | 310 | * @} |
| AnnaBridge | 167:e84263d55307 | 311 | */ |
| AnnaBridge | 167:e84263d55307 | 312 | |
| AnnaBridge | 167:e84263d55307 | 313 | /** @addtogroup UTILS_EF_SYSTEM |
| AnnaBridge | 167:e84263d55307 | 314 | * @brief System Configuration functions |
| AnnaBridge | 167:e84263d55307 | 315 | * |
| AnnaBridge | 167:e84263d55307 | 316 | @verbatim |
| AnnaBridge | 167:e84263d55307 | 317 | =============================================================================== |
| AnnaBridge | 167:e84263d55307 | 318 | ##### System Configuration functions ##### |
| AnnaBridge | 167:e84263d55307 | 319 | =============================================================================== |
| AnnaBridge | 167:e84263d55307 | 320 | [..] |
| AnnaBridge | 167:e84263d55307 | 321 | System, AHB and APB buses clocks configuration |
| AnnaBridge | 167:e84263d55307 | 322 | |
| AnnaBridge | 167:e84263d55307 | 323 | (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz. |
| AnnaBridge | 167:e84263d55307 | 324 | @endverbatim |
| AnnaBridge | 167:e84263d55307 | 325 | @internal |
| AnnaBridge | 167:e84263d55307 | 326 | Depending on the device voltage range, the maximum frequency should be |
| AnnaBridge | 167:e84263d55307 | 327 | adapted accordingly to the Refenece manual. |
| AnnaBridge | 167:e84263d55307 | 328 | @endinternal |
| AnnaBridge | 167:e84263d55307 | 329 | * @{ |
| AnnaBridge | 167:e84263d55307 | 330 | */ |
| AnnaBridge | 167:e84263d55307 | 331 | |
| AnnaBridge | 167:e84263d55307 | 332 | /** |
| AnnaBridge | 167:e84263d55307 | 333 | * @brief This function sets directly SystemCoreClock CMSIS variable. |
| AnnaBridge | 167:e84263d55307 | 334 | * @note Variable can be calculated also through SystemCoreClockUpdate function. |
| AnnaBridge | 167:e84263d55307 | 335 | * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) |
| AnnaBridge | 167:e84263d55307 | 336 | * @retval None |
| AnnaBridge | 167:e84263d55307 | 337 | */ |
| AnnaBridge | 167:e84263d55307 | 338 | void LL_SetSystemCoreClock(uint32_t HCLKFrequency) |
| AnnaBridge | 167:e84263d55307 | 339 | { |
| AnnaBridge | 167:e84263d55307 | 340 | /* HCLK clock frequency */ |
| AnnaBridge | 167:e84263d55307 | 341 | SystemCoreClock = HCLKFrequency; |
| AnnaBridge | 167:e84263d55307 | 342 | } |
| AnnaBridge | 167:e84263d55307 | 343 | |
| AnnaBridge | 167:e84263d55307 | 344 | /** |
| AnnaBridge | 167:e84263d55307 | 345 | * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL |
| AnnaBridge | 167:e84263d55307 | 346 | * @note The application need to ensure that PLL is disabled. |
| AnnaBridge | 167:e84263d55307 | 347 | * @note Function is based on the following formula: |
| AnnaBridge | 167:e84263d55307 | 348 | * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) |
| AnnaBridge | 167:e84263d55307 | 349 | * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM) |
| AnnaBridge | 167:e84263d55307 | 350 | * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN) |
| AnnaBridge | 167:e84263d55307 | 351 | * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP) |
| AnnaBridge | 167:e84263d55307 | 352 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| AnnaBridge | 167:e84263d55307 | 353 | * the configuration information for the PLL. |
| AnnaBridge | 167:e84263d55307 | 354 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| AnnaBridge | 167:e84263d55307 | 355 | * the configuration information for the BUS prescalers. |
| AnnaBridge | 167:e84263d55307 | 356 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 167:e84263d55307 | 357 | * - SUCCESS: Max frequency configuration done |
| AnnaBridge | 167:e84263d55307 | 358 | * - ERROR: Max frequency configuration not done |
| AnnaBridge | 167:e84263d55307 | 359 | */ |
| AnnaBridge | 167:e84263d55307 | 360 | ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, |
| AnnaBridge | 167:e84263d55307 | 361 | LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| AnnaBridge | 167:e84263d55307 | 362 | { |
| AnnaBridge | 167:e84263d55307 | 363 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 167:e84263d55307 | 364 | uint32_t pllfreq = 0U; |
| AnnaBridge | 167:e84263d55307 | 365 | |
| AnnaBridge | 167:e84263d55307 | 366 | /* Check if one of the PLL is enabled */ |
| AnnaBridge | 167:e84263d55307 | 367 | if(UTILS_PLL_IsBusy() == SUCCESS) |
| AnnaBridge | 167:e84263d55307 | 368 | { |
| AnnaBridge | 167:e84263d55307 | 369 | /* Calculate the new PLL output frequency */ |
| AnnaBridge | 167:e84263d55307 | 370 | pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); |
| AnnaBridge | 167:e84263d55307 | 371 | |
| AnnaBridge | 167:e84263d55307 | 372 | /* Enable HSI if not enabled */ |
| AnnaBridge | 167:e84263d55307 | 373 | if(LL_RCC_HSI_IsReady() != 1U) |
| AnnaBridge | 167:e84263d55307 | 374 | { |
| AnnaBridge | 167:e84263d55307 | 375 | LL_RCC_HSI_Enable(); |
| AnnaBridge | 167:e84263d55307 | 376 | while (LL_RCC_HSI_IsReady() != 1U) |
| AnnaBridge | 167:e84263d55307 | 377 | { |
| AnnaBridge | 167:e84263d55307 | 378 | /* Wait for HSI ready */ |
| AnnaBridge | 167:e84263d55307 | 379 | } |
| AnnaBridge | 167:e84263d55307 | 380 | } |
| AnnaBridge | 167:e84263d55307 | 381 | |
| AnnaBridge | 167:e84263d55307 | 382 | /* Configure PLL */ |
| AnnaBridge | 167:e84263d55307 | 383 | LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, |
| AnnaBridge | 167:e84263d55307 | 384 | UTILS_PLLInitStruct->PLLP); |
| AnnaBridge | 167:e84263d55307 | 385 | |
| AnnaBridge | 167:e84263d55307 | 386 | /* Enable PLL and switch system clock to PLL */ |
| AnnaBridge | 167:e84263d55307 | 387 | status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
| AnnaBridge | 167:e84263d55307 | 388 | } |
| AnnaBridge | 167:e84263d55307 | 389 | else |
| AnnaBridge | 167:e84263d55307 | 390 | { |
| AnnaBridge | 167:e84263d55307 | 391 | /* Current PLL configuration cannot be modified */ |
| AnnaBridge | 167:e84263d55307 | 392 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 393 | } |
| AnnaBridge | 167:e84263d55307 | 394 | |
| AnnaBridge | 167:e84263d55307 | 395 | return status; |
| AnnaBridge | 167:e84263d55307 | 396 | } |
| AnnaBridge | 167:e84263d55307 | 397 | |
| AnnaBridge | 167:e84263d55307 | 398 | /** |
| AnnaBridge | 167:e84263d55307 | 399 | * @brief This function configures system clock with HSE as clock source of the PLL |
| AnnaBridge | 167:e84263d55307 | 400 | * @note The application need to ensure that PLL is disabled. |
| AnnaBridge | 167:e84263d55307 | 401 | * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) |
| AnnaBridge | 167:e84263d55307 | 402 | * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM) |
| AnnaBridge | 167:e84263d55307 | 403 | * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN) |
| AnnaBridge | 167:e84263d55307 | 404 | * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP) |
| AnnaBridge | 167:e84263d55307 | 405 | * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000 |
| AnnaBridge | 167:e84263d55307 | 406 | * @param HSEBypass This parameter can be one of the following values: |
| AnnaBridge | 167:e84263d55307 | 407 | * @arg @ref LL_UTILS_HSEBYPASS_ON |
| AnnaBridge | 167:e84263d55307 | 408 | * @arg @ref LL_UTILS_HSEBYPASS_OFF |
| AnnaBridge | 167:e84263d55307 | 409 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| AnnaBridge | 167:e84263d55307 | 410 | * the configuration information for the PLL. |
| AnnaBridge | 167:e84263d55307 | 411 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| AnnaBridge | 167:e84263d55307 | 412 | * the configuration information for the BUS prescalers. |
| AnnaBridge | 167:e84263d55307 | 413 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 167:e84263d55307 | 414 | * - SUCCESS: Max frequency configuration done |
| AnnaBridge | 167:e84263d55307 | 415 | * - ERROR: Max frequency configuration not done |
| AnnaBridge | 167:e84263d55307 | 416 | */ |
| AnnaBridge | 167:e84263d55307 | 417 | ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, |
| AnnaBridge | 167:e84263d55307 | 418 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| AnnaBridge | 167:e84263d55307 | 419 | { |
| AnnaBridge | 167:e84263d55307 | 420 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 167:e84263d55307 | 421 | uint32_t pllfreq = 0U; |
| AnnaBridge | 167:e84263d55307 | 422 | |
| AnnaBridge | 167:e84263d55307 | 423 | /* Check the parameters */ |
| AnnaBridge | 167:e84263d55307 | 424 | assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); |
| AnnaBridge | 167:e84263d55307 | 425 | assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); |
| AnnaBridge | 167:e84263d55307 | 426 | |
| AnnaBridge | 167:e84263d55307 | 427 | /* Check if one of the PLL is enabled */ |
| AnnaBridge | 167:e84263d55307 | 428 | if(UTILS_PLL_IsBusy() == SUCCESS) |
| AnnaBridge | 167:e84263d55307 | 429 | { |
| AnnaBridge | 167:e84263d55307 | 430 | /* Calculate the new PLL output frequency */ |
| AnnaBridge | 167:e84263d55307 | 431 | pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); |
| AnnaBridge | 167:e84263d55307 | 432 | |
| AnnaBridge | 167:e84263d55307 | 433 | /* Enable HSE if not enabled */ |
| AnnaBridge | 167:e84263d55307 | 434 | if(LL_RCC_HSE_IsReady() != 1U) |
| AnnaBridge | 167:e84263d55307 | 435 | { |
| AnnaBridge | 167:e84263d55307 | 436 | /* Check if need to enable HSE bypass feature or not */ |
| AnnaBridge | 167:e84263d55307 | 437 | if(HSEBypass == LL_UTILS_HSEBYPASS_ON) |
| AnnaBridge | 167:e84263d55307 | 438 | { |
| AnnaBridge | 167:e84263d55307 | 439 | LL_RCC_HSE_EnableBypass(); |
| AnnaBridge | 167:e84263d55307 | 440 | } |
| AnnaBridge | 167:e84263d55307 | 441 | else |
| AnnaBridge | 167:e84263d55307 | 442 | { |
| AnnaBridge | 167:e84263d55307 | 443 | LL_RCC_HSE_DisableBypass(); |
| AnnaBridge | 167:e84263d55307 | 444 | } |
| AnnaBridge | 167:e84263d55307 | 445 | |
| AnnaBridge | 167:e84263d55307 | 446 | /* Enable HSE */ |
| AnnaBridge | 167:e84263d55307 | 447 | LL_RCC_HSE_Enable(); |
| AnnaBridge | 167:e84263d55307 | 448 | while (LL_RCC_HSE_IsReady() != 1U) |
| AnnaBridge | 167:e84263d55307 | 449 | { |
| AnnaBridge | 167:e84263d55307 | 450 | /* Wait for HSE ready */ |
| AnnaBridge | 167:e84263d55307 | 451 | } |
| AnnaBridge | 167:e84263d55307 | 452 | } |
| AnnaBridge | 167:e84263d55307 | 453 | |
| AnnaBridge | 167:e84263d55307 | 454 | /* Configure PLL */ |
| AnnaBridge | 167:e84263d55307 | 455 | LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, |
| AnnaBridge | 167:e84263d55307 | 456 | UTILS_PLLInitStruct->PLLP); |
| AnnaBridge | 167:e84263d55307 | 457 | |
| AnnaBridge | 167:e84263d55307 | 458 | /* Enable PLL and switch system clock to PLL */ |
| AnnaBridge | 167:e84263d55307 | 459 | status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
| AnnaBridge | 167:e84263d55307 | 460 | } |
| AnnaBridge | 167:e84263d55307 | 461 | else |
| AnnaBridge | 167:e84263d55307 | 462 | { |
| AnnaBridge | 167:e84263d55307 | 463 | /* Current PLL configuration cannot be modified */ |
| AnnaBridge | 167:e84263d55307 | 464 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 465 | } |
| AnnaBridge | 167:e84263d55307 | 466 | |
| AnnaBridge | 167:e84263d55307 | 467 | return status; |
| AnnaBridge | 167:e84263d55307 | 468 | } |
| AnnaBridge | 167:e84263d55307 | 469 | |
| AnnaBridge | 167:e84263d55307 | 470 | /** |
| AnnaBridge | 167:e84263d55307 | 471 | * @} |
| AnnaBridge | 167:e84263d55307 | 472 | */ |
| AnnaBridge | 167:e84263d55307 | 473 | |
| AnnaBridge | 167:e84263d55307 | 474 | /** |
| AnnaBridge | 167:e84263d55307 | 475 | * @} |
| AnnaBridge | 167:e84263d55307 | 476 | */ |
| AnnaBridge | 167:e84263d55307 | 477 | |
| AnnaBridge | 167:e84263d55307 | 478 | /** @addtogroup UTILS_LL_Private_Functions |
| AnnaBridge | 167:e84263d55307 | 479 | * @{ |
| AnnaBridge | 167:e84263d55307 | 480 | */ |
| AnnaBridge | 167:e84263d55307 | 481 | /** |
| AnnaBridge | 167:e84263d55307 | 482 | * @brief Update number of Flash wait states in line with new frequency and current |
| AnnaBridge | 167:e84263d55307 | 483 | voltage range. |
| AnnaBridge | 167:e84263d55307 | 484 | * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V |
| AnnaBridge | 167:e84263d55307 | 485 | * @param HCLK_Frequency HCLK frequency |
| AnnaBridge | 167:e84263d55307 | 486 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 167:e84263d55307 | 487 | * - SUCCESS: Latency has been modified |
| AnnaBridge | 167:e84263d55307 | 488 | * - ERROR: Latency cannot be modified |
| AnnaBridge | 167:e84263d55307 | 489 | */ |
| AnnaBridge | 167:e84263d55307 | 490 | static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) |
| AnnaBridge | 167:e84263d55307 | 491 | { |
| AnnaBridge | 167:e84263d55307 | 492 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 167:e84263d55307 | 493 | |
| AnnaBridge | 167:e84263d55307 | 494 | uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ |
| AnnaBridge | 167:e84263d55307 | 495 | |
| AnnaBridge | 167:e84263d55307 | 496 | /* Frequency cannot be equal to 0 */ |
| AnnaBridge | 167:e84263d55307 | 497 | if(HCLK_Frequency == 0U) |
| AnnaBridge | 167:e84263d55307 | 498 | { |
| AnnaBridge | 167:e84263d55307 | 499 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 500 | } |
| AnnaBridge | 167:e84263d55307 | 501 | else |
| AnnaBridge | 167:e84263d55307 | 502 | { |
| AnnaBridge | 167:e84263d55307 | 503 | if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) |
| AnnaBridge | 167:e84263d55307 | 504 | { |
| AnnaBridge | 167:e84263d55307 | 505 | #if defined (UTILS_SCALE1_LATENCY5_FREQ) |
| AnnaBridge | 167:e84263d55307 | 506 | if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 507 | { |
| AnnaBridge | 167:e84263d55307 | 508 | latency = LL_FLASH_LATENCY_5; |
| AnnaBridge | 167:e84263d55307 | 509 | } |
| AnnaBridge | 167:e84263d55307 | 510 | #endif /*UTILS_SCALE1_LATENCY5_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 511 | #if defined (UTILS_SCALE1_LATENCY4_FREQ) |
| AnnaBridge | 167:e84263d55307 | 512 | if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 513 | { |
| AnnaBridge | 167:e84263d55307 | 514 | latency = LL_FLASH_LATENCY_4; |
| AnnaBridge | 167:e84263d55307 | 515 | } |
| AnnaBridge | 167:e84263d55307 | 516 | #endif /* UTILS_SCALE1_LATENCY4_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 517 | #if defined (UTILS_SCALE1_LATENCY3_FREQ) |
| AnnaBridge | 167:e84263d55307 | 518 | if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 519 | { |
| AnnaBridge | 167:e84263d55307 | 520 | latency = LL_FLASH_LATENCY_3; |
| AnnaBridge | 167:e84263d55307 | 521 | } |
| AnnaBridge | 167:e84263d55307 | 522 | #endif /* UTILS_SCALE1_LATENCY3_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 523 | #if defined (UTILS_SCALE1_LATENCY2_FREQ) |
| AnnaBridge | 167:e84263d55307 | 524 | if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 525 | { |
| AnnaBridge | 167:e84263d55307 | 526 | latency = LL_FLASH_LATENCY_2; |
| AnnaBridge | 167:e84263d55307 | 527 | } |
| AnnaBridge | 167:e84263d55307 | 528 | else |
| AnnaBridge | 167:e84263d55307 | 529 | { |
| AnnaBridge | 167:e84263d55307 | 530 | if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 531 | { |
| AnnaBridge | 167:e84263d55307 | 532 | latency = LL_FLASH_LATENCY_1; |
| AnnaBridge | 167:e84263d55307 | 533 | } |
| AnnaBridge | 167:e84263d55307 | 534 | } |
| AnnaBridge | 167:e84263d55307 | 535 | #endif /* UTILS_SCALE1_LATENCY2_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 536 | } |
| AnnaBridge | 167:e84263d55307 | 537 | if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) |
| AnnaBridge | 167:e84263d55307 | 538 | { |
| AnnaBridge | 167:e84263d55307 | 539 | #if defined (UTILS_SCALE2_LATENCY5_FREQ) |
| AnnaBridge | 167:e84263d55307 | 540 | if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 541 | { |
| AnnaBridge | 167:e84263d55307 | 542 | latency = LL_FLASH_LATENCY_5; |
| AnnaBridge | 167:e84263d55307 | 543 | } |
| AnnaBridge | 167:e84263d55307 | 544 | #endif /*UTILS_SCALE1_LATENCY5_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 545 | #if defined (UTILS_SCALE2_LATENCY4_FREQ) |
| AnnaBridge | 167:e84263d55307 | 546 | if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 547 | { |
| AnnaBridge | 167:e84263d55307 | 548 | latency = LL_FLASH_LATENCY_4; |
| AnnaBridge | 167:e84263d55307 | 549 | } |
| AnnaBridge | 167:e84263d55307 | 550 | #endif /*UTILS_SCALE1_LATENCY4_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 551 | #if defined (UTILS_SCALE2_LATENCY3_FREQ) |
| AnnaBridge | 167:e84263d55307 | 552 | if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 553 | { |
| AnnaBridge | 167:e84263d55307 | 554 | latency = LL_FLASH_LATENCY_3; |
| AnnaBridge | 167:e84263d55307 | 555 | } |
| AnnaBridge | 167:e84263d55307 | 556 | #endif /*UTILS_SCALE1_LATENCY3_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 557 | if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 558 | { |
| AnnaBridge | 167:e84263d55307 | 559 | latency = LL_FLASH_LATENCY_2; |
| AnnaBridge | 167:e84263d55307 | 560 | } |
| AnnaBridge | 167:e84263d55307 | 561 | else |
| AnnaBridge | 167:e84263d55307 | 562 | { |
| AnnaBridge | 167:e84263d55307 | 563 | if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 564 | { |
| AnnaBridge | 167:e84263d55307 | 565 | latency = LL_FLASH_LATENCY_1; |
| AnnaBridge | 167:e84263d55307 | 566 | } |
| AnnaBridge | 167:e84263d55307 | 567 | } |
| AnnaBridge | 167:e84263d55307 | 568 | } |
| AnnaBridge | 167:e84263d55307 | 569 | #if defined (LL_PWR_REGU_VOLTAGE_SCALE3) |
| AnnaBridge | 167:e84263d55307 | 570 | if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3) |
| AnnaBridge | 167:e84263d55307 | 571 | { |
| AnnaBridge | 167:e84263d55307 | 572 | #if defined (UTILS_SCALE3_LATENCY3_FREQ) |
| AnnaBridge | 167:e84263d55307 | 573 | if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 574 | { |
| AnnaBridge | 167:e84263d55307 | 575 | latency = LL_FLASH_LATENCY_3; |
| AnnaBridge | 167:e84263d55307 | 576 | } |
| AnnaBridge | 167:e84263d55307 | 577 | #endif /*UTILS_SCALE1_LATENCY3_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 578 | #if defined (UTILS_SCALE3_LATENCY2_FREQ) |
| AnnaBridge | 167:e84263d55307 | 579 | if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 580 | { |
| AnnaBridge | 167:e84263d55307 | 581 | latency = LL_FLASH_LATENCY_2; |
| AnnaBridge | 167:e84263d55307 | 582 | } |
| AnnaBridge | 167:e84263d55307 | 583 | else |
| AnnaBridge | 167:e84263d55307 | 584 | { |
| AnnaBridge | 167:e84263d55307 | 585 | if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) |
| AnnaBridge | 167:e84263d55307 | 586 | { |
| AnnaBridge | 167:e84263d55307 | 587 | latency = LL_FLASH_LATENCY_1; |
| AnnaBridge | 167:e84263d55307 | 588 | } |
| AnnaBridge | 167:e84263d55307 | 589 | } |
| AnnaBridge | 167:e84263d55307 | 590 | } |
| AnnaBridge | 167:e84263d55307 | 591 | #endif /*UTILS_SCALE1_LATENCY2_FREQ */ |
| AnnaBridge | 167:e84263d55307 | 592 | #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */ |
| AnnaBridge | 167:e84263d55307 | 593 | |
| AnnaBridge | 167:e84263d55307 | 594 | LL_FLASH_SetLatency(latency); |
| AnnaBridge | 167:e84263d55307 | 595 | |
| AnnaBridge | 167:e84263d55307 | 596 | /* Check that the new number of wait states is taken into account to access the Flash |
| AnnaBridge | 167:e84263d55307 | 597 | memory by reading the FLASH_ACR register */ |
| AnnaBridge | 167:e84263d55307 | 598 | if(LL_FLASH_GetLatency() != latency) |
| AnnaBridge | 167:e84263d55307 | 599 | { |
| AnnaBridge | 167:e84263d55307 | 600 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 601 | } |
| AnnaBridge | 167:e84263d55307 | 602 | } |
| AnnaBridge | 167:e84263d55307 | 603 | return status; |
| AnnaBridge | 167:e84263d55307 | 604 | } |
| AnnaBridge | 167:e84263d55307 | 605 | |
| AnnaBridge | 167:e84263d55307 | 606 | /** |
| AnnaBridge | 167:e84263d55307 | 607 | * @brief Function to check that PLL can be modified |
| AnnaBridge | 167:e84263d55307 | 608 | * @param PLL_InputFrequency PLL input frequency (in Hz) |
| AnnaBridge | 167:e84263d55307 | 609 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| AnnaBridge | 167:e84263d55307 | 610 | * the configuration information for the PLL. |
| AnnaBridge | 167:e84263d55307 | 611 | * @retval PLL output frequency (in Hz) |
| AnnaBridge | 167:e84263d55307 | 612 | */ |
| AnnaBridge | 167:e84263d55307 | 613 | static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) |
| AnnaBridge | 167:e84263d55307 | 614 | { |
| AnnaBridge | 167:e84263d55307 | 615 | uint32_t pllfreq = 0U; |
| AnnaBridge | 167:e84263d55307 | 616 | |
| AnnaBridge | 167:e84263d55307 | 617 | /* Check the parameters */ |
| AnnaBridge | 167:e84263d55307 | 618 | assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); |
| AnnaBridge | 167:e84263d55307 | 619 | assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); |
| AnnaBridge | 167:e84263d55307 | 620 | assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); |
| AnnaBridge | 167:e84263d55307 | 621 | |
| AnnaBridge | 167:e84263d55307 | 622 | /* Check different PLL parameters according to RM */ |
| AnnaBridge | 167:e84263d55307 | 623 | /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */ |
| AnnaBridge | 167:e84263d55307 | 624 | pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos)); |
| AnnaBridge | 167:e84263d55307 | 625 | assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); |
| AnnaBridge | 167:e84263d55307 | 626 | |
| AnnaBridge | 167:e84263d55307 | 627 | /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/ |
| AnnaBridge | 167:e84263d55307 | 628 | pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); |
| AnnaBridge | 167:e84263d55307 | 629 | assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); |
| AnnaBridge | 167:e84263d55307 | 630 | |
| AnnaBridge | 167:e84263d55307 | 631 | /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */ |
| AnnaBridge | 167:e84263d55307 | 632 | pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); |
| AnnaBridge | 167:e84263d55307 | 633 | assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); |
| AnnaBridge | 167:e84263d55307 | 634 | |
| AnnaBridge | 167:e84263d55307 | 635 | return pllfreq; |
| AnnaBridge | 167:e84263d55307 | 636 | } |
| AnnaBridge | 167:e84263d55307 | 637 | |
| AnnaBridge | 167:e84263d55307 | 638 | /** |
| AnnaBridge | 167:e84263d55307 | 639 | * @brief Function to check that PLL can be modified |
| AnnaBridge | 167:e84263d55307 | 640 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 167:e84263d55307 | 641 | * - SUCCESS: PLL modification can be done |
| AnnaBridge | 167:e84263d55307 | 642 | * - ERROR: PLL is busy |
| AnnaBridge | 167:e84263d55307 | 643 | */ |
| AnnaBridge | 167:e84263d55307 | 644 | static ErrorStatus UTILS_PLL_IsBusy(void) |
| AnnaBridge | 167:e84263d55307 | 645 | { |
| AnnaBridge | 167:e84263d55307 | 646 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 167:e84263d55307 | 647 | |
| AnnaBridge | 167:e84263d55307 | 648 | /* Check if PLL is busy*/ |
| AnnaBridge | 167:e84263d55307 | 649 | if(LL_RCC_PLL_IsReady() != 0U) |
| AnnaBridge | 167:e84263d55307 | 650 | { |
| AnnaBridge | 167:e84263d55307 | 651 | /* PLL configuration cannot be modified */ |
| AnnaBridge | 167:e84263d55307 | 652 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 653 | } |
| AnnaBridge | 167:e84263d55307 | 654 | |
| AnnaBridge | 167:e84263d55307 | 655 | #if defined(RCC_PLLSAI_SUPPORT) |
| AnnaBridge | 167:e84263d55307 | 656 | /* Check if PLLSAI is busy*/ |
| AnnaBridge | 167:e84263d55307 | 657 | if(LL_RCC_PLLSAI_IsReady() != 0U) |
| AnnaBridge | 167:e84263d55307 | 658 | { |
| AnnaBridge | 167:e84263d55307 | 659 | /* PLLSAI1 configuration cannot be modified */ |
| AnnaBridge | 167:e84263d55307 | 660 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 661 | } |
| AnnaBridge | 167:e84263d55307 | 662 | #endif /*RCC_PLLSAI_SUPPORT*/ |
| AnnaBridge | 167:e84263d55307 | 663 | #if defined(RCC_PLLI2S_SUPPORT) |
| AnnaBridge | 167:e84263d55307 | 664 | /* Check if PLLI2S is busy*/ |
| AnnaBridge | 167:e84263d55307 | 665 | if(LL_RCC_PLLI2S_IsReady() != 0U) |
| AnnaBridge | 167:e84263d55307 | 666 | { |
| AnnaBridge | 167:e84263d55307 | 667 | /* PLLI2S configuration cannot be modified */ |
| AnnaBridge | 167:e84263d55307 | 668 | status = ERROR; |
| AnnaBridge | 167:e84263d55307 | 669 | } |
| AnnaBridge | 167:e84263d55307 | 670 | #endif /*RCC_PLLI2S_SUPPORT*/ |
| AnnaBridge | 167:e84263d55307 | 671 | return status; |
| AnnaBridge | 167:e84263d55307 | 672 | } |
| AnnaBridge | 167:e84263d55307 | 673 | |
| AnnaBridge | 167:e84263d55307 | 674 | /** |
| AnnaBridge | 167:e84263d55307 | 675 | * @brief Function to enable PLL and switch system clock to PLL |
| AnnaBridge | 167:e84263d55307 | 676 | * @param SYSCLK_Frequency SYSCLK frequency |
| AnnaBridge | 167:e84263d55307 | 677 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| AnnaBridge | 167:e84263d55307 | 678 | * the configuration information for the BUS prescalers. |
| AnnaBridge | 167:e84263d55307 | 679 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 167:e84263d55307 | 680 | * - SUCCESS: No problem to switch system to PLL |
| AnnaBridge | 167:e84263d55307 | 681 | * - ERROR: Problem to switch system to PLL |
| AnnaBridge | 167:e84263d55307 | 682 | */ |
| AnnaBridge | 167:e84263d55307 | 683 | static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| AnnaBridge | 167:e84263d55307 | 684 | { |
| AnnaBridge | 167:e84263d55307 | 685 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 167:e84263d55307 | 686 | uint32_t hclk_frequency = 0U; |
| AnnaBridge | 167:e84263d55307 | 687 | |
| AnnaBridge | 167:e84263d55307 | 688 | assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); |
| AnnaBridge | 167:e84263d55307 | 689 | assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); |
| AnnaBridge | 167:e84263d55307 | 690 | assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); |
| AnnaBridge | 167:e84263d55307 | 691 | |
| AnnaBridge | 167:e84263d55307 | 692 | /* Calculate HCLK frequency */ |
| AnnaBridge | 167:e84263d55307 | 693 | hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); |
| AnnaBridge | 167:e84263d55307 | 694 | |
| AnnaBridge | 167:e84263d55307 | 695 | /* Increasing the number of wait states because of higher CPU frequency */ |
| AnnaBridge | 167:e84263d55307 | 696 | if(SystemCoreClock < hclk_frequency) |
| AnnaBridge | 167:e84263d55307 | 697 | { |
| AnnaBridge | 167:e84263d55307 | 698 | /* Set FLASH latency to highest latency */ |
| AnnaBridge | 167:e84263d55307 | 699 | status = UTILS_SetFlashLatency(hclk_frequency); |
| AnnaBridge | 167:e84263d55307 | 700 | } |
| AnnaBridge | 167:e84263d55307 | 701 | |
| AnnaBridge | 167:e84263d55307 | 702 | /* Update system clock configuration */ |
| AnnaBridge | 167:e84263d55307 | 703 | if(status == SUCCESS) |
| AnnaBridge | 167:e84263d55307 | 704 | { |
| AnnaBridge | 167:e84263d55307 | 705 | /* Enable PLL */ |
| AnnaBridge | 167:e84263d55307 | 706 | LL_RCC_PLL_Enable(); |
| AnnaBridge | 167:e84263d55307 | 707 | while (LL_RCC_PLL_IsReady() != 1U) |
| AnnaBridge | 167:e84263d55307 | 708 | { |
| AnnaBridge | 167:e84263d55307 | 709 | /* Wait for PLL ready */ |
| AnnaBridge | 167:e84263d55307 | 710 | } |
| AnnaBridge | 167:e84263d55307 | 711 | |
| AnnaBridge | 167:e84263d55307 | 712 | /* Sysclk activation on the main PLL */ |
| AnnaBridge | 167:e84263d55307 | 713 | LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); |
| AnnaBridge | 167:e84263d55307 | 714 | LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); |
| AnnaBridge | 167:e84263d55307 | 715 | while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) |
| AnnaBridge | 167:e84263d55307 | 716 | { |
| AnnaBridge | 167:e84263d55307 | 717 | /* Wait for system clock switch to PLL */ |
| AnnaBridge | 167:e84263d55307 | 718 | } |
| AnnaBridge | 167:e84263d55307 | 719 | |
| AnnaBridge | 167:e84263d55307 | 720 | /* Set APB1 & APB2 prescaler*/ |
| AnnaBridge | 167:e84263d55307 | 721 | LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); |
| AnnaBridge | 167:e84263d55307 | 722 | LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); |
| AnnaBridge | 167:e84263d55307 | 723 | } |
| AnnaBridge | 167:e84263d55307 | 724 | |
| AnnaBridge | 167:e84263d55307 | 725 | /* Decreasing the number of wait states because of lower CPU frequency */ |
| AnnaBridge | 167:e84263d55307 | 726 | if(SystemCoreClock > hclk_frequency) |
| AnnaBridge | 167:e84263d55307 | 727 | { |
| AnnaBridge | 167:e84263d55307 | 728 | /* Set FLASH latency to lowest latency */ |
| AnnaBridge | 167:e84263d55307 | 729 | status = UTILS_SetFlashLatency(hclk_frequency); |
| AnnaBridge | 167:e84263d55307 | 730 | } |
| AnnaBridge | 167:e84263d55307 | 731 | |
| AnnaBridge | 167:e84263d55307 | 732 | /* Update SystemCoreClock variable */ |
| AnnaBridge | 167:e84263d55307 | 733 | if(status == SUCCESS) |
| AnnaBridge | 167:e84263d55307 | 734 | { |
| AnnaBridge | 167:e84263d55307 | 735 | LL_SetSystemCoreClock(hclk_frequency); |
| AnnaBridge | 167:e84263d55307 | 736 | } |
| AnnaBridge | 167:e84263d55307 | 737 | |
| AnnaBridge | 167:e84263d55307 | 738 | return status; |
| AnnaBridge | 167:e84263d55307 | 739 | } |
| AnnaBridge | 167:e84263d55307 | 740 | |
| AnnaBridge | 167:e84263d55307 | 741 | /** |
| AnnaBridge | 167:e84263d55307 | 742 | * @} |
| AnnaBridge | 167:e84263d55307 | 743 | */ |
| AnnaBridge | 167:e84263d55307 | 744 | |
| AnnaBridge | 167:e84263d55307 | 745 | /** |
| AnnaBridge | 167:e84263d55307 | 746 | * @} |
| AnnaBridge | 167:e84263d55307 | 747 | */ |
| AnnaBridge | 167:e84263d55307 | 748 | |
| AnnaBridge | 167:e84263d55307 | 749 | /** |
| AnnaBridge | 167:e84263d55307 | 750 | * @} |
| AnnaBridge | 167:e84263d55307 | 751 | */ |
| AnnaBridge | 167:e84263d55307 | 752 | |
| AnnaBridge | 167:e84263d55307 | 753 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |