mbed library sources. Supersedes mbed-src.
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Diff: platform/mbed_application.c
- Revision:
- 186:707f6e361f3e
- Parent:
- 173:e131a1973e81
--- a/platform/mbed_application.c Thu Apr 19 17:12:19 2018 +0100 +++ b/platform/mbed_application.c Fri Jun 22 16:45:37 2018 +0100 @@ -48,12 +48,21 @@ int i; int j; +#if defined(__CORTEX_M23) + // M23 doesn't support ICTR and supports up to 240 external interrupts. + isr_groups_32 = 8; +#else isr_groups_32 = ((SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos) + 1; +#endif for (i = 0; i < isr_groups_32; i++) { NVIC->ICER[i] = 0xFFFFFFFF; NVIC->ICPR[i] = 0xFFFFFFFF; for (j = 0; j < 8; j++) { +#if defined(__CORTEX_M23) + NVIC->IPR[i * 8 + j] = 0x00000000; +#else NVIC->IP[i * 8 + j] = 0x00000000; +#endif } } } @@ -68,6 +77,11 @@ SCB->AIRCR = 0x05FA | 0x0000; SCB->SCR = 0x00000000; // SCB->CCR - Implementation defined value +#if defined(__CORTEX_M23) + for (i = 0; i < 2; i++) { + SCB->SHPR[i] = 0x00; + } +#else for (i = 0; i < 12; i++) { #if defined(__CORTEX_M7) SCB->SHPR[i] = 0x00; @@ -75,11 +89,15 @@ SCB->SHP[i] = 0x00; #endif } +#endif SCB->SHCSR = 0x00000000; +#if defined(__CORTEX_M23) +#else SCB->CFSR = 0xFFFFFFFF; SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk; SCB->DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk | SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk; +#endif // SCB->MMFAR - Implementation defined value // SCB->BFAR - Implementation defined value // SCB->AFSR - Implementation defined value @@ -107,7 +125,9 @@ void start_new_application(void *sp, void *pc) { __asm volatile ( - "mov r2, #0 \n" + "movw r2, #0 \n" // Fail to compile "mov r2, #0" with ARMC6. Replace with MOVW. + // We needn't "movt r2, #0" immediately following because MOVW + // will zero-extend the 16-bit immediate. "msr control, r2 \n" // Switch to main stack "mov sp, %0 \n" "msr primask, r2 \n" // Enable interrupts