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targets/TARGET_Maxim/TARGET_MAX32630/device/uart_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-31 17:35:11 -0500 (Mon, 31 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24860 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* **** Includes **** */
<> 157:ff67d9f36b67 43 #include <stdint.h>
<> 157:ff67d9f36b67 44
<> 157:ff67d9f36b67 45 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 46 #ifndef _MXC_UART_REGS_H_
<> 157:ff67d9f36b67 47 #define _MXC_UART_REGS_H_
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 ///@cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 ///@endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * @ingroup uart_comm
<> 157:ff67d9f36b67 73 * @defgroup uart_registers UART Registers
<> 157:ff67d9f36b67 74 * @brief Registers, Bit Masks and Bit Positions
<> 157:ff67d9f36b67 75 * @{
<> 157:ff67d9f36b67 76 */
<> 157:ff67d9f36b67 77
<> 157:ff67d9f36b67 78 /**
<> 157:ff67d9f36b67 79 * Structure type for the UART peripheral registers allowing direct 32-bit access to each register.
<> 157:ff67d9f36b67 80 */
<> 157:ff67d9f36b67 81 typedef struct {
<> 157:ff67d9f36b67 82 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART_CTRL Register - UART Control Register. */
<> 157:ff67d9f36b67 83 __IO uint32_t baud; /**< <tt>\b 0x0004:</tt> UART_BAUD Register - UART Baud Control Register. */
<> 157:ff67d9f36b67 84 __IO uint32_t tx_fifo_ctrl; /**< <tt>\b 0x0008:</tt> UART_TX_FIFO_CTRL Register - UART TX FIFO Control Register. */
<> 157:ff67d9f36b67 85 __IO uint32_t rx_fifo_ctrl; /**< <tt>\b 0x000C:</tt> UART_RX_FIFO_CTRL Register - UART RX FIFO Control Register. */
<> 157:ff67d9f36b67 86 __IO uint32_t md_ctrl; /**< <tt>\b 0x0010:</tt> UART_MD_CTRL Register - UART Multidrop Control Register. */
<> 157:ff67d9f36b67 87 __IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> UART_INTFL Register - UART Interrupt Flags. */
<> 157:ff67d9f36b67 88 __IO uint32_t inten; /**< <tt>\b 0x0018:</tt> UART_INTEN Register - UART Interrupt Enable/Disable Control. */
<> 157:ff67d9f36b67 89 #if (MXC_UART_REV > 0)
<> 157:ff67d9f36b67 90 __RO uint32_t idle; /**< <tt>\b 0x001C:</tt> UART_IDLE Register - UART Idle Status */
<> 157:ff67d9f36b67 91 #endif
<> 157:ff67d9f36b67 92 } mxc_uart_regs_t;
<> 157:ff67d9f36b67 93 /**@} end of group uart_registers */
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95 /**
<> 157:ff67d9f36b67 96 * @ingroup uart_registers
<> 157:ff67d9f36b67 97 * @defgroup uart_fifos UART TX and RX FIFOs
<> 157:ff67d9f36b67 98 * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
<> 157:ff67d9f36b67 99 * @{
<> 157:ff67d9f36b67 100 */
<> 157:ff67d9f36b67 101 /**
<> 157:ff67d9f36b67 102 * Structure type for accessing the UART Transmit and Receive FIFOs.
<> 157:ff67d9f36b67 103 */
<> 157:ff67d9f36b67 104 typedef struct {
<> 157:ff67d9f36b67 105 union {
<> 157:ff67d9f36b67 106 __IO uint8_t tx; /**< TX FIFO write point for data to transmit. */
<> 157:ff67d9f36b67 107 __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO. */
<> 157:ff67d9f36b67 108 __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO. */
<> 157:ff67d9f36b67 109 __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO. */
<> 157:ff67d9f36b67 110 };
<> 157:ff67d9f36b67 111 union {
<> 157:ff67d9f36b67 112 __IO uint8_t rx; /**< RX FIFO read point for received data. */
<> 157:ff67d9f36b67 113 __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO. */
<> 157:ff67d9f36b67 114 __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO. */
<> 157:ff67d9f36b67 115 __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO. */
<> 157:ff67d9f36b67 116 };
<> 157:ff67d9f36b67 117 } mxc_uart_fifo_regs_t;
<> 157:ff67d9f36b67 118 /**@} end of group uart_fifos */
<> 157:ff67d9f36b67 119
<> 157:ff67d9f36b67 120 /*
<> 157:ff67d9f36b67 121 Register offsets for module UART.
<> 157:ff67d9f36b67 122 */
<> 157:ff67d9f36b67 123
<> 157:ff67d9f36b67 124 #define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 157:ff67d9f36b67 125 #define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
<> 157:ff67d9f36b67 126 #define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
<> 157:ff67d9f36b67 127 #define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
<> 157:ff67d9f36b67 128 #define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
<> 157:ff67d9f36b67 129 #define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
<> 157:ff67d9f36b67 130 #define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 157:ff67d9f36b67 131 #define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
<> 157:ff67d9f36b67 132 #define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
<> 157:ff67d9f36b67 133
<> 157:ff67d9f36b67 134
<> 157:ff67d9f36b67 135 /*
<> 157:ff67d9f36b67 136 Field positions and masks for module UART.
<> 157:ff67d9f36b67 137 */
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 #define MXC_F_UART_CTRL_UART_EN_POS 0
<> 157:ff67d9f36b67 140 #define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
<> 157:ff67d9f36b67 141 #define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
<> 157:ff67d9f36b67 142 #define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
<> 157:ff67d9f36b67 143 #define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
<> 157:ff67d9f36b67 144 #define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
<> 157:ff67d9f36b67 145 #define MXC_F_UART_CTRL_DATA_SIZE_POS 4
<> 157:ff67d9f36b67 146 #define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 157:ff67d9f36b67 147 #define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
<> 157:ff67d9f36b67 148 #define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
<> 157:ff67d9f36b67 149 #define MXC_F_UART_CTRL_PARITY_POS 12
<> 157:ff67d9f36b67 150 #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
<> 157:ff67d9f36b67 151 #define MXC_F_UART_CTRL_CTS_EN_POS 16
<> 157:ff67d9f36b67 152 #define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
<> 157:ff67d9f36b67 153 #define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
<> 157:ff67d9f36b67 154 #define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
<> 157:ff67d9f36b67 155 #define MXC_F_UART_CTRL_RTS_EN_POS 18
<> 157:ff67d9f36b67 156 #define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
<> 157:ff67d9f36b67 157 #define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
<> 157:ff67d9f36b67 158 #define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
<> 157:ff67d9f36b67 159 #define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
<> 157:ff67d9f36b67 160 #define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
<> 157:ff67d9f36b67 161
<> 157:ff67d9f36b67 162 #define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
<> 157:ff67d9f36b67 163 #define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
<> 157:ff67d9f36b67 164 #define MXC_F_UART_BAUD_BAUD_MODE_POS 8
<> 157:ff67d9f36b67 165 #define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
<> 157:ff67d9f36b67 166
<> 157:ff67d9f36b67 167 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
<> 157:ff67d9f36b67 168 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
<> 157:ff67d9f36b67 169 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
<> 157:ff67d9f36b67 170 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
<> 157:ff67d9f36b67 171
<> 157:ff67d9f36b67 172 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
<> 157:ff67d9f36b67 173 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
<> 157:ff67d9f36b67 174 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
<> 157:ff67d9f36b67 175 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
<> 157:ff67d9f36b67 176
<> 157:ff67d9f36b67 177 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
<> 157:ff67d9f36b67 178 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
<> 157:ff67d9f36b67 179 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
<> 157:ff67d9f36b67 180 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
<> 157:ff67d9f36b67 181 #define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
<> 157:ff67d9f36b67 182 #define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
<> 157:ff67d9f36b67 183 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
<> 157:ff67d9f36b67 184 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
<> 157:ff67d9f36b67 185
<> 157:ff67d9f36b67 186 /**
<> 157:ff67d9f36b67 187 * @ingroup uart_registers
<> 157:ff67d9f36b67 188 * @defgroup UART_INTFL_Register UART_INTFL
<> 157:ff67d9f36b67 189 * @{
<> 157:ff67d9f36b67 190 */
<> 157:ff67d9f36b67 191 #define MXC_F_UART_INTFL_TX_DONE_POS 0
<> 157:ff67d9f36b67 192 #define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
<> 157:ff67d9f36b67 193 #define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
<> 157:ff67d9f36b67 194 #define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
<> 157:ff67d9f36b67 195 #define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
<> 157:ff67d9f36b67 196 #define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
<> 157:ff67d9f36b67 197 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
<> 157:ff67d9f36b67 198 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
<> 157:ff67d9f36b67 199 #define MXC_F_UART_INTFL_RX_STALLED_POS 4
<> 157:ff67d9f36b67 200 #define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
<> 157:ff67d9f36b67 201 #define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
<> 157:ff67d9f36b67 202 #define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
<> 157:ff67d9f36b67 203 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
<> 157:ff67d9f36b67 204 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
<> 157:ff67d9f36b67 205 #define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
<> 157:ff67d9f36b67 206 #define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
<> 157:ff67d9f36b67 207 #define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
<> 157:ff67d9f36b67 208 #define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
<> 157:ff67d9f36b67 209 /**@} end of group UART_INTFL_Register */
<> 157:ff67d9f36b67 210
<> 157:ff67d9f36b67 211 #define MXC_F_UART_INTEN_TX_DONE_POS 0
<> 157:ff67d9f36b67 212 #define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
<> 157:ff67d9f36b67 213 #define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
<> 157:ff67d9f36b67 214 #define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
<> 157:ff67d9f36b67 215 #define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
<> 157:ff67d9f36b67 216 #define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
<> 157:ff67d9f36b67 217 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
<> 157:ff67d9f36b67 218 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
<> 157:ff67d9f36b67 219 #define MXC_F_UART_INTEN_RX_STALLED_POS 4
<> 157:ff67d9f36b67 220 #define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
<> 157:ff67d9f36b67 221 #define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
<> 157:ff67d9f36b67 222 #define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
<> 157:ff67d9f36b67 223 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
<> 157:ff67d9f36b67 224 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
<> 157:ff67d9f36b67 225 #define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
<> 157:ff67d9f36b67 226 #define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
<> 157:ff67d9f36b67 227 #define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
<> 157:ff67d9f36b67 228 #define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
<> 157:ff67d9f36b67 229
<> 157:ff67d9f36b67 230 #if (MXC_UART_REV > 0)
<> 157:ff67d9f36b67 231 #define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
<> 157:ff67d9f36b67 232 #define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
<> 157:ff67d9f36b67 233 #define MXC_F_UART_IDLE_TX_IDLE_POS 1
<> 157:ff67d9f36b67 234 #define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
<> 157:ff67d9f36b67 235 #define MXC_F_UART_IDLE_RX_IDLE_POS 2
<> 157:ff67d9f36b67 236 #define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
<> 157:ff67d9f36b67 237 #endif
<> 157:ff67d9f36b67 238
<> 157:ff67d9f36b67 239 /*
<> 157:ff67d9f36b67 240 Field values and shifted values for module UART.
<> 157:ff67d9f36b67 241 */
<> 157:ff67d9f36b67 242
<> 157:ff67d9f36b67 243 #define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 244 #define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 245 #define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 246 #define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 247
<> 157:ff67d9f36b67 248 #define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 157:ff67d9f36b67 249 #define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 157:ff67d9f36b67 250 #define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 157:ff67d9f36b67 251 #define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 157:ff67d9f36b67 252
<> 157:ff67d9f36b67 253 #define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 254 #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 255 #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 256 #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 257
<> 157:ff67d9f36b67 258 #define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
<> 157:ff67d9f36b67 259 #define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
<> 157:ff67d9f36b67 260 #define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
<> 157:ff67d9f36b67 261 #define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
<> 157:ff67d9f36b67 262
<> 157:ff67d9f36b67 263
<> 157:ff67d9f36b67 264
<> 157:ff67d9f36b67 265 #ifdef __cplusplus
<> 157:ff67d9f36b67 266 }
<> 157:ff67d9f36b67 267 #endif
<> 157:ff67d9f36b67 268
<> 157:ff67d9f36b67 269 #endif /* _MXC_UART_REGS_H_ */
<> 157:ff67d9f36b67 270