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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
19:112740acecfa 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_ll_fsmc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 06-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of FSMC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F4xx_LL_FSMC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F4xx_LL_FSMC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FSMC_LL
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
<> 144:ef7eb2e8f9f7 58 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief FSMC NORSRAM Configuration Structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
<> 144:ef7eb2e8f9f7 72 multiplexed on the data bus or not.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
<> 144:ef7eb2e8f9f7 76 the corresponding memory device.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref FSMC_Memory_Type */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
<> 144:ef7eb2e8f9f7 83 valid only with synchronous burst Flash memories.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
<> 144:ef7eb2e8f9f7 87 the Flash memory in burst mode.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
<> 144:ef7eb2e8f9f7 91 memory, valid only when accessing Flash memories in burst mode.
<> 144:ef7eb2e8f9f7 92 This parameter can be a value of @ref FSMC_Wrap_Mode
<> 144:ef7eb2e8f9f7 93 This mode is available only for the STM32F405/407/4015/417xx devices */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
<> 144:ef7eb2e8f9f7 96 clock cycle before the wait state or during the wait state,
<> 144:ef7eb2e8f9f7 97 valid only when accessing memories in burst mode.
<> 144:ef7eb2e8f9f7 98 This parameter can be a value of @ref FSMC_Wait_Timing */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
<> 144:ef7eb2e8f9f7 101 This parameter can be a value of @ref FSMC_Write_Operation */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
<> 144:ef7eb2e8f9f7 104 signal, valid for Flash memory access in burst mode.
<> 144:ef7eb2e8f9f7 105 This parameter can be a value of @ref FSMC_Wait_Signal */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
<> 144:ef7eb2e8f9f7 108 This parameter can be a value of @ref FSMC_Extended_Mode */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
<> 144:ef7eb2e8f9f7 111 valid only with asynchronous Flash memories.
<> 144:ef7eb2e8f9f7 112 This parameter can be a value of @ref FSMC_AsynchronousWait */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
<> 144:ef7eb2e8f9f7 115 This parameter can be a value of @ref FSMC_Write_Burst */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
<> 144:ef7eb2e8f9f7 118 This parameter is only enabled through the FMC_BCR1 register, and don't care
<> 144:ef7eb2e8f9f7 119 through FMC_BCR2..4 registers.
<> 144:ef7eb2e8f9f7 120 This parameter can be a value of @ref FMC_Continous_Clock
<> 144:ef7eb2e8f9f7 121 This mode is available only for the STM32F412Vx/Zx/Rx devices */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
<> 144:ef7eb2e8f9f7 124 This parameter is only enabled through the FMC_BCR1 register, and don't care
<> 144:ef7eb2e8f9f7 125 through FMC_BCR2..4 registers.
<> 144:ef7eb2e8f9f7 126 This parameter can be a value of @ref FMC_Write_FIFO
<> 144:ef7eb2e8f9f7 127 This mode is available only for the STM32F412Vx/Vx devices */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 uint32_t PageSize; /*!< Specifies the memory page size.
<> 144:ef7eb2e8f9f7 130 This parameter can be a value of @ref FMC_Page_Size */
<> 144:ef7eb2e8f9f7 131 }FSMC_NORSRAM_InitTypeDef;
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @brief FSMC NORSRAM Timing parameters structure definition
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 typedef struct
<> 144:ef7eb2e8f9f7 137 {
<> 144:ef7eb2e8f9f7 138 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 139 the duration of the address setup time.
<> 144:ef7eb2e8f9f7 140 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 141 @note This parameter is not used with synchronous NOR Flash memories. */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 144 the duration of the address hold time.
<> 144:ef7eb2e8f9f7 145 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 146 @note This parameter is not used with synchronous NOR Flash memories. */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 149 the duration of the data setup time.
<> 144:ef7eb2e8f9f7 150 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 151 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
<> 144:ef7eb2e8f9f7 152 NOR Flash memories. */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 155 the duration of the bus turnaround.
<> 144:ef7eb2e8f9f7 156 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 157 @note This parameter is only used for multiplexed NOR Flash memories. */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
<> 144:ef7eb2e8f9f7 160 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
<> 144:ef7eb2e8f9f7 161 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
<> 144:ef7eb2e8f9f7 162 accesses. */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
<> 144:ef7eb2e8f9f7 165 to the memory before getting the first data.
<> 144:ef7eb2e8f9f7 166 The parameter value depends on the memory type as shown below:
<> 144:ef7eb2e8f9f7 167 - It must be set to 0 in case of a CRAM
<> 144:ef7eb2e8f9f7 168 - It is don't care in asynchronous NOR, SRAM or ROM accesses
<> 144:ef7eb2e8f9f7 169 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
<> 144:ef7eb2e8f9f7 170 with synchronous burst mode enable */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
<> 144:ef7eb2e8f9f7 173 This parameter can be a value of @ref FSMC_Access_Mode */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 }FSMC_NORSRAM_TimingTypeDef;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief FSMC NAND Configuration Structure definition
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 typedef struct
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
<> 144:ef7eb2e8f9f7 184 This parameter can be a value of @ref FSMC_NAND_Bank */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
<> 144:ef7eb2e8f9f7 187 This parameter can be any value of @ref FSMC_Wait_feature */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 144:ef7eb2e8f9f7 190 This parameter can be any value of @ref FSMC_NAND_Data_Width */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
<> 144:ef7eb2e8f9f7 193 This parameter can be any value of @ref FSMC_ECC */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
<> 144:ef7eb2e8f9f7 196 This parameter can be any value of @ref FSMC_ECC_Page_Size */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 199 delay between CLE low and RE low.
<> 144:ef7eb2e8f9f7 200 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 203 delay between ALE low and RE low.
<> 144:ef7eb2e8f9f7 204 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 }FSMC_NAND_InitTypeDef;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief FSMC NAND/PCCARD Timing parameters structure definition
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 typedef struct
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
<> 144:ef7eb2e8f9f7 214 the command assertion for NAND-Flash read or write access
<> 144:ef7eb2e8f9f7 215 to common/Attribute or I/O memory space (depending on
<> 144:ef7eb2e8f9f7 216 the memory space timing to be configured).
<> 144:ef7eb2e8f9f7 217 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
<> 144:ef7eb2e8f9f7 220 command for NAND-Flash read or write access to
<> 144:ef7eb2e8f9f7 221 common/Attribute or I/O memory space (depending on the
<> 144:ef7eb2e8f9f7 222 memory space timing to be configured).
<> 144:ef7eb2e8f9f7 223 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
<> 144:ef7eb2e8f9f7 226 (and data for write access) after the command de-assertion
<> 144:ef7eb2e8f9f7 227 for NAND-Flash read or write access to common/Attribute
<> 144:ef7eb2e8f9f7 228 or I/O memory space (depending on the memory space timing
<> 144:ef7eb2e8f9f7 229 to be configured).
<> 144:ef7eb2e8f9f7 230 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
<> 144:ef7eb2e8f9f7 233 data bus is kept in HiZ after the start of a NAND-Flash
<> 144:ef7eb2e8f9f7 234 write access to common/Attribute or I/O memory space (depending
<> 144:ef7eb2e8f9f7 235 on the memory space timing to be configured).
<> 144:ef7eb2e8f9f7 236 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 }FSMC_NAND_PCC_TimingTypeDef;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief FSMC NAND Configuration Structure definition
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 typedef struct
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
<> 144:ef7eb2e8f9f7 246 This parameter can be any value of @ref FSMC_Wait_feature */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 249 delay between CLE low and RE low.
<> 144:ef7eb2e8f9f7 250 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 253 delay between ALE low and RE low.
<> 144:ef7eb2e8f9f7 254 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 }FSMC_PCCARD_InitTypeDef;
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @}
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 263 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 274 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 275 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 276 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @}
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
<> 144:ef7eb2e8f9f7 282 * @{
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 285 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /** @defgroup FSMC_Memory_Type FSMC Memory Type
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 294 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 295 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @}
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 314 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @}
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 323 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 332 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @}
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
<> 144:ef7eb2e8f9f7 338 * @note These values are available only for the STM32F405/415/407/417xx devices.
<> 144:ef7eb2e8f9f7 339 * @{
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 342 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @}
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
<> 144:ef7eb2e8f9f7 348 * @{
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 351 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @}
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /** @defgroup FSMC_Write_Operation FSMC Write Operation
<> 144:ef7eb2e8f9f7 357 * @{
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 360 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 369 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @}
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
<> 144:ef7eb2e8f9f7 375 * @{
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 378 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @}
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
<> 144:ef7eb2e8f9f7 384 * @{
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 387 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /** @defgroup FSMC_Page_Size FSMC Page Size
<> 144:ef7eb2e8f9f7 393 * @{
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 396 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
<> 144:ef7eb2e8f9f7 397 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
<> 144:ef7eb2e8f9f7 398 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
<> 144:ef7eb2e8f9f7 399 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
<> 144:ef7eb2e8f9f7 405 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
<> 144:ef7eb2e8f9f7 406 * @{
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
<> 144:ef7eb2e8f9f7 409 #define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /** @defgroup FSMC_Write_Burst FSMC Write Burst
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 418 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @}
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
<> 144:ef7eb2e8f9f7 424 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
<> 144:ef7eb2e8f9f7 425 * @{
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @defgroup FSMC_Access_Mode FSMC Access Mode
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 437 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 438 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 439 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @}
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 448 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
<> 144:ef7eb2e8f9f7 449 * @{
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
<> 144:ef7eb2e8f9f7 452 * @{
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 455 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /** @defgroup FSMC_Wait_feature FSMC Wait feature
<> 144:ef7eb2e8f9f7 461 * @{
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 464 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 473 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @}
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
<> 144:ef7eb2e8f9f7 479 * @{
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 483 /**
<> 144:ef7eb2e8f9f7 484 * @}
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /** @defgroup FSMC_ECC FSMC ECC
<> 144:ef7eb2e8f9f7 488 * @{
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 491 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
<> 144:ef7eb2e8f9f7 497 * @{
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 500 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 501 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 502 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
<> 144:ef7eb2e8f9f7 503 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 504 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
<> 144:ef7eb2e8f9f7 505 /**
<> 144:ef7eb2e8f9f7 506 * @}
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @}
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
<> 144:ef7eb2e8f9f7 514 * @{
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 517 #define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 518 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 519 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 520 /**
<> 144:ef7eb2e8f9f7 521 * @}
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
<> 144:ef7eb2e8f9f7 525 * @{
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 528 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 529 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 530 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
<> 144:ef7eb2e8f9f7 539 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
<> 144:ef7eb2e8f9f7 540 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 541 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
<> 144:ef7eb2e8f9f7 542 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
<> 144:ef7eb2e8f9f7 543 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
<> 144:ef7eb2e8f9f7 546 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
<> 144:ef7eb2e8f9f7 547 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 548 #define FSMC_NAND_DEVICE FSMC_Bank2_3
<> 144:ef7eb2e8f9f7 549 #define FSMC_PCCARD_DEVICE FSMC_Bank4
<> 144:ef7eb2e8f9f7 550 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
<> 144:ef7eb2e8f9f7 553 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
<> 144:ef7eb2e8f9f7 554 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
<> 144:ef7eb2e8f9f7 557 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
<> 144:ef7eb2e8f9f7 558 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 559 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
<> 144:ef7eb2e8f9f7 562 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
<> 144:ef7eb2e8f9f7 563 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
<> 144:ef7eb2e8f9f7 564 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
<> 144:ef7eb2e8f9f7 565 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
<> 144:ef7eb2e8f9f7 566 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
<> 144:ef7eb2e8f9f7 569 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 572 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
<> 144:ef7eb2e8f9f7 573 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
<> 144:ef7eb2e8f9f7 574 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #define FMC_NAND_Init FSMC_NAND_Init
<> 144:ef7eb2e8f9f7 577 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
<> 144:ef7eb2e8f9f7 578 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
<> 144:ef7eb2e8f9f7 579 #define FMC_NAND_DeInit FSMC_NAND_DeInit
<> 144:ef7eb2e8f9f7 580 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
<> 144:ef7eb2e8f9f7 581 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
<> 144:ef7eb2e8f9f7 582 #define FMC_NAND_GetECC FSMC_NAND_GetECC
<> 144:ef7eb2e8f9f7 583 #define FMC_PCCARD_Init FSMC_PCCARD_Init
<> 144:ef7eb2e8f9f7 584 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
<> 144:ef7eb2e8f9f7 585 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
<> 144:ef7eb2e8f9f7 586 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
<> 144:ef7eb2e8f9f7 587 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
<> 144:ef7eb2e8f9f7 590 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
<> 144:ef7eb2e8f9f7 591 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
<> 144:ef7eb2e8f9f7 592 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
<> 144:ef7eb2e8f9f7 593 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
<> 144:ef7eb2e8f9f7 594 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
<> 144:ef7eb2e8f9f7 595 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
<> 144:ef7eb2e8f9f7 596 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
<> 144:ef7eb2e8f9f7 597 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
<> 144:ef7eb2e8f9f7 598 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
<> 144:ef7eb2e8f9f7 599 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
<> 144:ef7eb2e8f9f7 600 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
<> 144:ef7eb2e8f9f7 601 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
<> 144:ef7eb2e8f9f7 604 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
<> 144:ef7eb2e8f9f7 605 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 606 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
<> 144:ef7eb2e8f9f7 607 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
<> 144:ef7eb2e8f9f7 608 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
<> 144:ef7eb2e8f9f7 611 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
<> 144:ef7eb2e8f9f7 612 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 613 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
<> 144:ef7eb2e8f9f7 614 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
<> 144:ef7eb2e8f9f7 617 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
<> 144:ef7eb2e8f9f7 620 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
<> 144:ef7eb2e8f9f7 621 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
<> 144:ef7eb2e8f9f7 624 #define FMC_IT_LEVEL FSMC_IT_LEVEL
<> 144:ef7eb2e8f9f7 625 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
<> 144:ef7eb2e8f9f7 626 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
<> 144:ef7eb2e8f9f7 629 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
<> 144:ef7eb2e8f9f7 630 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
<> 144:ef7eb2e8f9f7 631 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
<> 144:ef7eb2e8f9f7 632 /**
<> 144:ef7eb2e8f9f7 633 * @}
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 641 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
<> 144:ef7eb2e8f9f7 642 * @{
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
<> 144:ef7eb2e8f9f7 646 * @brief macros to handle NOR device enable/disable and read/write operations
<> 144:ef7eb2e8f9f7 647 * @{
<> 144:ef7eb2e8f9f7 648 */
<> 144:ef7eb2e8f9f7 649 /**
<> 144:ef7eb2e8f9f7 650 * @brief Enable the NORSRAM device access.
<> 144:ef7eb2e8f9f7 651 * @param __INSTANCE__: FSMC_NORSRAM Instance
<> 144:ef7eb2e8f9f7 652 * @param __BANK__: FSMC_NORSRAM Bank
<> 144:ef7eb2e8f9f7 653 * @retval none
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @brief Disable the NORSRAM device access.
<> 144:ef7eb2e8f9f7 659 * @param __INSTANCE__: FSMC_NORSRAM Instance
<> 144:ef7eb2e8f9f7 660 * @param __BANK__: FSMC_NORSRAM Bank
<> 144:ef7eb2e8f9f7 661 * @retval none
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @}
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
<> 144:ef7eb2e8f9f7 669 * @brief macros to handle NAND device enable/disable
<> 144:ef7eb2e8f9f7 670 * @{
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @brief Enable the NAND device access.
<> 144:ef7eb2e8f9f7 675 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 676 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 677 * @retval none
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
<> 144:ef7eb2e8f9f7 680 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @brief Disable the NAND device access.
<> 144:ef7eb2e8f9f7 684 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 685 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 686 * @retval none
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
<> 144:ef7eb2e8f9f7 689 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
<> 144:ef7eb2e8f9f7 690 /**
<> 144:ef7eb2e8f9f7 691 * @}
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
<> 144:ef7eb2e8f9f7 695 * @brief macros to handle SRAM read/write operations
<> 144:ef7eb2e8f9f7 696 * @{
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Enable the PCCARD device access.
<> 144:ef7eb2e8f9f7 700 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 701 * @retval none
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @brief Disable the PCCARD device access.
<> 144:ef7eb2e8f9f7 707 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 708 * @retval none
<> 144:ef7eb2e8f9f7 709 */
<> 144:ef7eb2e8f9f7 710 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
<> 144:ef7eb2e8f9f7 711 /**
<> 144:ef7eb2e8f9f7 712 * @}
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
<> 144:ef7eb2e8f9f7 716 * @brief macros to handle FSMC flags and interrupts
<> 144:ef7eb2e8f9f7 717 * @{
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 /**
<> 144:ef7eb2e8f9f7 720 * @brief Enable the NAND device interrupt.
<> 144:ef7eb2e8f9f7 721 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 722 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 723 * @param __INTERRUPT__: FSMC_NAND interrupt
<> 144:ef7eb2e8f9f7 724 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 725 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 726 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 727 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 728 * @retval None
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
<> 144:ef7eb2e8f9f7 731 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @brief Disable the NAND device interrupt.
<> 144:ef7eb2e8f9f7 735 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 736 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 737 * @param __INTERRUPT__: FSMC_NAND interrupt
<> 144:ef7eb2e8f9f7 738 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 739 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 740 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 741 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 742 * @retval None
<> 144:ef7eb2e8f9f7 743 */
<> 144:ef7eb2e8f9f7 744 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
<> 144:ef7eb2e8f9f7 745 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @brief Get flag status of the NAND device.
<> 144:ef7eb2e8f9f7 749 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 750 * @param __BANK__ : FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 751 * @param __FLAG__ : FSMC_NAND flag
<> 144:ef7eb2e8f9f7 752 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 753 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 754 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 755 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 756 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 757 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 758 */
<> 144:ef7eb2e8f9f7 759 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
<> 144:ef7eb2e8f9f7 760 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /**
<> 144:ef7eb2e8f9f7 763 * @brief Clear flag status of the NAND device.
<> 144:ef7eb2e8f9f7 764 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 765 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 766 * @param __FLAG__: FSMC_NAND flag
<> 144:ef7eb2e8f9f7 767 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 768 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 769 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 770 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 771 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 772 * @retval None
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
<> 144:ef7eb2e8f9f7 775 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /**
<> 144:ef7eb2e8f9f7 778 * @brief Enable the PCCARD device interrupt.
<> 144:ef7eb2e8f9f7 779 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 780 * @param __INTERRUPT__: FSMC_PCCARD interrupt
<> 144:ef7eb2e8f9f7 781 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 782 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 783 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 784 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 785 * @retval None
<> 144:ef7eb2e8f9f7 786 */
<> 144:ef7eb2e8f9f7 787 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /**
<> 144:ef7eb2e8f9f7 790 * @brief Disable the PCCARD device interrupt.
<> 144:ef7eb2e8f9f7 791 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 792 * @param __INTERRUPT__: FSMC_PCCARD interrupt
<> 144:ef7eb2e8f9f7 793 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 794 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 795 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 796 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 797 * @retval None
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /**
<> 144:ef7eb2e8f9f7 802 * @brief Get flag status of the PCCARD device.
<> 144:ef7eb2e8f9f7 803 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 804 * @param __FLAG__: FSMC_PCCARD flag
<> 144:ef7eb2e8f9f7 805 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 806 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 807 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 808 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 809 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 810 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /**
<> 144:ef7eb2e8f9f7 815 * @brief Clear flag status of the PCCARD device.
<> 144:ef7eb2e8f9f7 816 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 817 * @param __FLAG__: FSMC_PCCARD flag
<> 144:ef7eb2e8f9f7 818 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 819 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 820 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 821 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 822 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 823 * @retval None
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
<> 144:ef7eb2e8f9f7 826 /**
<> 144:ef7eb2e8f9f7 827 * @}
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
<> 144:ef7eb2e8f9f7 832 * @{
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
<> 144:ef7eb2e8f9f7 835 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
<> 144:ef7eb2e8f9f7 836 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
<> 144:ef7eb2e8f9f7 837 ((__BANK__) == FSMC_NORSRAM_BANK4))
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
<> 144:ef7eb2e8f9f7 840 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
<> 144:ef7eb2e8f9f7 843 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
<> 144:ef7eb2e8f9f7 844 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 847 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
<> 144:ef7eb2e8f9f7 848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
<> 144:ef7eb2e8f9f7 851 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
<> 144:ef7eb2e8f9f7 852 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
<> 144:ef7eb2e8f9f7 853 ((__MODE__) == FSMC_ACCESS_MODE_D))
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
<> 144:ef7eb2e8f9f7 856 ((BANK) == FSMC_NAND_BANK3))
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
<> 144:ef7eb2e8f9f7 859 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 862 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
<> 144:ef7eb2e8f9f7 865 ((STATE) == FSMC_NAND_ECC_ENABLE))
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
<> 144:ef7eb2e8f9f7 868 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
<> 144:ef7eb2e8f9f7 869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
<> 144:ef7eb2e8f9f7 870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
<> 144:ef7eb2e8f9f7 871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
<> 144:ef7eb2e8f9f7 872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 895 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 898 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 901 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
<> 144:ef7eb2e8f9f7 904 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 907 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
<> 144:ef7eb2e8f9f7 910 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 913 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
<> 144:ef7eb2e8f9f7 916 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
<> 144:ef7eb2e8f9f7 921 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
<> 144:ef7eb2e8f9f7 932 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
<> 144:ef7eb2e8f9f7 937 ((SIZE) == FSMC_PAGE_SIZE_128) || \
<> 144:ef7eb2e8f9f7 938 ((SIZE) == FSMC_PAGE_SIZE_256) || \
<> 144:ef7eb2e8f9f7 939 ((SIZE) == FSMC_PAGE_SIZE_1024))
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
<> 144:ef7eb2e8f9f7 942 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /**
<> 144:ef7eb2e8f9f7 945 * @}
<> 144:ef7eb2e8f9f7 946 */
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @}
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 952 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
<> 144:ef7eb2e8f9f7 953 * @{
<> 144:ef7eb2e8f9f7 954 */
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
<> 144:ef7eb2e8f9f7 957 * @{
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 961 * @{
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 964 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 965 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
<> 144:ef7eb2e8f9f7 966 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
<> 144:ef7eb2e8f9f7 967 /**
<> 144:ef7eb2e8f9f7 968 * @}
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
<> 144:ef7eb2e8f9f7 972 * @{
<> 144:ef7eb2e8f9f7 973 */
<> 144:ef7eb2e8f9f7 974 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 975 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @}
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979 /**
<> 144:ef7eb2e8f9f7 980 * @}
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
<> 144:ef7eb2e8f9f7 984 /** @defgroup FSMC_LL_NAND NAND
<> 144:ef7eb2e8f9f7 985 * @{
<> 144:ef7eb2e8f9f7 986 */
<> 144:ef7eb2e8f9f7 987 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 988 * @{
<> 144:ef7eb2e8f9f7 989 */
<> 144:ef7eb2e8f9f7 990 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 991 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 992 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 993 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 994 /**
<> 144:ef7eb2e8f9f7 995 * @}
<> 144:ef7eb2e8f9f7 996 */
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
<> 144:ef7eb2e8f9f7 999 * @{
<> 144:ef7eb2e8f9f7 1000 */
<> 144:ef7eb2e8f9f7 1001 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1002 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1003 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @}
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007 /**
<> 144:ef7eb2e8f9f7 1008 * @}
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /** @defgroup FSMC_LL_PCCARD PCCARD
<> 144:ef7eb2e8f9f7 1012 * @{
<> 144:ef7eb2e8f9f7 1013 */
<> 144:ef7eb2e8f9f7 1014 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 1015 * @{
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 1018 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 1019 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 1020 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 1021 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
<> 144:ef7eb2e8f9f7 1022 /**
<> 144:ef7eb2e8f9f7 1023 * @}
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 /**
<> 144:ef7eb2e8f9f7 1026 * @}
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * @}
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @}
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @}
<> 144:ef7eb2e8f9f7 1041 */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 #endif
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 #endif /* __STM32F4xx_LL_FSMC_H */
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/