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targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h@172:7d866c31b3c5, 2017-08-31 (annotated)

Committer:
AnnaBridge
Date:
Thu Aug 31 17:27:04 2017 +0100
Revision:
172:7d866c31b3c5
This updates the lib to the mbed lib v 150

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /**
AnnaBridge 172:7d866c31b3c5 2 *******************************************************************************
AnnaBridge 172:7d866c31b3c5 3 * @file tmpm066_tmrb.h
AnnaBridge 172:7d866c31b3c5 4 * @brief This file provides all the functions prototypes for TMRB driver.
AnnaBridge 172:7d866c31b3c5 5 * @version V2.0.2.1
AnnaBridge 172:7d866c31b3c5 6 * @date 2015/10/09
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
AnnaBridge 172:7d866c31b3c5 9 *******************************************************************************
AnnaBridge 172:7d866c31b3c5 10 */
AnnaBridge 172:7d866c31b3c5 11
AnnaBridge 172:7d866c31b3c5 12 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:7d866c31b3c5 13 #ifndef __TMPM066_TMRB_H
AnnaBridge 172:7d866c31b3c5 14 #define __TMPM066_TMRB_H
AnnaBridge 172:7d866c31b3c5 15
AnnaBridge 172:7d866c31b3c5 16 #ifdef __cplusplus
AnnaBridge 172:7d866c31b3c5 17 extern "C" {
AnnaBridge 172:7d866c31b3c5 18 #endif /* __cplusplus */
AnnaBridge 172:7d866c31b3c5 19
AnnaBridge 172:7d866c31b3c5 20 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:7d866c31b3c5 21 #include "TMPM066.h"
AnnaBridge 172:7d866c31b3c5 22 #include "tx00_common.h"
AnnaBridge 172:7d866c31b3c5 23
AnnaBridge 172:7d866c31b3c5 24 #if defined(__TMPM066_TMRB_H)
AnnaBridge 172:7d866c31b3c5 25 /** @addtogroup TX00_Periph_Driver
AnnaBridge 172:7d866c31b3c5 26 * @{
AnnaBridge 172:7d866c31b3c5 27 */
AnnaBridge 172:7d866c31b3c5 28 /** @addtogroup TMRB
AnnaBridge 172:7d866c31b3c5 29 * @{
AnnaBridge 172:7d866c31b3c5 30 */
AnnaBridge 172:7d866c31b3c5 31 /** @defgroup TMRB_Exported_Types
AnnaBridge 172:7d866c31b3c5 32 * @{
AnnaBridge 172:7d866c31b3c5 33 */
AnnaBridge 172:7d866c31b3c5 34 /**
AnnaBridge 172:7d866c31b3c5 35 * @brief TMRB Init Structure definition
AnnaBridge 172:7d866c31b3c5 36 */
AnnaBridge 172:7d866c31b3c5 37 typedef struct {
AnnaBridge 172:7d866c31b3c5 38 uint32_t Mode; /*!< Select TMRB mode between internal interval
AnnaBridge 172:7d866c31b3c5 39 timer mode and external event counter */
AnnaBridge 172:7d866c31b3c5 40 uint32_t ClkDiv; /*!< Select the division for TMRB source clock */
AnnaBridge 172:7d866c31b3c5 41 uint32_t TrailingTiming; /*!< Specify the trailingtiming value to be written
AnnaBridge 172:7d866c31b3c5 42 into TBnRG1 */
AnnaBridge 172:7d866c31b3c5 43 uint32_t UpCntCtrl; /*!< Select up-counter work mode between
AnnaBridge 172:7d866c31b3c5 44 freerun and auto-reload */
AnnaBridge 172:7d866c31b3c5 45 uint32_t LeadingTiming; /*!< Specify the leadingtiming value to be written
AnnaBridge 172:7d866c31b3c5 46 into TBnRG0 */
AnnaBridge 172:7d866c31b3c5 47 } TMRB_InitTypeDef;
AnnaBridge 172:7d866c31b3c5 48
AnnaBridge 172:7d866c31b3c5 49 /**
AnnaBridge 172:7d866c31b3c5 50 * @brief TMRB Flip-flop Structure definition
AnnaBridge 172:7d866c31b3c5 51 */
AnnaBridge 172:7d866c31b3c5 52
AnnaBridge 172:7d866c31b3c5 53 typedef struct {
AnnaBridge 172:7d866c31b3c5 54 uint32_t FlipflopCtrl; /*!< Select TMRB flip-flop output level */
AnnaBridge 172:7d866c31b3c5 55 uint32_t FlipflopReverseTrg; /*!< Specify TMRB flip-flop reverse trigger */
AnnaBridge 172:7d866c31b3c5 56 } TMRB_FFOutputTypeDef;
AnnaBridge 172:7d866c31b3c5 57
AnnaBridge 172:7d866c31b3c5 58 /**
AnnaBridge 172:7d866c31b3c5 59 * @brief TMRB Interrupt factor Union definition
AnnaBridge 172:7d866c31b3c5 60 */
AnnaBridge 172:7d866c31b3c5 61 typedef union {
AnnaBridge 172:7d866c31b3c5 62 uint32_t All;
AnnaBridge 172:7d866c31b3c5 63 struct {
AnnaBridge 172:7d866c31b3c5 64 uint32_t MatchLeadingTiming:1;
AnnaBridge 172:7d866c31b3c5 65 uint32_t MatchTrailingTiming:1;
AnnaBridge 172:7d866c31b3c5 66 uint32_t OverFlow:1;
AnnaBridge 172:7d866c31b3c5 67 uint32_t Reserverd:29;
AnnaBridge 172:7d866c31b3c5 68 } Bit;
AnnaBridge 172:7d866c31b3c5 69 } TMRB_INTFactor;
AnnaBridge 172:7d866c31b3c5 70
AnnaBridge 172:7d866c31b3c5 71 /**
AnnaBridge 172:7d866c31b3c5 72 * @brief TMRB Interrupt masked Union definition
AnnaBridge 172:7d866c31b3c5 73 */
AnnaBridge 172:7d866c31b3c5 74 typedef union {
AnnaBridge 172:7d866c31b3c5 75 uint32_t All;
AnnaBridge 172:7d866c31b3c5 76 struct {
AnnaBridge 172:7d866c31b3c5 77 uint32_t MatchLeadingTimingMask:1;
AnnaBridge 172:7d866c31b3c5 78 uint32_t MatchTrailingTimingMask:1;
AnnaBridge 172:7d866c31b3c5 79 uint32_t OverFlowMask:1;
AnnaBridge 172:7d866c31b3c5 80 uint32_t Reserverd:29;
AnnaBridge 172:7d866c31b3c5 81 } Bit;
AnnaBridge 172:7d866c31b3c5 82 } TMRB_INTMask;
AnnaBridge 172:7d866c31b3c5 83
AnnaBridge 172:7d866c31b3c5 84 /** @} */
AnnaBridge 172:7d866c31b3c5 85 /* End of group TMRB_Exported_Types */
AnnaBridge 172:7d866c31b3c5 86
AnnaBridge 172:7d866c31b3c5 87 /** @defgroup TMRB_Exported_Constants
AnnaBridge 172:7d866c31b3c5 88 * @{
AnnaBridge 172:7d866c31b3c5 89 */
AnnaBridge 172:7d866c31b3c5 90 #define IS_TMRB_ALL_PERIPH(param) (((param) == TSB_TB0) || \
AnnaBridge 172:7d866c31b3c5 91 ((param) == TSB_TB1) || \
AnnaBridge 172:7d866c31b3c5 92 ((param) == TSB_TB2) || \
AnnaBridge 172:7d866c31b3c5 93 ((param) == TSB_TB3) || \
AnnaBridge 172:7d866c31b3c5 94 ((param) == TSB_TB4) || \
AnnaBridge 172:7d866c31b3c5 95 ((param) == TSB_TB5) || \
AnnaBridge 172:7d866c31b3c5 96 ((param) == TSB_TB6) || \
AnnaBridge 172:7d866c31b3c5 97 ((param) == TSB_TB7))
AnnaBridge 172:7d866c31b3c5 98
AnnaBridge 172:7d866c31b3c5 99 #define IS_TMRB_SYNC_PERIPH(param) (((param) == TSB_TB1) || \
AnnaBridge 172:7d866c31b3c5 100 ((param) == TSB_TB2) || \
AnnaBridge 172:7d866c31b3c5 101 ((param) == TSB_TB3) || \
AnnaBridge 172:7d866c31b3c5 102 ((param) == TSB_TB5) || \
AnnaBridge 172:7d866c31b3c5 103 ((param) == TSB_TB6) || \
AnnaBridge 172:7d866c31b3c5 104 ((param) == TSB_TB7))
AnnaBridge 172:7d866c31b3c5 105
AnnaBridge 172:7d866c31b3c5 106 #define IS_TMRB_CAP_PERIPH(param) (((param) == TSB_TB0) || \
AnnaBridge 172:7d866c31b3c5 107 ((param) == TSB_TB1) || \
AnnaBridge 172:7d866c31b3c5 108 ((param) == TSB_TB2) || \
AnnaBridge 172:7d866c31b3c5 109 ((param) == TSB_TB3) || \
AnnaBridge 172:7d866c31b3c5 110 ((param) == TSB_TB4) || \
AnnaBridge 172:7d866c31b3c5 111 ((param) == TSB_TB5))
AnnaBridge 172:7d866c31b3c5 112
AnnaBridge 172:7d866c31b3c5 113 #define TMRB_INTERVAL_TIMER ((uint32_t)0x00000001)
AnnaBridge 172:7d866c31b3c5 114 #define TMRB_EVENT_CNT ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 115 #define IS_TMRB_MODE(param) (((param) == TMRB_INTERVAL_TIMER) || \
AnnaBridge 172:7d866c31b3c5 116 ((param) == TMRB_EVENT_CNT))
AnnaBridge 172:7d866c31b3c5 117
AnnaBridge 172:7d866c31b3c5 118 #define TMRB_CLK_DIV_2 ((uint32_t)0x00000001)
AnnaBridge 172:7d866c31b3c5 119 #define TMRB_CLK_DIV_8 ((uint32_t)0x00000002)
AnnaBridge 172:7d866c31b3c5 120 #define TMRB_CLK_DIV_32 ((uint32_t)0x00000003)
AnnaBridge 172:7d866c31b3c5 121 #define TMRB_CLK_DIV_64 ((uint32_t)0x00000004)
AnnaBridge 172:7d866c31b3c5 122 #define TMRB_CLK_DIV_128 ((uint32_t)0x00000005)
AnnaBridge 172:7d866c31b3c5 123 #define TMRB_CLK_DIV_256 ((uint32_t)0x00000006)
AnnaBridge 172:7d866c31b3c5 124 #define TMRB_CLK_DIV_512 ((uint32_t)0x00000007)
AnnaBridge 172:7d866c31b3c5 125 #define IS_TMRB_CLK_DIV(param) (((param) == TMRB_CLK_DIV_2) || \
AnnaBridge 172:7d866c31b3c5 126 ((param) == TMRB_CLK_DIV_8) || \
AnnaBridge 172:7d866c31b3c5 127 ((param) == TMRB_CLK_DIV_32) || \
AnnaBridge 172:7d866c31b3c5 128 ((param) == TMRB_CLK_DIV_64) || \
AnnaBridge 172:7d866c31b3c5 129 ((param) == TMRB_CLK_DIV_128) || \
AnnaBridge 172:7d866c31b3c5 130 ((param) == TMRB_CLK_DIV_256) || \
AnnaBridge 172:7d866c31b3c5 131 ((param) == TMRB_CLK_DIV_512))
AnnaBridge 172:7d866c31b3c5 132
AnnaBridge 172:7d866c31b3c5 133 #define TMRB_FREE_RUN ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 134 #define TMRB_AUTO_CLEAR ((uint32_t)0x00000008)
AnnaBridge 172:7d866c31b3c5 135 #define IS_TMRB_UC_CTRL(param) (((param) == TMRB_FREE_RUN) || \
AnnaBridge 172:7d866c31b3c5 136 ((param) == TMRB_AUTO_CLEAR))
AnnaBridge 172:7d866c31b3c5 137
AnnaBridge 172:7d866c31b3c5 138 #define TMRB_FLIPFLOP_INVERT ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 139 #define TMRB_FLIPFLOP_SET ((uint32_t)0x00000001)
AnnaBridge 172:7d866c31b3c5 140 #define TMRB_FLIPFLOP_CLEAR ((uint32_t)0x00000002)
AnnaBridge 172:7d866c31b3c5 141 #define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \
AnnaBridge 172:7d866c31b3c5 142 ((param) == TMRB_FLIPFLOP_SET) || \
AnnaBridge 172:7d866c31b3c5 143 ((param) == TMRB_FLIPFLOP_CLEAR))
AnnaBridge 172:7d866c31b3c5 144
AnnaBridge 172:7d866c31b3c5 145 #define TMRB_DISABLE_FLIPFLOP ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 146 #define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010)
AnnaBridge 172:7d866c31b3c5 147 #define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020)
AnnaBridge 172:7d866c31b3c5 148 #define TMRB_FLIPFLOP_MATCH_TRAILINGTIMING ((uint32_t)0x00000008)
AnnaBridge 172:7d866c31b3c5 149 #define TMRB_FLIPFLOP_MATCH_LEADINGTIMING ((uint32_t)0x00000004)
AnnaBridge 172:7d866c31b3c5 150 #define IS_TMRB_FLIPFLOP_TRG(param) (((param) == TMRB_DISABLE_FLIPFLOP) || \
AnnaBridge 172:7d866c31b3c5 151 ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \
AnnaBridge 172:7d866c31b3c5 152 ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \
AnnaBridge 172:7d866c31b3c5 153 ((param) == TMRB_FLIPFLOP_MATCH_TRAILINGTIMING) || \
AnnaBridge 172:7d866c31b3c5 154 ((param) == TMRB_FLIPFLOP_MATCH_LEADINGTIMING) || \
AnnaBridge 172:7d866c31b3c5 155 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \
AnnaBridge 172:7d866c31b3c5 156 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 157 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 158 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 159 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 160 ((param) == (TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 161 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 162 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 163 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 164 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \
AnnaBridge 172:7d866c31b3c5 165 ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)))
AnnaBridge 172:7d866c31b3c5 166
AnnaBridge 172:7d866c31b3c5 167 #define TMRB_DISABLE_CAPTURE ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 168 #define TMRB_CAPTURE_IN_RISING_FALLING ((uint32_t)0x00000020)
AnnaBridge 172:7d866c31b3c5 169 #define TMRB_CAPTURE_FF_RISING_FALLING ((uint32_t)0x00000030)
AnnaBridge 172:7d866c31b3c5 170 #define IS_TMRB_CAPTURE_TIMING(param) (((param) == TMRB_DISABLE_CAPTURE) || \
AnnaBridge 172:7d866c31b3c5 171 ((param) == TMRB_CAPTURE_IN_RISING_FALLING) || \
AnnaBridge 172:7d866c31b3c5 172 ((param) == TMRB_CAPTURE_FF_RISING_FALLING))
AnnaBridge 172:7d866c31b3c5 173
AnnaBridge 172:7d866c31b3c5 174 #define TMRB_RUN ((uint32_t)0x00000005)
AnnaBridge 172:7d866c31b3c5 175 #define TMRB_STOP ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 176 #define IS_TMRB_CMD(param) (((param) == TMRB_RUN) || ((param) == TMRB_STOP))
AnnaBridge 172:7d866c31b3c5 177
AnnaBridge 172:7d866c31b3c5 178 #define TMRB_REG_0 ((uint8_t)0x00)
AnnaBridge 172:7d866c31b3c5 179 #define TMRB_REG_1 ((uint8_t)0x01)
AnnaBridge 172:7d866c31b3c5 180 #define IS_TMRB_REG(param) (((param) == TMRB_REG_0) || ((param) == TMRB_REG_1))
AnnaBridge 172:7d866c31b3c5 181
AnnaBridge 172:7d866c31b3c5 182 #define TMRB_CAPTURE_0 ((uint8_t)0x00)
AnnaBridge 172:7d866c31b3c5 183 #define TMRB_CAPTURE_1 ((uint8_t)0x01)
AnnaBridge 172:7d866c31b3c5 184 #define IS_TMRB_CAPTURE_REG(param) (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1))
AnnaBridge 172:7d866c31b3c5 185
AnnaBridge 172:7d866c31b3c5 186 #define TMRB_NO_INT_MASK ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 187 #define TMRB_MASK_MATCH_LEADINGTIMING_INT ((uint32_t)0x00000001)
AnnaBridge 172:7d866c31b3c5 188 #define TMRB_MASK_MATCH_TRAILINGTIMING_INT ((uint32_t)0x00000002)
AnnaBridge 172:7d866c31b3c5 189 #define TMRB_MASK_OVERFLOW_INT ((uint32_t)0x00000004)
AnnaBridge 172:7d866c31b3c5 190 #define IS_TMRB_INT_MASK(param) (((param) == TMRB_NO_INT_MASK) || \
AnnaBridge 172:7d866c31b3c5 191 ((param) == TMRB_MASK_MATCH_LEADINGTIMING_INT) || \
AnnaBridge 172:7d866c31b3c5 192 ((param) == TMRB_MASK_MATCH_TRAILINGTIMING_INT) || \
AnnaBridge 172:7d866c31b3c5 193 ((param) == TMRB_MASK_OVERFLOW_INT) || \
AnnaBridge 172:7d866c31b3c5 194 ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT)) || \
AnnaBridge 172:7d866c31b3c5 195 ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \
AnnaBridge 172:7d866c31b3c5 196 ((param) == (TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \
AnnaBridge 172:7d866c31b3c5 197 ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)))
AnnaBridge 172:7d866c31b3c5 198
AnnaBridge 172:7d866c31b3c5 199 #define TMRB_TRG_EDGE_RISING ((uint8_t)0x00)
AnnaBridge 172:7d866c31b3c5 200 #define TMRB_TRG_EDGE_FALLING ((uint8_t)0x02)
AnnaBridge 172:7d866c31b3c5 201 #define IS_TMRB_TRG_EDGE(param) (((param) == TMRB_TRG_EDGE_RISING) || \
AnnaBridge 172:7d866c31b3c5 202 ((param) == TMRB_TRG_EDGE_FALLING))
AnnaBridge 172:7d866c31b3c5 203
AnnaBridge 172:7d866c31b3c5 204 #define TMRB_RUNNING_IN_CORE_HALT ((uint8_t)0x00)
AnnaBridge 172:7d866c31b3c5 205 #define TMRB_STOP_IN_CORE_HALT ((uint8_t)0x40)
AnnaBridge 172:7d866c31b3c5 206 #define IS_TMRB_CLK_IN_CORE_HALT(param) (((param) == TMRB_RUNNING_IN_CORE_HALT) || \
AnnaBridge 172:7d866c31b3c5 207 ((param) == TMRB_STOP_IN_CORE_HALT))
AnnaBridge 172:7d866c31b3c5 208
AnnaBridge 172:7d866c31b3c5 209 #define TMRB_NO_INT ((uint32_t)0x00000000)
AnnaBridge 172:7d866c31b3c5 210 #define IS_TMRB_VALUE(param) ((param) <= 0x0000FFFFU)
AnnaBridge 172:7d866c31b3c5 211 #define IS_VALID_LEADINGTIMING(param1, param2) ((param1) <= (param2))
AnnaBridge 172:7d866c31b3c5 212
AnnaBridge 172:7d866c31b3c5 213 #define TMRB_DMA_REQ_CMP_MATCH ((uint32_t)0x000000004)
AnnaBridge 172:7d866c31b3c5 214 #define TMRB_DMA_REQ_CAPTURE_1 ((uint32_t)0x000000002)
AnnaBridge 172:7d866c31b3c5 215 #define TMRB_DMA_REQ_CAPTURE_0 ((uint32_t)0x000000001)
AnnaBridge 172:7d866c31b3c5 216 #define IS_TMRB_DMA_REQ(param) (((param) == TMRB_DMA_REQ_CMP_MATCH) || \
AnnaBridge 172:7d866c31b3c5 217 ((param) == TMRB_DMA_REQ_CAPTURE_1) || \
AnnaBridge 172:7d866c31b3c5 218 ((param) == TMRB_DMA_REQ_CAPTURE_0))
AnnaBridge 172:7d866c31b3c5 219
AnnaBridge 172:7d866c31b3c5 220 /** @} */
AnnaBridge 172:7d866c31b3c5 221 /* End of group TMRB_Exported_Constants */
AnnaBridge 172:7d866c31b3c5 222 /** @defgroup TMRB_Exported_FunctionPrototypes
AnnaBridge 172:7d866c31b3c5 223 * @{
AnnaBridge 172:7d866c31b3c5 224 */
AnnaBridge 172:7d866c31b3c5 225 void TMRB_Enable(TSB_TB_TypeDef * TBx);
AnnaBridge 172:7d866c31b3c5 226 void TMRB_Disable(TSB_TB_TypeDef * TBx);
AnnaBridge 172:7d866c31b3c5 227 void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd);
AnnaBridge 172:7d866c31b3c5 228 void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct);
AnnaBridge 172:7d866c31b3c5 229 void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming);
AnnaBridge 172:7d866c31b3c5 230 void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct);
AnnaBridge 172:7d866c31b3c5 231 TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx);
AnnaBridge 172:7d866c31b3c5 232 TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx);
AnnaBridge 172:7d866c31b3c5 233 void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask);
AnnaBridge 172:7d866c31b3c5 234 void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming);
AnnaBridge 172:7d866c31b3c5 235 void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming);
AnnaBridge 172:7d866c31b3c5 236 uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg);
AnnaBridge 172:7d866c31b3c5 237 uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx);
AnnaBridge 172:7d866c31b3c5 238 uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg);
AnnaBridge 172:7d866c31b3c5 239 void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx);
AnnaBridge 172:7d866c31b3c5 240 void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
AnnaBridge 172:7d866c31b3c5 241 void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState);
AnnaBridge 172:7d866c31b3c5 242 void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode);
AnnaBridge 172:7d866c31b3c5 243 void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState);
AnnaBridge 172:7d866c31b3c5 244 void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq);
AnnaBridge 172:7d866c31b3c5 245
AnnaBridge 172:7d866c31b3c5 246 /** @} */
AnnaBridge 172:7d866c31b3c5 247 /* End of group TMRB_Exported_FunctionPrototypes */
AnnaBridge 172:7d866c31b3c5 248
AnnaBridge 172:7d866c31b3c5 249 /** @} */
AnnaBridge 172:7d866c31b3c5 250 /* End of group TMRB */
AnnaBridge 172:7d866c31b3c5 251
AnnaBridge 172:7d866c31b3c5 252 /** @} */
AnnaBridge 172:7d866c31b3c5 253 /* End of group TX00_Periph_Driver */
AnnaBridge 172:7d866c31b3c5 254 #endif /* defined(__TMPM066_TMRB_H) */
AnnaBridge 172:7d866c31b3c5 255
AnnaBridge 172:7d866c31b3c5 256 #ifdef __cplusplus
AnnaBridge 172:7d866c31b3c5 257 }
AnnaBridge 172:7d866c31b3c5 258 #endif /* __cplusplus */
AnnaBridge 172:7d866c31b3c5 259 #endif /* __TMPM066_TMRB_H */