Pratyush Mallick / Mbed OS testing

this is testing

app/noos_mbed/drivers/adc/ad7606/ad7606.h@0:3afcd581558d, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 18:54:16 2021 +0530
Revision:
0:3afcd581558d
this is testing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 0:3afcd581558d 1 /***************************************************************************//**
pmallick 0:3afcd581558d 2 * @file ad7606.h
pmallick 0:3afcd581558d 3 * @brief Header file for the ad7606 Driver.
pmallick 0:3afcd581558d 4 * @author Stefan Popa (stefan.popa@analog.com)
pmallick 0:3afcd581558d 5 * @author Darius Berghe (darius.berghe@analog.com)
pmallick 0:3afcd581558d 6 ********************************************************************************
pmallick 0:3afcd581558d 7 * Copyright 2020(c) Analog Devices, Inc.
pmallick 0:3afcd581558d 8 *
pmallick 0:3afcd581558d 9 * All rights reserved.
pmallick 0:3afcd581558d 10 *
pmallick 0:3afcd581558d 11 * Redistribution and use in source and binary forms, with or without
pmallick 0:3afcd581558d 12 * modification, are permitted provided that the following conditions are met:
pmallick 0:3afcd581558d 13 * - Redistributions of source code must retain the above copyright
pmallick 0:3afcd581558d 14 * notice, this list of conditions and the following disclaimer.
pmallick 0:3afcd581558d 15 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:3afcd581558d 16 * notice, this list of conditions and the following disclaimer in
pmallick 0:3afcd581558d 17 * the documentation and/or other materials provided with the
pmallick 0:3afcd581558d 18 * distribution.
pmallick 0:3afcd581558d 19 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:3afcd581558d 20 * contributors may be used to endorse or promote products derived
pmallick 0:3afcd581558d 21 * from this software without specific prior written permission.
pmallick 0:3afcd581558d 22 * - The use of this software may or may not infringe the patent rights
pmallick 0:3afcd581558d 23 * of one or more patent holders. This license does not release you
pmallick 0:3afcd581558d 24 * from the requirement that you obtain separate licenses from these
pmallick 0:3afcd581558d 25 * patent holders to use this software.
pmallick 0:3afcd581558d 26 * - Use of the software either in source or binary form, must be run
pmallick 0:3afcd581558d 27 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:3afcd581558d 28 *
pmallick 0:3afcd581558d 29 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:3afcd581558d 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:3afcd581558d 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:3afcd581558d 32 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:3afcd581558d 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:3afcd581558d 34 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 0:3afcd581558d 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 0:3afcd581558d 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 0:3afcd581558d 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 0:3afcd581558d 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:3afcd581558d 39 *******************************************************************************/
pmallick 0:3afcd581558d 40 #ifndef AD7606_H_
pmallick 0:3afcd581558d 41 #define AD7606_H_
pmallick 0:3afcd581558d 42
pmallick 0:3afcd581558d 43 /******************************************************************************/
pmallick 0:3afcd581558d 44 /***************************** Include Files **********************************/
pmallick 0:3afcd581558d 45 /******************************************************************************/
pmallick 0:3afcd581558d 46 #include <stdint.h>
pmallick 0:3afcd581558d 47 #include <stdbool.h>
pmallick 0:3afcd581558d 48
pmallick 0:3afcd581558d 49 //#include "platform_drivers.h"
pmallick 0:3afcd581558d 50 #include "irq.h"
pmallick 0:3afcd581558d 51 #include "util.h"
pmallick 0:3afcd581558d 52 #include "delay.h"
pmallick 0:3afcd581558d 53 #include "error.h"
pmallick 0:3afcd581558d 54 #include "gpio.h"
pmallick 0:3afcd581558d 55 #include "i2c.h"
pmallick 0:3afcd581558d 56 #include "spi.h"
pmallick 0:3afcd581558d 57 #include "uart.h"
pmallick 0:3afcd581558d 58
pmallick 0:3afcd581558d 59 /******************************************************************************/
pmallick 0:3afcd581558d 60 /********************** Macros and Constants Definitions **********************/
pmallick 0:3afcd581558d 61 /******************************************************************************/
pmallick 0:3afcd581558d 62 /* Error codes defined in 'errno.h' file but can't find by Mbed online/offline
pmallick 0:3afcd581558d 63 * compiler
pmallick 0:3afcd581558d 64 * */
pmallick 0:3afcd581558d 65 #define ENOTSUP 134
pmallick 0:3afcd581558d 66 #define EBADMSG 77 /* Bad message */
pmallick 0:3afcd581558d 67 #define ETIME 62 /* Stream ioctl timeout */
pmallick 0:3afcd581558d 68 #define ENODEV 19 /* No such device */
pmallick 0:3afcd581558d 69
pmallick 0:3afcd581558d 70 #define AD7606_REG_STATUS 0x01
pmallick 0:3afcd581558d 71 #define AD7606_REG_CONFIG 0x02
pmallick 0:3afcd581558d 72 #define AD7606_REG_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1))
pmallick 0:3afcd581558d 73 #define AD7606_REG_BANDWIDTH 0x07
pmallick 0:3afcd581558d 74 #define AD7606_REG_OVERSAMPLING 0x08
pmallick 0:3afcd581558d 75 #define AD7606_REG_GAIN_CH(ch) (0x09 + (ch))
pmallick 0:3afcd581558d 76 #define AD7606_REG_OFFSET_CH(ch) (0x11 + (ch))
pmallick 0:3afcd581558d 77 #define AD7606_REG_PHASE_CH(ch) (0x19 + (ch))
pmallick 0:3afcd581558d 78 #define AD7606_REG_DIGITAL_DIAG_ENABLE 0x21
pmallick 0:3afcd581558d 79 #define AD7606_REG_DIGITAL_DIAG_ERR 0x22
pmallick 0:3afcd581558d 80 #define AD7606_REG_OPEN_DETECT_ENABLE 0x23
pmallick 0:3afcd581558d 81 #define AD7606_REG_OPEN_DETECTED 0x24
pmallick 0:3afcd581558d 82 #define AD7606_REG_AIN_OV_UV_DIAG_ENABLE 0x25
pmallick 0:3afcd581558d 83 #define AD7606_REG_AIN_OV_DIAG_ERROR 0x26
pmallick 0:3afcd581558d 84 #define AD7606_REG_AIN_UV_DIAG_ERROR 0x27
pmallick 0:3afcd581558d 85 #define AD7606_REG_DIAGNOSTIC_MUX_CH(ch) (0x28 + ((ch) >> 1))
pmallick 0:3afcd581558d 86 #define AD7606_REG_OPEN_DETECT_QUEUE 0x2C
pmallick 0:3afcd581558d 87 #define AD7606_REG_CLK_FS_COUNTER 0x2D
pmallick 0:3afcd581558d 88 #define AD7606_REG_CLK_OS_COUNTER 0x2E
pmallick 0:3afcd581558d 89 #define AD7606_REG_ID 0x2F
pmallick 0:3afcd581558d 90
pmallick 0:3afcd581558d 91 /* AD7606_REG_STATUS */
pmallick 0:3afcd581558d 92 #define AD7606_STATUS_CHANNEL_MSK GENMASK(2,0)
pmallick 0:3afcd581558d 93 #define AD7606_AIN_UV_ERR_MSK BIT(3)
pmallick 0:3afcd581558d 94 #define AD7606_AIN_OV_ERR_MSK BIT(4)
pmallick 0:3afcd581558d 95 #define AD7606_OPEN_DETECTED_MSK BIT(5)
pmallick 0:3afcd581558d 96 #define AD7606_DIGITAL_ERROR_MSK BIT(6)
pmallick 0:3afcd581558d 97 #define AD7606_RESET_DETECT_MSK BIT(7)
pmallick 0:3afcd581558d 98
pmallick 0:3afcd581558d 99 /* AD7606_REG_CONFIG */
pmallick 0:3afcd581558d 100 #define AD7606_CONFIG_OPERATION_MODE_MSK GENMASK(1,0)
pmallick 0:3afcd581558d 101 #define AD7606_CONFIG_DOUT_FORMAT_MSK GENMASK(4,3)
pmallick 0:3afcd581558d 102 #define AD7606_CONFIG_EXT_OS_CLOCK_MSK BIT(5)
pmallick 0:3afcd581558d 103 #define AD7606_CONFIG_STATUS_HEADER_MSK BIT(6)
pmallick 0:3afcd581558d 104
pmallick 0:3afcd581558d 105 /* AD7606_REG_RANGE_CH_X_Y */
pmallick 0:3afcd581558d 106 #define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) % 2)))
pmallick 0:3afcd581558d 107 #define AD7606_RANGE_CH_MODE(ch, mode) \
pmallick 0:3afcd581558d 108 ((GENMASK(3, 0) & mode) << (4 * ((ch) % 2)))
pmallick 0:3afcd581558d 109
pmallick 0:3afcd581558d 110 /* AD7606_REG_OVERSAMPLING */
pmallick 0:3afcd581558d 111 #define AD7606_OS_PAD_MSK GENMASK(7,4)
pmallick 0:3afcd581558d 112 #define AD7606_OS_RATIO_MSK GENMASK(3,0)
pmallick 0:3afcd581558d 113
pmallick 0:3afcd581558d 114 /* AD7606_REG_ID */
pmallick 0:3afcd581558d 115 #define AD7606_ID_DEVICE_ID_MSK GENMASK(7,4)
pmallick 0:3afcd581558d 116 #define AD7606_ID_SILICON_REVISION_MSK GENMASK(3,0)
pmallick 0:3afcd581558d 117
pmallick 0:3afcd581558d 118 /* AD7606_REG_GAIN_CH */
pmallick 0:3afcd581558d 119 #define AD7606_GAIN_MSK GENMASK(5,0)
pmallick 0:3afcd581558d 120
pmallick 0:3afcd581558d 121 /* AD7606_REG_DIGITAL_DIAG_ENABLE */
pmallick 0:3afcd581558d 122 #define AD7606_ROM_CRC_ERR_EN_MSK BIT(0)
pmallick 0:3afcd581558d 123 #define AD7606_MM_CRC_ERR_EN_MSK BIT(1)
pmallick 0:3afcd581558d 124 #define AD7606_INT_CRC_ERR_EN_MSK BIT(2)
pmallick 0:3afcd581558d 125 #define AD7606_SPI_WRITE_ERR_EN_MSK BIT(3)
pmallick 0:3afcd581558d 126 #define AD7606_SPI_READ_ERR_EN_MSK BIT(4)
pmallick 0:3afcd581558d 127 #define AD7606_BUSY_STUCK_HIGH_ERR_EN_MSK BIT(5)
pmallick 0:3afcd581558d 128 #define AD7606_CLK_FS_OS_COUNTER_EN_MSK BIT(6)
pmallick 0:3afcd581558d 129 #define AD7606_INTERFACE_CHECK_EN_MSK BIT(7)
pmallick 0:3afcd581558d 130
pmallick 0:3afcd581558d 131 /* AD7606_REG_DIAGNOSTIC_MUX_CH */
pmallick 0:3afcd581558d 132 #define AD7606_DIAGN_MUX_CH_MSK(ch) (GENMASK(2, 0) << (3 * (ch & 0x1)))
pmallick 0:3afcd581558d 133
pmallick 0:3afcd581558d 134 #define AD7606_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
pmallick 0:3afcd581558d 135 #define AD7606_WR_FLAG_MSK(x) ((x) & 0x3F)
pmallick 0:3afcd581558d 136
pmallick 0:3afcd581558d 137 #define AD7606_MAX_CHANNELS 8
pmallick 0:3afcd581558d 138
pmallick 0:3afcd581558d 139 /**
pmallick 0:3afcd581558d 140 * @enum ad7606_device_id
pmallick 0:3afcd581558d 141 * @brief Device ID definitions
pmallick 0:3afcd581558d 142 */
pmallick 0:3afcd581558d 143 enum ad7606_device_id {
pmallick 0:3afcd581558d 144 /** 4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 145 ID_AD7605_4,
pmallick 0:3afcd581558d 146 /** 4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 147 ID_AD7606_4,
pmallick 0:3afcd581558d 148 /** 6-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 149 ID_AD7606_6,
pmallick 0:3afcd581558d 150 /** 8-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 151 ID_AD7606_8,
pmallick 0:3afcd581558d 152 /** 8-Channel DAS with 16-Bit, 800 kSPS, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 153 ID_AD7606B,
pmallick 0:3afcd581558d 154 /** 8-Channel DAS with 16-Bit, 1 MSPS, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 155 ID_AD7606C_16,
pmallick 0:3afcd581558d 156 /** 8-Channel DAS with 18-Bit, 1 MSPS, Bipolar Input, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 157 ID_AD7606C_18,
pmallick 0:3afcd581558d 158 /** 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 159 ID_AD7608,
pmallick 0:3afcd581558d 160 /** 8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC */
pmallick 0:3afcd581558d 161 ID_AD7609,
pmallick 0:3afcd581558d 162 };
pmallick 0:3afcd581558d 163
pmallick 0:3afcd581558d 164 /**
pmallick 0:3afcd581558d 165 * @enum ad7606_osr
pmallick 0:3afcd581558d 166 * @brief Oversampling ratio
pmallick 0:3afcd581558d 167 */
pmallick 0:3afcd581558d 168 enum ad7606_osr {
pmallick 0:3afcd581558d 169 /** Oversample by 1 */
pmallick 0:3afcd581558d 170 AD7606_OSR_1,
pmallick 0:3afcd581558d 171 /** Oversample by 2 */
pmallick 0:3afcd581558d 172 AD7606_OSR_2,
pmallick 0:3afcd581558d 173 /** Oversample by 4 */
pmallick 0:3afcd581558d 174 AD7606_OSR_4,
pmallick 0:3afcd581558d 175 /** Oversample by 8 */
pmallick 0:3afcd581558d 176 AD7606_OSR_8,
pmallick 0:3afcd581558d 177 /** Oversample by 16 */
pmallick 0:3afcd581558d 178 AD7606_OSR_16,
pmallick 0:3afcd581558d 179 /** Oversample by 32 */
pmallick 0:3afcd581558d 180 AD7606_OSR_32,
pmallick 0:3afcd581558d 181 /** Oversample by 64 */
pmallick 0:3afcd581558d 182 AD7606_OSR_64,
pmallick 0:3afcd581558d 183 /** Oversample by 128, available for chips that have software mode only */
pmallick 0:3afcd581558d 184 AD7606_OSR_128,
pmallick 0:3afcd581558d 185 /** Oversample by 256, available for chips that have software mode only */
pmallick 0:3afcd581558d 186 AD7606_OSR_256
pmallick 0:3afcd581558d 187 };
pmallick 0:3afcd581558d 188
pmallick 0:3afcd581558d 189 /**
pmallick 0:3afcd581558d 190 * @enum ad7606_op_mode
pmallick 0:3afcd581558d 191 * @brief Operation mode
pmallick 0:3afcd581558d 192 */
pmallick 0:3afcd581558d 193 enum ad7606_op_mode {
pmallick 0:3afcd581558d 194 /** Normal operation mode */
pmallick 0:3afcd581558d 195 AD7606_NORMAL,
pmallick 0:3afcd581558d 196 /** Standby mode, all the PGAs, and all the SAR ADCs enter a low power mode */
pmallick 0:3afcd581558d 197 AD7606_STANDBY,
pmallick 0:3afcd581558d 198 /** Autostandby mode, available only in software mode */
pmallick 0:3afcd581558d 199 AD7606_AUTOSTANDBY,
pmallick 0:3afcd581558d 200 /** Shutdown mode, all circuitry is powered down */
pmallick 0:3afcd581558d 201 AD7606_SHUTDOWN
pmallick 0:3afcd581558d 202 };
pmallick 0:3afcd581558d 203
pmallick 0:3afcd581558d 204 /**
pmallick 0:3afcd581558d 205 * @enum ad7606_dout_format
pmallick 0:3afcd581558d 206 * @brief Number of DOUT lines
pmallick 0:3afcd581558d 207 */
pmallick 0:3afcd581558d 208 enum ad7606_dout_format {
pmallick 0:3afcd581558d 209 /** DOUT A line is used */
pmallick 0:3afcd581558d 210 AD7606_1_DOUT,
pmallick 0:3afcd581558d 211 /** DOUT A,B lines are used. */
pmallick 0:3afcd581558d 212 AD7606_2_DOUT,
pmallick 0:3afcd581558d 213 /** DOUT A,B,C,D lines are used. */
pmallick 0:3afcd581558d 214 AD7606_4_DOUT,
pmallick 0:3afcd581558d 215 /** DOUT A,B,C,D,E,F,G,H lines are used. */
pmallick 0:3afcd581558d 216 AD7606_8_DOUT
pmallick 0:3afcd581558d 217 };
pmallick 0:3afcd581558d 218
pmallick 0:3afcd581558d 219 /**
pmallick 0:3afcd581558d 220 * @struct ad7606_config
pmallick 0:3afcd581558d 221 * @brief AD7606_REG_CONFIG configuration parameters
pmallick 0:3afcd581558d 222 */
pmallick 0:3afcd581558d 223 struct ad7606_config {
pmallick 0:3afcd581558d 224 /** Operation mode */
pmallick 0:3afcd581558d 225 enum ad7606_op_mode op_mode;
pmallick 0:3afcd581558d 226 /** Number of DOUT lines */
pmallick 0:3afcd581558d 227 enum ad7606_dout_format dout_format;
pmallick 0:3afcd581558d 228 /** External oversampling clock switch */
pmallick 0:3afcd581558d 229 bool ext_os_clock;
pmallick 0:3afcd581558d 230 /** Status header switch */
pmallick 0:3afcd581558d 231 bool status_header;
pmallick 0:3afcd581558d 232 };
pmallick 0:3afcd581558d 233
pmallick 0:3afcd581558d 234 /**
pmallick 0:3afcd581558d 235 * @struct ad7606_range
pmallick 0:3afcd581558d 236 * @brief Operation range as specified in datasheet (in uV)
pmallick 0:3afcd581558d 237 */
pmallick 0:3afcd581558d 238 struct ad7606_range {
pmallick 0:3afcd581558d 239 /** Minimum range value (may be negative) */
pmallick 0:3afcd581558d 240 int32_t min;
pmallick 0:3afcd581558d 241 /** Maximum range value */
pmallick 0:3afcd581558d 242 int32_t max;
pmallick 0:3afcd581558d 243 /** Whether the range is differential */
pmallick 0:3afcd581558d 244 bool differential;
pmallick 0:3afcd581558d 245 };
pmallick 0:3afcd581558d 246
pmallick 0:3afcd581558d 247 /**
pmallick 0:3afcd581558d 248 * @struct ad7606_digital_diag
pmallick 0:3afcd581558d 249 * @brief Oversampling settings
pmallick 0:3afcd581558d 250 */
pmallick 0:3afcd581558d 251 struct ad7606_oversampling {
pmallick 0:3afcd581558d 252 /** Oversampling padding */
pmallick 0:3afcd581558d 253 uint8_t os_pad:4;
pmallick 0:3afcd581558d 254 /** Oversampling ratio */
pmallick 0:3afcd581558d 255 enum ad7606_osr os_ratio:4;
pmallick 0:3afcd581558d 256 };
pmallick 0:3afcd581558d 257
pmallick 0:3afcd581558d 258 /**
pmallick 0:3afcd581558d 259 * @struct ad7606_digital_diag
pmallick 0:3afcd581558d 260 * @brief Digital diagnostics configuration switches
pmallick 0:3afcd581558d 261 */
pmallick 0:3afcd581558d 262 struct ad7606_digital_diag {
pmallick 0:3afcd581558d 263 /** ROM CRC check switch */
pmallick 0:3afcd581558d 264 bool rom_crc_err_en: 1;
pmallick 0:3afcd581558d 265 /** Mempry map CRC check switch */
pmallick 0:3afcd581558d 266 bool mm_crc_err_en: 1;
pmallick 0:3afcd581558d 267 /** Conversion and register data CRC check switch */
pmallick 0:3afcd581558d 268 bool int_crc_err_en: 1;
pmallick 0:3afcd581558d 269 /** SPI write error switch */
pmallick 0:3afcd581558d 270 bool spi_write_err_en: 1;
pmallick 0:3afcd581558d 271 /** SPI read error switch */
pmallick 0:3afcd581558d 272 bool spi_read_err_en: 1;
pmallick 0:3afcd581558d 273 /** Busy stuck high for more than 4us error switch */
pmallick 0:3afcd581558d 274 bool busy_stuck_high_err_en: 1;
pmallick 0:3afcd581558d 275 /** Frame sync and oversampling clock counter switch */
pmallick 0:3afcd581558d 276 bool clk_fs_os_counter_en: 1;
pmallick 0:3afcd581558d 277 /** Interface check switch */
pmallick 0:3afcd581558d 278 bool interface_check_en: 1;
pmallick 0:3afcd581558d 279 };
pmallick 0:3afcd581558d 280
pmallick 0:3afcd581558d 281 /**
pmallick 0:3afcd581558d 282 * @struct ad7606_dev
pmallick 0:3afcd581558d 283 * @brief Device driver structure
pmallick 0:3afcd581558d 284 */
pmallick 0:3afcd581558d 285 struct ad7606_dev {
pmallick 0:3afcd581558d 286 /** SPI descriptor*/
pmallick 0:3afcd581558d 287 spi_desc *spi_desc;
pmallick 0:3afcd581558d 288 /** RESET GPIO descriptor */
pmallick 0:3afcd581558d 289 struct gpio_desc *gpio_reset;
pmallick 0:3afcd581558d 290 /** CONVST GPIO descriptor */
pmallick 0:3afcd581558d 291 struct gpio_desc *gpio_convst;
pmallick 0:3afcd581558d 292 /** BUSY GPIO descriptor */
pmallick 0:3afcd581558d 293 struct gpio_desc *gpio_busy;
pmallick 0:3afcd581558d 294 /** STBYn GPIO descriptor */
pmallick 0:3afcd581558d 295 struct gpio_desc *gpio_stby_n;
pmallick 0:3afcd581558d 296 /** RANGE GPIO descriptor */
pmallick 0:3afcd581558d 297 struct gpio_desc *gpio_range;
pmallick 0:3afcd581558d 298 /** OS0 GPIO descriptor */
pmallick 0:3afcd581558d 299 struct gpio_desc *gpio_os0;
pmallick 0:3afcd581558d 300 /** OS1 GPIO descriptor */
pmallick 0:3afcd581558d 301 struct gpio_desc *gpio_os1;
pmallick 0:3afcd581558d 302 /** OS2 GPIO descriptor */
pmallick 0:3afcd581558d 303 struct gpio_desc *gpio_os2;
pmallick 0:3afcd581558d 304 /** PARn/SER GPIO descriptor */
pmallick 0:3afcd581558d 305 struct gpio_desc *gpio_par_ser;
pmallick 0:3afcd581558d 306 /** Device ID */
pmallick 0:3afcd581558d 307 enum ad7606_device_id device_id;
pmallick 0:3afcd581558d 308 /** Oversampling settings */
pmallick 0:3afcd581558d 309 struct ad7606_oversampling oversampling;
pmallick 0:3afcd581558d 310 /** Whether the device is running in hardware or software mode */
pmallick 0:3afcd581558d 311 bool sw_mode;
pmallick 0:3afcd581558d 312 /** Whether the device is running in register or ADC reading mode */
pmallick 0:3afcd581558d 313 bool reg_mode;
pmallick 0:3afcd581558d 314 /** Number of DOUT lines supported by the device */
pmallick 0:3afcd581558d 315 enum ad7606_dout_format max_dout_lines;
pmallick 0:3afcd581558d 316 /** Configuration register settings */
pmallick 0:3afcd581558d 317 struct ad7606_config config;
pmallick 0:3afcd581558d 318 /** Digital diagnostics register settings */
pmallick 0:3afcd581558d 319 struct ad7606_digital_diag digital_diag_enable;
pmallick 0:3afcd581558d 320 /** Number of input channels of the device */
pmallick 0:3afcd581558d 321 uint8_t num_channels;
pmallick 0:3afcd581558d 322 /** Channel offset calibration */
pmallick 0:3afcd581558d 323 int8_t offset_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 324 /** Channel phase calibration */
pmallick 0:3afcd581558d 325 uint8_t phase_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 326 /** Channel gain calibration */
pmallick 0:3afcd581558d 327 uint8_t gain_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 328 /** Channel operating range */
pmallick 0:3afcd581558d 329 struct ad7606_range range_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 330 /** Data buffer (used internally by the SPI communication functions) */
pmallick 0:3afcd581558d 331 uint8_t data[28];
pmallick 0:3afcd581558d 332 };
pmallick 0:3afcd581558d 333
pmallick 0:3afcd581558d 334 /**
pmallick 0:3afcd581558d 335 * @struct ad7606_dev
pmallick 0:3afcd581558d 336 * @brief Device driver initialization parameters
pmallick 0:3afcd581558d 337 */
pmallick 0:3afcd581558d 338 struct ad7606_init_param {
pmallick 0:3afcd581558d 339 /** SPI initialization parameters */
pmallick 0:3afcd581558d 340 spi_init_param spi_init;
pmallick 0:3afcd581558d 341 /** RESET GPIO initialization parameters */
pmallick 0:3afcd581558d 342 struct gpio_init_param *gpio_reset;
pmallick 0:3afcd581558d 343 /** CONVST GPIO initialization parameters */
pmallick 0:3afcd581558d 344 struct gpio_init_param *gpio_convst;
pmallick 0:3afcd581558d 345 /** BUSY GPIO initialization parameters */
pmallick 0:3afcd581558d 346 struct gpio_init_param *gpio_busy;
pmallick 0:3afcd581558d 347 /** STBYn GPIO initialization parameters */
pmallick 0:3afcd581558d 348 struct gpio_init_param *gpio_stby_n;
pmallick 0:3afcd581558d 349 /** RANGE GPIO initialization parameters */
pmallick 0:3afcd581558d 350 struct gpio_init_param *gpio_range;
pmallick 0:3afcd581558d 351 /** OS0 GPIO initialization parameters */
pmallick 0:3afcd581558d 352 struct gpio_init_param *gpio_os0;
pmallick 0:3afcd581558d 353 /** OS1 GPIO initialization parameters */
pmallick 0:3afcd581558d 354 struct gpio_init_param *gpio_os1;
pmallick 0:3afcd581558d 355 /** OS2 GPIO initialization parameters */
pmallick 0:3afcd581558d 356 struct gpio_init_param *gpio_os2;
pmallick 0:3afcd581558d 357 /** PARn/SER GPIO initialization parameters */
pmallick 0:3afcd581558d 358 struct gpio_init_param *gpio_par_ser;
pmallick 0:3afcd581558d 359 /** Device ID */
pmallick 0:3afcd581558d 360 enum ad7606_device_id device_id;
pmallick 0:3afcd581558d 361 /** Oversampling settings */
pmallick 0:3afcd581558d 362 struct ad7606_oversampling oversampling;
pmallick 0:3afcd581558d 363 /** Whether the device is running in hardware or software mode */
pmallick 0:3afcd581558d 364 bool sw_mode;
pmallick 0:3afcd581558d 365 /** Configuration register settings */
pmallick 0:3afcd581558d 366 struct ad7606_config config;
pmallick 0:3afcd581558d 367 /** Digital diagnostics register settings */
pmallick 0:3afcd581558d 368 struct ad7606_digital_diag digital_diag_enable;
pmallick 0:3afcd581558d 369 /** Channel offset calibration */
pmallick 0:3afcd581558d 370 int8_t offset_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 371 /** Channel phase calibration */
pmallick 0:3afcd581558d 372 uint8_t phase_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 373 /** Channel gain calibration */
pmallick 0:3afcd581558d 374 uint8_t gain_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 375 /** Channel operating range */
pmallick 0:3afcd581558d 376 struct ad7606_range range_ch[AD7606_MAX_CHANNELS];
pmallick 0:3afcd581558d 377 };
pmallick 0:3afcd581558d 378
pmallick 0:3afcd581558d 379 int32_t ad7606_spi_reg_read(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 380 uint8_t reg_addr,
pmallick 0:3afcd581558d 381 uint8_t *reg_data);
pmallick 0:3afcd581558d 382 int32_t ad7606_spi_reg_write(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 383 uint8_t reg_addr,
pmallick 0:3afcd581558d 384 uint8_t reg_data);
pmallick 0:3afcd581558d 385 int32_t ad7606_spi_write_mask(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 386 uint32_t addr,
pmallick 0:3afcd581558d 387 uint32_t mask,
pmallick 0:3afcd581558d 388 uint32_t val);
pmallick 0:3afcd581558d 389 int32_t ad7606_spi_data_read(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 390 uint32_t *data);
pmallick 0:3afcd581558d 391 int32_t ad7606_read(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 392 uint32_t *data);
pmallick 0:3afcd581558d 393 int32_t ad7606_convst(struct ad7606_dev *dev);
pmallick 0:3afcd581558d 394 int32_t ad7606_reset(struct ad7606_dev *dev);
pmallick 0:3afcd581558d 395 int32_t ad7606_set_oversampling(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 396 struct ad7606_oversampling oversampling);
pmallick 0:3afcd581558d 397 int32_t ad7606_set_ch_range(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:3afcd581558d 398 struct ad7606_range range);
pmallick 0:3afcd581558d 399 int32_t ad7606_set_ch_offset(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:3afcd581558d 400 int8_t offset);
pmallick 0:3afcd581558d 401 int32_t ad7606_set_ch_phase(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:3afcd581558d 402 uint8_t phase);
pmallick 0:3afcd581558d 403 int32_t ad7606_set_ch_gain(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:3afcd581558d 404 uint8_t gain);
pmallick 0:3afcd581558d 405 int32_t ad7606_set_config(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 406 struct ad7606_config config);
pmallick 0:3afcd581558d 407 int32_t ad7606_set_digital_diag(struct ad7606_dev *dev,
pmallick 0:3afcd581558d 408 struct ad7606_digital_diag diag);
pmallick 0:3afcd581558d 409 int32_t ad7606_init(struct ad7606_dev **device,
pmallick 0:3afcd581558d 410 struct ad7606_init_param *init_param);
pmallick 0:3afcd581558d 411 int32_t ad7606_remove(struct ad7606_dev *dev);
pmallick 0:3afcd581558d 412 #endif /* AD7606_H_ */