Pratyush Mallick / Mbed OS testing

this is testing

app/noos_mbed/drivers/adc-dac/ad5592r/ad5592r-base.h@0:3afcd581558d, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 18:54:16 2021 +0530
Revision:
0:3afcd581558d
this is testing

Who changed what in which revision?

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pmallick 0:3afcd581558d 1 /***************************************************************************//**
pmallick 0:3afcd581558d 2 * @file ad5592r-base.h
pmallick 0:3afcd581558d 3 * @brief Header file of AD5592R Base Driver.
pmallick 0:3afcd581558d 4 * @author Mircea Caprioru (mircea.caprioru@analog.com)
pmallick 0:3afcd581558d 5 ********************************************************************************
pmallick 0:3afcd581558d 6 * Copyright 2018, 2020(c) Analog Devices, Inc.
pmallick 0:3afcd581558d 7 *
pmallick 0:3afcd581558d 8 * All rights reserved.
pmallick 0:3afcd581558d 9 *
pmallick 0:3afcd581558d 10 * Redistribution and use in source and binary forms, with or without
pmallick 0:3afcd581558d 11 * modification, are permitted provided that the following conditions are met:
pmallick 0:3afcd581558d 12 * - Redistributions of source code must retain the above copyright
pmallick 0:3afcd581558d 13 * notice, this list of conditions and the following disclaimer.
pmallick 0:3afcd581558d 14 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:3afcd581558d 15 * notice, this list of conditions and the following disclaimer in
pmallick 0:3afcd581558d 16 * the documentation and/or other materials provided with the
pmallick 0:3afcd581558d 17 * distribution.
pmallick 0:3afcd581558d 18 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:3afcd581558d 19 * contributors may be used to endorse or promote products derived
pmallick 0:3afcd581558d 20 * from this software without specific prior written permission.
pmallick 0:3afcd581558d 21 * - The use of this software may or may not infringe the patent rights
pmallick 0:3afcd581558d 22 * of one or more patent holders. This license does not release you
pmallick 0:3afcd581558d 23 * from the requirement that you obtain separate licenses from these
pmallick 0:3afcd581558d 24 * patent holders to use this software.
pmallick 0:3afcd581558d 25 * - Use of the software either in source or binary form, must be run
pmallick 0:3afcd581558d 26 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:3afcd581558d 27 *
pmallick 0:3afcd581558d 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:3afcd581558d 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:3afcd581558d 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:3afcd581558d 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:3afcd581558d 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:3afcd581558d 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 0:3afcd581558d 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 0:3afcd581558d 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 0:3afcd581558d 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 0:3afcd581558d 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:3afcd581558d 38 *******************************************************************************/
pmallick 0:3afcd581558d 39 #ifndef AD5592R_BASE_H_
pmallick 0:3afcd581558d 40 #define AD5592R_BASE_H_
pmallick 0:3afcd581558d 41
pmallick 0:3afcd581558d 42 #include "stdint.h"
pmallick 0:3afcd581558d 43 #include "platform_drivers.h"
pmallick 0:3afcd581558d 44
pmallick 0:3afcd581558d 45 #include <stdbool.h>
pmallick 0:3afcd581558d 46
pmallick 0:3afcd581558d 47 #define CH_MODE_UNUSED 0
pmallick 0:3afcd581558d 48 #define CH_MODE_ADC 1
pmallick 0:3afcd581558d 49 #define CH_MODE_DAC 2
pmallick 0:3afcd581558d 50 #define CH_MODE_DAC_AND_ADC 3
pmallick 0:3afcd581558d 51 #define CH_MODE_GPI 4
pmallick 0:3afcd581558d 52 #define CH_MODE_GPO 5
pmallick 0:3afcd581558d 53
pmallick 0:3afcd581558d 54 #define CH_OFFSTATE_PULLDOWN 0
pmallick 0:3afcd581558d 55 #define CH_OFFSTATE_OUT_LOW 1
pmallick 0:3afcd581558d 56 #define CH_OFFSTATE_OUT_HIGH 2
pmallick 0:3afcd581558d 57 #define CH_OFFSTATE_OUT_TRISTATE 3
pmallick 0:3afcd581558d 58
pmallick 0:3afcd581558d 59 enum ad5592r_registers {
pmallick 0:3afcd581558d 60 AD5592R_REG_NOOP = 0x0,
pmallick 0:3afcd581558d 61 AD5592R_REG_DAC_READBACK = 0x1,
pmallick 0:3afcd581558d 62 AD5592R_REG_ADC_SEQ = 0x2,
pmallick 0:3afcd581558d 63 AD5592R_REG_CTRL = 0x3,
pmallick 0:3afcd581558d 64 AD5592R_REG_ADC_EN = 0x4,
pmallick 0:3afcd581558d 65 AD5592R_REG_DAC_EN = 0x5,
pmallick 0:3afcd581558d 66 AD5592R_REG_PULLDOWN = 0x6,
pmallick 0:3afcd581558d 67 AD5592R_REG_LDAC = 0x7,
pmallick 0:3afcd581558d 68 AD5592R_REG_GPIO_OUT_EN = 0x8,
pmallick 0:3afcd581558d 69 AD5592R_REG_GPIO_SET = 0x9,
pmallick 0:3afcd581558d 70 AD5592R_REG_GPIO_IN_EN = 0xA,
pmallick 0:3afcd581558d 71 AD5592R_REG_PD = 0xB,
pmallick 0:3afcd581558d 72 AD5592R_REG_OPEN_DRAIN = 0xC,
pmallick 0:3afcd581558d 73 AD5592R_REG_TRISTATE = 0xD,
pmallick 0:3afcd581558d 74 AD5592R_REG_RESET = 0xF,
pmallick 0:3afcd581558d 75 };
pmallick 0:3afcd581558d 76
pmallick 0:3afcd581558d 77 #define AD5592R_REG_PD_PD_ALL BIT(10)
pmallick 0:3afcd581558d 78 #define AD5592R_REG_PD_EN_REF BIT(9)
pmallick 0:3afcd581558d 79
pmallick 0:3afcd581558d 80 #define AD5592R_REG_CTRL_ADC_PC_BUFF BIT(9)
pmallick 0:3afcd581558d 81 #define AD5592R_REG_CTRL_ADC_BUFF_EN BIT(8)
pmallick 0:3afcd581558d 82 #define AD5592R_REG_CTRL_CONFIG_LOCK BIT(7)
pmallick 0:3afcd581558d 83 #define AD5592R_REG_CTRL_W_ALL_DACS BIT(6)
pmallick 0:3afcd581558d 84 #define AD5592R_REG_CTRL_ADC_RANGE BIT(5)
pmallick 0:3afcd581558d 85 #define AD5592R_REG_CTRL_DAC_RANGE BIT(4)
pmallick 0:3afcd581558d 86
pmallick 0:3afcd581558d 87 #define AD5592R_REG_ADC_SEQ_REP BIT(9)
pmallick 0:3afcd581558d 88 #define AD5592R_REG_ADC_SEQ_TEMP_READBACK BIT(8)
pmallick 0:3afcd581558d 89 #define AD5592R_REG_ADC_SEQ_CODE_MSK(x) ((x) & 0x0FFF)
pmallick 0:3afcd581558d 90
pmallick 0:3afcd581558d 91 #define AD5592R_REG_GPIO_OUT_EN_ADC_NOT_BUSY BIT(8)
pmallick 0:3afcd581558d 92
pmallick 0:3afcd581558d 93 #define AD5592R_REG_LDAC_IMMEDIATE_OUT 0x00
pmallick 0:3afcd581558d 94 #define AD5592R_REG_LDAC_INPUT_REG_ONLY 0x01
pmallick 0:3afcd581558d 95 #define AD5592R_REG_LDAC_INPUT_REG_OUT 0x02
pmallick 0:3afcd581558d 96
pmallick 0:3afcd581558d 97 #define INTERNAL_VREF_VOLTAGE 2.5
pmallick 0:3afcd581558d 98
pmallick 0:3afcd581558d 99 struct ad5592r_dev;
pmallick 0:3afcd581558d 100
pmallick 0:3afcd581558d 101 struct ad5592r_rw_ops {
pmallick 0:3afcd581558d 102 int32_t (*write_dac)(struct ad5592r_dev *dev, uint8_t chan,
pmallick 0:3afcd581558d 103 uint16_t value);
pmallick 0:3afcd581558d 104 int32_t (*read_adc)(struct ad5592r_dev *dev, uint8_t chan,
pmallick 0:3afcd581558d 105 uint16_t *value);
pmallick 0:3afcd581558d 106 int32_t(*multi_read_adc)(struct ad5592r_dev *dev,
pmallick 0:3afcd581558d 107 uint16_t chans, uint16_t *value);
pmallick 0:3afcd581558d 108 int32_t (*reg_write)(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:3afcd581558d 109 uint16_t value);
pmallick 0:3afcd581558d 110 int32_t (*reg_read)(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:3afcd581558d 111 uint16_t *value);
pmallick 0:3afcd581558d 112 int32_t (*gpio_read)(struct ad5592r_dev *dev, uint8_t *value);
pmallick 0:3afcd581558d 113 };
pmallick 0:3afcd581558d 114
pmallick 0:3afcd581558d 115 struct ad5592r_init_param {
pmallick 0:3afcd581558d 116 bool int_ref;
pmallick 0:3afcd581558d 117 };
pmallick 0:3afcd581558d 118
pmallick 0:3afcd581558d 119 struct ad5592r_dev {
pmallick 0:3afcd581558d 120 const struct ad5592r_rw_ops *ops;
pmallick 0:3afcd581558d 121 i2c_desc *i2c;
pmallick 0:3afcd581558d 122 spi_desc *spi;
pmallick 0:3afcd581558d 123 uint16_t spi_msg;
pmallick 0:3afcd581558d 124 uint8_t num_channels;
pmallick 0:3afcd581558d 125 uint16_t cached_dac[8];
pmallick 0:3afcd581558d 126 uint16_t cached_gp_ctrl;
pmallick 0:3afcd581558d 127 uint8_t channel_modes[8];
pmallick 0:3afcd581558d 128 uint8_t channel_offstate[8];
pmallick 0:3afcd581558d 129 uint8_t gpio_out;
pmallick 0:3afcd581558d 130 uint8_t gpio_in;
pmallick 0:3afcd581558d 131 uint8_t gpio_val;
pmallick 0:3afcd581558d 132 uint8_t ldac_mode;
pmallick 0:3afcd581558d 133 };
pmallick 0:3afcd581558d 134
pmallick 0:3afcd581558d 135 int32_t ad5592r_base_reg_write(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:3afcd581558d 136 uint16_t value);
pmallick 0:3afcd581558d 137 int32_t ad5592r_base_reg_read(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:3afcd581558d 138 uint16_t *value);
pmallick 0:3afcd581558d 139 int32_t ad5592r_gpio_get(struct ad5592r_dev *dev, uint8_t offset);
pmallick 0:3afcd581558d 140 int32_t ad5592r_gpio_set(struct ad5592r_dev *dev, uint8_t offset,
pmallick 0:3afcd581558d 141 int32_t value);
pmallick 0:3afcd581558d 142 int32_t ad5592r_gpio_direction_input(struct ad5592r_dev *dev, uint8_t offset);
pmallick 0:3afcd581558d 143 int32_t ad5592r_gpio_direction_output(struct ad5592r_dev *dev,
pmallick 0:3afcd581558d 144 uint8_t offset, int32_t value);
pmallick 0:3afcd581558d 145 int32_t ad5592r_software_reset(struct ad5592r_dev *dev);
pmallick 0:3afcd581558d 146 int32_t ad5592r_set_channel_modes(struct ad5592r_dev *dev);
pmallick 0:3afcd581558d 147 int32_t ad5592r_reset_channel_modes(struct ad5592r_dev *dev);
pmallick 0:3afcd581558d 148
pmallick 0:3afcd581558d 149 #endif /* AD5592R_BASE_H_ */