Pratyush Mallick / Mbed OS nano_dac

this is testing

noos_mbed/drivers/adc/ad7606/ad7606.c@0:e8a1ba50c46b, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 19:12:57 2021 +0530
Revision:
0:e8a1ba50c46b
this is testing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 0:e8a1ba50c46b 1 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 2 * @file ad7606.c
pmallick 0:e8a1ba50c46b 3 * @brief Implementation of ad7606 Driver.
pmallick 0:e8a1ba50c46b 4 * @author Stefan Popa (stefan.popa@analog.com)
pmallick 0:e8a1ba50c46b 5 * @author Darius Berghe (darius.berghe@analog.com)
pmallick 0:e8a1ba50c46b 6 ********************************************************************************
pmallick 0:e8a1ba50c46b 7 * Copyright 2020(c) Analog Devices, Inc.
pmallick 0:e8a1ba50c46b 8 *
pmallick 0:e8a1ba50c46b 9 * All rights reserved.
pmallick 0:e8a1ba50c46b 10 *
pmallick 0:e8a1ba50c46b 11 * Redistribution and use in source and binary forms, with or without
pmallick 0:e8a1ba50c46b 12 * modification, are permitted provided that the following conditions are met:
pmallick 0:e8a1ba50c46b 13 * - Redistributions of source code must retain the above copyright
pmallick 0:e8a1ba50c46b 14 * notice, this list of conditions and the following disclaimer.
pmallick 0:e8a1ba50c46b 15 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:e8a1ba50c46b 16 * notice, this list of conditions and the following disclaimer in
pmallick 0:e8a1ba50c46b 17 * the documentation and/or other materials provided with the
pmallick 0:e8a1ba50c46b 18 * distribution.
pmallick 0:e8a1ba50c46b 19 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:e8a1ba50c46b 20 * contributors may be used to endorse or promote products derived
pmallick 0:e8a1ba50c46b 21 * from this software without specific prior written permission.
pmallick 0:e8a1ba50c46b 22 * - The use of this software may or may not infringe the patent rights
pmallick 0:e8a1ba50c46b 23 * of one or more patent holders. This license does not release you
pmallick 0:e8a1ba50c46b 24 * from the requirement that you obtain separate licenses from these
pmallick 0:e8a1ba50c46b 25 * patent holders to use this software.
pmallick 0:e8a1ba50c46b 26 * - Use of the software either in source or binary form, must be run
pmallick 0:e8a1ba50c46b 27 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:e8a1ba50c46b 28 *
pmallick 0:e8a1ba50c46b 29 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:e8a1ba50c46b 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:e8a1ba50c46b 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:e8a1ba50c46b 32 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:e8a1ba50c46b 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:e8a1ba50c46b 34 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 0:e8a1ba50c46b 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 0:e8a1ba50c46b 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 0:e8a1ba50c46b 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 0:e8a1ba50c46b 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:e8a1ba50c46b 39 *******************************************************************************/
pmallick 0:e8a1ba50c46b 40
pmallick 0:e8a1ba50c46b 41 /******************************************************************************/
pmallick 0:e8a1ba50c46b 42 /***************************** Include Files **********************************/
pmallick 0:e8a1ba50c46b 43 /******************************************************************************/
pmallick 0:e8a1ba50c46b 44 #include <stdio.h>
pmallick 0:e8a1ba50c46b 45 #include <stdlib.h>
pmallick 0:e8a1ba50c46b 46 #include <stdbool.h>
pmallick 0:e8a1ba50c46b 47 #include <string.h>
pmallick 0:e8a1ba50c46b 48 #include <errno.h>
pmallick 0:e8a1ba50c46b 49 #include "ad7606.h"
pmallick 0:e8a1ba50c46b 50 #include "error.h"
pmallick 0:e8a1ba50c46b 51 #include "util.h"
pmallick 0:e8a1ba50c46b 52 #include "crc.h"
pmallick 0:e8a1ba50c46b 53
pmallick 0:e8a1ba50c46b 54 struct ad7606_chip_info {
pmallick 0:e8a1ba50c46b 55 uint8_t num_channels;
pmallick 0:e8a1ba50c46b 56 uint8_t bits;
pmallick 0:e8a1ba50c46b 57 uint8_t max_dout_lines;
pmallick 0:e8a1ba50c46b 58 bool has_oversampling;
pmallick 0:e8a1ba50c46b 59 bool has_registers;
pmallick 0:e8a1ba50c46b 60 uint8_t device_id;
pmallick 0:e8a1ba50c46b 61 const struct ad7606_range *hw_range_table;
pmallick 0:e8a1ba50c46b 62 uint32_t hw_range_table_sz;
pmallick 0:e8a1ba50c46b 63 const struct ad7606_range *sw_range_table;
pmallick 0:e8a1ba50c46b 64 uint32_t sw_range_table_sz;
pmallick 0:e8a1ba50c46b 65 };
pmallick 0:e8a1ba50c46b 66
pmallick 0:e8a1ba50c46b 67 DECLARE_CRC8_TABLE(ad7606_crc8);
pmallick 0:e8a1ba50c46b 68 DECLARE_CRC16_TABLE(ad7606_crc16);
pmallick 0:e8a1ba50c46b 69
pmallick 0:e8a1ba50c46b 70 static const struct ad7606_range ad7606_range_table[] = {
pmallick 0:e8a1ba50c46b 71 {-5000, 5000, false}, /* RANGE pin LOW */
pmallick 0:e8a1ba50c46b 72 {-10000, 10000, false}, /* RANGE pin HIGH */
pmallick 0:e8a1ba50c46b 73 };
pmallick 0:e8a1ba50c46b 74
pmallick 0:e8a1ba50c46b 75 static const struct ad7606_range ad7609_range_table[] = {
pmallick 0:e8a1ba50c46b 76 {-10000, 10000, true}, /* RANGE pin LOW */
pmallick 0:e8a1ba50c46b 77 {-20000, 20000, true}, /* RANGE pin HIGH */
pmallick 0:e8a1ba50c46b 78 };
pmallick 0:e8a1ba50c46b 79
pmallick 0:e8a1ba50c46b 80 static const struct ad7606_range ad7606b_range_table[] = {
pmallick 0:e8a1ba50c46b 81 {-2500, 2500, false}, /* 0000 */
pmallick 0:e8a1ba50c46b 82 {-5000, 5000, false}, /* 0001 */
pmallick 0:e8a1ba50c46b 83 {-10000, 10000, false}, /* 0010 */
pmallick 0:e8a1ba50c46b 84 {-10000, 10000, false}, /* 0011 */
pmallick 0:e8a1ba50c46b 85 {-10000, 10000, false}, /* 0100 */
pmallick 0:e8a1ba50c46b 86 {-10000, 10000, false}, /* 0101 */
pmallick 0:e8a1ba50c46b 87 {-10000, 10000, false}, /* 0110 */
pmallick 0:e8a1ba50c46b 88 {-10000, 10000, false}, /* 0111 */
pmallick 0:e8a1ba50c46b 89 {-10000, 10000, false}, /* 1000 */
pmallick 0:e8a1ba50c46b 90 {-10000, 10000, false}, /* 1001 */
pmallick 0:e8a1ba50c46b 91 {-10000, 10000, false}, /* 1010 */
pmallick 0:e8a1ba50c46b 92 {-10000, 10000, false}, /* 1011 */
pmallick 0:e8a1ba50c46b 93 };
pmallick 0:e8a1ba50c46b 94
pmallick 0:e8a1ba50c46b 95 static const struct ad7606_range ad7606c_range_table[] = {
pmallick 0:e8a1ba50c46b 96 {-2500, 2500, false}, /* 0000 */
pmallick 0:e8a1ba50c46b 97 {-5000, 5000, false}, /* 0001 */
pmallick 0:e8a1ba50c46b 98 {-6250, 6250, false}, /* 0010 */
pmallick 0:e8a1ba50c46b 99 {-10000, 10000, false}, /* 0011 */
pmallick 0:e8a1ba50c46b 100 {-12500, 12500, false}, /* 0100 */
pmallick 0:e8a1ba50c46b 101 {0, 5000, false}, /* 0101 */
pmallick 0:e8a1ba50c46b 102 {0, 10000, false}, /* 0110 */
pmallick 0:e8a1ba50c46b 103 {0, 12500, false}, /* 0111 */
pmallick 0:e8a1ba50c46b 104 {-5000, 5000, true}, /* 1000 */
pmallick 0:e8a1ba50c46b 105 {-10000, 10000, true}, /* 1001 */
pmallick 0:e8a1ba50c46b 106 {-12500, 12500, true}, /* 1010 */
pmallick 0:e8a1ba50c46b 107 {-20000, 20000, true}, /* 1011 */
pmallick 0:e8a1ba50c46b 108 {-20000, 20000, true}, /* 1100 */
pmallick 0:e8a1ba50c46b 109 {-20000, 20000, true}, /* 1101 */
pmallick 0:e8a1ba50c46b 110 {-20000, 20000, true}, /* 1110 */
pmallick 0:e8a1ba50c46b 111 {-20000, 20000, true}, /* 1111 */
pmallick 0:e8a1ba50c46b 112 };
pmallick 0:e8a1ba50c46b 113
pmallick 0:e8a1ba50c46b 114 static const struct ad7606_chip_info ad7606_chip_info_tbl[] = {
pmallick 0:e8a1ba50c46b 115 [ID_AD7605_4] = {
pmallick 0:e8a1ba50c46b 116 .num_channels = 4,
pmallick 0:e8a1ba50c46b 117 .bits = 16,
pmallick 0:e8a1ba50c46b 118 .max_dout_lines = AD7606_2_DOUT,
pmallick 0:e8a1ba50c46b 119 .has_oversampling = false,
pmallick 0:e8a1ba50c46b 120 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 121 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 122 },
pmallick 0:e8a1ba50c46b 123 [ID_AD7606_4] = {
pmallick 0:e8a1ba50c46b 124 .num_channels = 4,
pmallick 0:e8a1ba50c46b 125 .bits = 16,
pmallick 0:e8a1ba50c46b 126 .max_dout_lines = AD7606_2_DOUT,
pmallick 0:e8a1ba50c46b 127 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 128 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 129 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 130 },
pmallick 0:e8a1ba50c46b 131 [ID_AD7606_6] = {
pmallick 0:e8a1ba50c46b 132 .num_channels = 6,
pmallick 0:e8a1ba50c46b 133 .bits = 16,
pmallick 0:e8a1ba50c46b 134 .max_dout_lines = AD7606_2_DOUT,
pmallick 0:e8a1ba50c46b 135 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 136 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 137 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 138 },
pmallick 0:e8a1ba50c46b 139 [ID_AD7606_8] = {
pmallick 0:e8a1ba50c46b 140 .num_channels = 8,
pmallick 0:e8a1ba50c46b 141 .bits = 16,
pmallick 0:e8a1ba50c46b 142 .max_dout_lines = AD7606_2_DOUT,
pmallick 0:e8a1ba50c46b 143 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 144 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 145 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 146 },
pmallick 0:e8a1ba50c46b 147 [ID_AD7606B] = {
pmallick 0:e8a1ba50c46b 148 .num_channels = 8,
pmallick 0:e8a1ba50c46b 149 .bits = 16,
pmallick 0:e8a1ba50c46b 150 .max_dout_lines = AD7606_4_DOUT,
pmallick 0:e8a1ba50c46b 151 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 152 .has_registers = true,
pmallick 0:e8a1ba50c46b 153 .device_id = 0x1,
pmallick 0:e8a1ba50c46b 154 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 155 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 156 .sw_range_table = ad7606b_range_table,
pmallick 0:e8a1ba50c46b 157 .sw_range_table_sz = ARRAY_SIZE(ad7606b_range_table),
pmallick 0:e8a1ba50c46b 158 },
pmallick 0:e8a1ba50c46b 159 [ID_AD7606C_16] = {
pmallick 0:e8a1ba50c46b 160 .num_channels = 8,
pmallick 0:e8a1ba50c46b 161 .bits = 16,
pmallick 0:e8a1ba50c46b 162 .max_dout_lines = AD7606_8_DOUT,
pmallick 0:e8a1ba50c46b 163 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 164 .has_registers = true,
pmallick 0:e8a1ba50c46b 165 .device_id = 0x3,
pmallick 0:e8a1ba50c46b 166 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 167 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 168 .sw_range_table = ad7606c_range_table,
pmallick 0:e8a1ba50c46b 169 .sw_range_table_sz = ARRAY_SIZE(ad7606c_range_table),
pmallick 0:e8a1ba50c46b 170 },
pmallick 0:e8a1ba50c46b 171 [ID_AD7606C_18] = {
pmallick 0:e8a1ba50c46b 172 .num_channels = 8,
pmallick 0:e8a1ba50c46b 173 .bits = 18,
pmallick 0:e8a1ba50c46b 174 .max_dout_lines = AD7606_8_DOUT,
pmallick 0:e8a1ba50c46b 175 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 176 .has_registers = true,
pmallick 0:e8a1ba50c46b 177 .device_id = 0x3,
pmallick 0:e8a1ba50c46b 178 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 179 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 180 .sw_range_table = ad7606c_range_table,
pmallick 0:e8a1ba50c46b 181 .sw_range_table_sz = ARRAY_SIZE(ad7606c_range_table),
pmallick 0:e8a1ba50c46b 182 },
pmallick 0:e8a1ba50c46b 183 [ID_AD7608] = {
pmallick 0:e8a1ba50c46b 184 .num_channels = 8,
pmallick 0:e8a1ba50c46b 185 .bits = 18,
pmallick 0:e8a1ba50c46b 186 .max_dout_lines = AD7606_2_DOUT,
pmallick 0:e8a1ba50c46b 187 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 188 .hw_range_table = ad7606_range_table,
pmallick 0:e8a1ba50c46b 189 .hw_range_table_sz = ARRAY_SIZE(ad7606_range_table),
pmallick 0:e8a1ba50c46b 190 },
pmallick 0:e8a1ba50c46b 191 [ID_AD7609] = {
pmallick 0:e8a1ba50c46b 192 .num_channels = 8,
pmallick 0:e8a1ba50c46b 193 .bits = 18,
pmallick 0:e8a1ba50c46b 194 .max_dout_lines = AD7606_2_DOUT,
pmallick 0:e8a1ba50c46b 195 .has_oversampling = true,
pmallick 0:e8a1ba50c46b 196 .hw_range_table = ad7609_range_table,
pmallick 0:e8a1ba50c46b 197 .hw_range_table_sz = ARRAY_SIZE(ad7609_range_table),
pmallick 0:e8a1ba50c46b 198 },
pmallick 0:e8a1ba50c46b 199 };
pmallick 0:e8a1ba50c46b 200
pmallick 0:e8a1ba50c46b 201 static const uint16_t tconv_max[] = {
pmallick 0:e8a1ba50c46b 202 1, /* AD7606_OSR_1 */
pmallick 0:e8a1ba50c46b 203 3, /* AD7606_OSR_2 */
pmallick 0:e8a1ba50c46b 204 5, /* AD7606_OSR_4 */
pmallick 0:e8a1ba50c46b 205 10, /* AD7606_OSR_8 */
pmallick 0:e8a1ba50c46b 206 20, /* AD7606_OSR_16 */
pmallick 0:e8a1ba50c46b 207 41, /* AD7606_OSR_32 */
pmallick 0:e8a1ba50c46b 208 81, /* AD7606_OSR_64 */
pmallick 0:e8a1ba50c46b 209 162, /* AD7606_OSR_128 */
pmallick 0:e8a1ba50c46b 210 324 /* AD7606_OSR_256 */
pmallick 0:e8a1ba50c46b 211 };
pmallick 0:e8a1ba50c46b 212
pmallick 0:e8a1ba50c46b 213
pmallick 0:e8a1ba50c46b 214 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 215 * @brief Read a device register via SPI.
pmallick 0:e8a1ba50c46b 216 *
pmallick 0:e8a1ba50c46b 217 * This function performs CRC8 computation and checking if enabled in the device.
pmallick 0:e8a1ba50c46b 218 *
pmallick 0:e8a1ba50c46b 219 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 220 * @param reg_addr - Register address in device memory.
pmallick 0:e8a1ba50c46b 221 * @param reg_data - Pointer to the location where to store the register value.
pmallick 0:e8a1ba50c46b 222 *
pmallick 0:e8a1ba50c46b 223 * @return ret - return code.
pmallick 0:e8a1ba50c46b 224 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 225 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 226 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 227 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 228 *******************************************************************************/
pmallick 0:e8a1ba50c46b 229 int32_t ad7606_spi_reg_read(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 230 uint8_t reg_addr,
pmallick 0:e8a1ba50c46b 231 uint8_t *reg_data)
pmallick 0:e8a1ba50c46b 232 {
pmallick 0:e8a1ba50c46b 233 uint8_t buf[3];
pmallick 0:e8a1ba50c46b 234 uint8_t crc;
pmallick 0:e8a1ba50c46b 235 uint32_t sz = 2;
pmallick 0:e8a1ba50c46b 236 int32_t ret;
pmallick 0:e8a1ba50c46b 237
pmallick 0:e8a1ba50c46b 238 if (!dev->sw_mode)
pmallick 0:e8a1ba50c46b 239 return -ENOTSUP;
pmallick 0:e8a1ba50c46b 240
pmallick 0:e8a1ba50c46b 241 buf[0] = AD7606_RD_FLAG_MSK(reg_addr);
pmallick 0:e8a1ba50c46b 242 buf[1] = 0x00;
pmallick 0:e8a1ba50c46b 243 if (dev->digital_diag_enable.int_crc_err_en) {
pmallick 0:e8a1ba50c46b 244 crc = crc8(ad7606_crc8, buf, 2, 0);
pmallick 0:e8a1ba50c46b 245 buf[2] = crc;
pmallick 0:e8a1ba50c46b 246 sz += 1;
pmallick 0:e8a1ba50c46b 247 }
pmallick 0:e8a1ba50c46b 248 ret = spi_write_and_read(dev->spi_desc, buf, sz);
pmallick 0:e8a1ba50c46b 249 if (ret < 0)
pmallick 0:e8a1ba50c46b 250 return ret;
pmallick 0:e8a1ba50c46b 251
pmallick 0:e8a1ba50c46b 252 dev->reg_mode = true;
pmallick 0:e8a1ba50c46b 253
pmallick 0:e8a1ba50c46b 254 buf[0] = AD7606_RD_FLAG_MSK(reg_addr);
pmallick 0:e8a1ba50c46b 255 buf[1] = 0x00;
pmallick 0:e8a1ba50c46b 256 if (dev->digital_diag_enable.int_crc_err_en) {
pmallick 0:e8a1ba50c46b 257 crc = crc8(ad7606_crc8, buf, 2, 0);
pmallick 0:e8a1ba50c46b 258 buf[2] = crc;
pmallick 0:e8a1ba50c46b 259 }
pmallick 0:e8a1ba50c46b 260 ret = spi_write_and_read(dev->spi_desc, buf, sz);
pmallick 0:e8a1ba50c46b 261 if (ret < 0)
pmallick 0:e8a1ba50c46b 262 return ret;
pmallick 0:e8a1ba50c46b 263
pmallick 0:e8a1ba50c46b 264 if (dev->digital_diag_enable.int_crc_err_en) {
pmallick 0:e8a1ba50c46b 265 crc = crc8(ad7606_crc8, buf, 2, 0);
pmallick 0:e8a1ba50c46b 266 if (crc != buf[2])
pmallick 0:e8a1ba50c46b 267 return -EBADMSG;
pmallick 0:e8a1ba50c46b 268 }
pmallick 0:e8a1ba50c46b 269
pmallick 0:e8a1ba50c46b 270 if (reg_data)
pmallick 0:e8a1ba50c46b 271 *reg_data = buf[1];
pmallick 0:e8a1ba50c46b 272
pmallick 0:e8a1ba50c46b 273 return ret;
pmallick 0:e8a1ba50c46b 274 }
pmallick 0:e8a1ba50c46b 275
pmallick 0:e8a1ba50c46b 276 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 277 * @brief Write a device register via SPI.
pmallick 0:e8a1ba50c46b 278 *
pmallick 0:e8a1ba50c46b 279 * This function performs CRC8 computation and checking if enabled in the device.
pmallick 0:e8a1ba50c46b 280 *
pmallick 0:e8a1ba50c46b 281 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 282 * @param reg_addr - Register address in device memory.
pmallick 0:e8a1ba50c46b 283 * @param reg_data - Value to write to register.
pmallick 0:e8a1ba50c46b 284 *
pmallick 0:e8a1ba50c46b 285 * @return ret - return code.
pmallick 0:e8a1ba50c46b 286 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 287 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 288 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 289 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 290 *******************************************************************************/
pmallick 0:e8a1ba50c46b 291 int32_t ad7606_spi_reg_write(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 292 uint8_t reg_addr,
pmallick 0:e8a1ba50c46b 293 uint8_t reg_data)
pmallick 0:e8a1ba50c46b 294 {
pmallick 0:e8a1ba50c46b 295 uint8_t buf[3];
pmallick 0:e8a1ba50c46b 296 int32_t ret;
pmallick 0:e8a1ba50c46b 297 uint8_t crc;
pmallick 0:e8a1ba50c46b 298 uint32_t sz = 2;
pmallick 0:e8a1ba50c46b 299
pmallick 0:e8a1ba50c46b 300 if (!dev->sw_mode)
pmallick 0:e8a1ba50c46b 301 return -ENOTSUP;
pmallick 0:e8a1ba50c46b 302
pmallick 0:e8a1ba50c46b 303 /* Dummy read to place the chip in register mode. */
pmallick 0:e8a1ba50c46b 304 if (!dev->reg_mode) {
pmallick 0:e8a1ba50c46b 305 ret = ad7606_spi_reg_read(dev, reg_addr, NULL);
pmallick 0:e8a1ba50c46b 306 if (ret < 0)
pmallick 0:e8a1ba50c46b 307 return ret;
pmallick 0:e8a1ba50c46b 308 }
pmallick 0:e8a1ba50c46b 309
pmallick 0:e8a1ba50c46b 310 buf[0] = AD7606_WR_FLAG_MSK(reg_addr);
pmallick 0:e8a1ba50c46b 311 buf[1] = reg_data;
pmallick 0:e8a1ba50c46b 312 if (dev->digital_diag_enable.int_crc_err_en) {
pmallick 0:e8a1ba50c46b 313 crc = crc8(ad7606_crc8, buf, 2, 0);
pmallick 0:e8a1ba50c46b 314 buf[2] = crc;
pmallick 0:e8a1ba50c46b 315 sz += 1;
pmallick 0:e8a1ba50c46b 316 }
pmallick 0:e8a1ba50c46b 317
pmallick 0:e8a1ba50c46b 318 ret = spi_write_and_read(dev->spi_desc, buf, sz);
pmallick 0:e8a1ba50c46b 319 if (ret < 0)
pmallick 0:e8a1ba50c46b 320 return ret;
pmallick 0:e8a1ba50c46b 321
pmallick 0:e8a1ba50c46b 322 return ret;
pmallick 0:e8a1ba50c46b 323 }
pmallick 0:e8a1ba50c46b 324
pmallick 0:e8a1ba50c46b 325 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 326 * @brief Write a device register via SPI with masking.
pmallick 0:e8a1ba50c46b 327 *
pmallick 0:e8a1ba50c46b 328 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 329 * @param addr - Register address in device memory.
pmallick 0:e8a1ba50c46b 330 * @param mask - Only bits set to 1 in mask will be modified.
pmallick 0:e8a1ba50c46b 331 * @param val - Value to write to register.
pmallick 0:e8a1ba50c46b 332 *
pmallick 0:e8a1ba50c46b 333 * @return ret - return code.
pmallick 0:e8a1ba50c46b 334 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 335 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 336 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 337 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 338 *******************************************************************************/
pmallick 0:e8a1ba50c46b 339 int32_t ad7606_spi_write_mask(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 340 uint32_t addr,
pmallick 0:e8a1ba50c46b 341 uint32_t mask,
pmallick 0:e8a1ba50c46b 342 uint32_t val)
pmallick 0:e8a1ba50c46b 343 {
pmallick 0:e8a1ba50c46b 344 uint8_t reg_data;
pmallick 0:e8a1ba50c46b 345 int ret;
pmallick 0:e8a1ba50c46b 346
pmallick 0:e8a1ba50c46b 347 ret = ad7606_spi_reg_read(dev, addr, &reg_data);
pmallick 0:e8a1ba50c46b 348 if (ret < 0)
pmallick 0:e8a1ba50c46b 349 return ret;
pmallick 0:e8a1ba50c46b 350
pmallick 0:e8a1ba50c46b 351 reg_data &= ~mask;
pmallick 0:e8a1ba50c46b 352 reg_data |= val;
pmallick 0:e8a1ba50c46b 353
pmallick 0:e8a1ba50c46b 354 return ad7606_spi_reg_write(dev, addr, reg_data);
pmallick 0:e8a1ba50c46b 355 }
pmallick 0:e8a1ba50c46b 356
pmallick 0:e8a1ba50c46b 357 /* Internal function to copy the content of a buffer in 18-bit chunks to a 32-bit buffer by
pmallick 0:e8a1ba50c46b 358 * extending the chunks to 32-bit size. */
pmallick 0:e8a1ba50c46b 359 static int32_t cpy18b32b(uint8_t *psrc, uint32_t srcsz, uint32_t *pdst)
pmallick 0:e8a1ba50c46b 360 {
pmallick 0:e8a1ba50c46b 361 unsigned int i, j;
pmallick 0:e8a1ba50c46b 362
pmallick 0:e8a1ba50c46b 363 if (srcsz % 9)
pmallick 0:e8a1ba50c46b 364 return -EINVAL;
pmallick 0:e8a1ba50c46b 365
pmallick 0:e8a1ba50c46b 366 for(i = 0; i < srcsz; i += 9) {
pmallick 0:e8a1ba50c46b 367 j = 4 * (i / 9);
pmallick 0:e8a1ba50c46b 368 pdst[j+0] = ((uint32_t)(psrc[i+0] & 0xff) << 10) | ((uint32_t)psrc[i+1] << 2)
pmallick 0:e8a1ba50c46b 369 | ((uint32_t)psrc[i+2] >> 6);
pmallick 0:e8a1ba50c46b 370 pdst[j+1] = ((uint32_t)(psrc[i+2] & 0x3f) << 12) | ((uint32_t)psrc[i+3] << 4)
pmallick 0:e8a1ba50c46b 371 | ((uint32_t)psrc[i+4] >> 4);
pmallick 0:e8a1ba50c46b 372 pdst[j+2] = ((uint32_t)(psrc[i+4] & 0x0f) << 14) | ((uint32_t)psrc[i+5] << 6)
pmallick 0:e8a1ba50c46b 373 | ((uint32_t)psrc[i+6] >> 2);
pmallick 0:e8a1ba50c46b 374 pdst[j+3] = ((uint32_t)(psrc[i+6] & 0x03) << 16) | ((uint32_t)psrc[i+7] << 8)
pmallick 0:e8a1ba50c46b 375 | ((uint32_t)psrc[i+8] >> 0);
pmallick 0:e8a1ba50c46b 376 }
pmallick 0:e8a1ba50c46b 377 return SUCCESS;
pmallick 0:e8a1ba50c46b 378 }
pmallick 0:e8a1ba50c46b 379
pmallick 0:e8a1ba50c46b 380 /* Internal function to copy the content of a buffer in 26-bit chunks to a 32-bit buffer by
pmallick 0:e8a1ba50c46b 381 * extending the chunks to 32-bit size. */
pmallick 0:e8a1ba50c46b 382 static int32_t cpy26b32b(uint8_t *psrc, uint32_t srcsz, uint32_t *pdst)
pmallick 0:e8a1ba50c46b 383 {
pmallick 0:e8a1ba50c46b 384 unsigned int i, j;
pmallick 0:e8a1ba50c46b 385
pmallick 0:e8a1ba50c46b 386 if (srcsz % 13)
pmallick 0:e8a1ba50c46b 387 return -EINVAL;
pmallick 0:e8a1ba50c46b 388
pmallick 0:e8a1ba50c46b 389 for(i = 0; i < srcsz; i += 13) {
pmallick 0:e8a1ba50c46b 390 j = 4 * (i / 13);
pmallick 0:e8a1ba50c46b 391 pdst[j+0] = ((uint32_t)(psrc[i+0] & 0xff) << 18) | ((uint32_t)psrc[i+1] << 10)
pmallick 0:e8a1ba50c46b 392 | ((uint32_t)psrc[i+2] << 2) | ((uint32_t)psrc[i+3] >> 6);
pmallick 0:e8a1ba50c46b 393 pdst[j+1] = ((uint32_t)(psrc[i+3] & 0x3f) << 20) | ((uint32_t)psrc[i+4] << 12)
pmallick 0:e8a1ba50c46b 394 | ((uint32_t)psrc[i+5] << 4) | ((uint32_t)psrc[i+6] >> 4);
pmallick 0:e8a1ba50c46b 395 pdst[j+2] = ((uint32_t)(psrc[i+6] & 0x0f) << 22) | ((uint32_t)psrc[i+7] << 14)
pmallick 0:e8a1ba50c46b 396 | ((uint32_t)psrc[i+8] << 6) | ((uint32_t)psrc[i+9] >> 2);
pmallick 0:e8a1ba50c46b 397 pdst[j+3] = ((uint32_t)(psrc[i+9] & 0x03) << 24) | ((uint32_t)psrc[i+10] << 16)
pmallick 0:e8a1ba50c46b 398 | ((uint32_t)psrc[i+11] << 8) | ((uint32_t)psrc[i+12] >> 0);
pmallick 0:e8a1ba50c46b 399 }
pmallick 0:e8a1ba50c46b 400 return SUCCESS;
pmallick 0:e8a1ba50c46b 401 }
pmallick 0:e8a1ba50c46b 402
pmallick 0:e8a1ba50c46b 403 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 404 * @brief Toggle the CONVST pin to start a conversion.
pmallick 0:e8a1ba50c46b 405 *
pmallick 0:e8a1ba50c46b 406 * If needed, this function also puts the device in ADC reading mode by a write
pmallick 0:e8a1ba50c46b 407 * at address zero.
pmallick 0:e8a1ba50c46b 408 *
pmallick 0:e8a1ba50c46b 409 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 410 *
pmallick 0:e8a1ba50c46b 411 * @return ret - return code.
pmallick 0:e8a1ba50c46b 412 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 413 * -EIO - CONVST GPIO not available.
pmallick 0:e8a1ba50c46b 414 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 415 *******************************************************************************/
pmallick 0:e8a1ba50c46b 416 int32_t ad7606_convst(struct ad7606_dev *dev)
pmallick 0:e8a1ba50c46b 417 {
pmallick 0:e8a1ba50c46b 418 int32_t ret;
pmallick 0:e8a1ba50c46b 419
pmallick 0:e8a1ba50c46b 420 if (dev->reg_mode) {
pmallick 0:e8a1ba50c46b 421 /* Enter ADC reading mode by writing at address zero. */
pmallick 0:e8a1ba50c46b 422 ret = ad7606_spi_reg_write(dev, 0, 0);
pmallick 0:e8a1ba50c46b 423 if (ret < 0)
pmallick 0:e8a1ba50c46b 424 return ret;
pmallick 0:e8a1ba50c46b 425
pmallick 0:e8a1ba50c46b 426 dev->reg_mode = false;
pmallick 0:e8a1ba50c46b 427 }
pmallick 0:e8a1ba50c46b 428
pmallick 0:e8a1ba50c46b 429 ret = gpio_set_value(dev->gpio_convst, 0);
pmallick 0:e8a1ba50c46b 430 if (ret < 0)
pmallick 0:e8a1ba50c46b 431 return ret;
pmallick 0:e8a1ba50c46b 432
pmallick 0:e8a1ba50c46b 433 /* wait LP_CNV time */
pmallick 0:e8a1ba50c46b 434 udelay(1);
pmallick 0:e8a1ba50c46b 435
pmallick 0:e8a1ba50c46b 436 return gpio_set_value(dev->gpio_convst, 1);
pmallick 0:e8a1ba50c46b 437 }
pmallick 0:e8a1ba50c46b 438
pmallick 0:e8a1ba50c46b 439 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 440 * @brief Read conversion data.
pmallick 0:e8a1ba50c46b 441 *
pmallick 0:e8a1ba50c46b 442 * This function performs CRC16 computation and checking if enabled in the device.
pmallick 0:e8a1ba50c46b 443 * If the status is enabled in device settings, each sample of data will contain
pmallick 0:e8a1ba50c46b 444 * status information in the lowest 8 bits.
pmallick 0:e8a1ba50c46b 445 *
pmallick 0:e8a1ba50c46b 446 * The output buffer provided by the user should be as wide as to be able to
pmallick 0:e8a1ba50c46b 447 * contain 1 sample from each channel since this function reads conversion data
pmallick 0:e8a1ba50c46b 448 * across all channels.
pmallick 0:e8a1ba50c46b 449 *
pmallick 0:e8a1ba50c46b 450 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 451 * @param data - Pointer to location of buffer where to store the data.
pmallick 0:e8a1ba50c46b 452 *
pmallick 0:e8a1ba50c46b 453 * @return ret - return code.
pmallick 0:e8a1ba50c46b 454 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 455 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 456 * -ENOTSUP - Device bits per sample not supported.
pmallick 0:e8a1ba50c46b 457 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 458 *******************************************************************************/
pmallick 0:e8a1ba50c46b 459 int32_t ad7606_spi_data_read(struct ad7606_dev *dev, uint32_t *data)
pmallick 0:e8a1ba50c46b 460 {
pmallick 0:e8a1ba50c46b 461 uint32_t sz;
pmallick 0:e8a1ba50c46b 462 int32_t ret, i;
pmallick 0:e8a1ba50c46b 463 uint16_t crc, icrc;
pmallick 0:e8a1ba50c46b 464 uint8_t bits = ad7606_chip_info_tbl[dev->device_id].bits;
pmallick 0:e8a1ba50c46b 465 uint8_t sbits = dev->config.status_header ? 8 : 0;
pmallick 0:e8a1ba50c46b 466 uint8_t nchannels = ad7606_chip_info_tbl[dev->device_id].num_channels;
pmallick 0:e8a1ba50c46b 467
pmallick 0:e8a1ba50c46b 468 sz = nchannels * (bits + sbits);
pmallick 0:e8a1ba50c46b 469
pmallick 0:e8a1ba50c46b 470 /* Number of bits to read, corresponds to SCLK cycles in transfer.
pmallick 0:e8a1ba50c46b 471 * This should always be a multiple of 8 to work with most SPI's.
pmallick 0:e8a1ba50c46b 472 * With this chip family this holds true because we either:
pmallick 0:e8a1ba50c46b 473 * - multiply 8 channels * bits per sample
pmallick 0:e8a1ba50c46b 474 * - multiply 4 channels * bits per sample (always multiple of 2)
pmallick 0:e8a1ba50c46b 475 * Therefore, due to design reasons, we don't check for the
pmallick 0:e8a1ba50c46b 476 * remainder of this division because it is zero by design.
pmallick 0:e8a1ba50c46b 477 */
pmallick 0:e8a1ba50c46b 478 sz /= 8;
pmallick 0:e8a1ba50c46b 479
pmallick 0:e8a1ba50c46b 480 if (dev->digital_diag_enable.int_crc_err_en) {
pmallick 0:e8a1ba50c46b 481 sz += 2;
pmallick 0:e8a1ba50c46b 482 }
pmallick 0:e8a1ba50c46b 483
pmallick 0:e8a1ba50c46b 484 memset(dev->data, 0, sz);
pmallick 0:e8a1ba50c46b 485 ret = spi_write_and_read(dev->spi_desc, dev->data, sz);
pmallick 0:e8a1ba50c46b 486 if (ret < 0)
pmallick 0:e8a1ba50c46b 487 return ret;
pmallick 0:e8a1ba50c46b 488
pmallick 0:e8a1ba50c46b 489 if (dev->digital_diag_enable.int_crc_err_en) {
pmallick 0:e8a1ba50c46b 490 sz -= 2;
pmallick 0:e8a1ba50c46b 491 crc = crc16(ad7606_crc16, dev->data, sz, 0);
pmallick 0:e8a1ba50c46b 492 icrc = ((uint16_t)dev->data[sz] << 8) |
pmallick 0:e8a1ba50c46b 493 dev->data[sz+1];
pmallick 0:e8a1ba50c46b 494 if (icrc != crc)
pmallick 0:e8a1ba50c46b 495 return -EBADMSG;
pmallick 0:e8a1ba50c46b 496 }
pmallick 0:e8a1ba50c46b 497
pmallick 0:e8a1ba50c46b 498 switch(bits) {
pmallick 0:e8a1ba50c46b 499 case 18:
pmallick 0:e8a1ba50c46b 500 if (dev->config.status_header)
pmallick 0:e8a1ba50c46b 501 ret = cpy26b32b(dev->data, sz, data);
pmallick 0:e8a1ba50c46b 502 else
pmallick 0:e8a1ba50c46b 503 ret = cpy18b32b(dev->data, sz, data);
pmallick 0:e8a1ba50c46b 504 if (ret < 0)
pmallick 0:e8a1ba50c46b 505 return ret;
pmallick 0:e8a1ba50c46b 506 break;
pmallick 0:e8a1ba50c46b 507 case 16:
pmallick 0:e8a1ba50c46b 508 for(i = 0; i < nchannels; i++) {
pmallick 0:e8a1ba50c46b 509 if (dev->config.status_header) {
pmallick 0:e8a1ba50c46b 510 data[i] = (uint32_t)dev->data[i*3] << 16;
pmallick 0:e8a1ba50c46b 511 data[i] |= (uint32_t)dev->data[i*3+1] << 8;
pmallick 0:e8a1ba50c46b 512 data[i] |= (uint32_t)dev->data[i*3+2];
pmallick 0:e8a1ba50c46b 513 } else {
pmallick 0:e8a1ba50c46b 514 data[i] = (uint32_t)dev->data[i*2] << 8;
pmallick 0:e8a1ba50c46b 515 data[i] |= (uint32_t)dev->data[i*2+1];
pmallick 0:e8a1ba50c46b 516 }
pmallick 0:e8a1ba50c46b 517 }
pmallick 0:e8a1ba50c46b 518 break;
pmallick 0:e8a1ba50c46b 519 default:
pmallick 0:e8a1ba50c46b 520 ret = -ENOTSUP;
pmallick 0:e8a1ba50c46b 521 break;
pmallick 0:e8a1ba50c46b 522 };
pmallick 0:e8a1ba50c46b 523
pmallick 0:e8a1ba50c46b 524 return ret;
pmallick 0:e8a1ba50c46b 525 }
pmallick 0:e8a1ba50c46b 526
pmallick 0:e8a1ba50c46b 527 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 528 * @brief Blocking conversion start and data read.
pmallick 0:e8a1ba50c46b 529 *
pmallick 0:e8a1ba50c46b 530 * This function performs a conversion start and then proceeds to reading
pmallick 0:e8a1ba50c46b 531 * the conversion data.
pmallick 0:e8a1ba50c46b 532 *
pmallick 0:e8a1ba50c46b 533 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 534 * @param data - Pointer to location of buffer where to store the data.
pmallick 0:e8a1ba50c46b 535 *
pmallick 0:e8a1ba50c46b 536 * @return ret - return code.
pmallick 0:e8a1ba50c46b 537 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 538 * -ETIME - Timeout while waiting for the BUSY signal.
pmallick 0:e8a1ba50c46b 539 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 540 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 541 *******************************************************************************/
pmallick 0:e8a1ba50c46b 542 int32_t ad7606_read(struct ad7606_dev *dev, uint32_t * data)
pmallick 0:e8a1ba50c46b 543 {
pmallick 0:e8a1ba50c46b 544 int32_t ret;
pmallick 0:e8a1ba50c46b 545 uint8_t busy;
pmallick 0:e8a1ba50c46b 546 uint32_t timeout = tconv_max[AD7606_OSR_256];
pmallick 0:e8a1ba50c46b 547
pmallick 0:e8a1ba50c46b 548 ret = ad7606_convst(dev);
pmallick 0:e8a1ba50c46b 549 if (ret < 0)
pmallick 0:e8a1ba50c46b 550 return ret;
pmallick 0:e8a1ba50c46b 551
pmallick 0:e8a1ba50c46b 552 if (dev->gpio_busy) {
pmallick 0:e8a1ba50c46b 553 /* Wait for BUSY falling edge */
pmallick 0:e8a1ba50c46b 554 while(timeout) {
pmallick 0:e8a1ba50c46b 555 ret = gpio_get_value(dev->gpio_busy, &busy);
pmallick 0:e8a1ba50c46b 556 if (ret < 0)
pmallick 0:e8a1ba50c46b 557 return ret;
pmallick 0:e8a1ba50c46b 558
pmallick 0:e8a1ba50c46b 559 if (busy == 0)
pmallick 0:e8a1ba50c46b 560 break;
pmallick 0:e8a1ba50c46b 561
pmallick 0:e8a1ba50c46b 562 udelay(1);
pmallick 0:e8a1ba50c46b 563 timeout--;
pmallick 0:e8a1ba50c46b 564 }
pmallick 0:e8a1ba50c46b 565
pmallick 0:e8a1ba50c46b 566 if (timeout == 0)
pmallick 0:e8a1ba50c46b 567 return -ETIME;
pmallick 0:e8a1ba50c46b 568 } else {
pmallick 0:e8a1ba50c46b 569 /* wait CONV time */
pmallick 0:e8a1ba50c46b 570 udelay(tconv_max[dev->oversampling.os_ratio]);
pmallick 0:e8a1ba50c46b 571 }
pmallick 0:e8a1ba50c46b 572
pmallick 0:e8a1ba50c46b 573 return ad7606_spi_data_read(dev, data);
pmallick 0:e8a1ba50c46b 574 }
pmallick 0:e8a1ba50c46b 575
pmallick 0:e8a1ba50c46b 576 /* Internal function to reset device settings to default state after chip reset. */
pmallick 0:e8a1ba50c46b 577 static inline void ad7606_reset_settings(struct ad7606_dev *dev)
pmallick 0:e8a1ba50c46b 578 {
pmallick 0:e8a1ba50c46b 579 int i;
pmallick 0:e8a1ba50c46b 580 const struct ad7606_range *rt = dev->sw_mode ?
pmallick 0:e8a1ba50c46b 581 ad7606_chip_info_tbl[dev->device_id].sw_range_table:
pmallick 0:e8a1ba50c46b 582 ad7606_chip_info_tbl[dev->device_id].hw_range_table;
pmallick 0:e8a1ba50c46b 583
pmallick 0:e8a1ba50c46b 584 for(i = 0; i < dev->num_channels; i++) {
pmallick 0:e8a1ba50c46b 585 if (dev->sw_mode)
pmallick 0:e8a1ba50c46b 586 dev->range_ch[i] = rt[3];
pmallick 0:e8a1ba50c46b 587 else
pmallick 0:e8a1ba50c46b 588 dev->range_ch[i] = rt[0];
pmallick 0:e8a1ba50c46b 589
pmallick 0:e8a1ba50c46b 590 dev->offset_ch[i] = 0;
pmallick 0:e8a1ba50c46b 591 dev->phase_ch[i] = 0;
pmallick 0:e8a1ba50c46b 592 dev->gain_ch[i] = 0;
pmallick 0:e8a1ba50c46b 593 }
pmallick 0:e8a1ba50c46b 594
pmallick 0:e8a1ba50c46b 595 dev->oversampling.os_ratio = AD7606_OSR_1;
pmallick 0:e8a1ba50c46b 596 dev->oversampling.os_pad = 0;
pmallick 0:e8a1ba50c46b 597 dev->config.op_mode = AD7606_NORMAL;
pmallick 0:e8a1ba50c46b 598 dev->config.dout_format = AD7606_2_DOUT;
pmallick 0:e8a1ba50c46b 599 dev->config.ext_os_clock = false;
pmallick 0:e8a1ba50c46b 600 dev->config.status_header = false;
pmallick 0:e8a1ba50c46b 601 dev->digital_diag_enable.rom_crc_err_en = true;
pmallick 0:e8a1ba50c46b 602 dev->digital_diag_enable.mm_crc_err_en = false;
pmallick 0:e8a1ba50c46b 603 dev->digital_diag_enable.int_crc_err_en = false;
pmallick 0:e8a1ba50c46b 604 dev->digital_diag_enable.spi_write_err_en = false;
pmallick 0:e8a1ba50c46b 605 dev->digital_diag_enable.spi_read_err_en = false;
pmallick 0:e8a1ba50c46b 606 dev->digital_diag_enable.busy_stuck_high_err_en = false;
pmallick 0:e8a1ba50c46b 607 dev->digital_diag_enable.clk_fs_os_counter_en = false;
pmallick 0:e8a1ba50c46b 608 dev->digital_diag_enable.interface_check_en = false;
pmallick 0:e8a1ba50c46b 609 dev->reg_mode = false;
pmallick 0:e8a1ba50c46b 610 }
pmallick 0:e8a1ba50c46b 611
pmallick 0:e8a1ba50c46b 612 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 613 * @brief Reset the device by toggling the reset GPIO.
pmallick 0:e8a1ba50c46b 614 *
pmallick 0:e8a1ba50c46b 615 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 616 *
pmallick 0:e8a1ba50c46b 617 * @return ret - return code.
pmallick 0:e8a1ba50c46b 618 * Example: -EIO - Reset GPIO not available.
pmallick 0:e8a1ba50c46b 619 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 620 *******************************************************************************/
pmallick 0:e8a1ba50c46b 621 int32_t ad7606_reset(struct ad7606_dev *dev)
pmallick 0:e8a1ba50c46b 622 {
pmallick 0:e8a1ba50c46b 623 int32_t ret;
pmallick 0:e8a1ba50c46b 624
pmallick 0:e8a1ba50c46b 625 ret = gpio_set_value(dev->gpio_reset, 1);
pmallick 0:e8a1ba50c46b 626 if (ret < 0)
pmallick 0:e8a1ba50c46b 627 return ret;
pmallick 0:e8a1ba50c46b 628
pmallick 0:e8a1ba50c46b 629 udelay(3);
pmallick 0:e8a1ba50c46b 630
pmallick 0:e8a1ba50c46b 631 ret = gpio_set_value(dev->gpio_reset, 0);
pmallick 0:e8a1ba50c46b 632 if (ret < 0)
pmallick 0:e8a1ba50c46b 633 return ret;
pmallick 0:e8a1ba50c46b 634
pmallick 0:e8a1ba50c46b 635 ad7606_reset_settings(dev);
pmallick 0:e8a1ba50c46b 636
pmallick 0:e8a1ba50c46b 637 return ret;
pmallick 0:e8a1ba50c46b 638 }
pmallick 0:e8a1ba50c46b 639
pmallick 0:e8a1ba50c46b 640 /* Internal function that initializes GPIOs. */
pmallick 0:e8a1ba50c46b 641 static int32_t ad7606_request_gpios(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 642 struct ad7606_init_param *init_param)
pmallick 0:e8a1ba50c46b 643 {
pmallick 0:e8a1ba50c46b 644 int32_t ret;
pmallick 0:e8a1ba50c46b 645
pmallick 0:e8a1ba50c46b 646 ret = gpio_get_optional(&dev->gpio_reset, init_param->gpio_reset);
pmallick 0:e8a1ba50c46b 647 if (ret < 0)
pmallick 0:e8a1ba50c46b 648 return ret;
pmallick 0:e8a1ba50c46b 649
pmallick 0:e8a1ba50c46b 650 if (dev->gpio_reset) {
pmallick 0:e8a1ba50c46b 651 ret = gpio_direction_output(dev->gpio_reset, GPIO_LOW);
pmallick 0:e8a1ba50c46b 652 if (ret < 0)
pmallick 0:e8a1ba50c46b 653 return ret;
pmallick 0:e8a1ba50c46b 654 }
pmallick 0:e8a1ba50c46b 655
pmallick 0:e8a1ba50c46b 656 ret = gpio_get_optional(&dev->gpio_convst, init_param->gpio_convst);
pmallick 0:e8a1ba50c46b 657 if (ret < 0)
pmallick 0:e8a1ba50c46b 658 return ret;
pmallick 0:e8a1ba50c46b 659
pmallick 0:e8a1ba50c46b 660 if (dev->gpio_convst) {
pmallick 0:e8a1ba50c46b 661 ret = gpio_direction_output(dev->gpio_convst, GPIO_LOW);
pmallick 0:e8a1ba50c46b 662 if (ret < 0)
pmallick 0:e8a1ba50c46b 663 return ret;
pmallick 0:e8a1ba50c46b 664 }
pmallick 0:e8a1ba50c46b 665
pmallick 0:e8a1ba50c46b 666 ret = gpio_get_optional(&dev->gpio_busy, init_param->gpio_busy);
pmallick 0:e8a1ba50c46b 667 if (ret < 0)
pmallick 0:e8a1ba50c46b 668 return ret;
pmallick 0:e8a1ba50c46b 669
pmallick 0:e8a1ba50c46b 670 if (dev->gpio_busy) {
pmallick 0:e8a1ba50c46b 671 ret = gpio_direction_input(dev->gpio_busy);
pmallick 0:e8a1ba50c46b 672 if (ret < 0)
pmallick 0:e8a1ba50c46b 673 return ret;
pmallick 0:e8a1ba50c46b 674 }
pmallick 0:e8a1ba50c46b 675
pmallick 0:e8a1ba50c46b 676 ret = gpio_get_optional(&dev->gpio_stby_n, init_param->gpio_stby_n);
pmallick 0:e8a1ba50c46b 677 if (ret < 0)
pmallick 0:e8a1ba50c46b 678 return ret;
pmallick 0:e8a1ba50c46b 679
pmallick 0:e8a1ba50c46b 680 if (dev->gpio_stby_n) {
pmallick 0:e8a1ba50c46b 681 ret = gpio_direction_output(dev->gpio_stby_n, GPIO_HIGH);
pmallick 0:e8a1ba50c46b 682 if (ret < 0)
pmallick 0:e8a1ba50c46b 683 return ret;
pmallick 0:e8a1ba50c46b 684 }
pmallick 0:e8a1ba50c46b 685
pmallick 0:e8a1ba50c46b 686 ret = gpio_get_optional(&dev->gpio_range, init_param->gpio_range);
pmallick 0:e8a1ba50c46b 687 if (ret < 0)
pmallick 0:e8a1ba50c46b 688 return ret;
pmallick 0:e8a1ba50c46b 689
pmallick 0:e8a1ba50c46b 690 if (dev->gpio_range) {
pmallick 0:e8a1ba50c46b 691 ret = gpio_direction_output(dev->gpio_range, GPIO_LOW);
pmallick 0:e8a1ba50c46b 692 if (ret < 0)
pmallick 0:e8a1ba50c46b 693 return ret;
pmallick 0:e8a1ba50c46b 694 }
pmallick 0:e8a1ba50c46b 695
pmallick 0:e8a1ba50c46b 696 if (!ad7606_chip_info_tbl[dev->device_id].has_oversampling)
pmallick 0:e8a1ba50c46b 697 return ret;
pmallick 0:e8a1ba50c46b 698
pmallick 0:e8a1ba50c46b 699 ret = gpio_get_optional(&dev->gpio_os0, init_param->gpio_os0);
pmallick 0:e8a1ba50c46b 700 if (ret < 0)
pmallick 0:e8a1ba50c46b 701 return ret;
pmallick 0:e8a1ba50c46b 702
pmallick 0:e8a1ba50c46b 703 if (dev->gpio_os0) {
pmallick 0:e8a1ba50c46b 704 ret = gpio_direction_output(dev->gpio_os0, GPIO_LOW);
pmallick 0:e8a1ba50c46b 705 if (ret < 0)
pmallick 0:e8a1ba50c46b 706 return ret;
pmallick 0:e8a1ba50c46b 707 }
pmallick 0:e8a1ba50c46b 708
pmallick 0:e8a1ba50c46b 709 ret = gpio_get_optional(&dev->gpio_os1, init_param->gpio_os1);
pmallick 0:e8a1ba50c46b 710 if (ret < 0)
pmallick 0:e8a1ba50c46b 711 return ret;
pmallick 0:e8a1ba50c46b 712
pmallick 0:e8a1ba50c46b 713 if (dev->gpio_os1) {
pmallick 0:e8a1ba50c46b 714 ret = gpio_direction_output(dev->gpio_os1, GPIO_LOW);
pmallick 0:e8a1ba50c46b 715 if (ret < 0)
pmallick 0:e8a1ba50c46b 716 return ret;
pmallick 0:e8a1ba50c46b 717 }
pmallick 0:e8a1ba50c46b 718
pmallick 0:e8a1ba50c46b 719 ret = gpio_get_optional(&dev->gpio_os2, init_param->gpio_os2);
pmallick 0:e8a1ba50c46b 720 if (ret < 0)
pmallick 0:e8a1ba50c46b 721 return ret;
pmallick 0:e8a1ba50c46b 722
pmallick 0:e8a1ba50c46b 723 if (dev->gpio_os2) {
pmallick 0:e8a1ba50c46b 724 ret = gpio_direction_output(dev->gpio_os2, GPIO_LOW);
pmallick 0:e8a1ba50c46b 725 if (ret < 0)
pmallick 0:e8a1ba50c46b 726 return ret;
pmallick 0:e8a1ba50c46b 727 }
pmallick 0:e8a1ba50c46b 728
pmallick 0:e8a1ba50c46b 729 ret = gpio_get_optional(&dev->gpio_par_ser, init_param->gpio_par_ser);
pmallick 0:e8a1ba50c46b 730 if (ret < 0)
pmallick 0:e8a1ba50c46b 731 return ret;
pmallick 0:e8a1ba50c46b 732
pmallick 0:e8a1ba50c46b 733 if (dev->gpio_par_ser) {
pmallick 0:e8a1ba50c46b 734 /* Driver currently supports only serial interface, therefore,
pmallick 0:e8a1ba50c46b 735 * if available, pull the GPIO HIGH. */
pmallick 0:e8a1ba50c46b 736 ret = gpio_direction_output(dev->gpio_par_ser, GPIO_HIGH);
pmallick 0:e8a1ba50c46b 737 if (ret < 0)
pmallick 0:e8a1ba50c46b 738 return ret;
pmallick 0:e8a1ba50c46b 739 }
pmallick 0:e8a1ba50c46b 740
pmallick 0:e8a1ba50c46b 741 return ret;
pmallick 0:e8a1ba50c46b 742 }
pmallick 0:e8a1ba50c46b 743
pmallick 0:e8a1ba50c46b 744 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 745 * @brief Set the oversampling ratio.
pmallick 0:e8a1ba50c46b 746 *
pmallick 0:e8a1ba50c46b 747 * In hardware mode, it silently sets AD7606_OSR_64 if higher oversampling
pmallick 0:e8a1ba50c46b 748 * is provided.
pmallick 0:e8a1ba50c46b 749 *
pmallick 0:e8a1ba50c46b 750 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 751 * @param oversampling - Oversampling settings.
pmallick 0:e8a1ba50c46b 752 *
pmallick 0:e8a1ba50c46b 753 * @return ret - return code.
pmallick 0:e8a1ba50c46b 754 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 755 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 756 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 757 *******************************************************************************/
pmallick 0:e8a1ba50c46b 758 int32_t ad7606_set_oversampling(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 759 struct ad7606_oversampling oversampling)
pmallick 0:e8a1ba50c46b 760 {
pmallick 0:e8a1ba50c46b 761 int32_t ret;
pmallick 0:e8a1ba50c46b 762 uint8_t val;
pmallick 0:e8a1ba50c46b 763
pmallick 0:e8a1ba50c46b 764 if (dev->sw_mode) {
pmallick 0:e8a1ba50c46b 765 val = field_prep(AD7606_OS_RATIO_MSK, oversampling.os_ratio);
pmallick 0:e8a1ba50c46b 766 val |= field_prep(AD7606_OS_PAD_MSK, oversampling.os_pad);
pmallick 0:e8a1ba50c46b 767 ret = ad7606_spi_reg_write(dev, AD7606_REG_OVERSAMPLING, val);
pmallick 0:e8a1ba50c46b 768 if (ret < 0)
pmallick 0:e8a1ba50c46b 769 return ret;
pmallick 0:e8a1ba50c46b 770 } else {
pmallick 0:e8a1ba50c46b 771 /* In hardware mode, OSR 128 and 256 are not avaialable */
pmallick 0:e8a1ba50c46b 772 if (oversampling.os_ratio > AD7606_OSR_64)
pmallick 0:e8a1ba50c46b 773 oversampling.os_ratio = AD7606_OSR_64;
pmallick 0:e8a1ba50c46b 774
pmallick 0:e8a1ba50c46b 775 ret = gpio_set_value(dev->gpio_os0, ((oversampling.os_ratio & 0x01) >> 0));
pmallick 0:e8a1ba50c46b 776 if (ret < 0)
pmallick 0:e8a1ba50c46b 777 return ret;
pmallick 0:e8a1ba50c46b 778
pmallick 0:e8a1ba50c46b 779 ret = gpio_set_value(dev->gpio_os1, ((oversampling.os_ratio & 0x02) >> 1));
pmallick 0:e8a1ba50c46b 780 if (ret < 0)
pmallick 0:e8a1ba50c46b 781 return ret;
pmallick 0:e8a1ba50c46b 782
pmallick 0:e8a1ba50c46b 783 ret = gpio_set_value(dev->gpio_os2, ((oversampling.os_ratio & 0x04) >> 2));
pmallick 0:e8a1ba50c46b 784 if (ret < 0)
pmallick 0:e8a1ba50c46b 785 return ret;
pmallick 0:e8a1ba50c46b 786 }
pmallick 0:e8a1ba50c46b 787
pmallick 0:e8a1ba50c46b 788 dev->oversampling = oversampling;
pmallick 0:e8a1ba50c46b 789
pmallick 0:e8a1ba50c46b 790 return SUCCESS;
pmallick 0:e8a1ba50c46b 791 }
pmallick 0:e8a1ba50c46b 792
pmallick 0:e8a1ba50c46b 793 /* Internal function to find the index of a given operation range in the
pmallick 0:e8a1ba50c46b 794 * operation range table specific to a device. */
pmallick 0:e8a1ba50c46b 795 static int8_t ad7606_find_range(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 796 struct ad7606_range range)
pmallick 0:e8a1ba50c46b 797 {
pmallick 0:e8a1ba50c46b 798 uint8_t i;
pmallick 0:e8a1ba50c46b 799 int8_t v = -1;
pmallick 0:e8a1ba50c46b 800 const struct ad7606_range *rt = dev->sw_mode ?
pmallick 0:e8a1ba50c46b 801 ad7606_chip_info_tbl[dev->device_id].sw_range_table:
pmallick 0:e8a1ba50c46b 802 ad7606_chip_info_tbl[dev->device_id].hw_range_table;
pmallick 0:e8a1ba50c46b 803
pmallick 0:e8a1ba50c46b 804 uint32_t rtsz = dev->sw_mode ?
pmallick 0:e8a1ba50c46b 805 ad7606_chip_info_tbl[dev->device_id].sw_range_table_sz:
pmallick 0:e8a1ba50c46b 806 ad7606_chip_info_tbl[dev->device_id].hw_range_table_sz;
pmallick 0:e8a1ba50c46b 807
pmallick 0:e8a1ba50c46b 808 for (i = 0; i < rtsz; i++) {
pmallick 0:e8a1ba50c46b 809 if (range.min != rt[i].min)
pmallick 0:e8a1ba50c46b 810 continue;
pmallick 0:e8a1ba50c46b 811 if (range.max != rt[i].max)
pmallick 0:e8a1ba50c46b 812 continue;
pmallick 0:e8a1ba50c46b 813 if (range.differential != rt[i].differential)
pmallick 0:e8a1ba50c46b 814 continue;
pmallick 0:e8a1ba50c46b 815 v = i;
pmallick 0:e8a1ba50c46b 816 break;
pmallick 0:e8a1ba50c46b 817 }
pmallick 0:e8a1ba50c46b 818
pmallick 0:e8a1ba50c46b 819 return v;
pmallick 0:e8a1ba50c46b 820 }
pmallick 0:e8a1ba50c46b 821
pmallick 0:e8a1ba50c46b 822 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 823 * @brief Set the channel operation range.
pmallick 0:e8a1ba50c46b 824 *
pmallick 0:e8a1ba50c46b 825 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 826 * @param ch - Channel number (0-7).
pmallick 0:e8a1ba50c46b 827 * @param range - Operation range.
pmallick 0:e8a1ba50c46b 828 *
pmallick 0:e8a1ba50c46b 829 * @return ret - return code.
pmallick 0:e8a1ba50c46b 830 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 831 * -EINVAL - Invalid input.
pmallick 0:e8a1ba50c46b 832 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 833 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 834 *******************************************************************************/
pmallick 0:e8a1ba50c46b 835 int32_t ad7606_set_ch_range(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:e8a1ba50c46b 836 struct ad7606_range range)
pmallick 0:e8a1ba50c46b 837 {
pmallick 0:e8a1ba50c46b 838 int value;
pmallick 0:e8a1ba50c46b 839 int32_t ret;
pmallick 0:e8a1ba50c46b 840
pmallick 0:e8a1ba50c46b 841 if (range.min > range.max)
pmallick 0:e8a1ba50c46b 842 return -EINVAL;
pmallick 0:e8a1ba50c46b 843
pmallick 0:e8a1ba50c46b 844 if (ch >= dev->num_channels)
pmallick 0:e8a1ba50c46b 845 return -EINVAL;
pmallick 0:e8a1ba50c46b 846
pmallick 0:e8a1ba50c46b 847 value = ad7606_find_range(dev, range);
pmallick 0:e8a1ba50c46b 848 if (value < 0)
pmallick 0:e8a1ba50c46b 849 return -EINVAL;
pmallick 0:e8a1ba50c46b 850
pmallick 0:e8a1ba50c46b 851 if (dev->sw_mode)
pmallick 0:e8a1ba50c46b 852 ret = ad7606_spi_write_mask(dev, AD7606_REG_RANGE_CH_ADDR(ch),
pmallick 0:e8a1ba50c46b 853 AD7606_RANGE_CH_MSK(ch),
pmallick 0:e8a1ba50c46b 854 AD7606_RANGE_CH_MODE(ch, value));
pmallick 0:e8a1ba50c46b 855 else
pmallick 0:e8a1ba50c46b 856 ret = gpio_set_value(dev->gpio_range, value);
pmallick 0:e8a1ba50c46b 857
pmallick 0:e8a1ba50c46b 858 if (ret)
pmallick 0:e8a1ba50c46b 859 return ret;
pmallick 0:e8a1ba50c46b 860
pmallick 0:e8a1ba50c46b 861 dev->range_ch[ch] = range;
pmallick 0:e8a1ba50c46b 862
pmallick 0:e8a1ba50c46b 863 return ret;
pmallick 0:e8a1ba50c46b 864 }
pmallick 0:e8a1ba50c46b 865
pmallick 0:e8a1ba50c46b 866 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 867 * @brief Set the channel offset.
pmallick 0:e8a1ba50c46b 868 *
pmallick 0:e8a1ba50c46b 869 * The offset parameter is a signed 8-bit integer ranging from -128 to 127 to
pmallick 0:e8a1ba50c46b 870 * make it intuitive and user-friendly.
pmallick 0:e8a1ba50c46b 871 *
pmallick 0:e8a1ba50c46b 872 * This offset gets converted to the register representation where 0x80 is
pmallick 0:e8a1ba50c46b 873 * calibration offset 0, 0x0 is calibration offset -128 and 0xFF is calibration
pmallick 0:e8a1ba50c46b 874 * offset 127, etc.
pmallick 0:e8a1ba50c46b 875 *
pmallick 0:e8a1ba50c46b 876 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 877 * @param ch - Channel number (0-7).
pmallick 0:e8a1ba50c46b 878 * @param offset - Offset calibration amount (-128...127).
pmallick 0:e8a1ba50c46b 879 *
pmallick 0:e8a1ba50c46b 880 * @return ret - return code.
pmallick 0:e8a1ba50c46b 881 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 882 * -EINVAL - Invalid input.
pmallick 0:e8a1ba50c46b 883 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 884 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 885 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 886 *******************************************************************************/
pmallick 0:e8a1ba50c46b 887 int32_t ad7606_set_ch_offset(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:e8a1ba50c46b 888 int8_t offset)
pmallick 0:e8a1ba50c46b 889 {
pmallick 0:e8a1ba50c46b 890 int ret;
pmallick 0:e8a1ba50c46b 891 uint8_t value = (uint8_t)(offset - 0x80);
pmallick 0:e8a1ba50c46b 892
pmallick 0:e8a1ba50c46b 893 if (ch >= dev->num_channels)
pmallick 0:e8a1ba50c46b 894 return -EINVAL;
pmallick 0:e8a1ba50c46b 895
pmallick 0:e8a1ba50c46b 896 if (!dev->sw_mode)
pmallick 0:e8a1ba50c46b 897 return -ENOTSUP;
pmallick 0:e8a1ba50c46b 898
pmallick 0:e8a1ba50c46b 899 ret = ad7606_spi_reg_write(dev, AD7606_REG_OFFSET_CH(ch), value);
pmallick 0:e8a1ba50c46b 900 if (ret < 0)
pmallick 0:e8a1ba50c46b 901 return ret;
pmallick 0:e8a1ba50c46b 902
pmallick 0:e8a1ba50c46b 903 dev->offset_ch[ch] = offset;
pmallick 0:e8a1ba50c46b 904
pmallick 0:e8a1ba50c46b 905 return ret;
pmallick 0:e8a1ba50c46b 906 }
pmallick 0:e8a1ba50c46b 907
pmallick 0:e8a1ba50c46b 908 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 909 * @brief Set the channel phase.
pmallick 0:e8a1ba50c46b 910 *
pmallick 0:e8a1ba50c46b 911 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 912 * @param ch - Channel number (0-7).
pmallick 0:e8a1ba50c46b 913 * @param phase - Phase calibration amount.
pmallick 0:e8a1ba50c46b 914 *
pmallick 0:e8a1ba50c46b 915 * @return ret - return code.
pmallick 0:e8a1ba50c46b 916 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 917 * -EINVAL - Invalid input.
pmallick 0:e8a1ba50c46b 918 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 919 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 920 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 921 *******************************************************************************/
pmallick 0:e8a1ba50c46b 922 int32_t ad7606_set_ch_phase(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:e8a1ba50c46b 923 uint8_t phase)
pmallick 0:e8a1ba50c46b 924 {
pmallick 0:e8a1ba50c46b 925 int ret;
pmallick 0:e8a1ba50c46b 926
pmallick 0:e8a1ba50c46b 927 if (ch >= dev->num_channels)
pmallick 0:e8a1ba50c46b 928 return -EINVAL;
pmallick 0:e8a1ba50c46b 929
pmallick 0:e8a1ba50c46b 930 if (!dev->sw_mode)
pmallick 0:e8a1ba50c46b 931 return -ENOTSUP;
pmallick 0:e8a1ba50c46b 932
pmallick 0:e8a1ba50c46b 933 ret = ad7606_spi_reg_write(dev, AD7606_REG_PHASE_CH(ch), phase);
pmallick 0:e8a1ba50c46b 934 if (ret < 0)
pmallick 0:e8a1ba50c46b 935 return ret;
pmallick 0:e8a1ba50c46b 936
pmallick 0:e8a1ba50c46b 937 dev->phase_ch[ch] = phase;
pmallick 0:e8a1ba50c46b 938
pmallick 0:e8a1ba50c46b 939 return ret;
pmallick 0:e8a1ba50c46b 940 }
pmallick 0:e8a1ba50c46b 941
pmallick 0:e8a1ba50c46b 942 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 943 * @brief Set the channel gain.
pmallick 0:e8a1ba50c46b 944 *
pmallick 0:e8a1ba50c46b 945 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 946 * @param ch - Channel number (0-7).
pmallick 0:e8a1ba50c46b 947 * @param gain - Gain calibration amount.
pmallick 0:e8a1ba50c46b 948 *
pmallick 0:e8a1ba50c46b 949 * @return ret - return code.
pmallick 0:e8a1ba50c46b 950 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 951 * -EINVAL - Invalid input.
pmallick 0:e8a1ba50c46b 952 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 953 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 954 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 955 *******************************************************************************/
pmallick 0:e8a1ba50c46b 956 int32_t ad7606_set_ch_gain(struct ad7606_dev *dev, uint8_t ch,
pmallick 0:e8a1ba50c46b 957 uint8_t gain)
pmallick 0:e8a1ba50c46b 958 {
pmallick 0:e8a1ba50c46b 959 int ret;
pmallick 0:e8a1ba50c46b 960
pmallick 0:e8a1ba50c46b 961 if (ch >= dev->num_channels)
pmallick 0:e8a1ba50c46b 962 return -EINVAL;
pmallick 0:e8a1ba50c46b 963
pmallick 0:e8a1ba50c46b 964 if (!dev->sw_mode)
pmallick 0:e8a1ba50c46b 965 return -ENOTSUP;
pmallick 0:e8a1ba50c46b 966
pmallick 0:e8a1ba50c46b 967 gain = field_get(AD7606_GAIN_MSK, gain);
pmallick 0:e8a1ba50c46b 968 ret = ad7606_spi_reg_write(dev, AD7606_REG_GAIN_CH(ch), gain);
pmallick 0:e8a1ba50c46b 969 if (ret < 0)
pmallick 0:e8a1ba50c46b 970 return ret;
pmallick 0:e8a1ba50c46b 971
pmallick 0:e8a1ba50c46b 972 dev->gain_ch[ch] = gain;
pmallick 0:e8a1ba50c46b 973
pmallick 0:e8a1ba50c46b 974 return ret;
pmallick 0:e8a1ba50c46b 975 }
pmallick 0:e8a1ba50c46b 976
pmallick 0:e8a1ba50c46b 977 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 978 * @brief Set the device config register.
pmallick 0:e8a1ba50c46b 979 *
pmallick 0:e8a1ba50c46b 980 * Configuration structure affects the CONFIG register of the device.
pmallick 0:e8a1ba50c46b 981 *
pmallick 0:e8a1ba50c46b 982 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 983 * @param config - Configuration structure.
pmallick 0:e8a1ba50c46b 984 *
pmallick 0:e8a1ba50c46b 985 * @return ret - return code.
pmallick 0:e8a1ba50c46b 986 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 987 * -EIO - GPIO not available.
pmallick 0:e8a1ba50c46b 988 * -EINVAL - Invalid input.
pmallick 0:e8a1ba50c46b 989 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 990 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 991 *******************************************************************************/
pmallick 0:e8a1ba50c46b 992 int32_t ad7606_set_config(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 993 struct ad7606_config config)
pmallick 0:e8a1ba50c46b 994 {
pmallick 0:e8a1ba50c46b 995 int32_t ret;
pmallick 0:e8a1ba50c46b 996 uint8_t val = 0;
pmallick 0:e8a1ba50c46b 997 uint8_t range_pin, stby_n_pin;
pmallick 0:e8a1ba50c46b 998
pmallick 0:e8a1ba50c46b 999 if (dev->sw_mode) {
pmallick 0:e8a1ba50c46b 1000
pmallick 0:e8a1ba50c46b 1001 val |= field_prep(AD7606_CONFIG_OPERATION_MODE_MSK, config.op_mode);
pmallick 0:e8a1ba50c46b 1002 /* This driver currently supports only normal SPI with 1 DOUT line.
pmallick 0:e8a1ba50c46b 1003 * TODO: remove this check when implementing multi-line DOUT. */
pmallick 0:e8a1ba50c46b 1004 if ((uint8_t)config.dout_format > AD7606_1_DOUT)
pmallick 0:e8a1ba50c46b 1005 return -EINVAL;
pmallick 0:e8a1ba50c46b 1006 if ((uint8_t)config.dout_format > (uint8_t)dev->max_dout_lines)
pmallick 0:e8a1ba50c46b 1007 return -EINVAL;
pmallick 0:e8a1ba50c46b 1008 val |= field_prep(AD7606_CONFIG_DOUT_FORMAT_MSK, config.dout_format);
pmallick 0:e8a1ba50c46b 1009 val |= field_prep(AD7606_CONFIG_EXT_OS_CLOCK_MSK, config.ext_os_clock);
pmallick 0:e8a1ba50c46b 1010 val |= field_prep(AD7606_CONFIG_STATUS_HEADER_MSK, config.status_header);
pmallick 0:e8a1ba50c46b 1011
pmallick 0:e8a1ba50c46b 1012 ret = ad7606_spi_reg_write(dev, AD7606_REG_CONFIG, val);
pmallick 0:e8a1ba50c46b 1013 if (ret)
pmallick 0:e8a1ba50c46b 1014 return ret;
pmallick 0:e8a1ba50c46b 1015 } else {
pmallick 0:e8a1ba50c46b 1016 switch(config.op_mode) {
pmallick 0:e8a1ba50c46b 1017 case AD7606_NORMAL:
pmallick 0:e8a1ba50c46b 1018 range_pin = GPIO_LOW;
pmallick 0:e8a1ba50c46b 1019 stby_n_pin = GPIO_HIGH;
pmallick 0:e8a1ba50c46b 1020 break;
pmallick 0:e8a1ba50c46b 1021 case AD7606_STANDBY:
pmallick 0:e8a1ba50c46b 1022 range_pin = GPIO_LOW;
pmallick 0:e8a1ba50c46b 1023 stby_n_pin = GPIO_LOW;
pmallick 0:e8a1ba50c46b 1024 break;
pmallick 0:e8a1ba50c46b 1025 case AD7606_SHUTDOWN:
pmallick 0:e8a1ba50c46b 1026 range_pin = GPIO_HIGH;
pmallick 0:e8a1ba50c46b 1027 stby_n_pin = GPIO_LOW;
pmallick 0:e8a1ba50c46b 1028 break;
pmallick 0:e8a1ba50c46b 1029 default:
pmallick 0:e8a1ba50c46b 1030 return -EINVAL;
pmallick 0:e8a1ba50c46b 1031 };
pmallick 0:e8a1ba50c46b 1032
pmallick 0:e8a1ba50c46b 1033 ret = gpio_set_value(dev->gpio_stby_n, stby_n_pin);
pmallick 0:e8a1ba50c46b 1034 if (ret)
pmallick 0:e8a1ba50c46b 1035 return ret;
pmallick 0:e8a1ba50c46b 1036
pmallick 0:e8a1ba50c46b 1037 ret = gpio_set_value(dev->gpio_range, range_pin);
pmallick 0:e8a1ba50c46b 1038 if (ret)
pmallick 0:e8a1ba50c46b 1039 return ret;
pmallick 0:e8a1ba50c46b 1040 }
pmallick 0:e8a1ba50c46b 1041
pmallick 0:e8a1ba50c46b 1042 dev->config = config;
pmallick 0:e8a1ba50c46b 1043
pmallick 0:e8a1ba50c46b 1044 return ret;
pmallick 0:e8a1ba50c46b 1045 }
pmallick 0:e8a1ba50c46b 1046
pmallick 0:e8a1ba50c46b 1047 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 1048 * @brief Set the device digital diagnostics configuration.
pmallick 0:e8a1ba50c46b 1049 *
pmallick 0:e8a1ba50c46b 1050 * Digital diagnostics structure affects the DIGITAL_DIAG register of the device.
pmallick 0:e8a1ba50c46b 1051 *
pmallick 0:e8a1ba50c46b 1052 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 1053 * @param diag - Configuration structure.
pmallick 0:e8a1ba50c46b 1054 *
pmallick 0:e8a1ba50c46b 1055 * @return ret - return code.
pmallick 0:e8a1ba50c46b 1056 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 1057 * -ENOTSUP - Device not in software mode.
pmallick 0:e8a1ba50c46b 1058 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 1059 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 1060 *******************************************************************************/
pmallick 0:e8a1ba50c46b 1061 int32_t ad7606_set_digital_diag(struct ad7606_dev *dev,
pmallick 0:e8a1ba50c46b 1062 struct ad7606_digital_diag diag)
pmallick 0:e8a1ba50c46b 1063 {
pmallick 0:e8a1ba50c46b 1064 int32_t ret;
pmallick 0:e8a1ba50c46b 1065 uint8_t val = 0;
pmallick 0:e8a1ba50c46b 1066
pmallick 0:e8a1ba50c46b 1067 if (!dev->sw_mode)
pmallick 0:e8a1ba50c46b 1068 return -ENOTSUP;
pmallick 0:e8a1ba50c46b 1069
pmallick 0:e8a1ba50c46b 1070 val |= field_prep(AD7606_ROM_CRC_ERR_EN_MSK, diag.rom_crc_err_en);
pmallick 0:e8a1ba50c46b 1071 val |= field_prep(AD7606_MM_CRC_ERR_EN_MSK, diag.mm_crc_err_en);
pmallick 0:e8a1ba50c46b 1072 val |= field_prep(AD7606_INT_CRC_ERR_EN_MSK, diag.int_crc_err_en);
pmallick 0:e8a1ba50c46b 1073 val |= field_prep(AD7606_SPI_WRITE_ERR_EN_MSK, diag.spi_write_err_en);
pmallick 0:e8a1ba50c46b 1074 val |= field_prep(AD7606_SPI_READ_ERR_EN_MSK, diag.spi_read_err_en);
pmallick 0:e8a1ba50c46b 1075 val |= field_prep(AD7606_BUSY_STUCK_HIGH_ERR_EN_MSK,
pmallick 0:e8a1ba50c46b 1076 diag.busy_stuck_high_err_en);
pmallick 0:e8a1ba50c46b 1077 val |= field_prep(AD7606_CLK_FS_OS_COUNTER_EN_MSK, diag.clk_fs_os_counter_en);
pmallick 0:e8a1ba50c46b 1078 val |= field_prep(AD7606_INTERFACE_CHECK_EN_MSK, diag.interface_check_en);
pmallick 0:e8a1ba50c46b 1079
pmallick 0:e8a1ba50c46b 1080 ret = ad7606_spi_reg_write(dev, AD7606_REG_DIGITAL_DIAG_ENABLE, val);
pmallick 0:e8a1ba50c46b 1081 if (ret < 0)
pmallick 0:e8a1ba50c46b 1082 return ret;
pmallick 0:e8a1ba50c46b 1083
pmallick 0:e8a1ba50c46b 1084 dev->digital_diag_enable = diag;
pmallick 0:e8a1ba50c46b 1085
pmallick 0:e8a1ba50c46b 1086 return ret;
pmallick 0:e8a1ba50c46b 1087 }
pmallick 0:e8a1ba50c46b 1088
pmallick 0:e8a1ba50c46b 1089 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 1090 * @brief Initialize the ad7606 device structure.
pmallick 0:e8a1ba50c46b 1091 *
pmallick 0:e8a1ba50c46b 1092 * Performs memory allocation of the device structure.
pmallick 0:e8a1ba50c46b 1093 *
pmallick 0:e8a1ba50c46b 1094 * @param device - Pointer to location of device structure to write.
pmallick 0:e8a1ba50c46b 1095 * @param init_param - Pointer to configuration of the driver.
pmallick 0:e8a1ba50c46b 1096 *
pmallick 0:e8a1ba50c46b 1097 * @return ret - return code.
pmallick 0:e8a1ba50c46b 1098 * Example: -ENOMEM - Memory allocation error.
pmallick 0:e8a1ba50c46b 1099 * -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 1100 * -EIO - GPIO initialization error.
pmallick 0:e8a1ba50c46b 1101 * -ENODEV - Unexpected device id.
pmallick 0:e8a1ba50c46b 1102 * -EBADMSG - CRC computation mismatch.
pmallick 0:e8a1ba50c46b 1103 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 1104 *******************************************************************************/
pmallick 0:e8a1ba50c46b 1105 int32_t ad7606_init(struct ad7606_dev **device,
pmallick 0:e8a1ba50c46b 1106 struct ad7606_init_param *init_param)
pmallick 0:e8a1ba50c46b 1107 {
pmallick 0:e8a1ba50c46b 1108 struct ad7606_dev *dev;
pmallick 0:e8a1ba50c46b 1109 uint8_t reg, id;
pmallick 0:e8a1ba50c46b 1110 int32_t i, ret;
pmallick 0:e8a1ba50c46b 1111
pmallick 0:e8a1ba50c46b 1112 crc8_populate_msb(ad7606_crc8, 0x7);
pmallick 0:e8a1ba50c46b 1113 crc16_populate_msb(ad7606_crc16, 0x755b);
pmallick 0:e8a1ba50c46b 1114
pmallick 0:e8a1ba50c46b 1115 dev = (struct ad7606_dev *)calloc(1, sizeof(*dev));
pmallick 0:e8a1ba50c46b 1116 if (!dev)
pmallick 0:e8a1ba50c46b 1117 return -ENOMEM;
pmallick 0:e8a1ba50c46b 1118
pmallick 0:e8a1ba50c46b 1119 dev->device_id = init_param->device_id;
pmallick 0:e8a1ba50c46b 1120 dev->num_channels = ad7606_chip_info_tbl[dev->device_id].num_channels;
pmallick 0:e8a1ba50c46b 1121 dev->max_dout_lines = ad7606_chip_info_tbl[dev->device_id].max_dout_lines;
pmallick 0:e8a1ba50c46b 1122 if (ad7606_chip_info_tbl[dev->device_id].has_registers)
pmallick 0:e8a1ba50c46b 1123 dev->sw_mode = init_param->sw_mode;
pmallick 0:e8a1ba50c46b 1124
pmallick 0:e8a1ba50c46b 1125 ret = ad7606_request_gpios(dev, init_param);
pmallick 0:e8a1ba50c46b 1126 if (ret < 0)
pmallick 0:e8a1ba50c46b 1127 goto error;
pmallick 0:e8a1ba50c46b 1128
pmallick 0:e8a1ba50c46b 1129 if (init_param->sw_mode) {
pmallick 0:e8a1ba50c46b 1130 ret = gpio_set_value(dev->gpio_os0, GPIO_HIGH);
pmallick 0:e8a1ba50c46b 1131 if (ret < 0)
pmallick 0:e8a1ba50c46b 1132 goto error;
pmallick 0:e8a1ba50c46b 1133
pmallick 0:e8a1ba50c46b 1134 ret = gpio_set_value(dev->gpio_os1, GPIO_HIGH);
pmallick 0:e8a1ba50c46b 1135 if (ret < 0)
pmallick 0:e8a1ba50c46b 1136 goto error;
pmallick 0:e8a1ba50c46b 1137
pmallick 0:e8a1ba50c46b 1138 ret = gpio_set_value(dev->gpio_os2, GPIO_HIGH);
pmallick 0:e8a1ba50c46b 1139 if (ret < 0)
pmallick 0:e8a1ba50c46b 1140 goto error;
pmallick 0:e8a1ba50c46b 1141 }
pmallick 0:e8a1ba50c46b 1142
pmallick 0:e8a1ba50c46b 1143 ret = ad7606_reset(dev);
pmallick 0:e8a1ba50c46b 1144 if (ret < 0)
pmallick 0:e8a1ba50c46b 1145 goto error;
pmallick 0:e8a1ba50c46b 1146
pmallick 0:e8a1ba50c46b 1147 /* wait DEVICE_SETUP time */
pmallick 0:e8a1ba50c46b 1148 udelay(253);
pmallick 0:e8a1ba50c46b 1149
pmallick 0:e8a1ba50c46b 1150 ret = spi_init(&dev->spi_desc, &init_param->spi_init);
pmallick 0:e8a1ba50c46b 1151 if (ret < 0)
pmallick 0:e8a1ba50c46b 1152 goto error;
pmallick 0:e8a1ba50c46b 1153
pmallick 0:e8a1ba50c46b 1154 if (dev->sw_mode) {
pmallick 0:e8a1ba50c46b 1155 ret = ad7606_spi_reg_read(dev, AD7606_REG_ID, &reg);
pmallick 0:e8a1ba50c46b 1156 if (ret < 0)
pmallick 0:e8a1ba50c46b 1157 goto error;
pmallick 0:e8a1ba50c46b 1158
pmallick 0:e8a1ba50c46b 1159 id = ad7606_chip_info_tbl[dev->device_id].device_id;
pmallick 0:e8a1ba50c46b 1160 if (field_get(AD7606_ID_DEVICE_ID_MSK, reg) != id) {
pmallick 0:e8a1ba50c46b 1161 printf("ad7606: device id mismatch, expected 0x%.2x, got 0x%.2x\n",
pmallick 0:e8a1ba50c46b 1162 id,
pmallick 0:e8a1ba50c46b 1163 (int)field_get(AD7606_ID_DEVICE_ID_MSK, reg));
pmallick 0:e8a1ba50c46b 1164 ret = -ENODEV;
pmallick 0:e8a1ba50c46b 1165 goto error;
pmallick 0:e8a1ba50c46b 1166 }
pmallick 0:e8a1ba50c46b 1167
pmallick 0:e8a1ba50c46b 1168 ret = ad7606_set_digital_diag(dev, init_param->digital_diag_enable);
pmallick 0:e8a1ba50c46b 1169 if (ret < 0)
pmallick 0:e8a1ba50c46b 1170 goto error;
pmallick 0:e8a1ba50c46b 1171
pmallick 0:e8a1ba50c46b 1172 ret = ad7606_set_config(dev, init_param->config);
pmallick 0:e8a1ba50c46b 1173 if (ret < 0)
pmallick 0:e8a1ba50c46b 1174 goto error;
pmallick 0:e8a1ba50c46b 1175
pmallick 0:e8a1ba50c46b 1176 for (i = 0; i < dev->num_channels; i++) {
pmallick 0:e8a1ba50c46b 1177 ret = ad7606_set_ch_range(dev, i, init_param->range_ch[i]);
pmallick 0:e8a1ba50c46b 1178 if (ret < 0)
pmallick 0:e8a1ba50c46b 1179 goto error;
pmallick 0:e8a1ba50c46b 1180 }
pmallick 0:e8a1ba50c46b 1181
pmallick 0:e8a1ba50c46b 1182 for(i = 0; i < dev->num_channels; i++) {
pmallick 0:e8a1ba50c46b 1183 ret = ad7606_set_ch_offset(dev, i, init_param->offset_ch[i]);
pmallick 0:e8a1ba50c46b 1184 if (ret < 0)
pmallick 0:e8a1ba50c46b 1185 goto error;
pmallick 0:e8a1ba50c46b 1186 }
pmallick 0:e8a1ba50c46b 1187
pmallick 0:e8a1ba50c46b 1188 for(i = 0; i < dev->num_channels; i++) {
pmallick 0:e8a1ba50c46b 1189 ret = ad7606_set_ch_phase(dev, i, init_param->phase_ch[i]);
pmallick 0:e8a1ba50c46b 1190 if (ret < 0)
pmallick 0:e8a1ba50c46b 1191 goto error;
pmallick 0:e8a1ba50c46b 1192 }
pmallick 0:e8a1ba50c46b 1193
pmallick 0:e8a1ba50c46b 1194 for(i = 0; i < dev->num_channels; i++) {
pmallick 0:e8a1ba50c46b 1195 ret = ad7606_set_ch_gain(dev, i, init_param->gain_ch[i]);
pmallick 0:e8a1ba50c46b 1196 if (ret < 0)
pmallick 0:e8a1ba50c46b 1197 goto error;
pmallick 0:e8a1ba50c46b 1198 }
pmallick 0:e8a1ba50c46b 1199 } else {
pmallick 0:e8a1ba50c46b 1200 ret = ad7606_set_ch_range(dev, 0, init_param->range_ch[0]);
pmallick 0:e8a1ba50c46b 1201 if (ret < 0)
pmallick 0:e8a1ba50c46b 1202 goto error;
pmallick 0:e8a1ba50c46b 1203 }
pmallick 0:e8a1ba50c46b 1204
pmallick 0:e8a1ba50c46b 1205 ret = gpio_set_value(dev->gpio_convst, 1);
pmallick 0:e8a1ba50c46b 1206 if (ret < 0)
pmallick 0:e8a1ba50c46b 1207 goto error;
pmallick 0:e8a1ba50c46b 1208
pmallick 0:e8a1ba50c46b 1209 if (ad7606_chip_info_tbl[dev->device_id].has_oversampling)
pmallick 0:e8a1ba50c46b 1210 ad7606_set_oversampling(dev, init_param->oversampling);
pmallick 0:e8a1ba50c46b 1211
pmallick 0:e8a1ba50c46b 1212 *device = dev;
pmallick 0:e8a1ba50c46b 1213
pmallick 0:e8a1ba50c46b 1214 printf("ad7606 successfully initialized\n");
pmallick 0:e8a1ba50c46b 1215
pmallick 0:e8a1ba50c46b 1216 return ret;
pmallick 0:e8a1ba50c46b 1217 error:
pmallick 0:e8a1ba50c46b 1218 printf("ad7606 initialization failed\n");
pmallick 0:e8a1ba50c46b 1219 ad7606_remove(dev);
pmallick 0:e8a1ba50c46b 1220 return ret;
pmallick 0:e8a1ba50c46b 1221 }
pmallick 0:e8a1ba50c46b 1222
pmallick 0:e8a1ba50c46b 1223 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 1224 * @brief Free any resource used by the driver.
pmallick 0:e8a1ba50c46b 1225 *
pmallick 0:e8a1ba50c46b 1226 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 1227 *
pmallick 0:e8a1ba50c46b 1228 * @return ret - return code.
pmallick 0:e8a1ba50c46b 1229 * Example: -EIO - SPI communication error.
pmallick 0:e8a1ba50c46b 1230 * SUCCESS - No errors encountered.
pmallick 0:e8a1ba50c46b 1231 *******************************************************************************/
pmallick 0:e8a1ba50c46b 1232 int32_t ad7606_remove(struct ad7606_dev *dev)
pmallick 0:e8a1ba50c46b 1233 {
pmallick 0:e8a1ba50c46b 1234 int32_t ret;
pmallick 0:e8a1ba50c46b 1235
pmallick 0:e8a1ba50c46b 1236 gpio_remove(dev->gpio_reset);
pmallick 0:e8a1ba50c46b 1237 gpio_remove(dev->gpio_convst);
pmallick 0:e8a1ba50c46b 1238 gpio_remove(dev->gpio_busy);
pmallick 0:e8a1ba50c46b 1239 gpio_remove(dev->gpio_stby_n);
pmallick 0:e8a1ba50c46b 1240 gpio_remove(dev->gpio_range);
pmallick 0:e8a1ba50c46b 1241 gpio_remove(dev->gpio_os0);
pmallick 0:e8a1ba50c46b 1242 gpio_remove(dev->gpio_os1);
pmallick 0:e8a1ba50c46b 1243 gpio_remove(dev->gpio_os2);
pmallick 0:e8a1ba50c46b 1244 gpio_remove(dev->gpio_par_ser);
pmallick 0:e8a1ba50c46b 1245
pmallick 0:e8a1ba50c46b 1246 ret = spi_remove(dev->spi_desc);
pmallick 0:e8a1ba50c46b 1247
pmallick 0:e8a1ba50c46b 1248 free(dev);
pmallick 0:e8a1ba50c46b 1249
pmallick 0:e8a1ba50c46b 1250 return ret;
pmallick 0:e8a1ba50c46b 1251 }