Pratyush Mallick
this is testing
noos_mbed/drivers/adc/ad7124/ad7124.h@0:e8a1ba50c46b, 2021-01-14 (annotated)
- Committer:
- pmallick
- Date:
- Thu Jan 14 19:12:57 2021 +0530
- Revision:
- 0:e8a1ba50c46b
this is testing
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| pmallick | 0:e8a1ba50c46b | 1 | /***************************************************************************//** |
| pmallick | 0:e8a1ba50c46b | 2 | * @file ad7124.h |
| pmallick | 0:e8a1ba50c46b | 3 | * @brief AD7124 header file. |
| pmallick | 0:e8a1ba50c46b | 4 | * Devices AD7124-4, AD7124-8 |
| pmallick | 0:e8a1ba50c46b | 5 | * |
| pmallick | 0:e8a1ba50c46b | 6 | ******************************************************************************** |
| pmallick | 0:e8a1ba50c46b | 7 | * Copyright 2015-2020(c) Analog Devices, Inc. |
| pmallick | 0:e8a1ba50c46b | 8 | * |
| pmallick | 0:e8a1ba50c46b | 9 | * All rights reserved. |
| pmallick | 0:e8a1ba50c46b | 10 | * |
| pmallick | 0:e8a1ba50c46b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| pmallick | 0:e8a1ba50c46b | 12 | * are permitted provided that the following conditions are met: |
| pmallick | 0:e8a1ba50c46b | 13 | * - Redistributions of source code must retain the above copyright |
| pmallick | 0:e8a1ba50c46b | 14 | * notice, this list of conditions and the following disclaimer. |
| pmallick | 0:e8a1ba50c46b | 15 | * - Redistributions in binary form must reproduce the above copyright |
| pmallick | 0:e8a1ba50c46b | 16 | * notice, this list of conditions and the following disclaimer in |
| pmallick | 0:e8a1ba50c46b | 17 | * the documentation and/or other materials provided with the |
| pmallick | 0:e8a1ba50c46b | 18 | * distribution. |
| pmallick | 0:e8a1ba50c46b | 19 | * - Neither the name of Analog Devices, Inc. nor the names of its |
| pmallick | 0:e8a1ba50c46b | 20 | * contributors may be used to endorse or promote products derived |
| pmallick | 0:e8a1ba50c46b | 21 | * from this software without specific prior written permission. |
| pmallick | 0:e8a1ba50c46b | 22 | * - The use of this software may or may not infringe the patent rights |
| pmallick | 0:e8a1ba50c46b | 23 | * of one or more patent holders. This license does not release you |
| pmallick | 0:e8a1ba50c46b | 24 | * from the requirement that you obtain separate licenses from these |
| pmallick | 0:e8a1ba50c46b | 25 | * patent holders to use this software. |
| pmallick | 0:e8a1ba50c46b | 26 | * - Use of the software either in source or binary form, must be run |
| pmallick | 0:e8a1ba50c46b | 27 | * on or directly connected to an Analog Devices Inc. component. |
| pmallick | 0:e8a1ba50c46b | 28 | * |
| pmallick | 0:e8a1ba50c46b | 29 | * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED |
| pmallick | 0:e8a1ba50c46b | 30 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY |
| pmallick | 0:e8a1ba50c46b | 31 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| pmallick | 0:e8a1ba50c46b | 32 | * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| pmallick | 0:e8a1ba50c46b | 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| pmallick | 0:e8a1ba50c46b | 34 | * INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| pmallick | 0:e8a1ba50c46b | 35 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| pmallick | 0:e8a1ba50c46b | 36 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| pmallick | 0:e8a1ba50c46b | 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| pmallick | 0:e8a1ba50c46b | 38 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| pmallick | 0:e8a1ba50c46b | 39 | *******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 40 | |
| pmallick | 0:e8a1ba50c46b | 41 | #ifndef __AD7124_H__ |
| pmallick | 0:e8a1ba50c46b | 42 | #define __AD7124_H__ |
| pmallick | 0:e8a1ba50c46b | 43 | |
| pmallick | 0:e8a1ba50c46b | 44 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 45 | /***************************** Include Files **********************************/ |
| pmallick | 0:e8a1ba50c46b | 46 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 47 | #include <stdint.h> |
| pmallick | 0:e8a1ba50c46b | 48 | #include "platform_drivers.h" |
| pmallick | 0:e8a1ba50c46b | 49 | |
| pmallick | 0:e8a1ba50c46b | 50 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 51 | /******************* Register map and register definitions ********************/ |
| pmallick | 0:e8a1ba50c46b | 52 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 53 | /* |
| pmallick | 0:e8a1ba50c46b | 54 | * Create a contiguous bitmask starting at bit position @l and ending at |
| pmallick | 0:e8a1ba50c46b | 55 | * position @h. |
| pmallick | 0:e8a1ba50c46b | 56 | */ |
| pmallick | 0:e8a1ba50c46b | 57 | #ifndef GENMASK |
| pmallick | 0:e8a1ba50c46b | 58 | #define GENMASK(h, l) (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (31 - (h)))) |
| pmallick | 0:e8a1ba50c46b | 59 | #endif |
| pmallick | 0:e8a1ba50c46b | 60 | #define BIT(x) (1UL << (x)) |
| pmallick | 0:e8a1ba50c46b | 61 | |
| pmallick | 0:e8a1ba50c46b | 62 | #define AD7124_RW 1 /* Read and Write */ |
| pmallick | 0:e8a1ba50c46b | 63 | #define AD7124_R 2 /* Read only */ |
| pmallick | 0:e8a1ba50c46b | 64 | #define AD7124_W 3 /* Write only */ |
| pmallick | 0:e8a1ba50c46b | 65 | |
| pmallick | 0:e8a1ba50c46b | 66 | /* AD7124 Register Map */ |
| pmallick | 0:e8a1ba50c46b | 67 | #define AD7124_COMM_REG 0x00 |
| pmallick | 0:e8a1ba50c46b | 68 | #define AD7124_STATUS_REG 0x00 |
| pmallick | 0:e8a1ba50c46b | 69 | #define AD7124_ADC_CTRL_REG 0x01 |
| pmallick | 0:e8a1ba50c46b | 70 | #define AD7124_DATA_REG 0x02 |
| pmallick | 0:e8a1ba50c46b | 71 | #define AD7124_IO_CTRL1_REG 0x03 |
| pmallick | 0:e8a1ba50c46b | 72 | #define AD7124_IO_CTRL2_REG 0x04 |
| pmallick | 0:e8a1ba50c46b | 73 | #define AD7124_ID_REG 0x05 |
| pmallick | 0:e8a1ba50c46b | 74 | #define AD7124_ERR_REG 0x06 |
| pmallick | 0:e8a1ba50c46b | 75 | #define AD7124_ERREN_REG 0x07 |
| pmallick | 0:e8a1ba50c46b | 76 | #define AD7124_CH0_MAP_REG 0x09 |
| pmallick | 0:e8a1ba50c46b | 77 | #define AD7124_CH1_MAP_REG 0x0A |
| pmallick | 0:e8a1ba50c46b | 78 | #define AD7124_CH2_MAP_REG 0x0B |
| pmallick | 0:e8a1ba50c46b | 79 | #define AD7124_CH3_MAP_REG 0x0C |
| pmallick | 0:e8a1ba50c46b | 80 | #define AD7124_CH4_MAP_REG 0x0D |
| pmallick | 0:e8a1ba50c46b | 81 | #define AD7124_CH5_MAP_REG 0x0E |
| pmallick | 0:e8a1ba50c46b | 82 | #define AD7124_CH6_MAP_REG 0x0F |
| pmallick | 0:e8a1ba50c46b | 83 | #define AD7124_CH7_MAP_REG 0x10 |
| pmallick | 0:e8a1ba50c46b | 84 | #define AD7124_CH8_MAP_REG 0x11 |
| pmallick | 0:e8a1ba50c46b | 85 | #define AD7124_CH9_MAP_REG 0x12 |
| pmallick | 0:e8a1ba50c46b | 86 | #define AD7124_CH10_MAP_REG 0x13 |
| pmallick | 0:e8a1ba50c46b | 87 | #define AD7124_CH11_MAP_REG 0x14 |
| pmallick | 0:e8a1ba50c46b | 88 | #define AD7124_CH12_MAP_REG 0x15 |
| pmallick | 0:e8a1ba50c46b | 89 | #define AD7124_CH13_MAP_REG 0x16 |
| pmallick | 0:e8a1ba50c46b | 90 | #define AD7124_CH14_MAP_REG 0x17 |
| pmallick | 0:e8a1ba50c46b | 91 | #define AD7124_CH15_MAP_REG 0x18 |
| pmallick | 0:e8a1ba50c46b | 92 | #define AD7124_CFG0_REG 0x19 |
| pmallick | 0:e8a1ba50c46b | 93 | #define AD7124_CFG1_REG 0x1A |
| pmallick | 0:e8a1ba50c46b | 94 | #define AD7124_CFG2_REG 0x1B |
| pmallick | 0:e8a1ba50c46b | 95 | #define AD7124_CFG3_REG 0x1C |
| pmallick | 0:e8a1ba50c46b | 96 | #define AD7124_CFG4_REG 0x1D |
| pmallick | 0:e8a1ba50c46b | 97 | #define AD7124_CFG5_REG 0x1E |
| pmallick | 0:e8a1ba50c46b | 98 | #define AD7124_CFG6_REG 0x1F |
| pmallick | 0:e8a1ba50c46b | 99 | #define AD7124_CFG7_REG 0x20 |
| pmallick | 0:e8a1ba50c46b | 100 | #define AD7124_FILT0_REG 0x21 |
| pmallick | 0:e8a1ba50c46b | 101 | #define AD7124_FILT1_REG 0x22 |
| pmallick | 0:e8a1ba50c46b | 102 | #define AD7124_FILT2_REG 0x23 |
| pmallick | 0:e8a1ba50c46b | 103 | #define AD7124_FILT3_REG 0x24 |
| pmallick | 0:e8a1ba50c46b | 104 | #define AD7124_FILT4_REG 0x25 |
| pmallick | 0:e8a1ba50c46b | 105 | #define AD7124_FILT5_REG 0x26 |
| pmallick | 0:e8a1ba50c46b | 106 | #define AD7124_FILT6_REG 0x27 |
| pmallick | 0:e8a1ba50c46b | 107 | #define AD7124_FILT7_REG 0x28 |
| pmallick | 0:e8a1ba50c46b | 108 | #define AD7124_OFFS0_REG 0x29 |
| pmallick | 0:e8a1ba50c46b | 109 | #define AD7124_OFFS1_REG 0x2A |
| pmallick | 0:e8a1ba50c46b | 110 | #define AD7124_OFFS2_REG 0x2B |
| pmallick | 0:e8a1ba50c46b | 111 | #define AD7124_OFFS3_REG 0x2C |
| pmallick | 0:e8a1ba50c46b | 112 | #define AD7124_OFFS4_REG 0x2D |
| pmallick | 0:e8a1ba50c46b | 113 | #define AD7124_OFFS5_REG 0x2E |
| pmallick | 0:e8a1ba50c46b | 114 | #define AD7124_OFFS6_REG 0x2F |
| pmallick | 0:e8a1ba50c46b | 115 | #define AD7124_OFFS7_REG 0x30 |
| pmallick | 0:e8a1ba50c46b | 116 | #define AD7124_GAIN0_REG 0x31 |
| pmallick | 0:e8a1ba50c46b | 117 | #define AD7124_GAIN1_REG 0x32 |
| pmallick | 0:e8a1ba50c46b | 118 | #define AD7124_GAIN2_REG 0x33 |
| pmallick | 0:e8a1ba50c46b | 119 | #define AD7124_GAIN3_REG 0x34 |
| pmallick | 0:e8a1ba50c46b | 120 | #define AD7124_GAIN4_REG 0x35 |
| pmallick | 0:e8a1ba50c46b | 121 | #define AD7124_GAIN5_REG 0x36 |
| pmallick | 0:e8a1ba50c46b | 122 | #define AD7124_GAIN6_REG 0x37 |
| pmallick | 0:e8a1ba50c46b | 123 | #define AD7124_GAIN7_REG 0x38 |
| pmallick | 0:e8a1ba50c46b | 124 | |
| pmallick | 0:e8a1ba50c46b | 125 | /* Communication Register bits */ |
| pmallick | 0:e8a1ba50c46b | 126 | #define AD7124_COMM_REG_WEN (0 << 7) |
| pmallick | 0:e8a1ba50c46b | 127 | #define AD7124_COMM_REG_WR (0 << 6) |
| pmallick | 0:e8a1ba50c46b | 128 | #define AD7124_COMM_REG_RD (1 << 6) |
| pmallick | 0:e8a1ba50c46b | 129 | #define AD7124_COMM_REG_RA(x) ((x) & 0x3F) |
| pmallick | 0:e8a1ba50c46b | 130 | |
| pmallick | 0:e8a1ba50c46b | 131 | /* Status Register bits */ |
| pmallick | 0:e8a1ba50c46b | 132 | #define AD7124_STATUS_REG_RDY (1 << 7) |
| pmallick | 0:e8a1ba50c46b | 133 | #define AD7124_STATUS_REG_ERROR_FLAG (1 << 6) |
| pmallick | 0:e8a1ba50c46b | 134 | #define AD7124_STATUS_REG_POR_FLAG (1 << 4) |
| pmallick | 0:e8a1ba50c46b | 135 | #define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF) |
| pmallick | 0:e8a1ba50c46b | 136 | |
| pmallick | 0:e8a1ba50c46b | 137 | /* ADC_Control Register bits */ |
| pmallick | 0:e8a1ba50c46b | 138 | #define AD7124_ADC_CTRL_REG_DOUT_RDY_DEL (1 << 12) |
| pmallick | 0:e8a1ba50c46b | 139 | #define AD7124_ADC_CTRL_REG_CONT_READ (1 << 11) |
| pmallick | 0:e8a1ba50c46b | 140 | #define AD7124_ADC_CTRL_REG_DATA_STATUS (1 << 10) |
| pmallick | 0:e8a1ba50c46b | 141 | #define AD7124_ADC_CTRL_REG_CS_EN (1 << 9) |
| pmallick | 0:e8a1ba50c46b | 142 | #define AD7124_ADC_CTRL_REG_REF_EN (1 << 8) |
| pmallick | 0:e8a1ba50c46b | 143 | #define AD7124_ADC_CTRL_REG_POWER_MODE_MSK GENMASK(7,6) |
| pmallick | 0:e8a1ba50c46b | 144 | #define AD7124_ADC_CTRL_REG_POWER_MODE_RD(x) (((x) >> 6) & 0x3) |
| pmallick | 0:e8a1ba50c46b | 145 | #define AD7124_ADC_CTRL_REG_POWER_MODE(x) (((x) & 0x3) << 6) |
| pmallick | 0:e8a1ba50c46b | 146 | #define AD7124_ADC_CTRL_REG_MSK GENMASK(5,2) |
| pmallick | 0:e8a1ba50c46b | 147 | #define AD7124_ADC_CTRL_REG_MODE_OUT(x) (((x) >> 2) & 0xF) |
| pmallick | 0:e8a1ba50c46b | 148 | #define AD7124_ADC_CTRL_REG_MODE(x) (((x) & 0xF) << 2) |
| pmallick | 0:e8a1ba50c46b | 149 | #define AD7124_ADC_CTRL_REG_CLK_SEL_MSK GENMASK(1,0) |
| pmallick | 0:e8a1ba50c46b | 150 | #define AD7124_ADC_CTRL_REG_CLK_SEL_RD(x) (((x) >> 0) & 0x3) |
| pmallick | 0:e8a1ba50c46b | 151 | #define AD7124_ADC_CTRL_REG_CLK_SEL(x) (((x) & 0x3) << 0) |
| pmallick | 0:e8a1ba50c46b | 152 | |
| pmallick | 0:e8a1ba50c46b | 153 | /* IO_Control_1 Register bits */ |
| pmallick | 0:e8a1ba50c46b | 154 | #define AD7124_IO_CTRL1_REG_GPIO_DAT2 (1 << 23) |
| pmallick | 0:e8a1ba50c46b | 155 | #define AD7124_IO_CTRL1_REG_GPIO_DAT1 (1 << 22) |
| pmallick | 0:e8a1ba50c46b | 156 | #define AD7124_IO_CTRL1_REG_GPIO_CTRL2 (1 << 19) |
| pmallick | 0:e8a1ba50c46b | 157 | #define AD7124_IO_CTRL1_REG_GPIO_CTRL1 (1 << 18) |
| pmallick | 0:e8a1ba50c46b | 158 | #define AD7124_IO_CTRL1_REG_PDSW (1 << 15) |
| pmallick | 0:e8a1ba50c46b | 159 | #define AD7124_IO_CTRL1_REG_IOUT1(x) (((x) & 0x7) << 11) |
| pmallick | 0:e8a1ba50c46b | 160 | #define AD7124_IO_CTRL1_REG_IOUT0(x) (((x) & 0x7) << 8) |
| pmallick | 0:e8a1ba50c46b | 161 | #define AD7124_IO_CTRL1_REG_IOUT_CH1(x) (((x) & 0xF) << 4) |
| pmallick | 0:e8a1ba50c46b | 162 | #define AD7124_IO_CTRL1_REG_IOUT_CH0(x) (((x) & 0xF) << 0) |
| pmallick | 0:e8a1ba50c46b | 163 | |
| pmallick | 0:e8a1ba50c46b | 164 | /* IO_Control_1 AD7124-8 specific bits */ |
| pmallick | 0:e8a1ba50c46b | 165 | #define AD7124_8_IO_CTRL1_REG_GPIO_DAT4 (1 << 23) |
| pmallick | 0:e8a1ba50c46b | 166 | #define AD7124_8_IO_CTRL1_REG_GPIO_DAT3 (1 << 22) |
| pmallick | 0:e8a1ba50c46b | 167 | #define AD7124_8_IO_CTRL1_REG_GPIO_DAT2 (1 << 21) |
| pmallick | 0:e8a1ba50c46b | 168 | #define AD7124_8_IO_CTRL1_REG_GPIO_DAT1 (1 << 20) |
| pmallick | 0:e8a1ba50c46b | 169 | #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL4 (1 << 19) |
| pmallick | 0:e8a1ba50c46b | 170 | #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL3 (1 << 18) |
| pmallick | 0:e8a1ba50c46b | 171 | #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL2 (1 << 17) |
| pmallick | 0:e8a1ba50c46b | 172 | #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL1 (1 << 16) |
| pmallick | 0:e8a1ba50c46b | 173 | |
| pmallick | 0:e8a1ba50c46b | 174 | /* IO_Control_2 Register bits */ |
| pmallick | 0:e8a1ba50c46b | 175 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 15) |
| pmallick | 0:e8a1ba50c46b | 176 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 14) |
| pmallick | 0:e8a1ba50c46b | 177 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 11) |
| pmallick | 0:e8a1ba50c46b | 178 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 10) |
| pmallick | 0:e8a1ba50c46b | 179 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 5) |
| pmallick | 0:e8a1ba50c46b | 180 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 4) |
| pmallick | 0:e8a1ba50c46b | 181 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1) |
| pmallick | 0:e8a1ba50c46b | 182 | #define AD7124_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0) |
| pmallick | 0:e8a1ba50c46b | 183 | |
| pmallick | 0:e8a1ba50c46b | 184 | /* IO_Control_2 AD7124-8 specific bits */ |
| pmallick | 0:e8a1ba50c46b | 185 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS15 (1 << 15) |
| pmallick | 0:e8a1ba50c46b | 186 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS14 (1 << 14) |
| pmallick | 0:e8a1ba50c46b | 187 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS13 (1 << 13) |
| pmallick | 0:e8a1ba50c46b | 188 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS12 (1 << 12) |
| pmallick | 0:e8a1ba50c46b | 189 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS11 (1 << 11) |
| pmallick | 0:e8a1ba50c46b | 190 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS10 (1 << 10) |
| pmallick | 0:e8a1ba50c46b | 191 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS9 (1 << 9) |
| pmallick | 0:e8a1ba50c46b | 192 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS8 (1 << 8) |
| pmallick | 0:e8a1ba50c46b | 193 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 7) |
| pmallick | 0:e8a1ba50c46b | 194 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 6) |
| pmallick | 0:e8a1ba50c46b | 195 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 5) |
| pmallick | 0:e8a1ba50c46b | 196 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 4) |
| pmallick | 0:e8a1ba50c46b | 197 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 3) |
| pmallick | 0:e8a1ba50c46b | 198 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 2) |
| pmallick | 0:e8a1ba50c46b | 199 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1) |
| pmallick | 0:e8a1ba50c46b | 200 | #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0) |
| pmallick | 0:e8a1ba50c46b | 201 | |
| pmallick | 0:e8a1ba50c46b | 202 | /* ID Register bits */ |
| pmallick | 0:e8a1ba50c46b | 203 | #define AD7124_ID_REG_DEVICE_ID(x) (((x) & 0xF) << 4) |
| pmallick | 0:e8a1ba50c46b | 204 | #define AD7124_ID_REG_SILICON_REV(x) (((x) & 0xF) << 0) |
| pmallick | 0:e8a1ba50c46b | 205 | |
| pmallick | 0:e8a1ba50c46b | 206 | /* Error Register bits */ |
| pmallick | 0:e8a1ba50c46b | 207 | #define AD7124_ERR_REG_LDO_CAP_ERR (1 << 19) |
| pmallick | 0:e8a1ba50c46b | 208 | #define AD7124_ERR_REG_ADC_CAL_ERR (1 << 18) |
| pmallick | 0:e8a1ba50c46b | 209 | #define AD7124_ERR_REG_ADC_CONV_ERR (1 << 17) |
| pmallick | 0:e8a1ba50c46b | 210 | #define AD7124_ERR_REG_ADC_SAT_ERR (1 << 16) |
| pmallick | 0:e8a1ba50c46b | 211 | #define AD7124_ERR_REG_AINP_OV_ERR (1 << 15) |
| pmallick | 0:e8a1ba50c46b | 212 | #define AD7124_ERR_REG_AINP_UV_ERR (1 << 14) |
| pmallick | 0:e8a1ba50c46b | 213 | #define AD7124_ERR_REG_AINM_OV_ERR (1 << 13) |
| pmallick | 0:e8a1ba50c46b | 214 | #define AD7124_ERR_REG_AINM_UV_ERR (1 << 12) |
| pmallick | 0:e8a1ba50c46b | 215 | #define AD7124_ERR_REG_REF_DET_ERR (1 << 11) |
| pmallick | 0:e8a1ba50c46b | 216 | #define AD7124_ERR_REG_DLDO_PSM_ERR (1 << 9) |
| pmallick | 0:e8a1ba50c46b | 217 | #define AD7124_ERR_REG_ALDO_PSM_ERR (1 << 7) |
| pmallick | 0:e8a1ba50c46b | 218 | #define AD7124_ERR_REG_SPI_IGNORE_ERR (1 << 6) |
| pmallick | 0:e8a1ba50c46b | 219 | #define AD7124_ERR_REG_SPI_SLCK_CNT_ERR (1 << 5) |
| pmallick | 0:e8a1ba50c46b | 220 | #define AD7124_ERR_REG_SPI_READ_ERR (1 << 4) |
| pmallick | 0:e8a1ba50c46b | 221 | #define AD7124_ERR_REG_SPI_WRITE_ERR (1 << 3) |
| pmallick | 0:e8a1ba50c46b | 222 | #define AD7124_ERR_REG_SPI_CRC_ERR (1 << 2) |
| pmallick | 0:e8a1ba50c46b | 223 | #define AD7124_ERR_REG_MM_CRC_ERR (1 << 1) |
| pmallick | 0:e8a1ba50c46b | 224 | #define AD7124_ERR_REG_ROM_CRC_ERR (1 << 0) |
| pmallick | 0:e8a1ba50c46b | 225 | |
| pmallick | 0:e8a1ba50c46b | 226 | /* Error_En Register bits */ |
| pmallick | 0:e8a1ba50c46b | 227 | #define AD7124_ERREN_REG_MCLK_CNT_EN (1 << 22) |
| pmallick | 0:e8a1ba50c46b | 228 | #define AD7124_ERREN_REG_LDO_CAP_CHK_TEST_EN (1 << 21) |
| pmallick | 0:e8a1ba50c46b | 229 | #define AD7124_ERREN_REG_LDO_CAP_CHK(x) (((x) & 0x3) << 19) |
| pmallick | 0:e8a1ba50c46b | 230 | #define AD7124_ERREN_REG_ADC_CAL_ERR_EN (1 << 18) |
| pmallick | 0:e8a1ba50c46b | 231 | #define AD7124_ERREN_REG_ADC_CONV_ERR_EN (1 << 17) |
| pmallick | 0:e8a1ba50c46b | 232 | #define AD7124_ERREN_REG_ADC_SAT_ERR_EN (1 << 16) |
| pmallick | 0:e8a1ba50c46b | 233 | #define AD7124_ERREN_REG_AINP_OV_ERR_EN (1 << 15) |
| pmallick | 0:e8a1ba50c46b | 234 | #define AD7124_ERREN_REG_AINP_UV_ERR_EN (1 << 14) |
| pmallick | 0:e8a1ba50c46b | 235 | #define AD7124_ERREN_REG_AINM_OV_ERR_EN (1 << 13) |
| pmallick | 0:e8a1ba50c46b | 236 | #define AD7124_ERREN_REG_AINM_UV_ERR_EN (1 << 12) |
| pmallick | 0:e8a1ba50c46b | 237 | #define AD7124_ERREN_REG_REF_DET_ERR_EN (1 << 11) |
| pmallick | 0:e8a1ba50c46b | 238 | #define AD7124_ERREN_REG_DLDO_PSM_TRIP_TEST_EN (1 << 10) |
| pmallick | 0:e8a1ba50c46b | 239 | #define AD7124_ERREN_REG_DLDO_PSM_ERR_ERR (1 << 9) |
| pmallick | 0:e8a1ba50c46b | 240 | #define AD7124_ERREN_REG_ALDO_PSM_TRIP_TEST_EN (1 << 8) |
| pmallick | 0:e8a1ba50c46b | 241 | #define AD7124_ERREN_REG_ALDO_PSM_ERR_EN (1 << 7) |
| pmallick | 0:e8a1ba50c46b | 242 | #define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN (1 << 6) |
| pmallick | 0:e8a1ba50c46b | 243 | #define AD7124_ERREN_REG_SPI_SCLK_CNT_ERR_EN (1 << 5) |
| pmallick | 0:e8a1ba50c46b | 244 | #define AD7124_ERREN_REG_SPI_READ_ERR_EN (1 << 4) |
| pmallick | 0:e8a1ba50c46b | 245 | #define AD7124_ERREN_REG_SPI_WRITE_ERR_EN (1 << 3) |
| pmallick | 0:e8a1ba50c46b | 246 | #define AD7124_ERREN_REG_SPI_CRC_ERR_EN (1 << 2) |
| pmallick | 0:e8a1ba50c46b | 247 | #define AD7124_ERREN_REG_MM_CRC_ERR_EN (1 << 1) |
| pmallick | 0:e8a1ba50c46b | 248 | #define AD7124_ERREN_REG_ROM_CRC_ERR_EN (1 << 0) |
| pmallick | 0:e8a1ba50c46b | 249 | |
| pmallick | 0:e8a1ba50c46b | 250 | /* Channel Registers 0-15 bits */ |
| pmallick | 0:e8a1ba50c46b | 251 | #define AD7124_CH_MAP_REG_CH_ENABLE_RD(x) (((x) >> 15) & 0x1) |
| pmallick | 0:e8a1ba50c46b | 252 | #define AD7124_CH_MAP_REG_CH_ENABLE (1 << 15) |
| pmallick | 0:e8a1ba50c46b | 253 | #define AD7124_CH_MAP_REG_SETUP_MSK GENMASK(14, 12) |
| pmallick | 0:e8a1ba50c46b | 254 | #define AD7124_CH_MAP_REG_SETUP_RD(x) (((x) >> 12) & 0x7) |
| pmallick | 0:e8a1ba50c46b | 255 | #define AD7124_CH_MAP_REG_SETUP(x) (((x) & 0x7) << 12) |
| pmallick | 0:e8a1ba50c46b | 256 | #define AD7124_CH_MAP_REG_AINP_MSK GENMASK(9, 5) |
| pmallick | 0:e8a1ba50c46b | 257 | #define AD7124_CH_MAP_REG_AINP_RD(x) (((x) >> 5) & 0x1F) |
| pmallick | 0:e8a1ba50c46b | 258 | #define AD7124_CH_MAP_REG_AINP(x) (((x) & 0x1F) << 5) |
| pmallick | 0:e8a1ba50c46b | 259 | #define AD7124_CH_MAP_REG_AINM_MSK GENMASK(4, 0) |
| pmallick | 0:e8a1ba50c46b | 260 | #define AD7124_CH_MAP_REG_AINM_RD(x) (((x) >> 0) & 0x1F) |
| pmallick | 0:e8a1ba50c46b | 261 | #define AD7124_CH_MAP_REG_AINM(x) (((x) & 0x1F) << 0) |
| pmallick | 0:e8a1ba50c46b | 262 | |
| pmallick | 0:e8a1ba50c46b | 263 | /* Configuration Registers 0-7 bits */ |
| pmallick | 0:e8a1ba50c46b | 264 | #define AD7124_CFG_REG_BIPOLAR_RD(x) (((x) >> 11) & 0x1) |
| pmallick | 0:e8a1ba50c46b | 265 | #define AD7124_CFG_REG_BIPOLAR (1 << 11) |
| pmallick | 0:e8a1ba50c46b | 266 | #define AD7124_CFG_REG_BURNOUT_RD(x) (((x) >> 9) & 0x3) |
| pmallick | 0:e8a1ba50c46b | 267 | #define AD7124_CFG_REG_BURNOUT(x) (((x) & 0x3) << 9) |
| pmallick | 0:e8a1ba50c46b | 268 | #define AD7124_CFG_REG_REF_BUFP_RD(x) (((x) >> 8) & 0x1) |
| pmallick | 0:e8a1ba50c46b | 269 | #define AD7124_CFG_REG_REF_BUFP (1 << 8) |
| pmallick | 0:e8a1ba50c46b | 270 | #define AD7124_CFG_REG_REF_BUFM_RD(x) (((x) >> 7) & 0x1) |
| pmallick | 0:e8a1ba50c46b | 271 | #define AD7124_CFG_REG_REF_BUFM (1 << 7) |
| pmallick | 0:e8a1ba50c46b | 272 | #define AD7124_CFG_REG_AIN_BUFP_RD(x) (((x) >> 6) & 0x1) |
| pmallick | 0:e8a1ba50c46b | 273 | #define AD7124_CFG_REG_AIN_BUFP (1 << 6) |
| pmallick | 0:e8a1ba50c46b | 274 | #define AD7124_CFG_REG_AINM_BUFP_RD(x) (((x) >> 5) & 0x1) |
| pmallick | 0:e8a1ba50c46b | 275 | #define AD7124_CFG_REG_AINN_BUFM (1 << 5) |
| pmallick | 0:e8a1ba50c46b | 276 | #define AD7124_CFG_REG_REF_SEL_MSK GENMASK(4, 3) |
| pmallick | 0:e8a1ba50c46b | 277 | #define AD7124_CFG_REG_REF_SEL_RD(x) (((x) >> 3) & 0x3) |
| pmallick | 0:e8a1ba50c46b | 278 | #define AD7124_CFG_REG_REF_SEL(x) (((x) & 0x3) << 3) |
| pmallick | 0:e8a1ba50c46b | 279 | #define AD7124_CFG_REG_PGA_MSK GENMASK(2, 0) |
| pmallick | 0:e8a1ba50c46b | 280 | #define AD7124_CFG_REG_PGA_RD(x) (((x) >> 0) & 0x7) |
| pmallick | 0:e8a1ba50c46b | 281 | #define AD7124_CFG_REG_PGA(x) (((x) & 0x7) << 0) |
| pmallick | 0:e8a1ba50c46b | 282 | |
| pmallick | 0:e8a1ba50c46b | 283 | /* Filter Register 0-7 bits */ |
| pmallick | 0:e8a1ba50c46b | 284 | #define AD7124_FILT_REG_FILTER_MSK GENMASK(23, 21) |
| pmallick | 0:e8a1ba50c46b | 285 | #define AD7124_FILT_REG_FILTER_RD(x) (((x) >> 21) & 0x7) |
| pmallick | 0:e8a1ba50c46b | 286 | #define AD7124_FILT_REG_FILTER(x) (((x) & 0x7) << 21) |
| pmallick | 0:e8a1ba50c46b | 287 | #define AD7124_FILT_REG_REJ60 (1 << 20) |
| pmallick | 0:e8a1ba50c46b | 288 | #define AD7124_FILT_REG_POST_FILTER_MSK GENMASK(19, 17) |
| pmallick | 0:e8a1ba50c46b | 289 | #define AD7124_FILT_REG_POST_FILTER_RD(x) (((x) >> 17) & 0x7) |
| pmallick | 0:e8a1ba50c46b | 290 | #define AD7124_FILT_REG_POST_FILTER(x) (((x) & 0x7) << 17) |
| pmallick | 0:e8a1ba50c46b | 291 | #define AD7124_FILT_REG_SINGLE_CYCLE (1 << 16) |
| pmallick | 0:e8a1ba50c46b | 292 | #define AD7124_FILT_REG_FS_MSK GENMASK(10, 0) |
| pmallick | 0:e8a1ba50c46b | 293 | #define AD7124_FILT_REG_FS_RD(x) (((x) >> 0) & 0x7FF) |
| pmallick | 0:e8a1ba50c46b | 294 | #define AD7124_FILT_REG_FS(x) (((x) & 0x7FF) << 0) |
| pmallick | 0:e8a1ba50c46b | 295 | |
| pmallick | 0:e8a1ba50c46b | 296 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 297 | /*************************** Types Declarations *******************************/ |
| pmallick | 0:e8a1ba50c46b | 298 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 299 | |
| pmallick | 0:e8a1ba50c46b | 300 | /*! Device register info */ |
| pmallick | 0:e8a1ba50c46b | 301 | struct ad7124_st_reg { |
| pmallick | 0:e8a1ba50c46b | 302 | int32_t addr; |
| pmallick | 0:e8a1ba50c46b | 303 | int32_t value; |
| pmallick | 0:e8a1ba50c46b | 304 | int32_t size; |
| pmallick | 0:e8a1ba50c46b | 305 | int32_t rw; |
| pmallick | 0:e8a1ba50c46b | 306 | }; |
| pmallick | 0:e8a1ba50c46b | 307 | |
| pmallick | 0:e8a1ba50c46b | 308 | /*! AD7124 registers list*/ |
| pmallick | 0:e8a1ba50c46b | 309 | enum ad7124_registers { |
| pmallick | 0:e8a1ba50c46b | 310 | AD7124_Status = 0x00, |
| pmallick | 0:e8a1ba50c46b | 311 | AD7124_ADC_Control, |
| pmallick | 0:e8a1ba50c46b | 312 | AD7124_Data, |
| pmallick | 0:e8a1ba50c46b | 313 | AD7124_IOCon1, |
| pmallick | 0:e8a1ba50c46b | 314 | AD7124_IOCon2, |
| pmallick | 0:e8a1ba50c46b | 315 | AD7124_ID, |
| pmallick | 0:e8a1ba50c46b | 316 | AD7124_Error, |
| pmallick | 0:e8a1ba50c46b | 317 | AD7124_Error_En, |
| pmallick | 0:e8a1ba50c46b | 318 | AD7124_Mclk_Count, |
| pmallick | 0:e8a1ba50c46b | 319 | AD7124_Channel_0, |
| pmallick | 0:e8a1ba50c46b | 320 | AD7124_Channel_1, |
| pmallick | 0:e8a1ba50c46b | 321 | AD7124_Channel_2, |
| pmallick | 0:e8a1ba50c46b | 322 | AD7124_Channel_3, |
| pmallick | 0:e8a1ba50c46b | 323 | AD7124_Channel_4, |
| pmallick | 0:e8a1ba50c46b | 324 | AD7124_Channel_5, |
| pmallick | 0:e8a1ba50c46b | 325 | AD7124_Channel_6, |
| pmallick | 0:e8a1ba50c46b | 326 | AD7124_Channel_7, |
| pmallick | 0:e8a1ba50c46b | 327 | AD7124_Channel_8, |
| pmallick | 0:e8a1ba50c46b | 328 | AD7124_Channel_9, |
| pmallick | 0:e8a1ba50c46b | 329 | AD7124_Channel_10, |
| pmallick | 0:e8a1ba50c46b | 330 | AD7124_Channel_11, |
| pmallick | 0:e8a1ba50c46b | 331 | AD7124_Channel_12, |
| pmallick | 0:e8a1ba50c46b | 332 | AD7124_Channel_13, |
| pmallick | 0:e8a1ba50c46b | 333 | AD7124_Channel_14, |
| pmallick | 0:e8a1ba50c46b | 334 | AD7124_Channel_15, |
| pmallick | 0:e8a1ba50c46b | 335 | AD7124_Config_0, |
| pmallick | 0:e8a1ba50c46b | 336 | AD7124_Config_1, |
| pmallick | 0:e8a1ba50c46b | 337 | AD7124_Config_2, |
| pmallick | 0:e8a1ba50c46b | 338 | AD7124_Config_3, |
| pmallick | 0:e8a1ba50c46b | 339 | AD7124_Config_4, |
| pmallick | 0:e8a1ba50c46b | 340 | AD7124_Config_5, |
| pmallick | 0:e8a1ba50c46b | 341 | AD7124_Config_6, |
| pmallick | 0:e8a1ba50c46b | 342 | AD7124_Config_7, |
| pmallick | 0:e8a1ba50c46b | 343 | AD7124_Filter_0, |
| pmallick | 0:e8a1ba50c46b | 344 | AD7124_Filter_1, |
| pmallick | 0:e8a1ba50c46b | 345 | AD7124_Filter_2, |
| pmallick | 0:e8a1ba50c46b | 346 | AD7124_Filter_3, |
| pmallick | 0:e8a1ba50c46b | 347 | AD7124_Filter_4, |
| pmallick | 0:e8a1ba50c46b | 348 | AD7124_Filter_5, |
| pmallick | 0:e8a1ba50c46b | 349 | AD7124_Filter_6, |
| pmallick | 0:e8a1ba50c46b | 350 | AD7124_Filter_7, |
| pmallick | 0:e8a1ba50c46b | 351 | AD7124_Offset_0, |
| pmallick | 0:e8a1ba50c46b | 352 | AD7124_Offset_1, |
| pmallick | 0:e8a1ba50c46b | 353 | AD7124_Offset_2, |
| pmallick | 0:e8a1ba50c46b | 354 | AD7124_Offset_3, |
| pmallick | 0:e8a1ba50c46b | 355 | AD7124_Offset_4, |
| pmallick | 0:e8a1ba50c46b | 356 | AD7124_Offset_5, |
| pmallick | 0:e8a1ba50c46b | 357 | AD7124_Offset_6, |
| pmallick | 0:e8a1ba50c46b | 358 | AD7124_Offset_7, |
| pmallick | 0:e8a1ba50c46b | 359 | AD7124_Gain_0, |
| pmallick | 0:e8a1ba50c46b | 360 | AD7124_Gain_1, |
| pmallick | 0:e8a1ba50c46b | 361 | AD7124_Gain_2, |
| pmallick | 0:e8a1ba50c46b | 362 | AD7124_Gain_3, |
| pmallick | 0:e8a1ba50c46b | 363 | AD7124_Gain_4, |
| pmallick | 0:e8a1ba50c46b | 364 | AD7124_Gain_5, |
| pmallick | 0:e8a1ba50c46b | 365 | AD7124_Gain_6, |
| pmallick | 0:e8a1ba50c46b | 366 | AD7124_Gain_7, |
| pmallick | 0:e8a1ba50c46b | 367 | AD7124_REG_NO |
| pmallick | 0:e8a1ba50c46b | 368 | }; |
| pmallick | 0:e8a1ba50c46b | 369 | |
| pmallick | 0:e8a1ba50c46b | 370 | /* |
| pmallick | 0:e8a1ba50c46b | 371 | * The structure describes the device and is used with the ad7124 driver. |
| pmallick | 0:e8a1ba50c46b | 372 | * @spi_desc: A reference to the SPI configuration of the device. |
| pmallick | 0:e8a1ba50c46b | 373 | * @regs: A reference to the register list of the device that the user must |
| pmallick | 0:e8a1ba50c46b | 374 | * provide when calling the Setup() function. |
| pmallick | 0:e8a1ba50c46b | 375 | * @userCRC: Whether to do or not a cyclic redundancy check on SPI transfers. |
| pmallick | 0:e8a1ba50c46b | 376 | * @check_ready: When enabled all register read and write calls will first wait |
| pmallick | 0:e8a1ba50c46b | 377 | * until the device is ready to accept user requests. |
| pmallick | 0:e8a1ba50c46b | 378 | * @spi_rdy_poll_cnt: Number of times the driver should read the Error register |
| pmallick | 0:e8a1ba50c46b | 379 | * to check if the device is ready to accept user requests, |
| pmallick | 0:e8a1ba50c46b | 380 | * before a timeout error will be issued. |
| pmallick | 0:e8a1ba50c46b | 381 | */ |
| pmallick | 0:e8a1ba50c46b | 382 | struct ad7124_dev { |
| pmallick | 0:e8a1ba50c46b | 383 | /* SPI */ |
| pmallick | 0:e8a1ba50c46b | 384 | spi_desc *spi_desc; |
| pmallick | 0:e8a1ba50c46b | 385 | /* Device Settings */ |
| pmallick | 0:e8a1ba50c46b | 386 | struct ad7124_st_reg *regs; |
| pmallick | 0:e8a1ba50c46b | 387 | int16_t use_crc; |
| pmallick | 0:e8a1ba50c46b | 388 | int16_t check_ready; |
| pmallick | 0:e8a1ba50c46b | 389 | int16_t spi_rdy_poll_cnt; |
| pmallick | 0:e8a1ba50c46b | 390 | }; |
| pmallick | 0:e8a1ba50c46b | 391 | |
| pmallick | 0:e8a1ba50c46b | 392 | struct ad7124_init_param { |
| pmallick | 0:e8a1ba50c46b | 393 | /* SPI */ |
| pmallick | 0:e8a1ba50c46b | 394 | spi_init_param spi_init; |
| pmallick | 0:e8a1ba50c46b | 395 | /* Device Settings */ |
| pmallick | 0:e8a1ba50c46b | 396 | struct ad7124_st_reg *regs; |
| pmallick | 0:e8a1ba50c46b | 397 | int16_t spi_rdy_poll_cnt; |
| pmallick | 0:e8a1ba50c46b | 398 | }; |
| pmallick | 0:e8a1ba50c46b | 399 | |
| pmallick | 0:e8a1ba50c46b | 400 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 401 | /******************* AD7124 Constants *****************************************/ |
| pmallick | 0:e8a1ba50c46b | 402 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 403 | #define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */ |
| pmallick | 0:e8a1ba50c46b | 404 | #define AD7124_DISABLE_CRC 0 |
| pmallick | 0:e8a1ba50c46b | 405 | #define AD7124_USE_CRC 1 |
| pmallick | 0:e8a1ba50c46b | 406 | |
| pmallick | 0:e8a1ba50c46b | 407 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 408 | /************************ Functions Declarations ******************************/ |
| pmallick | 0:e8a1ba50c46b | 409 | /******************************************************************************/ |
| pmallick | 0:e8a1ba50c46b | 410 | |
| pmallick | 0:e8a1ba50c46b | 411 | /*! Reads the value of the specified register. */ |
| pmallick | 0:e8a1ba50c46b | 412 | int32_t ad7124_read_register(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 413 | struct ad7124_st_reg* p_reg); |
| pmallick | 0:e8a1ba50c46b | 414 | |
| pmallick | 0:e8a1ba50c46b | 415 | /*! Writes the value of the specified register. */ |
| pmallick | 0:e8a1ba50c46b | 416 | int32_t ad7124_write_register(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 417 | struct ad7124_st_reg reg); |
| pmallick | 0:e8a1ba50c46b | 418 | |
| pmallick | 0:e8a1ba50c46b | 419 | /*! Reads the value of the specified register without a device state check. */ |
| pmallick | 0:e8a1ba50c46b | 420 | int32_t ad7124_no_check_read_register(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 421 | struct ad7124_st_reg* p_reg); |
| pmallick | 0:e8a1ba50c46b | 422 | |
| pmallick | 0:e8a1ba50c46b | 423 | /*! Writes the value of the specified register without a device state check. */ |
| pmallick | 0:e8a1ba50c46b | 424 | int32_t ad7124_no_check_write_register(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 425 | struct ad7124_st_reg reg); |
| pmallick | 0:e8a1ba50c46b | 426 | |
| pmallick | 0:e8a1ba50c46b | 427 | /*! Resets the device. */ |
| pmallick | 0:e8a1ba50c46b | 428 | int32_t ad7124_reset(struct ad7124_dev *dev); |
| pmallick | 0:e8a1ba50c46b | 429 | |
| pmallick | 0:e8a1ba50c46b | 430 | /*! Waits until the device can accept read and write user actions. */ |
| pmallick | 0:e8a1ba50c46b | 431 | int32_t ad7124_wait_for_spi_ready(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 432 | uint32_t timeout); |
| pmallick | 0:e8a1ba50c46b | 433 | |
| pmallick | 0:e8a1ba50c46b | 434 | /*! Waits until the device finishes the power-on reset operation. */ |
| pmallick | 0:e8a1ba50c46b | 435 | int32_t ad7124_wait_to_power_on(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 436 | uint32_t timeout); |
| pmallick | 0:e8a1ba50c46b | 437 | |
| pmallick | 0:e8a1ba50c46b | 438 | /*! Waits until a new conversion result is available. */ |
| pmallick | 0:e8a1ba50c46b | 439 | int32_t ad7124_wait_for_conv_ready(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 440 | uint32_t timeout); |
| pmallick | 0:e8a1ba50c46b | 441 | |
| pmallick | 0:e8a1ba50c46b | 442 | /*! Reads the conversion result from the device. */ |
| pmallick | 0:e8a1ba50c46b | 443 | int32_t ad7124_read_data(struct ad7124_dev *dev, |
| pmallick | 0:e8a1ba50c46b | 444 | int32_t* p_data); |
| pmallick | 0:e8a1ba50c46b | 445 | |
| pmallick | 0:e8a1ba50c46b | 446 | /*! Computes the CRC checksum for a data buffer. */ |
| pmallick | 0:e8a1ba50c46b | 447 | uint8_t ad7124_compute_crc8(uint8_t* p_buf, |
| pmallick | 0:e8a1ba50c46b | 448 | uint8_t buf_size); |
| pmallick | 0:e8a1ba50c46b | 449 | |
| pmallick | 0:e8a1ba50c46b | 450 | /*! Updates the CRC settings. */ |
| pmallick | 0:e8a1ba50c46b | 451 | void ad7124_update_crcsetting(struct ad7124_dev *dev); |
| pmallick | 0:e8a1ba50c46b | 452 | |
| pmallick | 0:e8a1ba50c46b | 453 | /*! Updates the device SPI interface settings. */ |
| pmallick | 0:e8a1ba50c46b | 454 | void ad7124_update_dev_spi_settings(struct ad7124_dev *dev); |
| pmallick | 0:e8a1ba50c46b | 455 | |
| pmallick | 0:e8a1ba50c46b | 456 | /*! Initializes the AD7124. */ |
| pmallick | 0:e8a1ba50c46b | 457 | int32_t ad7124_setup(struct ad7124_dev **device, |
| pmallick | 0:e8a1ba50c46b | 458 | struct ad7124_init_param init_param); |
| pmallick | 0:e8a1ba50c46b | 459 | /*! Free the resources allocated by AD7124_Setup(). */ |
| pmallick | 0:e8a1ba50c46b | 460 | int32_t ad7124_remove(struct ad7124_dev *dev); |
| pmallick | 0:e8a1ba50c46b | 461 | |
| pmallick | 0:e8a1ba50c46b | 462 | #endif /* __AD7124_H__ */ |