Pratyush Mallick / Mbed OS nano_dac

this is testing

noos_mbed/drivers/adc/ad7124/ad7124.c@0:e8a1ba50c46b, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 19:12:57 2021 +0530
Revision:
0:e8a1ba50c46b
this is testing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 0:e8a1ba50c46b 1 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 2 * @file ad7124.c
pmallick 0:e8a1ba50c46b 3 * @brief AD7124 implementation file.
pmallick 0:e8a1ba50c46b 4 * @devices AD7124-4, AD7124-8
pmallick 0:e8a1ba50c46b 5 *
pmallick 0:e8a1ba50c46b 6 ********************************************************************************
pmallick 0:e8a1ba50c46b 7 * Copyright 2015-2019(c) Analog Devices, Inc.
pmallick 0:e8a1ba50c46b 8 *
pmallick 0:e8a1ba50c46b 9 * All rights reserved.
pmallick 0:e8a1ba50c46b 10 *
pmallick 0:e8a1ba50c46b 11 * Redistribution and use in source and binary forms, with or without modification,
pmallick 0:e8a1ba50c46b 12 * are permitted provided that the following conditions are met:
pmallick 0:e8a1ba50c46b 13 * - Redistributions of source code must retain the above copyright
pmallick 0:e8a1ba50c46b 14 * notice, this list of conditions and the following disclaimer.
pmallick 0:e8a1ba50c46b 15 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:e8a1ba50c46b 16 * notice, this list of conditions and the following disclaimer in
pmallick 0:e8a1ba50c46b 17 * the documentation and/or other materials provided with the
pmallick 0:e8a1ba50c46b 18 * distribution.
pmallick 0:e8a1ba50c46b 19 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:e8a1ba50c46b 20 * contributors may be used to endorse or promote products derived
pmallick 0:e8a1ba50c46b 21 * from this software without specific prior written permission.
pmallick 0:e8a1ba50c46b 22 * - The use of this software may or may not infringe the patent rights
pmallick 0:e8a1ba50c46b 23 * of one or more patent holders. This license does not release you
pmallick 0:e8a1ba50c46b 24 * from the requirement that you obtain separate licenses from these
pmallick 0:e8a1ba50c46b 25 * patent holders to use this software.
pmallick 0:e8a1ba50c46b 26 * - Use of the software either in source or binary form, must be run
pmallick 0:e8a1ba50c46b 27 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:e8a1ba50c46b 28 *
pmallick 0:e8a1ba50c46b 29 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
pmallick 0:e8a1ba50c46b 30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
pmallick 0:e8a1ba50c46b 31 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:e8a1ba50c46b 32 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
pmallick 0:e8a1ba50c46b 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
pmallick 0:e8a1ba50c46b 34 * INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
pmallick 0:e8a1ba50c46b 35 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
pmallick 0:e8a1ba50c46b 36 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
pmallick 0:e8a1ba50c46b 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
pmallick 0:e8a1ba50c46b 38 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:e8a1ba50c46b 39 *******************************************************************************/
pmallick 0:e8a1ba50c46b 40
pmallick 0:e8a1ba50c46b 41 /******************************************************************************/
pmallick 0:e8a1ba50c46b 42 /***************************** Include Files **********************************/
pmallick 0:e8a1ba50c46b 43 /******************************************************************************/
pmallick 0:e8a1ba50c46b 44 #include <stdlib.h>
pmallick 0:e8a1ba50c46b 45 #include <stdbool.h>
pmallick 0:e8a1ba50c46b 46 #include "ad7124.h"
pmallick 0:e8a1ba50c46b 47
pmallick 0:e8a1ba50c46b 48 /* Error codes */
pmallick 0:e8a1ba50c46b 49 #define INVALID_VAL -1 /* Invalid argument */
pmallick 0:e8a1ba50c46b 50 #define COMM_ERR -2 /* Communication error on receive */
pmallick 0:e8a1ba50c46b 51 #define TIMEOUT -3 /* A timeout has occured */
pmallick 0:e8a1ba50c46b 52
pmallick 0:e8a1ba50c46b 53 /*
pmallick 0:e8a1ba50c46b 54 * Post reset delay required to ensure all internal config done
pmallick 0:e8a1ba50c46b 55 * A time of 2ms should be enough based on the data sheet, but 4ms
pmallick 0:e8a1ba50c46b 56 * chosen to provide enough margin, in case mdelay is not accurate.
pmallick 0:e8a1ba50c46b 57 */
pmallick 0:e8a1ba50c46b 58 #define AD7124_POST_RESET_DELAY 4
pmallick 0:e8a1ba50c46b 59
pmallick 0:e8a1ba50c46b 60
pmallick 0:e8a1ba50c46b 61 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 62 * @brief Reads the value of the specified register without checking if the
pmallick 0:e8a1ba50c46b 63 * device is ready to accept user requests.
pmallick 0:e8a1ba50c46b 64 *
pmallick 0:e8a1ba50c46b 65 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 66 * @param p_reg - Pointer to the register structure holding info about the
pmallick 0:e8a1ba50c46b 67 * register to be read. The read value is stored inside the
pmallick 0:e8a1ba50c46b 68 * register structure.
pmallick 0:e8a1ba50c46b 69 *
pmallick 0:e8a1ba50c46b 70 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 71 *******************************************************************************/
pmallick 0:e8a1ba50c46b 72 int32_t ad7124_no_check_read_register(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 73 struct ad7124_st_reg* p_reg)
pmallick 0:e8a1ba50c46b 74 {
pmallick 0:e8a1ba50c46b 75 int32_t ret = 0;
pmallick 0:e8a1ba50c46b 76 uint8_t buffer[8] = {0, 0, 0, 0, 0, 0, 0, 0};
pmallick 0:e8a1ba50c46b 77 uint8_t i = 0;
pmallick 0:e8a1ba50c46b 78 uint8_t check8 = 0, add_status_length = 0;
pmallick 0:e8a1ba50c46b 79 uint8_t msg_buf[8] = {0, 0, 0, 0, 0, 0, 0, 0};
pmallick 0:e8a1ba50c46b 80
pmallick 0:e8a1ba50c46b 81 if(!dev || !p_reg)
pmallick 0:e8a1ba50c46b 82 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 83
pmallick 0:e8a1ba50c46b 84 /* Build the Command word */
pmallick 0:e8a1ba50c46b 85 buffer[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_RD |
pmallick 0:e8a1ba50c46b 86 AD7124_COMM_REG_RA(p_reg->addr);
pmallick 0:e8a1ba50c46b 87
pmallick 0:e8a1ba50c46b 88 /*
pmallick 0:e8a1ba50c46b 89 * If this is an AD7124_DATA register read, and the DATA_STATUS bit is set
pmallick 0:e8a1ba50c46b 90 * in ADC_CONTROL, need to read 4, not 3 bytes for DATA with STATUS
pmallick 0:e8a1ba50c46b 91 */
pmallick 0:e8a1ba50c46b 92 if ((p_reg->addr == AD7124_DATA_REG) &&
pmallick 0:e8a1ba50c46b 93 (dev->regs[AD7124_ADC_Control].value & AD7124_ADC_CTRL_REG_DATA_STATUS)) {
pmallick 0:e8a1ba50c46b 94 add_status_length = 1;
pmallick 0:e8a1ba50c46b 95 }
pmallick 0:e8a1ba50c46b 96
pmallick 0:e8a1ba50c46b 97 /* Read data from the device */
pmallick 0:e8a1ba50c46b 98 ret = spi_write_and_read(dev->spi_desc,
pmallick 0:e8a1ba50c46b 99 buffer,
pmallick 0:e8a1ba50c46b 100 ((dev->use_crc != AD7124_DISABLE_CRC) ? p_reg->size + 1
pmallick 0:e8a1ba50c46b 101 : p_reg->size) + 1 + add_status_length);
pmallick 0:e8a1ba50c46b 102 if(ret < 0)
pmallick 0:e8a1ba50c46b 103 return ret;
pmallick 0:e8a1ba50c46b 104
pmallick 0:e8a1ba50c46b 105 /* Check the CRC */
pmallick 0:e8a1ba50c46b 106 if(dev->use_crc == AD7124_USE_CRC) {
pmallick 0:e8a1ba50c46b 107 msg_buf[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_RD |
pmallick 0:e8a1ba50c46b 108 AD7124_COMM_REG_RA(p_reg->addr);
pmallick 0:e8a1ba50c46b 109 for(i = 1; i < p_reg->size + 2 + add_status_length; ++i) {
pmallick 0:e8a1ba50c46b 110 msg_buf[i] = buffer[i];
pmallick 0:e8a1ba50c46b 111 }
pmallick 0:e8a1ba50c46b 112 check8 = ad7124_compute_crc8(msg_buf, p_reg->size + 2 + add_status_length);
pmallick 0:e8a1ba50c46b 113 }
pmallick 0:e8a1ba50c46b 114
pmallick 0:e8a1ba50c46b 115 if(check8 != 0) {
pmallick 0:e8a1ba50c46b 116 /* ReadRegister checksum failed. */
pmallick 0:e8a1ba50c46b 117 return COMM_ERR;
pmallick 0:e8a1ba50c46b 118 }
pmallick 0:e8a1ba50c46b 119
pmallick 0:e8a1ba50c46b 120 /*
pmallick 0:e8a1ba50c46b 121 * if reading Data with 4 bytes, need to copy the status byte to the STATUS
pmallick 0:e8a1ba50c46b 122 * register struct value member
pmallick 0:e8a1ba50c46b 123 */
pmallick 0:e8a1ba50c46b 124 if (add_status_length) {
pmallick 0:e8a1ba50c46b 125 dev->regs[AD7124_Status].value = buffer[p_reg->size + 1];
pmallick 0:e8a1ba50c46b 126 }
pmallick 0:e8a1ba50c46b 127
pmallick 0:e8a1ba50c46b 128 /* Build the result */
pmallick 0:e8a1ba50c46b 129 p_reg->value = 0;
pmallick 0:e8a1ba50c46b 130 for(i = 1; i < p_reg->size + 1; i++) {
pmallick 0:e8a1ba50c46b 131 p_reg->value <<= 8;
pmallick 0:e8a1ba50c46b 132 p_reg->value += buffer[i];
pmallick 0:e8a1ba50c46b 133 }
pmallick 0:e8a1ba50c46b 134
pmallick 0:e8a1ba50c46b 135 return ret;
pmallick 0:e8a1ba50c46b 136 }
pmallick 0:e8a1ba50c46b 137
pmallick 0:e8a1ba50c46b 138 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 139 * @brief Writes the value of the specified register without checking if the
pmallick 0:e8a1ba50c46b 140 * device is ready to accept user requests.
pmallick 0:e8a1ba50c46b 141 *
pmallick 0:e8a1ba50c46b 142 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 143 * @param reg - Register structure holding info about the register to be written
pmallick 0:e8a1ba50c46b 144 *
pmallick 0:e8a1ba50c46b 145 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 146 *******************************************************************************/
pmallick 0:e8a1ba50c46b 147 int32_t ad7124_no_check_write_register(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 148 struct ad7124_st_reg reg)
pmallick 0:e8a1ba50c46b 149 {
pmallick 0:e8a1ba50c46b 150 int32_t ret = 0;
pmallick 0:e8a1ba50c46b 151 int32_t reg_value = 0;
pmallick 0:e8a1ba50c46b 152 uint8_t wr_buf[8] = {0, 0, 0, 0, 0, 0, 0, 0};
pmallick 0:e8a1ba50c46b 153 uint8_t i = 0;
pmallick 0:e8a1ba50c46b 154 uint8_t crc8 = 0;
pmallick 0:e8a1ba50c46b 155
pmallick 0:e8a1ba50c46b 156 if(!dev)
pmallick 0:e8a1ba50c46b 157 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 158
pmallick 0:e8a1ba50c46b 159 /* Build the Command word */
pmallick 0:e8a1ba50c46b 160 wr_buf[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_WR |
pmallick 0:e8a1ba50c46b 161 AD7124_COMM_REG_RA(reg.addr);
pmallick 0:e8a1ba50c46b 162
pmallick 0:e8a1ba50c46b 163 /* Fill the write buffer */
pmallick 0:e8a1ba50c46b 164 reg_value = reg.value;
pmallick 0:e8a1ba50c46b 165 for(i = 0; i < reg.size; i++) {
pmallick 0:e8a1ba50c46b 166 wr_buf[reg.size - i] = reg_value & 0xFF;
pmallick 0:e8a1ba50c46b 167 reg_value >>= 8;
pmallick 0:e8a1ba50c46b 168 }
pmallick 0:e8a1ba50c46b 169
pmallick 0:e8a1ba50c46b 170 /* Compute the CRC */
pmallick 0:e8a1ba50c46b 171 if(dev->use_crc != AD7124_DISABLE_CRC) {
pmallick 0:e8a1ba50c46b 172 crc8 = ad7124_compute_crc8(wr_buf, reg.size + 1);
pmallick 0:e8a1ba50c46b 173 wr_buf[reg.size + 1] = crc8;
pmallick 0:e8a1ba50c46b 174 }
pmallick 0:e8a1ba50c46b 175
pmallick 0:e8a1ba50c46b 176 /* Write data to the device */
pmallick 0:e8a1ba50c46b 177 ret = spi_write_and_read(dev->spi_desc,
pmallick 0:e8a1ba50c46b 178 wr_buf,
pmallick 0:e8a1ba50c46b 179 (dev->use_crc != AD7124_DISABLE_CRC) ? reg.size + 2
pmallick 0:e8a1ba50c46b 180 : reg.size + 1);
pmallick 0:e8a1ba50c46b 181
pmallick 0:e8a1ba50c46b 182 return ret;
pmallick 0:e8a1ba50c46b 183 }
pmallick 0:e8a1ba50c46b 184
pmallick 0:e8a1ba50c46b 185 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 186 * @brief Reads the value of the specified register only when the device is ready
pmallick 0:e8a1ba50c46b 187 * to accept user requests. If the device ready flag is deactivated the
pmallick 0:e8a1ba50c46b 188 * read operation will be executed without checking the device state.
pmallick 0:e8a1ba50c46b 189 *
pmallick 0:e8a1ba50c46b 190 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 191 * @param p_reg - Pointer to the register structure holding info about the
pmallick 0:e8a1ba50c46b 192 * register to be read. The read value is stored inside the
pmallick 0:e8a1ba50c46b 193 * register structure.
pmallick 0:e8a1ba50c46b 194 *
pmallick 0:e8a1ba50c46b 195 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 196 *******************************************************************************/
pmallick 0:e8a1ba50c46b 197 int32_t ad7124_read_register(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 198 struct ad7124_st_reg* p_reg)
pmallick 0:e8a1ba50c46b 199 {
pmallick 0:e8a1ba50c46b 200 int32_t ret;
pmallick 0:e8a1ba50c46b 201
pmallick 0:e8a1ba50c46b 202 if (p_reg->addr != AD7124_ERR_REG && dev->check_ready) {
pmallick 0:e8a1ba50c46b 203 ret = ad7124_wait_for_spi_ready(dev,
pmallick 0:e8a1ba50c46b 204 dev->spi_rdy_poll_cnt);
pmallick 0:e8a1ba50c46b 205 if (ret < 0)
pmallick 0:e8a1ba50c46b 206 return ret;
pmallick 0:e8a1ba50c46b 207 }
pmallick 0:e8a1ba50c46b 208 ret = ad7124_no_check_read_register(dev,
pmallick 0:e8a1ba50c46b 209 p_reg);
pmallick 0:e8a1ba50c46b 210
pmallick 0:e8a1ba50c46b 211 return ret;
pmallick 0:e8a1ba50c46b 212 }
pmallick 0:e8a1ba50c46b 213
pmallick 0:e8a1ba50c46b 214 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 215 * @brief Writes the value of the specified register only when the device is
pmallick 0:e8a1ba50c46b 216 * ready to accept user requests. If the device ready flag is deactivated
pmallick 0:e8a1ba50c46b 217 * the write operation will be executed without checking the device state.
pmallick 0:e8a1ba50c46b 218 *
pmallick 0:e8a1ba50c46b 219 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 220 * @param reg - Register structure holding info about the register to be written
pmallick 0:e8a1ba50c46b 221 *
pmallick 0:e8a1ba50c46b 222 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 223 *******************************************************************************/
pmallick 0:e8a1ba50c46b 224 int32_t ad7124_write_register(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 225 struct ad7124_st_reg p_reg)
pmallick 0:e8a1ba50c46b 226 {
pmallick 0:e8a1ba50c46b 227 int32_t ret;
pmallick 0:e8a1ba50c46b 228
pmallick 0:e8a1ba50c46b 229 if (dev->check_ready) {
pmallick 0:e8a1ba50c46b 230 ret = ad7124_wait_for_spi_ready(dev,
pmallick 0:e8a1ba50c46b 231 dev->spi_rdy_poll_cnt);
pmallick 0:e8a1ba50c46b 232 if (ret < 0)
pmallick 0:e8a1ba50c46b 233 return ret;
pmallick 0:e8a1ba50c46b 234 }
pmallick 0:e8a1ba50c46b 235 ret = ad7124_no_check_write_register(dev,
pmallick 0:e8a1ba50c46b 236 p_reg);
pmallick 0:e8a1ba50c46b 237
pmallick 0:e8a1ba50c46b 238 return ret;
pmallick 0:e8a1ba50c46b 239 }
pmallick 0:e8a1ba50c46b 240
pmallick 0:e8a1ba50c46b 241 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 242 * @brief Resets the device.
pmallick 0:e8a1ba50c46b 243 *
pmallick 0:e8a1ba50c46b 244 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 245 *
pmallick 0:e8a1ba50c46b 246 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 247 *******************************************************************************/
pmallick 0:e8a1ba50c46b 248 int32_t ad7124_reset(struct ad7124_dev *dev)
pmallick 0:e8a1ba50c46b 249 {
pmallick 0:e8a1ba50c46b 250 int32_t ret = 0;
pmallick 0:e8a1ba50c46b 251 uint8_t wr_buf[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
pmallick 0:e8a1ba50c46b 252
pmallick 0:e8a1ba50c46b 253 if(!dev)
pmallick 0:e8a1ba50c46b 254 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 255
pmallick 0:e8a1ba50c46b 256 ret = spi_write_and_read(dev->spi_desc,
pmallick 0:e8a1ba50c46b 257 wr_buf,
pmallick 0:e8a1ba50c46b 258 8);
pmallick 0:e8a1ba50c46b 259
pmallick 0:e8a1ba50c46b 260 /* CRC is disabled after reset */
pmallick 0:e8a1ba50c46b 261 dev->use_crc = AD7124_DISABLE_CRC;
pmallick 0:e8a1ba50c46b 262
pmallick 0:e8a1ba50c46b 263 /* Read POR bit to clear */
pmallick 0:e8a1ba50c46b 264 ret = ad7124_wait_to_power_on(dev,
pmallick 0:e8a1ba50c46b 265 dev->spi_rdy_poll_cnt);
pmallick 0:e8a1ba50c46b 266
pmallick 0:e8a1ba50c46b 267 mdelay(AD7124_POST_RESET_DELAY);
pmallick 0:e8a1ba50c46b 268
pmallick 0:e8a1ba50c46b 269 return ret;
pmallick 0:e8a1ba50c46b 270 }
pmallick 0:e8a1ba50c46b 271
pmallick 0:e8a1ba50c46b 272 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 273 * @brief Waits until the device can accept read and write user actions.
pmallick 0:e8a1ba50c46b 274 *
pmallick 0:e8a1ba50c46b 275 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 276 * @param timeout - Count representing the number of polls to be done until the
pmallick 0:e8a1ba50c46b 277 * function returns.
pmallick 0:e8a1ba50c46b 278 *
pmallick 0:e8a1ba50c46b 279 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 280 *******************************************************************************/
pmallick 0:e8a1ba50c46b 281 int32_t ad7124_wait_for_spi_ready(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 282 uint32_t timeout)
pmallick 0:e8a1ba50c46b 283 {
pmallick 0:e8a1ba50c46b 284 struct ad7124_st_reg *regs;
pmallick 0:e8a1ba50c46b 285 int32_t ret;
pmallick 0:e8a1ba50c46b 286 int8_t ready = 0;
pmallick 0:e8a1ba50c46b 287
pmallick 0:e8a1ba50c46b 288 if(!dev)
pmallick 0:e8a1ba50c46b 289 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 290
pmallick 0:e8a1ba50c46b 291 regs = dev->regs;
pmallick 0:e8a1ba50c46b 292
pmallick 0:e8a1ba50c46b 293 while(!ready && --timeout) {
pmallick 0:e8a1ba50c46b 294 /* Read the value of the Error Register */
pmallick 0:e8a1ba50c46b 295 ret = ad7124_read_register(dev, &regs[AD7124_Error]);
pmallick 0:e8a1ba50c46b 296 if(ret < 0)
pmallick 0:e8a1ba50c46b 297 return ret;
pmallick 0:e8a1ba50c46b 298
pmallick 0:e8a1ba50c46b 299 /* Check the SPI IGNORE Error bit in the Error Register */
pmallick 0:e8a1ba50c46b 300 ready = (regs[AD7124_Error].value &
pmallick 0:e8a1ba50c46b 301 AD7124_ERR_REG_SPI_IGNORE_ERR) == 0;
pmallick 0:e8a1ba50c46b 302 }
pmallick 0:e8a1ba50c46b 303
pmallick 0:e8a1ba50c46b 304 return timeout ? 0 : TIMEOUT;
pmallick 0:e8a1ba50c46b 305 }
pmallick 0:e8a1ba50c46b 306
pmallick 0:e8a1ba50c46b 307 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 308 * @brief Waits until the device finishes the power-on reset operation.
pmallick 0:e8a1ba50c46b 309 *
pmallick 0:e8a1ba50c46b 310 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 311 * @param timeout - Count representing the number of polls to be done until the
pmallick 0:e8a1ba50c46b 312 * function returns.
pmallick 0:e8a1ba50c46b 313 *
pmallick 0:e8a1ba50c46b 314 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 315 *******************************************************************************/
pmallick 0:e8a1ba50c46b 316 int32_t ad7124_wait_to_power_on(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 317 uint32_t timeout)
pmallick 0:e8a1ba50c46b 318 {
pmallick 0:e8a1ba50c46b 319 struct ad7124_st_reg *regs;
pmallick 0:e8a1ba50c46b 320 int32_t ret;
pmallick 0:e8a1ba50c46b 321 int8_t powered_on = 0;
pmallick 0:e8a1ba50c46b 322
pmallick 0:e8a1ba50c46b 323 if(!dev)
pmallick 0:e8a1ba50c46b 324 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 325
pmallick 0:e8a1ba50c46b 326 regs = dev->regs;
pmallick 0:e8a1ba50c46b 327
pmallick 0:e8a1ba50c46b 328 while(!powered_on && timeout--) {
pmallick 0:e8a1ba50c46b 329 ret = ad7124_read_register(dev,
pmallick 0:e8a1ba50c46b 330 &regs[AD7124_Status]);
pmallick 0:e8a1ba50c46b 331 if(ret < 0)
pmallick 0:e8a1ba50c46b 332 return ret;
pmallick 0:e8a1ba50c46b 333
pmallick 0:e8a1ba50c46b 334 /* Check the POR_FLAG bit in the Status Register */
pmallick 0:e8a1ba50c46b 335 powered_on = (regs[AD7124_Status].value &
pmallick 0:e8a1ba50c46b 336 AD7124_STATUS_REG_POR_FLAG) == 0;
pmallick 0:e8a1ba50c46b 337 }
pmallick 0:e8a1ba50c46b 338
pmallick 0:e8a1ba50c46b 339 return (timeout || powered_on) ? 0 : TIMEOUT;
pmallick 0:e8a1ba50c46b 340 }
pmallick 0:e8a1ba50c46b 341
pmallick 0:e8a1ba50c46b 342 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 343 * @brief Waits until a new conversion result is available.
pmallick 0:e8a1ba50c46b 344 *
pmallick 0:e8a1ba50c46b 345 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 346 * @param timeout - Count representing the number of polls to be done until the
pmallick 0:e8a1ba50c46b 347 * function returns if no new data is available.
pmallick 0:e8a1ba50c46b 348 *
pmallick 0:e8a1ba50c46b 349 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 350 *******************************************************************************/
pmallick 0:e8a1ba50c46b 351 int32_t ad7124_wait_for_conv_ready(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 352 uint32_t timeout)
pmallick 0:e8a1ba50c46b 353 {
pmallick 0:e8a1ba50c46b 354 struct ad7124_st_reg *regs;
pmallick 0:e8a1ba50c46b 355 int32_t ret;
pmallick 0:e8a1ba50c46b 356 int8_t ready = 0;
pmallick 0:e8a1ba50c46b 357
pmallick 0:e8a1ba50c46b 358 if(!dev)
pmallick 0:e8a1ba50c46b 359 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 360
pmallick 0:e8a1ba50c46b 361 regs = dev->regs;
pmallick 0:e8a1ba50c46b 362
pmallick 0:e8a1ba50c46b 363 while(!ready && --timeout) {
pmallick 0:e8a1ba50c46b 364 /* Read the value of the Status Register */
pmallick 0:e8a1ba50c46b 365 ret = ad7124_read_register(dev, &regs[AD7124_Status]);
pmallick 0:e8a1ba50c46b 366 if(ret < 0)
pmallick 0:e8a1ba50c46b 367 return ret;
pmallick 0:e8a1ba50c46b 368
pmallick 0:e8a1ba50c46b 369 /* Check the RDY bit in the Status Register */
pmallick 0:e8a1ba50c46b 370 ready = (regs[AD7124_Status].value &
pmallick 0:e8a1ba50c46b 371 AD7124_STATUS_REG_RDY) == 0;
pmallick 0:e8a1ba50c46b 372 }
pmallick 0:e8a1ba50c46b 373
pmallick 0:e8a1ba50c46b 374 return timeout ? 0 : TIMEOUT;
pmallick 0:e8a1ba50c46b 375 }
pmallick 0:e8a1ba50c46b 376
pmallick 0:e8a1ba50c46b 377 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 378 * @brief Reads the conversion result from the device.
pmallick 0:e8a1ba50c46b 379 *
pmallick 0:e8a1ba50c46b 380 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 381 * @param p_data - Pointer to store the read data.
pmallick 0:e8a1ba50c46b 382 *
pmallick 0:e8a1ba50c46b 383 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 384 *******************************************************************************/
pmallick 0:e8a1ba50c46b 385 int32_t ad7124_read_data(struct ad7124_dev *dev,
pmallick 0:e8a1ba50c46b 386 int32_t* p_data)
pmallick 0:e8a1ba50c46b 387 {
pmallick 0:e8a1ba50c46b 388 struct ad7124_st_reg *regs;
pmallick 0:e8a1ba50c46b 389 int32_t ret;
pmallick 0:e8a1ba50c46b 390
pmallick 0:e8a1ba50c46b 391 if(!dev)
pmallick 0:e8a1ba50c46b 392 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 393
pmallick 0:e8a1ba50c46b 394 regs = dev->regs;
pmallick 0:e8a1ba50c46b 395
pmallick 0:e8a1ba50c46b 396 /* Read the value of the Status Register */
pmallick 0:e8a1ba50c46b 397 ret = ad7124_read_register(dev, &regs[AD7124_Data]);
pmallick 0:e8a1ba50c46b 398
pmallick 0:e8a1ba50c46b 399 /* Get the read result */
pmallick 0:e8a1ba50c46b 400 *p_data = regs[AD7124_Data].value;
pmallick 0:e8a1ba50c46b 401
pmallick 0:e8a1ba50c46b 402 return ret;
pmallick 0:e8a1ba50c46b 403 }
pmallick 0:e8a1ba50c46b 404
pmallick 0:e8a1ba50c46b 405 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 406 * @brief Computes the CRC checksum for a data buffer.
pmallick 0:e8a1ba50c46b 407 *
pmallick 0:e8a1ba50c46b 408 * @param p_buf - Data buffer
pmallick 0:e8a1ba50c46b 409 * @param buf_size - Data buffer size in bytes
pmallick 0:e8a1ba50c46b 410 *
pmallick 0:e8a1ba50c46b 411 * @return Returns the computed CRC checksum.
pmallick 0:e8a1ba50c46b 412 *******************************************************************************/
pmallick 0:e8a1ba50c46b 413 uint8_t ad7124_compute_crc8(uint8_t * p_buf, uint8_t buf_size)
pmallick 0:e8a1ba50c46b 414 {
pmallick 0:e8a1ba50c46b 415 uint8_t i = 0;
pmallick 0:e8a1ba50c46b 416 uint8_t crc = 0;
pmallick 0:e8a1ba50c46b 417
pmallick 0:e8a1ba50c46b 418 while(buf_size) {
pmallick 0:e8a1ba50c46b 419 for(i = 0x80; i != 0; i >>= 1) {
pmallick 0:e8a1ba50c46b 420 bool cmp1 = (crc & 0x80) != 0;
pmallick 0:e8a1ba50c46b 421 bool cmp2 = (*p_buf & i) != 0;
pmallick 0:e8a1ba50c46b 422 if(cmp1 != cmp2) { /* MSB of CRC register XOR input Bit from Data */
pmallick 0:e8a1ba50c46b 423 crc <<= 1;
pmallick 0:e8a1ba50c46b 424 crc ^= AD7124_CRC8_POLYNOMIAL_REPRESENTATION;
pmallick 0:e8a1ba50c46b 425 } else {
pmallick 0:e8a1ba50c46b 426 crc <<= 1;
pmallick 0:e8a1ba50c46b 427 }
pmallick 0:e8a1ba50c46b 428 }
pmallick 0:e8a1ba50c46b 429 p_buf++;
pmallick 0:e8a1ba50c46b 430 buf_size--;
pmallick 0:e8a1ba50c46b 431 }
pmallick 0:e8a1ba50c46b 432 return crc;
pmallick 0:e8a1ba50c46b 433 }
pmallick 0:e8a1ba50c46b 434
pmallick 0:e8a1ba50c46b 435 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 436 * @brief Updates the CRC settings.
pmallick 0:e8a1ba50c46b 437 *
pmallick 0:e8a1ba50c46b 438 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 439 *
pmallick 0:e8a1ba50c46b 440 * @return None.
pmallick 0:e8a1ba50c46b 441 *******************************************************************************/
pmallick 0:e8a1ba50c46b 442 void ad7124_update_crcsetting(struct ad7124_dev *dev)
pmallick 0:e8a1ba50c46b 443 {
pmallick 0:e8a1ba50c46b 444 struct ad7124_st_reg *regs;
pmallick 0:e8a1ba50c46b 445
pmallick 0:e8a1ba50c46b 446 if(!dev)
pmallick 0:e8a1ba50c46b 447 return;
pmallick 0:e8a1ba50c46b 448
pmallick 0:e8a1ba50c46b 449 regs = dev->regs;
pmallick 0:e8a1ba50c46b 450
pmallick 0:e8a1ba50c46b 451 /* Get CRC State. */
pmallick 0:e8a1ba50c46b 452 if (regs[AD7124_Error_En].value & AD7124_ERREN_REG_SPI_CRC_ERR_EN) {
pmallick 0:e8a1ba50c46b 453 dev->use_crc = AD7124_USE_CRC;
pmallick 0:e8a1ba50c46b 454 } else {
pmallick 0:e8a1ba50c46b 455 dev->use_crc = AD7124_DISABLE_CRC;
pmallick 0:e8a1ba50c46b 456 }
pmallick 0:e8a1ba50c46b 457 }
pmallick 0:e8a1ba50c46b 458
pmallick 0:e8a1ba50c46b 459 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 460 * @brief Updates the device SPI interface settings.
pmallick 0:e8a1ba50c46b 461 *
pmallick 0:e8a1ba50c46b 462 * @param dev - The handler of the instance of the driver.
pmallick 0:e8a1ba50c46b 463 *
pmallick 0:e8a1ba50c46b 464 * @return None.
pmallick 0:e8a1ba50c46b 465 *******************************************************************************/
pmallick 0:e8a1ba50c46b 466 void ad7124_update_dev_spi_settings(struct ad7124_dev *dev)
pmallick 0:e8a1ba50c46b 467 {
pmallick 0:e8a1ba50c46b 468 struct ad7124_st_reg *regs;
pmallick 0:e8a1ba50c46b 469
pmallick 0:e8a1ba50c46b 470 if(!dev)
pmallick 0:e8a1ba50c46b 471 return;
pmallick 0:e8a1ba50c46b 472
pmallick 0:e8a1ba50c46b 473 regs = dev->regs;
pmallick 0:e8a1ba50c46b 474
pmallick 0:e8a1ba50c46b 475 if (regs[AD7124_Error_En].value & AD7124_ERREN_REG_SPI_IGNORE_ERR_EN) {
pmallick 0:e8a1ba50c46b 476 dev->check_ready = 1;
pmallick 0:e8a1ba50c46b 477 } else {
pmallick 0:e8a1ba50c46b 478 dev->check_ready = 0;
pmallick 0:e8a1ba50c46b 479 }
pmallick 0:e8a1ba50c46b 480 }
pmallick 0:e8a1ba50c46b 481
pmallick 0:e8a1ba50c46b 482 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 483 * @brief Initializes the AD7124.
pmallick 0:e8a1ba50c46b 484 *
pmallick 0:e8a1ba50c46b 485 * @param device - The device structure.
pmallick 0:e8a1ba50c46b 486 * @param init_param - The structure that contains the device initial
pmallick 0:e8a1ba50c46b 487 * parameters.
pmallick 0:e8a1ba50c46b 488 *
pmallick 0:e8a1ba50c46b 489 * @return Returns 0 for success or negative error code.
pmallick 0:e8a1ba50c46b 490 *******************************************************************************/
pmallick 0:e8a1ba50c46b 491 int32_t ad7124_setup(struct ad7124_dev **device,
pmallick 0:e8a1ba50c46b 492 struct ad7124_init_param init_param)
pmallick 0:e8a1ba50c46b 493 {
pmallick 0:e8a1ba50c46b 494 int32_t ret;
pmallick 0:e8a1ba50c46b 495 enum ad7124_registers reg_nr;
pmallick 0:e8a1ba50c46b 496 struct ad7124_dev *dev;
pmallick 0:e8a1ba50c46b 497
pmallick 0:e8a1ba50c46b 498 dev = (struct ad7124_dev *)malloc(sizeof(*dev));
pmallick 0:e8a1ba50c46b 499 if (!dev)
pmallick 0:e8a1ba50c46b 500 return INVALID_VAL;
pmallick 0:e8a1ba50c46b 501
pmallick 0:e8a1ba50c46b 502 dev->regs = init_param.regs;
pmallick 0:e8a1ba50c46b 503 dev->spi_rdy_poll_cnt = init_param.spi_rdy_poll_cnt;
pmallick 0:e8a1ba50c46b 504
pmallick 0:e8a1ba50c46b 505 /* Initialize the SPI communication. */
pmallick 0:e8a1ba50c46b 506 ret = spi_init(&dev->spi_desc, &init_param.spi_init);
pmallick 0:e8a1ba50c46b 507 if (ret < 0)
pmallick 0:e8a1ba50c46b 508 return ret;
pmallick 0:e8a1ba50c46b 509
pmallick 0:e8a1ba50c46b 510 /* Reset the device interface.*/
pmallick 0:e8a1ba50c46b 511 ret = ad7124_reset(dev);
pmallick 0:e8a1ba50c46b 512 if (ret < 0)
pmallick 0:e8a1ba50c46b 513 return ret;
pmallick 0:e8a1ba50c46b 514
pmallick 0:e8a1ba50c46b 515 /* Update the device structure with power-on/reset settings */
pmallick 0:e8a1ba50c46b 516 dev->check_ready = 1;
pmallick 0:e8a1ba50c46b 517
pmallick 0:e8a1ba50c46b 518 /* Initialize registers AD7124_ADC_Control through AD7124_Filter_7. */
pmallick 0:e8a1ba50c46b 519 for(reg_nr = AD7124_Status; (reg_nr < AD7124_Offset_0) && !(ret < 0);
pmallick 0:e8a1ba50c46b 520 reg_nr++) {
pmallick 0:e8a1ba50c46b 521 if (dev->regs[reg_nr].rw == AD7124_RW) {
pmallick 0:e8a1ba50c46b 522 ret = ad7124_write_register(dev, dev->regs[reg_nr]);
pmallick 0:e8a1ba50c46b 523 if (ret < 0)
pmallick 0:e8a1ba50c46b 524 break;
pmallick 0:e8a1ba50c46b 525 }
pmallick 0:e8a1ba50c46b 526
pmallick 0:e8a1ba50c46b 527 /* Get CRC State and device SPI interface settings */
pmallick 0:e8a1ba50c46b 528 if (reg_nr == AD7124_Error_En) {
pmallick 0:e8a1ba50c46b 529 ad7124_update_crcsetting(dev);
pmallick 0:e8a1ba50c46b 530 ad7124_update_dev_spi_settings(dev);
pmallick 0:e8a1ba50c46b 531 }
pmallick 0:e8a1ba50c46b 532 }
pmallick 0:e8a1ba50c46b 533
pmallick 0:e8a1ba50c46b 534 *device = dev;
pmallick 0:e8a1ba50c46b 535
pmallick 0:e8a1ba50c46b 536 return ret;
pmallick 0:e8a1ba50c46b 537 }
pmallick 0:e8a1ba50c46b 538
pmallick 0:e8a1ba50c46b 539 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 540 * @brief Free the resources allocated by AD7124_Setup().
pmallick 0:e8a1ba50c46b 541 *
pmallick 0:e8a1ba50c46b 542 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 543 *
pmallick 0:e8a1ba50c46b 544 * @return SUCCESS in case of success, negative error code otherwise.
pmallick 0:e8a1ba50c46b 545 *******************************************************************************/
pmallick 0:e8a1ba50c46b 546 int32_t ad7124_remove(struct ad7124_dev *dev)
pmallick 0:e8a1ba50c46b 547 {
pmallick 0:e8a1ba50c46b 548 int32_t ret;
pmallick 0:e8a1ba50c46b 549
pmallick 0:e8a1ba50c46b 550 ret = spi_remove(dev->spi_desc);
pmallick 0:e8a1ba50c46b 551
pmallick 0:e8a1ba50c46b 552 free(dev);
pmallick 0:e8a1ba50c46b 553
pmallick 0:e8a1ba50c46b 554 return ret;
pmallick 0:e8a1ba50c46b 555 }