Pratyush Mallick / Mbed OS nano_dac

this is testing

noos_mbed/drivers/adc-dac/ad5592r/ad5592r-base.h@0:e8a1ba50c46b, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 19:12:57 2021 +0530
Revision:
0:e8a1ba50c46b
this is testing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 0:e8a1ba50c46b 1 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 2 * @file ad5592r-base.h
pmallick 0:e8a1ba50c46b 3 * @brief Header file of AD5592R Base Driver.
pmallick 0:e8a1ba50c46b 4 * @author Mircea Caprioru (mircea.caprioru@analog.com)
pmallick 0:e8a1ba50c46b 5 ********************************************************************************
pmallick 0:e8a1ba50c46b 6 * Copyright 2018, 2020(c) Analog Devices, Inc.
pmallick 0:e8a1ba50c46b 7 *
pmallick 0:e8a1ba50c46b 8 * All rights reserved.
pmallick 0:e8a1ba50c46b 9 *
pmallick 0:e8a1ba50c46b 10 * Redistribution and use in source and binary forms, with or without
pmallick 0:e8a1ba50c46b 11 * modification, are permitted provided that the following conditions are met:
pmallick 0:e8a1ba50c46b 12 * - Redistributions of source code must retain the above copyright
pmallick 0:e8a1ba50c46b 13 * notice, this list of conditions and the following disclaimer.
pmallick 0:e8a1ba50c46b 14 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:e8a1ba50c46b 15 * notice, this list of conditions and the following disclaimer in
pmallick 0:e8a1ba50c46b 16 * the documentation and/or other materials provided with the
pmallick 0:e8a1ba50c46b 17 * distribution.
pmallick 0:e8a1ba50c46b 18 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:e8a1ba50c46b 19 * contributors may be used to endorse or promote products derived
pmallick 0:e8a1ba50c46b 20 * from this software without specific prior written permission.
pmallick 0:e8a1ba50c46b 21 * - The use of this software may or may not infringe the patent rights
pmallick 0:e8a1ba50c46b 22 * of one or more patent holders. This license does not release you
pmallick 0:e8a1ba50c46b 23 * from the requirement that you obtain separate licenses from these
pmallick 0:e8a1ba50c46b 24 * patent holders to use this software.
pmallick 0:e8a1ba50c46b 25 * - Use of the software either in source or binary form, must be run
pmallick 0:e8a1ba50c46b 26 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:e8a1ba50c46b 27 *
pmallick 0:e8a1ba50c46b 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:e8a1ba50c46b 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:e8a1ba50c46b 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:e8a1ba50c46b 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:e8a1ba50c46b 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:e8a1ba50c46b 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 0:e8a1ba50c46b 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 0:e8a1ba50c46b 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 0:e8a1ba50c46b 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 0:e8a1ba50c46b 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:e8a1ba50c46b 38 *******************************************************************************/
pmallick 0:e8a1ba50c46b 39 #ifndef AD5592R_BASE_H_
pmallick 0:e8a1ba50c46b 40 #define AD5592R_BASE_H_
pmallick 0:e8a1ba50c46b 41
pmallick 0:e8a1ba50c46b 42 #include "stdint.h"
pmallick 0:e8a1ba50c46b 43 #include "platform_drivers.h"
pmallick 0:e8a1ba50c46b 44
pmallick 0:e8a1ba50c46b 45 #include <stdbool.h>
pmallick 0:e8a1ba50c46b 46
pmallick 0:e8a1ba50c46b 47 #define CH_MODE_UNUSED 0
pmallick 0:e8a1ba50c46b 48 #define CH_MODE_ADC 1
pmallick 0:e8a1ba50c46b 49 #define CH_MODE_DAC 2
pmallick 0:e8a1ba50c46b 50 #define CH_MODE_DAC_AND_ADC 3
pmallick 0:e8a1ba50c46b 51 #define CH_MODE_GPI 4
pmallick 0:e8a1ba50c46b 52 #define CH_MODE_GPO 5
pmallick 0:e8a1ba50c46b 53
pmallick 0:e8a1ba50c46b 54 #define CH_OFFSTATE_PULLDOWN 0
pmallick 0:e8a1ba50c46b 55 #define CH_OFFSTATE_OUT_LOW 1
pmallick 0:e8a1ba50c46b 56 #define CH_OFFSTATE_OUT_HIGH 2
pmallick 0:e8a1ba50c46b 57 #define CH_OFFSTATE_OUT_TRISTATE 3
pmallick 0:e8a1ba50c46b 58
pmallick 0:e8a1ba50c46b 59 enum ad5592r_registers {
pmallick 0:e8a1ba50c46b 60 AD5592R_REG_NOOP = 0x0,
pmallick 0:e8a1ba50c46b 61 AD5592R_REG_DAC_READBACK = 0x1,
pmallick 0:e8a1ba50c46b 62 AD5592R_REG_ADC_SEQ = 0x2,
pmallick 0:e8a1ba50c46b 63 AD5592R_REG_CTRL = 0x3,
pmallick 0:e8a1ba50c46b 64 AD5592R_REG_ADC_EN = 0x4,
pmallick 0:e8a1ba50c46b 65 AD5592R_REG_DAC_EN = 0x5,
pmallick 0:e8a1ba50c46b 66 AD5592R_REG_PULLDOWN = 0x6,
pmallick 0:e8a1ba50c46b 67 AD5592R_REG_LDAC = 0x7,
pmallick 0:e8a1ba50c46b 68 AD5592R_REG_GPIO_OUT_EN = 0x8,
pmallick 0:e8a1ba50c46b 69 AD5592R_REG_GPIO_SET = 0x9,
pmallick 0:e8a1ba50c46b 70 AD5592R_REG_GPIO_IN_EN = 0xA,
pmallick 0:e8a1ba50c46b 71 AD5592R_REG_PD = 0xB,
pmallick 0:e8a1ba50c46b 72 AD5592R_REG_OPEN_DRAIN = 0xC,
pmallick 0:e8a1ba50c46b 73 AD5592R_REG_TRISTATE = 0xD,
pmallick 0:e8a1ba50c46b 74 AD5592R_REG_RESET = 0xF,
pmallick 0:e8a1ba50c46b 75 };
pmallick 0:e8a1ba50c46b 76
pmallick 0:e8a1ba50c46b 77 #define AD5592R_REG_PD_PD_ALL BIT(10)
pmallick 0:e8a1ba50c46b 78 #define AD5592R_REG_PD_EN_REF BIT(9)
pmallick 0:e8a1ba50c46b 79
pmallick 0:e8a1ba50c46b 80 #define AD5592R_REG_CTRL_ADC_PC_BUFF BIT(9)
pmallick 0:e8a1ba50c46b 81 #define AD5592R_REG_CTRL_ADC_BUFF_EN BIT(8)
pmallick 0:e8a1ba50c46b 82 #define AD5592R_REG_CTRL_CONFIG_LOCK BIT(7)
pmallick 0:e8a1ba50c46b 83 #define AD5592R_REG_CTRL_W_ALL_DACS BIT(6)
pmallick 0:e8a1ba50c46b 84 #define AD5592R_REG_CTRL_ADC_RANGE BIT(5)
pmallick 0:e8a1ba50c46b 85 #define AD5592R_REG_CTRL_DAC_RANGE BIT(4)
pmallick 0:e8a1ba50c46b 86
pmallick 0:e8a1ba50c46b 87 #define AD5592R_REG_ADC_SEQ_REP BIT(9)
pmallick 0:e8a1ba50c46b 88 #define AD5592R_REG_ADC_SEQ_TEMP_READBACK BIT(8)
pmallick 0:e8a1ba50c46b 89 #define AD5592R_REG_ADC_SEQ_CODE_MSK(x) ((x) & 0x0FFF)
pmallick 0:e8a1ba50c46b 90
pmallick 0:e8a1ba50c46b 91 #define AD5592R_REG_GPIO_OUT_EN_ADC_NOT_BUSY BIT(8)
pmallick 0:e8a1ba50c46b 92
pmallick 0:e8a1ba50c46b 93 #define AD5592R_REG_LDAC_IMMEDIATE_OUT 0x00
pmallick 0:e8a1ba50c46b 94 #define AD5592R_REG_LDAC_INPUT_REG_ONLY 0x01
pmallick 0:e8a1ba50c46b 95 #define AD5592R_REG_LDAC_INPUT_REG_OUT 0x02
pmallick 0:e8a1ba50c46b 96
pmallick 0:e8a1ba50c46b 97 #define INTERNAL_VREF_VOLTAGE 2.5
pmallick 0:e8a1ba50c46b 98
pmallick 0:e8a1ba50c46b 99 struct ad5592r_dev;
pmallick 0:e8a1ba50c46b 100
pmallick 0:e8a1ba50c46b 101 struct ad5592r_rw_ops {
pmallick 0:e8a1ba50c46b 102 int32_t (*write_dac)(struct ad5592r_dev *dev, uint8_t chan,
pmallick 0:e8a1ba50c46b 103 uint16_t value);
pmallick 0:e8a1ba50c46b 104 int32_t (*read_adc)(struct ad5592r_dev *dev, uint8_t chan,
pmallick 0:e8a1ba50c46b 105 uint16_t *value);
pmallick 0:e8a1ba50c46b 106 int32_t(*multi_read_adc)(struct ad5592r_dev *dev,
pmallick 0:e8a1ba50c46b 107 uint16_t chans, uint16_t *value);
pmallick 0:e8a1ba50c46b 108 int32_t (*reg_write)(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:e8a1ba50c46b 109 uint16_t value);
pmallick 0:e8a1ba50c46b 110 int32_t (*reg_read)(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:e8a1ba50c46b 111 uint16_t *value);
pmallick 0:e8a1ba50c46b 112 int32_t (*gpio_read)(struct ad5592r_dev *dev, uint8_t *value);
pmallick 0:e8a1ba50c46b 113 };
pmallick 0:e8a1ba50c46b 114
pmallick 0:e8a1ba50c46b 115 struct ad5592r_init_param {
pmallick 0:e8a1ba50c46b 116 bool int_ref;
pmallick 0:e8a1ba50c46b 117 };
pmallick 0:e8a1ba50c46b 118
pmallick 0:e8a1ba50c46b 119 struct ad5592r_dev {
pmallick 0:e8a1ba50c46b 120 const struct ad5592r_rw_ops *ops;
pmallick 0:e8a1ba50c46b 121 i2c_desc *i2c;
pmallick 0:e8a1ba50c46b 122 spi_desc *spi;
pmallick 0:e8a1ba50c46b 123 uint16_t spi_msg;
pmallick 0:e8a1ba50c46b 124 uint8_t num_channels;
pmallick 0:e8a1ba50c46b 125 uint16_t cached_dac[8];
pmallick 0:e8a1ba50c46b 126 uint16_t cached_gp_ctrl;
pmallick 0:e8a1ba50c46b 127 uint8_t channel_modes[8];
pmallick 0:e8a1ba50c46b 128 uint8_t channel_offstate[8];
pmallick 0:e8a1ba50c46b 129 uint8_t gpio_out;
pmallick 0:e8a1ba50c46b 130 uint8_t gpio_in;
pmallick 0:e8a1ba50c46b 131 uint8_t gpio_val;
pmallick 0:e8a1ba50c46b 132 uint8_t ldac_mode;
pmallick 0:e8a1ba50c46b 133 };
pmallick 0:e8a1ba50c46b 134
pmallick 0:e8a1ba50c46b 135 int32_t ad5592r_base_reg_write(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:e8a1ba50c46b 136 uint16_t value);
pmallick 0:e8a1ba50c46b 137 int32_t ad5592r_base_reg_read(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:e8a1ba50c46b 138 uint16_t *value);
pmallick 0:e8a1ba50c46b 139 int32_t ad5592r_gpio_get(struct ad5592r_dev *dev, uint8_t offset);
pmallick 0:e8a1ba50c46b 140 int32_t ad5592r_gpio_set(struct ad5592r_dev *dev, uint8_t offset,
pmallick 0:e8a1ba50c46b 141 int32_t value);
pmallick 0:e8a1ba50c46b 142 int32_t ad5592r_gpio_direction_input(struct ad5592r_dev *dev, uint8_t offset);
pmallick 0:e8a1ba50c46b 143 int32_t ad5592r_gpio_direction_output(struct ad5592r_dev *dev,
pmallick 0:e8a1ba50c46b 144 uint8_t offset, int32_t value);
pmallick 0:e8a1ba50c46b 145 int32_t ad5592r_software_reset(struct ad5592r_dev *dev);
pmallick 0:e8a1ba50c46b 146 int32_t ad5592r_set_channel_modes(struct ad5592r_dev *dev);
pmallick 0:e8a1ba50c46b 147 int32_t ad5592r_reset_channel_modes(struct ad5592r_dev *dev);
pmallick 0:e8a1ba50c46b 148
pmallick 0:e8a1ba50c46b 149 #endif /* AD5592R_BASE_H_ */