Pratyush Mallick / Mbed OS nano_dac

this is testing

noos_mbed/drivers/adc-dac/ad5592r/ad5592r-base.c@0:e8a1ba50c46b, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 19:12:57 2021 +0530
Revision:
0:e8a1ba50c46b
this is testing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 0:e8a1ba50c46b 1 /***************************************************************************//**
pmallick 0:e8a1ba50c46b 2 * @file ad5592r-base.c
pmallick 0:e8a1ba50c46b 3 * @brief Implementation of AD5592R Base Driver.
pmallick 0:e8a1ba50c46b 4 * @author Mircea Caprioru (mircea.caprioru@analog.com)
pmallick 0:e8a1ba50c46b 5 ********************************************************************************
pmallick 0:e8a1ba50c46b 6 * Copyright 2018, 2020(c) Analog Devices, Inc.
pmallick 0:e8a1ba50c46b 7 *
pmallick 0:e8a1ba50c46b 8 * All rights reserved.
pmallick 0:e8a1ba50c46b 9 *
pmallick 0:e8a1ba50c46b 10 * Redistribution and use in source and binary forms, with or without
pmallick 0:e8a1ba50c46b 11 * modification, are permitted provided that the following conditions are met:
pmallick 0:e8a1ba50c46b 12 * - Redistributions of source code must retain the above copyright
pmallick 0:e8a1ba50c46b 13 * notice, this list of conditions and the following disclaimer.
pmallick 0:e8a1ba50c46b 14 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:e8a1ba50c46b 15 * notice, this list of conditions and the following disclaimer in
pmallick 0:e8a1ba50c46b 16 * the documentation and/or other materials provided with the
pmallick 0:e8a1ba50c46b 17 * distribution.
pmallick 0:e8a1ba50c46b 18 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:e8a1ba50c46b 19 * contributors may be used to endorse or promote products derived
pmallick 0:e8a1ba50c46b 20 * from this software without specific prior written permission.
pmallick 0:e8a1ba50c46b 21 * - The use of this software may or may not infringe the patent rights
pmallick 0:e8a1ba50c46b 22 * of one or more patent holders. This license does not release you
pmallick 0:e8a1ba50c46b 23 * from the requirement that you obtain separate licenses from these
pmallick 0:e8a1ba50c46b 24 * patent holders to use this software.
pmallick 0:e8a1ba50c46b 25 * - Use of the software either in source or binary form, must be run
pmallick 0:e8a1ba50c46b 26 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:e8a1ba50c46b 27 *
pmallick 0:e8a1ba50c46b 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:e8a1ba50c46b 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:e8a1ba50c46b 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:e8a1ba50c46b 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:e8a1ba50c46b 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:e8a1ba50c46b 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 0:e8a1ba50c46b 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 0:e8a1ba50c46b 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 0:e8a1ba50c46b 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 0:e8a1ba50c46b 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:e8a1ba50c46b 38 *******************************************************************************/
pmallick 0:e8a1ba50c46b 39 #include "error.h"
pmallick 0:e8a1ba50c46b 40 #include "ad5592r-base.h"
pmallick 0:e8a1ba50c46b 41
pmallick 0:e8a1ba50c46b 42 /**
pmallick 0:e8a1ba50c46b 43 * Write register.
pmallick 0:e8a1ba50c46b 44 *
pmallick 0:e8a1ba50c46b 45 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 46 * @param reg - The register address.
pmallick 0:e8a1ba50c46b 47 * @param value - register value
pmallick 0:e8a1ba50c46b 48 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 49 */
pmallick 0:e8a1ba50c46b 50 int32_t ad5592r_base_reg_write(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:e8a1ba50c46b 51 uint16_t value)
pmallick 0:e8a1ba50c46b 52 {
pmallick 0:e8a1ba50c46b 53 return dev->ops->reg_write(dev, reg, value);
pmallick 0:e8a1ba50c46b 54 }
pmallick 0:e8a1ba50c46b 55
pmallick 0:e8a1ba50c46b 56 /**
pmallick 0:e8a1ba50c46b 57 * Read register.
pmallick 0:e8a1ba50c46b 58 *
pmallick 0:e8a1ba50c46b 59 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 60 * @param reg - The register address.
pmallick 0:e8a1ba50c46b 61 * @param value - register value
pmallick 0:e8a1ba50c46b 62 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 63 */
pmallick 0:e8a1ba50c46b 64 int32_t ad5592r_base_reg_read(struct ad5592r_dev *dev, uint8_t reg,
pmallick 0:e8a1ba50c46b 65 uint16_t *value)
pmallick 0:e8a1ba50c46b 66 {
pmallick 0:e8a1ba50c46b 67 return dev->ops->reg_read(dev, reg, value);
pmallick 0:e8a1ba50c46b 68 }
pmallick 0:e8a1ba50c46b 69
pmallick 0:e8a1ba50c46b 70 /**
pmallick 0:e8a1ba50c46b 71 * Get GPIO value
pmallick 0:e8a1ba50c46b 72 *
pmallick 0:e8a1ba50c46b 73 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 74 * @param offset - The channel number.
pmallick 0:e8a1ba50c46b 75 * @return 0 or 1 depending on the GPIO value.
pmallick 0:e8a1ba50c46b 76 */
pmallick 0:e8a1ba50c46b 77 int32_t ad5592r_gpio_get(struct ad5592r_dev *dev, uint8_t offset)
pmallick 0:e8a1ba50c46b 78 {
pmallick 0:e8a1ba50c46b 79 int32_t ret = 0;
pmallick 0:e8a1ba50c46b 80 uint8_t val;
pmallick 0:e8a1ba50c46b 81
pmallick 0:e8a1ba50c46b 82 if (!dev)
pmallick 0:e8a1ba50c46b 83 return FAILURE;
pmallick 0:e8a1ba50c46b 84
pmallick 0:e8a1ba50c46b 85 if (dev->gpio_out & BIT(offset))
pmallick 0:e8a1ba50c46b 86 val = dev->gpio_val;
pmallick 0:e8a1ba50c46b 87 else
pmallick 0:e8a1ba50c46b 88 ret = dev->ops->gpio_read(dev, &val);
pmallick 0:e8a1ba50c46b 89
pmallick 0:e8a1ba50c46b 90 if (ret < 0)
pmallick 0:e8a1ba50c46b 91 return ret;
pmallick 0:e8a1ba50c46b 92
pmallick 0:e8a1ba50c46b 93 return !!(val & BIT(offset));
pmallick 0:e8a1ba50c46b 94 }
pmallick 0:e8a1ba50c46b 95
pmallick 0:e8a1ba50c46b 96 /**
pmallick 0:e8a1ba50c46b 97 * Set GPIO value
pmallick 0:e8a1ba50c46b 98 *
pmallick 0:e8a1ba50c46b 99 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 100 * @param offset - The channel number.
pmallick 0:e8a1ba50c46b 101 * @param value - the GPIO value (0 or 1)
pmallick 0:e8a1ba50c46b 102 */
pmallick 0:e8a1ba50c46b 103 int32_t ad5592r_gpio_set(struct ad5592r_dev *dev, uint8_t offset, int32_t value)
pmallick 0:e8a1ba50c46b 104 {
pmallick 0:e8a1ba50c46b 105 if (!dev)
pmallick 0:e8a1ba50c46b 106 return FAILURE;
pmallick 0:e8a1ba50c46b 107
pmallick 0:e8a1ba50c46b 108 if (value)
pmallick 0:e8a1ba50c46b 109 dev->gpio_val |= BIT(offset);
pmallick 0:e8a1ba50c46b 110 else
pmallick 0:e8a1ba50c46b 111 dev->gpio_val &= ~BIT(offset);
pmallick 0:e8a1ba50c46b 112
pmallick 0:e8a1ba50c46b 113 return ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_SET,
pmallick 0:e8a1ba50c46b 114 dev->gpio_val);
pmallick 0:e8a1ba50c46b 115 }
pmallick 0:e8a1ba50c46b 116
pmallick 0:e8a1ba50c46b 117 /**
pmallick 0:e8a1ba50c46b 118 * Set GPIO as input
pmallick 0:e8a1ba50c46b 119 *
pmallick 0:e8a1ba50c46b 120 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 121 * @param offset - The channel number.
pmallick 0:e8a1ba50c46b 122 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 123 */
pmallick 0:e8a1ba50c46b 124 int32_t ad5592r_gpio_direction_input(struct ad5592r_dev *dev, uint8_t offset)
pmallick 0:e8a1ba50c46b 125 {
pmallick 0:e8a1ba50c46b 126 int32_t ret;
pmallick 0:e8a1ba50c46b 127
pmallick 0:e8a1ba50c46b 128 if (!dev)
pmallick 0:e8a1ba50c46b 129 return FAILURE;
pmallick 0:e8a1ba50c46b 130
pmallick 0:e8a1ba50c46b 131 dev->gpio_out &= ~BIT(offset);
pmallick 0:e8a1ba50c46b 132 dev->gpio_in |= BIT(offset);
pmallick 0:e8a1ba50c46b 133
pmallick 0:e8a1ba50c46b 134 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_OUT_EN,
pmallick 0:e8a1ba50c46b 135 dev->gpio_out);
pmallick 0:e8a1ba50c46b 136 if (ret < 0)
pmallick 0:e8a1ba50c46b 137 return ret;
pmallick 0:e8a1ba50c46b 138
pmallick 0:e8a1ba50c46b 139 return ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_IN_EN,
pmallick 0:e8a1ba50c46b 140 dev->gpio_in);
pmallick 0:e8a1ba50c46b 141 }
pmallick 0:e8a1ba50c46b 142
pmallick 0:e8a1ba50c46b 143 /**
pmallick 0:e8a1ba50c46b 144 * Set GPIO as output
pmallick 0:e8a1ba50c46b 145 *
pmallick 0:e8a1ba50c46b 146 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 147 * @param offset - The channel number.
pmallick 0:e8a1ba50c46b 148 * @param value - GPIO value to set.
pmallick 0:e8a1ba50c46b 149 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 150 */
pmallick 0:e8a1ba50c46b 151 int32_t ad5592r_gpio_direction_output(struct ad5592r_dev *dev,
pmallick 0:e8a1ba50c46b 152 uint8_t offset, int32_t value)
pmallick 0:e8a1ba50c46b 153 {
pmallick 0:e8a1ba50c46b 154 int32_t ret;
pmallick 0:e8a1ba50c46b 155
pmallick 0:e8a1ba50c46b 156 if (!dev)
pmallick 0:e8a1ba50c46b 157 return FAILURE;
pmallick 0:e8a1ba50c46b 158
pmallick 0:e8a1ba50c46b 159 if (value)
pmallick 0:e8a1ba50c46b 160 dev->gpio_val |= BIT(offset);
pmallick 0:e8a1ba50c46b 161 else
pmallick 0:e8a1ba50c46b 162 dev->gpio_val &= ~BIT(offset);
pmallick 0:e8a1ba50c46b 163
pmallick 0:e8a1ba50c46b 164 dev->gpio_in &= ~BIT(offset);
pmallick 0:e8a1ba50c46b 165 dev->gpio_out |= BIT(offset);
pmallick 0:e8a1ba50c46b 166
pmallick 0:e8a1ba50c46b 167 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_SET, dev->gpio_val);
pmallick 0:e8a1ba50c46b 168 if (ret < 0)
pmallick 0:e8a1ba50c46b 169 return ret;
pmallick 0:e8a1ba50c46b 170
pmallick 0:e8a1ba50c46b 171 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_OUT_EN,
pmallick 0:e8a1ba50c46b 172 dev->gpio_out);
pmallick 0:e8a1ba50c46b 173 if (ret < 0)
pmallick 0:e8a1ba50c46b 174 return ret;
pmallick 0:e8a1ba50c46b 175
pmallick 0:e8a1ba50c46b 176 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_IN_EN,
pmallick 0:e8a1ba50c46b 177 dev->gpio_in);
pmallick 0:e8a1ba50c46b 178
pmallick 0:e8a1ba50c46b 179 return ret;
pmallick 0:e8a1ba50c46b 180 }
pmallick 0:e8a1ba50c46b 181
pmallick 0:e8a1ba50c46b 182 /**
pmallick 0:e8a1ba50c46b 183 * Software reset device.
pmallick 0:e8a1ba50c46b 184 *
pmallick 0:e8a1ba50c46b 185 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 186 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 187 */
pmallick 0:e8a1ba50c46b 188 int32_t ad5592r_software_reset(struct ad5592r_dev *dev)
pmallick 0:e8a1ba50c46b 189 {
pmallick 0:e8a1ba50c46b 190 int32_t ret;
pmallick 0:e8a1ba50c46b 191
pmallick 0:e8a1ba50c46b 192 if (!dev)
pmallick 0:e8a1ba50c46b 193 return FAILURE;
pmallick 0:e8a1ba50c46b 194
pmallick 0:e8a1ba50c46b 195 /* Writing this magic value resets the device */
pmallick 0:e8a1ba50c46b 196 ret = ad5592r_base_reg_write(dev, AD5592R_REG_RESET, 0xdac);
pmallick 0:e8a1ba50c46b 197
pmallick 0:e8a1ba50c46b 198 mdelay(10);
pmallick 0:e8a1ba50c46b 199
pmallick 0:e8a1ba50c46b 200 return ret;
pmallick 0:e8a1ba50c46b 201 }
pmallick 0:e8a1ba50c46b 202
pmallick 0:e8a1ba50c46b 203 /**
pmallick 0:e8a1ba50c46b 204 * Set channels modes.
pmallick 0:e8a1ba50c46b 205 *
pmallick 0:e8a1ba50c46b 206 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 207 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 208 */
pmallick 0:e8a1ba50c46b 209 int32_t ad5592r_set_channel_modes(struct ad5592r_dev *dev)
pmallick 0:e8a1ba50c46b 210 {
pmallick 0:e8a1ba50c46b 211 int32_t ret;
pmallick 0:e8a1ba50c46b 212 uint8_t i;
pmallick 0:e8a1ba50c46b 213 uint8_t pulldown = 0, tristate = 0, dac = 0, adc = 0;
pmallick 0:e8a1ba50c46b 214 uint16_t read_back;
pmallick 0:e8a1ba50c46b 215
pmallick 0:e8a1ba50c46b 216 if (!dev)
pmallick 0:e8a1ba50c46b 217 return FAILURE;
pmallick 0:e8a1ba50c46b 218
pmallick 0:e8a1ba50c46b 219 dev->gpio_in = 0;
pmallick 0:e8a1ba50c46b 220 dev->gpio_out = 0;
pmallick 0:e8a1ba50c46b 221
pmallick 0:e8a1ba50c46b 222 for (i = 0; i < dev->num_channels; i++) {
pmallick 0:e8a1ba50c46b 223 switch (dev->channel_modes[i]) {
pmallick 0:e8a1ba50c46b 224 case CH_MODE_DAC:
pmallick 0:e8a1ba50c46b 225 dac |= BIT(i);
pmallick 0:e8a1ba50c46b 226 break;
pmallick 0:e8a1ba50c46b 227
pmallick 0:e8a1ba50c46b 228 case CH_MODE_ADC:
pmallick 0:e8a1ba50c46b 229 adc |= BIT(i);
pmallick 0:e8a1ba50c46b 230 break;
pmallick 0:e8a1ba50c46b 231
pmallick 0:e8a1ba50c46b 232 case CH_MODE_DAC_AND_ADC:
pmallick 0:e8a1ba50c46b 233 dac |= BIT(i);
pmallick 0:e8a1ba50c46b 234 adc |= BIT(i);
pmallick 0:e8a1ba50c46b 235 break;
pmallick 0:e8a1ba50c46b 236
pmallick 0:e8a1ba50c46b 237 case CH_MODE_GPI:
pmallick 0:e8a1ba50c46b 238 dev->gpio_in |= BIT(i);
pmallick 0:e8a1ba50c46b 239 break;
pmallick 0:e8a1ba50c46b 240
pmallick 0:e8a1ba50c46b 241 case CH_MODE_GPO:
pmallick 0:e8a1ba50c46b 242 dev->gpio_out |= BIT(i);
pmallick 0:e8a1ba50c46b 243 break;
pmallick 0:e8a1ba50c46b 244
pmallick 0:e8a1ba50c46b 245 case CH_MODE_UNUSED:
pmallick 0:e8a1ba50c46b 246 /* fall-through */
pmallick 0:e8a1ba50c46b 247 default:
pmallick 0:e8a1ba50c46b 248 switch (dev->channel_offstate[i]) {
pmallick 0:e8a1ba50c46b 249 case CH_OFFSTATE_OUT_TRISTATE:
pmallick 0:e8a1ba50c46b 250 tristate |= BIT(i);
pmallick 0:e8a1ba50c46b 251 break;
pmallick 0:e8a1ba50c46b 252
pmallick 0:e8a1ba50c46b 253 case CH_OFFSTATE_OUT_LOW:
pmallick 0:e8a1ba50c46b 254 dev->gpio_out |= BIT(i);
pmallick 0:e8a1ba50c46b 255 break;
pmallick 0:e8a1ba50c46b 256
pmallick 0:e8a1ba50c46b 257 case CH_OFFSTATE_OUT_HIGH:
pmallick 0:e8a1ba50c46b 258 dev->gpio_out |= BIT(i);
pmallick 0:e8a1ba50c46b 259 dev->gpio_val |= BIT(i);
pmallick 0:e8a1ba50c46b 260 break;
pmallick 0:e8a1ba50c46b 261
pmallick 0:e8a1ba50c46b 262 case CH_OFFSTATE_PULLDOWN:
pmallick 0:e8a1ba50c46b 263 /* fall-through */
pmallick 0:e8a1ba50c46b 264 default:
pmallick 0:e8a1ba50c46b 265 pulldown |= BIT(i);
pmallick 0:e8a1ba50c46b 266 break;
pmallick 0:e8a1ba50c46b 267 }
pmallick 0:e8a1ba50c46b 268 }
pmallick 0:e8a1ba50c46b 269 }
pmallick 0:e8a1ba50c46b 270
pmallick 0:e8a1ba50c46b 271 /* Pull down unused pins to GND */
pmallick 0:e8a1ba50c46b 272 ret = ad5592r_base_reg_write(dev, AD5592R_REG_PULLDOWN, pulldown);
pmallick 0:e8a1ba50c46b 273 if (ret < 0)
pmallick 0:e8a1ba50c46b 274 return ret;
pmallick 0:e8a1ba50c46b 275
pmallick 0:e8a1ba50c46b 276 ret = ad5592r_base_reg_write(dev, AD5592R_REG_TRISTATE, tristate);
pmallick 0:e8a1ba50c46b 277 if (ret < 0)
pmallick 0:e8a1ba50c46b 278 return ret;
pmallick 0:e8a1ba50c46b 279
pmallick 0:e8a1ba50c46b 280 /* Configure pins that we use */
pmallick 0:e8a1ba50c46b 281 ret = ad5592r_base_reg_write(dev, AD5592R_REG_DAC_EN, dac);
pmallick 0:e8a1ba50c46b 282 if (ret < 0)
pmallick 0:e8a1ba50c46b 283 return ret;
pmallick 0:e8a1ba50c46b 284
pmallick 0:e8a1ba50c46b 285 ret = ad5592r_base_reg_write(dev, AD5592R_REG_ADC_EN, adc);
pmallick 0:e8a1ba50c46b 286 if (ret < 0)
pmallick 0:e8a1ba50c46b 287 return ret;
pmallick 0:e8a1ba50c46b 288
pmallick 0:e8a1ba50c46b 289 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_SET, dev->gpio_val);
pmallick 0:e8a1ba50c46b 290 if (ret < 0)
pmallick 0:e8a1ba50c46b 291 return ret;
pmallick 0:e8a1ba50c46b 292
pmallick 0:e8a1ba50c46b 293 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_OUT_EN,
pmallick 0:e8a1ba50c46b 294 dev->gpio_out);
pmallick 0:e8a1ba50c46b 295 if (ret < 0)
pmallick 0:e8a1ba50c46b 296 return ret;
pmallick 0:e8a1ba50c46b 297
pmallick 0:e8a1ba50c46b 298 ret = ad5592r_base_reg_write(dev, AD5592R_REG_GPIO_IN_EN,
pmallick 0:e8a1ba50c46b 299 dev->gpio_in);
pmallick 0:e8a1ba50c46b 300 if (ret < 0)
pmallick 0:e8a1ba50c46b 301 return ret;
pmallick 0:e8a1ba50c46b 302
pmallick 0:e8a1ba50c46b 303 /* Verify that we can read back at least one register */
pmallick 0:e8a1ba50c46b 304 ret = ad5592r_base_reg_read(dev, AD5592R_REG_ADC_EN, &read_back);
pmallick 0:e8a1ba50c46b 305 if (!ret && (read_back & 0xff) != adc)
pmallick 0:e8a1ba50c46b 306 return FAILURE;
pmallick 0:e8a1ba50c46b 307
pmallick 0:e8a1ba50c46b 308 return ret;
pmallick 0:e8a1ba50c46b 309 }
pmallick 0:e8a1ba50c46b 310
pmallick 0:e8a1ba50c46b 311 /**
pmallick 0:e8a1ba50c46b 312 * Reset channels and set GPIO to unused.
pmallick 0:e8a1ba50c46b 313 *
pmallick 0:e8a1ba50c46b 314 * @param dev - The device structure.
pmallick 0:e8a1ba50c46b 315 * @return 0 in case of success, negative error code otherwise
pmallick 0:e8a1ba50c46b 316 */
pmallick 0:e8a1ba50c46b 317 int32_t ad5592r_reset_channel_modes(struct ad5592r_dev *dev)
pmallick 0:e8a1ba50c46b 318 {
pmallick 0:e8a1ba50c46b 319 uint32_t i;
pmallick 0:e8a1ba50c46b 320
pmallick 0:e8a1ba50c46b 321 if (!dev)
pmallick 0:e8a1ba50c46b 322 return FAILURE;
pmallick 0:e8a1ba50c46b 323
pmallick 0:e8a1ba50c46b 324 for (i = 0; i < sizeof(dev->channel_modes); i++)
pmallick 0:e8a1ba50c46b 325 dev->channel_modes[i] = CH_MODE_UNUSED;
pmallick 0:e8a1ba50c46b 326
pmallick 0:e8a1ba50c46b 327 return ad5592r_set_channel_modes(dev);
pmallick 0:e8a1ba50c46b 328 }