Pratyush Mallick / Mbed OS EVAL-AD4696

Forked repository for pushing changes to EVAL-AD4696

Dependencies:   platform_drivers

app/ad469x.h@1:8792acb5a039, 2021-09-30 (annotated)

Committer:
pmallick
Date:
Thu Sep 30 11:01:05 2021 +0530
Revision:
1:8792acb5a039
AD4696 IIO Application- Initial Revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pmallick 1:8792acb5a039 1 /***************************************************************************//**
pmallick 1:8792acb5a039 2 * @file ad469x.h
pmallick 1:8792acb5a039 3 * @brief Header file for ad469x Driver.
pmallick 1:8792acb5a039 4 * @author Cristian Pop (cristian.pop@analog.com)
pmallick 1:8792acb5a039 5 ********************************************************************************
pmallick 1:8792acb5a039 6 * Copyright 2021(c) Analog Devices, Inc.
pmallick 1:8792acb5a039 7 *
pmallick 1:8792acb5a039 8 * All rights reserved.
pmallick 1:8792acb5a039 9 *
pmallick 1:8792acb5a039 10 * Redistribution and use in source and binary forms, with or without
pmallick 1:8792acb5a039 11 * modification, are permitted provided that the following conditions are met:
pmallick 1:8792acb5a039 12 * - Redistributions of source code must retain the above copyright
pmallick 1:8792acb5a039 13 * notice, this list of conditions and the following disclaimer.
pmallick 1:8792acb5a039 14 * - Redistributions in binary form must reproduce the above copyright
pmallick 1:8792acb5a039 15 * notice, this list of conditions and the following disclaimer in
pmallick 1:8792acb5a039 16 * the documentation and/or other materials provided with the
pmallick 1:8792acb5a039 17 * distribution.
pmallick 1:8792acb5a039 18 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 1:8792acb5a039 19 * contributors may be used to endorse or promote products derived
pmallick 1:8792acb5a039 20 * from this software without specific prior written permission.
pmallick 1:8792acb5a039 21 * - The use of this software may or may not infringe the patent rights
pmallick 1:8792acb5a039 22 * of one or more patent holders. This license does not release you
pmallick 1:8792acb5a039 23 * from the requirement that you obtain separate licenses from these
pmallick 1:8792acb5a039 24 * patent holders to use this software.
pmallick 1:8792acb5a039 25 * - Use of the software either in source or binary form, must be run
pmallick 1:8792acb5a039 26 * on or directly connected to an Analog Devices Inc. component.
pmallick 1:8792acb5a039 27 *
pmallick 1:8792acb5a039 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 1:8792acb5a039 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 1:8792acb5a039 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 1:8792acb5a039 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 1:8792acb5a039 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 1:8792acb5a039 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 1:8792acb5a039 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 1:8792acb5a039 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 1:8792acb5a039 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 1:8792acb5a039 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 1:8792acb5a039 38 *******************************************************************************/
pmallick 1:8792acb5a039 39
pmallick 1:8792acb5a039 40 #ifndef SRC_AD469X_H_
pmallick 1:8792acb5a039 41 #define SRC_AD469X_H_
pmallick 1:8792acb5a039 42
pmallick 1:8792acb5a039 43 // **** Note for User: SPI Standard/Engine selection **** //
pmallick 1:8792acb5a039 44 /* By default the Standard SPI protocol is used for communicating with eval board.
pmallick 1:8792acb5a039 45 * Uncomment the "ENABLE_SPI_ENGINE" macro to enable the SPI engine controller
pmallick 1:8792acb5a039 46 * framework.
pmallick 1:8792acb5a039 47 * */
pmallick 1:8792acb5a039 48 //#define ENABLE_SPI_ENGINE
pmallick 1:8792acb5a039 49
pmallick 1:8792acb5a039 50 /******************************************************************************/
pmallick 1:8792acb5a039 51 /***************************** Include Files **********************************/
pmallick 1:8792acb5a039 52 /******************************************************************************/
pmallick 1:8792acb5a039 53 #include <stdlib.h>
pmallick 1:8792acb5a039 54 #include <stdbool.h>
pmallick 1:8792acb5a039 55
pmallick 1:8792acb5a039 56 #if defined(ENABLE_SPI_ENGINE)
pmallick 1:8792acb5a039 57 #include "spi_engine.h"
pmallick 1:8792acb5a039 58 #include "clk_axi_clkgen.h"
pmallick 1:8792acb5a039 59 #include "pwm.h"
pmallick 1:8792acb5a039 60 #else
pmallick 1:8792acb5a039 61 #include "spi.h"
pmallick 1:8792acb5a039 62 #endif
pmallick 1:8792acb5a039 63
pmallick 1:8792acb5a039 64 /******************************************************************************/
pmallick 1:8792acb5a039 65 /********************** Macros and Constants Definitions **********************/
pmallick 1:8792acb5a039 66 /******************************************************************************/
pmallick 1:8792acb5a039 67 /* AD469x registers */
pmallick 1:8792acb5a039 68 #define AD469x_REG_IF_CONFIG_A 0x000
pmallick 1:8792acb5a039 69 #define AD469x_REG_IF_CONFIG_B 0x001
pmallick 1:8792acb5a039 70 #define AD469x_REG_DEVICE_TYPE 0x003
pmallick 1:8792acb5a039 71 #define AD469x_REG_DEVICE_ID_L 0x004
pmallick 1:8792acb5a039 72 #define AD469x_REG_DEVICE_ID_H 0x005
pmallick 1:8792acb5a039 73 #define AD469x_REG_SCRATCH_PAD 0x00A
pmallick 1:8792acb5a039 74 #define AD469x_REG_VENDOR_L 0x00C
pmallick 1:8792acb5a039 75 #define AD469x_REG_VENDOR_H 0x00D
pmallick 1:8792acb5a039 76 #define AD469x_REG_LOOP_MODE 0x00E
pmallick 1:8792acb5a039 77 #define AD469x_REG_IF_CONFIG_C 0x010
pmallick 1:8792acb5a039 78 #define AD469x_REG_IF_STATUS 0x011
pmallick 1:8792acb5a039 79 #define AD469x_REG_STATUS 0x014
pmallick 1:8792acb5a039 80 #define AD469x_REG_ALERT_STATUS1 0x015
pmallick 1:8792acb5a039 81 #define AD469x_REG_ALERT_STATUS2 0x016
pmallick 1:8792acb5a039 82 #define AD469x_REG_ALERT_STATUS3 0x017
pmallick 1:8792acb5a039 83 #define AD469x_REG_ALERT_STATUS4 0x018
pmallick 1:8792acb5a039 84 #define AD469x_REG_CLAMP_STATUS1 0x01A
pmallick 1:8792acb5a039 85 #define AD469x_REG_CLAMP_STATUS2 0x01B
pmallick 1:8792acb5a039 86 #define AD469x_REG_SETUP 0x020
pmallick 1:8792acb5a039 87 #define AD469x_REG_REF_CTRL 0x021
pmallick 1:8792acb5a039 88 #define AD469x_REG_SEQ_CTRL 0x022
pmallick 1:8792acb5a039 89 #define AD469x_REG_AC_CTRL 0x023
pmallick 1:8792acb5a039 90 #define AD469x_REG_STD_SEQ_CONFIG 0x024
pmallick 1:8792acb5a039 91 #define AD469x_REG_GPIO_CTRL 0x026
pmallick 1:8792acb5a039 92 #define AD469x_REG_GP_MODE 0x027
pmallick 1:8792acb5a039 93 #define AD469x_REG_GPIO_STATE 0x028
pmallick 1:8792acb5a039 94 #define AD469x_REG_TEMP_CTRL 0x029
pmallick 1:8792acb5a039 95 #define AD469x_REG_CONFIG_IN(x) ((x & 0x0F) | 0x30)
pmallick 1:8792acb5a039 96 #define AD469x_REG_AS_SLOT(x) ((x & 0x7F) | 0x100)
pmallick 1:8792acb5a039 97
pmallick 1:8792acb5a039 98 /* 5-bit SDI Conversion Mode Commands */
pmallick 1:8792acb5a039 99 #define AD469x_CMD_REG_CONFIG_MODE (0x0A << 3)
pmallick 1:8792acb5a039 100 #define AD469x_CMD_SEL_TEMP_SNSOR_CH (0x0F << 3)
pmallick 1:8792acb5a039 101 #define AD469x_CMD_CONFIG_CH_SEL(x) ((0x10 | (0x0F & x)) << 3)
pmallick 1:8792acb5a039 102
pmallick 1:8792acb5a039 103 /* AD469x_REG_SETUP */
pmallick 1:8792acb5a039 104 #define AD469x_SETUP_IF_MODE_MASK (0x01 << 2)
pmallick 1:8792acb5a039 105 #define AD469x_SETUP_IF_MODE_CONV (0x01 << 2)
pmallick 1:8792acb5a039 106 #define AD469x_SETUP_CYC_CTRL_MASK (0x01 << 1)
pmallick 1:8792acb5a039 107 #define AD469x_SETUP_CYC_CTRL_SINGLE(x) ((x & 0x01) << 1)
pmallick 1:8792acb5a039 108 //Changed
pmallick 1:8792acb5a039 109 #define AD469x_SETUP_STATUSBIT_MODE_MASK (0x01 << 5)
pmallick 1:8792acb5a039 110 #define AD469x_SETUP_STATUSBIT_MODE_CONV (0x01 << 5)
pmallick 1:8792acb5a039 111
pmallick 1:8792acb5a039 112 /* AD469x_REG_GP_MODE */
pmallick 1:8792acb5a039 113 #define AD469x_GP_MODE_BUSY_GP_EN_MASK (0x01 << 1)
pmallick 1:8792acb5a039 114 #define AD469x_GP_MODE_BUSY_GP_EN(x) ((x & 0x01) << 1)
pmallick 1:8792acb5a039 115 #define AD469x_GP_MODE_BUSY_GP_SEL_MASK (0x01 << 4)
pmallick 1:8792acb5a039 116 #define AD469x_GP_MODE_BUSY_GP_SEL(x) ((x & 0x01) << 4)
pmallick 1:8792acb5a039 117
pmallick 1:8792acb5a039 118 /* AD469x_REG_SEQ_CTRL */
pmallick 1:8792acb5a039 119 #define AD469x_SEQ_CTRL_STD_SEQ_EN_MASK (0x01 << 7)
pmallick 1:8792acb5a039 120 #define AD469x_SEQ_CTRL_STD_SEQ_EN(x) ((x & 0x01) << 7)
pmallick 1:8792acb5a039 121 #define AD469x_SEQ_CTRL_NUM_SLOTS_AS_MASK (0x7f << 0)
pmallick 1:8792acb5a039 122 #define AD469x_SEQ_CTRL_NUM_SLOTS_AS(x) ((x & 0x7f) << 0)
pmallick 1:8792acb5a039 123
pmallick 1:8792acb5a039 124 /* AD469x_REG_TEMP_CTRL */
pmallick 1:8792acb5a039 125 #define AD469x_REG_TEMP_CTRL_TEMP_EN_MASK (0x01 << 0)
pmallick 1:8792acb5a039 126 #define AD469x_REG_TEMP_CTRL_TEMP_EN(x) ((x & 0x01) << 0)
pmallick 1:8792acb5a039 127
pmallick 1:8792acb5a039 128 /* AD469x_REG_AS_SLOT */
pmallick 1:8792acb5a039 129 #define AD469x_REG_AS_SLOT_INX(x) ((x & 0x0f) << 0)
pmallick 1:8792acb5a039 130
pmallick 1:8792acb5a039 131 /* AD469x_REG_IF_CONFIG_C */
pmallick 1:8792acb5a039 132 #define AD469x_REG_IF_CONFIG_C_MB_STRICT_MASK (0x01 << 5)
pmallick 1:8792acb5a039 133 #define AD469x_REG_IF_CONFIG_C_MB_STRICT(x) ((x & 0x01) << 5)
pmallick 1:8792acb5a039 134
pmallick 1:8792acb5a039 135 /* AD469x_REG_CONFIG_INn */
pmallick 1:8792acb5a039 136 #define AD469x_REG_CONFIG_IN_OSR_MASK (0x03 << 0)
pmallick 1:8792acb5a039 137 #define AD469x_REG_CONFIG_IN_OSR(x) ((x & 0x03) << 0)
pmallick 1:8792acb5a039 138 #define AD469x_REG_CONFIG_IN_HIZ_EN_MASK (0x01 << 3)
pmallick 1:8792acb5a039 139 #define AD469x_REG_CONFIG_IN_HIZ_EN(x) ((x & 0x01) << 3)
pmallick 1:8792acb5a039 140 #define AD469x_REG_CONFIG_IN_PAIR_MASK (0x03 << 4)
pmallick 1:8792acb5a039 141 #define AD469x_REG_CONFIG_IN_PAIR(x) ((x & 0x03) << 4)
pmallick 1:8792acb5a039 142 #define AD469x_REG_CONFIG_IN_MODE_MASK (0x01 << 6)
pmallick 1:8792acb5a039 143 #define AD469x_REG_CONFIG_IN_MODE(x) ((x & 0x01) << 6)
pmallick 1:8792acb5a039 144 #define AD469x_REG_CONFIG_IN_TD_EN_MASK (0x01 << 7)
pmallick 1:8792acb5a039 145 #define AD469x_REG_CONFIG_IN_TD_EN(x) ((x & 0x01) << 7)
pmallick 1:8792acb5a039 146
pmallick 1:8792acb5a039 147 #define AD469x_CHANNEL(x) (BIT(x) & 0xFFFF)
pmallick 1:8792acb5a039 148 #define AD469x_CHANNEL_NO 16
pmallick 1:8792acb5a039 149 #define AD469x_SLOTS_NO 0x80
pmallick 1:8792acb5a039 150 #define AD469x_CHANNEL_TEMP 16
pmallick 1:8792acb5a039 151
pmallick 1:8792acb5a039 152 /******************************************************************************/
pmallick 1:8792acb5a039 153 /*************************** Types Declarations *******************************/
pmallick 1:8792acb5a039 154 /******************************************************************************/
pmallick 1:8792acb5a039 155 /**
pmallick 1:8792acb5a039 156 * @enum ad469x_channel_sequencing
pmallick 1:8792acb5a039 157 * @brief Channel sequencing modes
pmallick 1:8792acb5a039 158 */
pmallick 1:8792acb5a039 159 enum ad469x_channel_sequencing {
pmallick 1:8792acb5a039 160 /** Single cycle read */
pmallick 1:8792acb5a039 161 AD469x_single_cycle,
pmallick 1:8792acb5a039 162 /** Two cycle read */
pmallick 1:8792acb5a039 163 AD469x_two_cycle,
pmallick 1:8792acb5a039 164 /** Sequence trough channels, standard mode */
pmallick 1:8792acb5a039 165 AD469x_standard_seq,
pmallick 1:8792acb5a039 166 /** Sequence trough channels, advanced mode */
pmallick 1:8792acb5a039 167 AD469x_advanced_seq,
pmallick 1:8792acb5a039 168 };
pmallick 1:8792acb5a039 169
pmallick 1:8792acb5a039 170 /**
pmallick 1:8792acb5a039 171 * @enum ad469x_busy_gp_sel
pmallick 1:8792acb5a039 172 * @brief Busy state, possible general purpose pin selections
pmallick 1:8792acb5a039 173 */
pmallick 1:8792acb5a039 174 enum ad469x_busy_gp_sel {
pmallick 1:8792acb5a039 175 /** Busy on gp0 */
pmallick 1:8792acb5a039 176 AD469x_busy_gp0 = 0,
pmallick 1:8792acb5a039 177 /** Busy on gp3 */
pmallick 1:8792acb5a039 178 AD469x_busy_gp3 = 1,
pmallick 1:8792acb5a039 179 };
pmallick 1:8792acb5a039 180
pmallick 1:8792acb5a039 181 /**
pmallick 1:8792acb5a039 182 * @enum ad469x_reg_access
pmallick 1:8792acb5a039 183 * @brief Register access modes
pmallick 1:8792acb5a039 184 */
pmallick 1:8792acb5a039 185 enum ad469x_reg_access {
pmallick 1:8792acb5a039 186 AD469x_BYTE_ACCESS,
pmallick 1:8792acb5a039 187 AD469x_WORD_ACCESS,
pmallick 1:8792acb5a039 188 };
pmallick 1:8792acb5a039 189
pmallick 1:8792acb5a039 190 /**
pmallick 1:8792acb5a039 191 * @enum ad469x_supported_dev_ids
pmallick 1:8792acb5a039 192 * @brief Supported devices
pmallick 1:8792acb5a039 193 */
pmallick 1:8792acb5a039 194 enum ad469x_supported_dev_ids {
pmallick 1:8792acb5a039 195 ID_AD4695,
pmallick 1:8792acb5a039 196 ID_AD4696,
pmallick 1:8792acb5a039 197 ID_AD4697,
pmallick 1:8792acb5a039 198 };
pmallick 1:8792acb5a039 199
pmallick 1:8792acb5a039 200 /**
pmallick 1:8792acb5a039 201 * @enum ad469x_osr_ratios
pmallick 1:8792acb5a039 202 * @brief Supported oversampling ratios
pmallick 1:8792acb5a039 203 */
pmallick 1:8792acb5a039 204 enum ad469x_osr_ratios {
pmallick 1:8792acb5a039 205 AD469x_OSR_1,
pmallick 1:8792acb5a039 206 AD469x_OSR_4,
pmallick 1:8792acb5a039 207 AD469x_OSR_16,
pmallick 1:8792acb5a039 208 AD469x_OSR_64
pmallick 1:8792acb5a039 209 };
pmallick 1:8792acb5a039 210
pmallick 1:8792acb5a039 211 /**
pmallick 1:8792acb5a039 212 * @struct ad469x_init_param
pmallick 1:8792acb5a039 213 * @brief Structure containing the init parameters needed by the ad469x device
pmallick 1:8792acb5a039 214 */
pmallick 1:8792acb5a039 215 struct ad469x_init_param {
pmallick 1:8792acb5a039 216 /* SPI */
pmallick 1:8792acb5a039 217 spi_init_param *spi_init;
pmallick 1:8792acb5a039 218 /* SPI module offload init */
pmallick 1:8792acb5a039 219 struct spi_engine_offload_init_param *offload_init_param;
pmallick 1:8792acb5a039 220 /* PWM generator init structure */
pmallick 1:8792acb5a039 221 struct pwm_init_param *trigger_pwm_init;
pmallick 1:8792acb5a039 222 /** RESET GPIO initialization structure. */
pmallick 1:8792acb5a039 223 struct gpio_init_param *gpio_resetn;
pmallick 1:8792acb5a039 224 //gpio_init_param * gpio_resetn;
pmallick 1:8792acb5a039 225 /** CONVST GPIO initialization parameters */
pmallick 1:8792acb5a039 226 struct gpio_init_param *gpio_convst;
pmallick 1:8792acb5a039 227 /** BUSY GPIO initialization parameters */
pmallick 1:8792acb5a039 228 struct gpio_init_param *gpio_busy;
pmallick 1:8792acb5a039 229 /* Clock gen for hdl design init structure */
pmallick 1:8792acb5a039 230 struct axi_clkgen_init *clkgen_init;
pmallick 1:8792acb5a039 231 /* Clock generator rate */
pmallick 1:8792acb5a039 232 uint32_t axi_clkgen_rate;
pmallick 1:8792acb5a039 233 /* Register access speed */
pmallick 1:8792acb5a039 234 uint32_t reg_access_speed;
pmallick 1:8792acb5a039 235 /* Register data width */
pmallick 1:8792acb5a039 236 uint8_t reg_data_width;
pmallick 1:8792acb5a039 237 /* Capture data width */
pmallick 1:8792acb5a039 238 uint8_t capture_data_width;
pmallick 1:8792acb5a039 239 /* Device Settings */
pmallick 1:8792acb5a039 240 enum ad469x_supported_dev_ids dev_id;
pmallick 1:8792acb5a039 241 /** Invalidate the Data cache for the given address range */
pmallick 1:8792acb5a039 242 void(*dcache_invalidate_range)(uint32_t address, uint32_t bytes_count);
pmallick 1:8792acb5a039 243 };
pmallick 1:8792acb5a039 244
pmallick 1:8792acb5a039 245 /**
pmallick 1:8792acb5a039 246 * @struct ad469x_dev
pmallick 1:8792acb5a039 247 * @brief Structure representing an ad469x device
pmallick 1:8792acb5a039 248 */
pmallick 1:8792acb5a039 249 struct ad469x_dev {
pmallick 1:8792acb5a039 250 /* SPI descriptor */
pmallick 1:8792acb5a039 251 spi_desc *spi_desc;
pmallick 1:8792acb5a039 252 /* Clock gen for hdl design structure */
pmallick 1:8792acb5a039 253 struct axi_clkgen *clkgen;
pmallick 1:8792acb5a039 254 /* Trigger conversion PWM generator descriptor */
pmallick 1:8792acb5a039 255 struct pwm_desc *trigger_pwm_desc;
pmallick 1:8792acb5a039 256 /* SPI module offload init */
pmallick 1:8792acb5a039 257 struct spi_engine_offload_init_param *offload_init_param;
pmallick 1:8792acb5a039 258 /* Register access speed */
pmallick 1:8792acb5a039 259 uint32_t reg_access_speed;
pmallick 1:8792acb5a039 260 /* Register data width */
pmallick 1:8792acb5a039 261 uint8_t reg_data_width;
pmallick 1:8792acb5a039 262 /* Capture data width */
pmallick 1:8792acb5a039 263 uint8_t capture_data_width;
pmallick 1:8792acb5a039 264 /* Device Settings */
pmallick 1:8792acb5a039 265 enum ad469x_supported_dev_ids dev_id;
pmallick 1:8792acb5a039 266 /** RESET GPIO handler. */
pmallick 1:8792acb5a039 267 struct gpio_desc *gpio_resetn;
pmallick 1:8792acb5a039 268 /** CONVST GPIO descriptor */
pmallick 1:8792acb5a039 269 struct gpio_desc *gpio_convst;
pmallick 1:8792acb5a039 270 /** BUSY GPIO descriptor */
pmallick 1:8792acb5a039 271 struct gpio_desc *gpio_busy;
pmallick 1:8792acb5a039 272 /** Invalidate the Data cache for the given address range */
pmallick 1:8792acb5a039 273 void(*dcache_invalidate_range)(uint32_t address, uint32_t bytes_count);
pmallick 1:8792acb5a039 274 /** Current channel sequence */
pmallick 1:8792acb5a039 275 enum ad469x_channel_sequencing ch_sequence;
pmallick 1:8792acb5a039 276 /** OSR resolution corresponding to each channel, when advanced
pmallick 1:8792acb5a039 277 * sequencer is selected. */
pmallick 1:8792acb5a039 278 enum ad469x_osr_ratios adv_seq_osr_resol[AD469x_CHANNEL_NO];
pmallick 1:8792acb5a039 279 /** Channel slots for advanced sequencer */
pmallick 1:8792acb5a039 280 uint8_t ch_slots[AD469x_SLOTS_NO];
pmallick 1:8792acb5a039 281 /** Temperature enabled for standard and advanced sequencer if set. */
pmallick 1:8792acb5a039 282 bool temp_enabled;
pmallick 1:8792acb5a039 283 /** Number of active channel slots, for advanced sequencer */
pmallick 1:8792acb5a039 284 uint8_t num_slots;
pmallick 1:8792acb5a039 285 /* Buffer to store the conv result */
pmallick 1:8792acb5a039 286 uint8_t data[16];
pmallick 1:8792acb5a039 287 };
pmallick 1:8792acb5a039 288
pmallick 1:8792acb5a039 289 /******************************************************************************/
pmallick 1:8792acb5a039 290 /************************ Functions Declarations ******************************/
pmallick 1:8792acb5a039 291 /******************************************************************************/
pmallick 1:8792acb5a039 292 /* Read device register. */
pmallick 1:8792acb5a039 293 int32_t ad469x_spi_reg_read(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 294 uint16_t reg_addr,
pmallick 1:8792acb5a039 295 uint8_t *reg_data);
pmallick 1:8792acb5a039 296
pmallick 1:8792acb5a039 297 /* Write device register */
pmallick 1:8792acb5a039 298 int32_t ad469x_spi_reg_write(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 299 uint16_t reg_addr,
pmallick 1:8792acb5a039 300 uint8_t reg_data);
pmallick 1:8792acb5a039 301
pmallick 1:8792acb5a039 302 /* Read from device using a mask */
pmallick 1:8792acb5a039 303 int32_t ad469x_spi_read_mask(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 304 uint16_t reg_addr,
pmallick 1:8792acb5a039 305 uint8_t mask,
pmallick 1:8792acb5a039 306 uint8_t *data);
pmallick 1:8792acb5a039 307
pmallick 1:8792acb5a039 308 /* Write to device using a mask */
pmallick 1:8792acb5a039 309 int32_t ad469x_spi_write_mask(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 310 uint16_t reg_addr,
pmallick 1:8792acb5a039 311 uint8_t mask,
pmallick 1:8792acb5a039 312 uint8_t data);
pmallick 1:8792acb5a039 313
pmallick 1:8792acb5a039 314 /* Read data from device */
pmallick 1:8792acb5a039 315 int32_t ad469x_read_data(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 316 uint8_t channel,
pmallick 1:8792acb5a039 317 uint32_t *buf,
pmallick 1:8792acb5a039 318 uint16_t samples);
pmallick 1:8792acb5a039 319
pmallick 1:8792acb5a039 320 /* Read from device when converter has the channel sequencer activated */
pmallick 1:8792acb5a039 321 int32_t ad469x_seq_read_data(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 322 uint32_t *buf,
pmallick 1:8792acb5a039 323 uint16_t samples);
pmallick 1:8792acb5a039 324
pmallick 1:8792acb5a039 325 /* Set channel sequence */
pmallick 1:8792acb5a039 326 int32_t ad469x_set_channel_sequence(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 327 enum ad469x_channel_sequencing seq);
pmallick 1:8792acb5a039 328
pmallick 1:8792acb5a039 329 /* Configure standard sequencer enabled channels */
pmallick 1:8792acb5a039 330 int32_t ad469x_std_sequence_ch(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 331 uint32_t ch_mask);
pmallick 1:8792acb5a039 332
pmallick 1:8792acb5a039 333 /* Configure advanced sequencer number of slots */
pmallick 1:8792acb5a039 334 int32_t ad469x_adv_sequence_set_num_slots(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 335 uint8_t num_slots);
pmallick 1:8792acb5a039 336
pmallick 1:8792acb5a039 337 /* Advanced sequencer, assign channel to a slot */
pmallick 1:8792acb5a039 338 int32_t ad469x_adv_sequence_set_slot(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 339 uint8_t slot,
pmallick 1:8792acb5a039 340 uint8_t channel);
pmallick 1:8792acb5a039 341
pmallick 1:8792acb5a039 342 /* Enable temperature read at the end of the sequence, for standard and */
pmallick 1:8792acb5a039 343 int32_t ad469x_sequence_enable_temp(struct ad469x_dev *dev);
pmallick 1:8792acb5a039 344
pmallick 1:8792acb5a039 345 /* Disable temperature read at the end of the sequence, for standard and */
pmallick 1:8792acb5a039 346 int32_t ad469x_sequence_disable_temp(struct ad469x_dev *dev);
pmallick 1:8792acb5a039 347
pmallick 1:8792acb5a039 348 /* Configure over sampling ratio in advanced sequencer mode */
pmallick 1:8792acb5a039 349 int32_t ad469x_adv_seq_osr(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 350 uint16_t ch,
pmallick 1:8792acb5a039 351 enum ad469x_osr_ratios ratio);
pmallick 1:8792acb5a039 352
pmallick 1:8792acb5a039 353 /* Configure over sampling ratio in standard sequencer mode */
pmallick 1:8792acb5a039 354 int32_t ad469x_std_seq_osr(struct ad469x_dev *dev,
pmallick 1:8792acb5a039 355 enum ad469x_osr_ratios ratio);
pmallick 1:8792acb5a039 356
pmallick 1:8792acb5a039 357 /* Enter conversion mode */
pmallick 1:8792acb5a039 358 int32_t ad469x_enter_conversion_mode(struct ad469x_dev *dev);
pmallick 1:8792acb5a039 359
pmallick 1:8792acb5a039 360 /* Exit conversion mode */
pmallick 1:8792acb5a039 361 int32_t ad469x_exit_conversion_mode(struct ad469x_dev *dev);
pmallick 1:8792acb5a039 362
pmallick 1:8792acb5a039 363 /* Initialize the device. */
pmallick 1:8792acb5a039 364 int32_t ad469x_init(struct ad469x_dev **device,
pmallick 1:8792acb5a039 365 struct ad469x_init_param *init_param);
pmallick 1:8792acb5a039 366
pmallick 1:8792acb5a039 367 /* Remove the device and release resources. */
pmallick 1:8792acb5a039 368 int32_t ad469x_remove(struct ad469x_dev *dev);
pmallick 1:8792acb5a039 369
pmallick 1:8792acb5a039 370 #endif /* SRC_AD469X_H_ */