Bryan Edelman
nrfl2041 NOT WORKING
nRF24L01.h@0:da73b7c64384, 2010-10-06 (annotated)
- Committer:
- pillsburydoughboy
- Date:
- Wed Oct 06 14:46:08 2010 +0000
- Revision:
- 0:da73b7c64384
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| pillsburydoughboy | 0:da73b7c64384 | 1 | /* Memory Map */ |
| pillsburydoughboy | 0:da73b7c64384 | 2 | #define CONFIG 0x00 |
| pillsburydoughboy | 0:da73b7c64384 | 3 | #define EN_AA 0x01 |
| pillsburydoughboy | 0:da73b7c64384 | 4 | #define EN_RXADDR 0x02 |
| pillsburydoughboy | 0:da73b7c64384 | 5 | #define SETUP_AW 0x03 |
| pillsburydoughboy | 0:da73b7c64384 | 6 | #define SETUP_RETR 0x04 |
| pillsburydoughboy | 0:da73b7c64384 | 7 | #define RF_CH 0x05 |
| pillsburydoughboy | 0:da73b7c64384 | 8 | #define RF_SETUP 0x06 |
| pillsburydoughboy | 0:da73b7c64384 | 9 | #define STATUS 0x07 |
| pillsburydoughboy | 0:da73b7c64384 | 10 | #define OBSERVE_TX 0x08 |
| pillsburydoughboy | 0:da73b7c64384 | 11 | #define CD 0x09 |
| pillsburydoughboy | 0:da73b7c64384 | 12 | #define RX_ADDR_P0 0x0A |
| pillsburydoughboy | 0:da73b7c64384 | 13 | #define RX_ADDR_P1 0x0B |
| pillsburydoughboy | 0:da73b7c64384 | 14 | #define RX_ADDR_P2 0x0C |
| pillsburydoughboy | 0:da73b7c64384 | 15 | #define RX_ADDR_P3 0x0D |
| pillsburydoughboy | 0:da73b7c64384 | 16 | #define RX_ADDR_P4 0x0E |
| pillsburydoughboy | 0:da73b7c64384 | 17 | #define RX_ADDR_P5 0x0F |
| pillsburydoughboy | 0:da73b7c64384 | 18 | #define TX_ADDR 0x10 |
| pillsburydoughboy | 0:da73b7c64384 | 19 | #define RX_PW_P0 0x11 |
| pillsburydoughboy | 0:da73b7c64384 | 20 | #define RX_PW_P1 0x12 |
| pillsburydoughboy | 0:da73b7c64384 | 21 | #define RX_PW_P2 0x13 |
| pillsburydoughboy | 0:da73b7c64384 | 22 | #define RX_PW_P3 0x14 |
| pillsburydoughboy | 0:da73b7c64384 | 23 | #define RX_PW_P4 0x15 |
| pillsburydoughboy | 0:da73b7c64384 | 24 | #define RX_PW_P5 0x16 |
| pillsburydoughboy | 0:da73b7c64384 | 25 | #define FIFO_STATUS 0x17 |
| pillsburydoughboy | 0:da73b7c64384 | 26 | |
| pillsburydoughboy | 0:da73b7c64384 | 27 | /* Bit Mnemonics */ |
| pillsburydoughboy | 0:da73b7c64384 | 28 | #define MASK_RX_DR 6 |
| pillsburydoughboy | 0:da73b7c64384 | 29 | #define MASK_TX_DS 5 |
| pillsburydoughboy | 0:da73b7c64384 | 30 | #define MASK_MAX_RT 4 |
| pillsburydoughboy | 0:da73b7c64384 | 31 | #define EN_CRC 3 |
| pillsburydoughboy | 0:da73b7c64384 | 32 | #define CRCO 2 |
| pillsburydoughboy | 0:da73b7c64384 | 33 | #define PWR_UP 1 |
| pillsburydoughboy | 0:da73b7c64384 | 34 | #define PRIM_RX 0 |
| pillsburydoughboy | 0:da73b7c64384 | 35 | #define ENAA_P5 5 |
| pillsburydoughboy | 0:da73b7c64384 | 36 | #define ENAA_P4 4 |
| pillsburydoughboy | 0:da73b7c64384 | 37 | #define ENAA_P3 3 |
| pillsburydoughboy | 0:da73b7c64384 | 38 | #define ENAA_P2 2 |
| pillsburydoughboy | 0:da73b7c64384 | 39 | #define ENAA_P1 1 |
| pillsburydoughboy | 0:da73b7c64384 | 40 | #define ENAA_P0 0 |
| pillsburydoughboy | 0:da73b7c64384 | 41 | #define ERX_P5 5 |
| pillsburydoughboy | 0:da73b7c64384 | 42 | #define ERX_P4 4 |
| pillsburydoughboy | 0:da73b7c64384 | 43 | #define ERX_P3 3 |
| pillsburydoughboy | 0:da73b7c64384 | 44 | #define ERX_P2 2 |
| pillsburydoughboy | 0:da73b7c64384 | 45 | #define ERX_P1 1 |
| pillsburydoughboy | 0:da73b7c64384 | 46 | #define ERX_P0 0 |
| pillsburydoughboy | 0:da73b7c64384 | 47 | #define AW 0 |
| pillsburydoughboy | 0:da73b7c64384 | 48 | #define ARD 4 |
| pillsburydoughboy | 0:da73b7c64384 | 49 | #define ARC 0 |
| pillsburydoughboy | 0:da73b7c64384 | 50 | #define RF_DR_LOW 5 |
| pillsburydoughboy | 0:da73b7c64384 | 51 | #define PLL_LOCK 4 |
| pillsburydoughboy | 0:da73b7c64384 | 52 | #define RF_DR_HIGH 3 |
| pillsburydoughboy | 0:da73b7c64384 | 53 | #define RF_PWR 1 |
| pillsburydoughboy | 0:da73b7c64384 | 54 | #define LNA_HCURR 0 |
| pillsburydoughboy | 0:da73b7c64384 | 55 | #define RX_DR 6 |
| pillsburydoughboy | 0:da73b7c64384 | 56 | #define TX_DS 5 |
| pillsburydoughboy | 0:da73b7c64384 | 57 | #define MAX_RT 4 |
| pillsburydoughboy | 0:da73b7c64384 | 58 | #define RX_P_NO 1 |
| pillsburydoughboy | 0:da73b7c64384 | 59 | #define TX_FULL 0 |
| pillsburydoughboy | 0:da73b7c64384 | 60 | #define PLOS_CNT 4 |
| pillsburydoughboy | 0:da73b7c64384 | 61 | #define ARC_CNT 0 |
| pillsburydoughboy | 0:da73b7c64384 | 62 | #define TX_REUSE 6 |
| pillsburydoughboy | 0:da73b7c64384 | 63 | #define FIFO_FULL 5 |
| pillsburydoughboy | 0:da73b7c64384 | 64 | #define TX_EMPTY 4 |
| pillsburydoughboy | 0:da73b7c64384 | 65 | #define RX_FULL 1 |
| pillsburydoughboy | 0:da73b7c64384 | 66 | #define RX_EMPTY 0 |
| pillsburydoughboy | 0:da73b7c64384 | 67 | |
| pillsburydoughboy | 0:da73b7c64384 | 68 | /* Instruction Mnemonics */ |
| pillsburydoughboy | 0:da73b7c64384 | 69 | #define READ 0x00 |
| pillsburydoughboy | 0:da73b7c64384 | 70 | #define WRITE 0x20 |
| pillsburydoughboy | 0:da73b7c64384 | 71 | #define REGISTER_MASK 0x1F |
| pillsburydoughboy | 0:da73b7c64384 | 72 | #define R_RX_PAYLOAD 0x61 |
| pillsburydoughboy | 0:da73b7c64384 | 73 | #define W_TX_PAYLOAD 0xA0 |
| pillsburydoughboy | 0:da73b7c64384 | 74 | #define FLUSH_TX 0xE1 |
| pillsburydoughboy | 0:da73b7c64384 | 75 | #define FLUSH_RX 0xE2 |
| pillsburydoughboy | 0:da73b7c64384 | 76 | #define REUSE_TX_PL 0xE3 |
| pillsburydoughboy | 0:da73b7c64384 | 77 | #define NOP 0xFF |