nrfl2041 - nrfl2041 NOT WORKING

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Bryan Edelman / Mbed 2 deprecated nrfl2041

nrfl2041 NOT WORKING

main.cpp@0:da73b7c64384, 2010-10-06 (annotated)

Committer:: pillsburydoughboy
Date:: Wed Oct 06 14:46:08 2010 +0000
Revision:: 0:da73b7c64384

Who changed what in which revision?

User	Revision	Line number	New contents of line
pillsburydoughboy	0:da73b7c64384	1	//Bryan Edelman
pillsburydoughboy	0:da73b7c64384	2	//edelmanb@colorado.edu
pillsburydoughboy	0:da73b7c64384	3	//2/24/2010
pillsburydoughboy	0:da73b7c64384	4	#include "mbed.h"
pillsburydoughboy	0:da73b7c64384	5	#include "nRF24L01.h"
pillsburydoughboy	0:da73b7c64384	6	//spi comms with nrf24l01+ chip. ms bit first, LSbyte first!
pillsburydoughboy	0:da73b7c64384	7	//or with below to get correct code
pillsburydoughboy	0:da73b7c64384	8	//--------------------------------------------------------------------------------------
pillsburydoughboy	0:da73b7c64384	9
pillsburydoughboy	0:da73b7c64384	10	//---------------------------Settable Configurations---------------------------------------
pillsburydoughboy	0:da73b7c64384	11	#define PAYLOAD_LENGTH 1 // Byte data packet length
pillsburydoughboy	0:da73b7c64384	12	#define CHANNEL 0x10 //Channel to transmit on
pillsburydoughboy	0:da73b7c64384	13	#define regCONFIG ( (1 << MASK_TX_DS) \| (1<<EN_CRC) \| (1<<CRCO) \| (1<<MASK_MAX_RT) ) //defualt config
pillsburydoughboy	0:da73b7c64384	14	#define regRF_SETUP ( (0<<RF_DR_HIGH)\|(3<<RF_PWR))
pillsburydoughboy	0:da73b7c64384	15	#define ADDRESS_LENGTH 0x01
pillsburydoughboy	0:da73b7c64384	16
pillsburydoughboy	0:da73b7c64384	17	//------------------------------------------------------------------------------------------
pillsburydoughboy	0:da73b7c64384	18	volatile int temp_byte1=0,temp_byte2=0,temp_byte3=0,temp_byte4=0,temp_byte5=0,temp_byte=0; //for reading spi results
pillsburydoughboy	0:da73b7c64384	19	SPI spi(p5, p6, p7); // mosi, miso, sclk
pillsburydoughboy	0:da73b7c64384	20	//RX Module
pillsburydoughboy	0:da73b7c64384	21	DigitalOut rx_cs(p29);
pillsburydoughboy	0:da73b7c64384	22	DigitalOut rx_ce(p30);
pillsburydoughboy	0:da73b7c64384	23	DigitalIn rx_irq(p28);
pillsburydoughboy	0:da73b7c64384	24	//TX Module
pillsburydoughboy	0:da73b7c64384	25	DigitalOut tx_cs(p23);
pillsburydoughboy	0:da73b7c64384	26	DigitalOut tx_ce(p24);
pillsburydoughboy	0:da73b7c64384	27	DigitalIn tx_irq(p22);
pillsburydoughboy	0:da73b7c64384	28
pillsburydoughboy	0:da73b7c64384	29	DigitalOut led1(LED1); //debug led
pillsburydoughboy	0:da73b7c64384	30	Serial pc(USBTX, USBRX); // tx, rx
pillsburydoughboy	0:da73b7c64384	31
pillsburydoughboy	0:da73b7c64384	32	bool PTX0 = 0;
pillsburydoughboy	0:da73b7c64384	33	bool PTX1 = 1;
pillsburydoughboy	0:da73b7c64384	34
pillsburydoughboy	0:da73b7c64384	35	//***************************Function Definitions********************
pillsburydoughboy	0:da73b7c64384	36	void setup_rx();
pillsburydoughboy	0:da73b7c64384	37	void setup_tx();
pillsburydoughboy	0:da73b7c64384	38	void setup();
pillsburydoughboy	0:da73b7c64384	39	uint8_t getStatusRX();
pillsburydoughboy	0:da73b7c64384	40	uint8_t getStatusTX();
pillsburydoughboy	0:da73b7c64384	41	bool dataReady(); //working
pillsburydoughboy	0:da73b7c64384	42	void configRegTX(uint8_t reg, uint8_t value); //working
pillsburydoughboy	0:da73b7c64384	43	void configRegRX(uint8_t reg, uint8_t value); //working
pillsburydoughboy	0:da73b7c64384	44	uint8_t readRegTX(uint8_t reg); //working
pillsburydoughboy	0:da73b7c64384	45	uint8_t readRegRX(uint8_t reg); //working
pillsburydoughboy	0:da73b7c64384	46	void sendData(uint8_t data_byte);
pillsburydoughboy	0:da73b7c64384	47	void transmitSync(uint8_t * dataout,uint8_t len); //not implemented yet
pillsburydoughboy	0:da73b7c64384	48	uint8_t getData();
pillsburydoughboy	0:da73b7c64384	49	//************************************************************************
pillsburydoughboy	0:da73b7c64384	50
pillsburydoughboy	0:da73b7c64384	51	//**************************Funciton Implementations******************
pillsburydoughboy	0:da73b7c64384	52	void setup() {
pillsburydoughboy	0:da73b7c64384	53	//setup pins, SPI format and speed....
pillsburydoughboy	0:da73b7c64384	54	rx_ce =0; // rx chip enable low
pillsburydoughboy	0:da73b7c64384	55	rx_cs =1; // rx cs line high please
pillsburydoughboy	0:da73b7c64384	56	tx_ce = 0;// tx chip enable low
pillsburydoughboy	0:da73b7c64384	57	tx_cs =1; // tx cs line high please
pillsburydoughboy	0:da73b7c64384	58	spi.format(8,0); // 8 bits per write, mode 0
pillsburydoughboy	0:da73b7c64384	59	spi.frequency(1000000); //1 megahurtz note: doesnt work lower
pillsburydoughboy	0:da73b7c64384	60	led1=0;
pillsburydoughboy	0:da73b7c64384	61	wait(.1); //startup time
pillsburydoughboy	0:da73b7c64384	62	/* pc.printf(" RX Registers \nConfig = %x \n",readRegRX(CONFIG));
pillsburydoughboy	0:da73b7c64384	63	pc.printf("enaa = %x \n",readRegRX(EN_AA));
pillsburydoughboy	0:da73b7c64384	64	*/pc.printf("enrxadr = %x \n",readRegRX(EN_RXADDR));
pillsburydoughboy	0:da73b7c64384	65	/*pc.printf("aw= %x \n",readRegRX(SETUP_AW));
pillsburydoughboy	0:da73b7c64384	66	pc.printf("retr = %x \n",readRegRX(SETUP_RETR));
pillsburydoughboy	0:da73b7c64384	67	pc.printf("rf ch = %x \n",readRegRX(RF_CH));
pillsburydoughboy	0:da73b7c64384	68	pc.printf("rf setup = %x \n",readRegRX(RF_SETUP));
pillsburydoughboy	0:da73b7c64384	69	pc.printf("rx pw 0 = %x \n",readRegRX(RX_PW_P0));
pillsburydoughboy	0:da73b7c64384	70	pc.printf("rx pw 1 = %x \n\n",readRegRX(RX_PW_P1));
pillsburydoughboy	0:da73b7c64384	71
pillsburydoughboy	0:da73b7c64384	72	pc.printf(" TX Registers \nConfig = %x \n",readRegTX(CONFIG));
pillsburydoughboy	0:da73b7c64384	73	pc.printf("enaa = %x \n",readRegTX(EN_AA));
pillsburydoughboy	0:da73b7c64384	74	pc.printf("aw= %x \n",readRegTX(SETUP_AW));
pillsburydoughboy	0:da73b7c64384	75	pc.printf("retr = %x \n",readRegTX(SETUP_RETR));
pillsburydoughboy	0:da73b7c64384	76	pc.printf("rf ch = %x \n",readRegTX(RF_CH));
pillsburydoughboy	0:da73b7c64384	77	pc.printf("rf setup = %x \n",readRegTX(RF_SETUP));
pillsburydoughboy	0:da73b7c64384	78	pc.printf("tx addy = %x \n",readRegTX(TX_ADDR));*/
pillsburydoughboy	0:da73b7c64384	79
pillsburydoughboy	0:da73b7c64384	80	}
pillsburydoughboy	0:da73b7c64384	81	void setup_rx() {
pillsburydoughboy	0:da73b7c64384	82	uint8_t regConfig =0, regRfChan=0, regRfSetup=0, status=0;
pillsburydoughboy	0:da73b7c64384	83
pillsburydoughboy	0:da73b7c64384	84	configRegRX(CONFIG,regCONFIG\|(1<<PWR_UP)\|(1<<PRIM_RX)); ///setup to receive, irq on recieve, CRC 2 byte, power up
pillsburydoughboy	0:da73b7c64384	85	configRegRX(RF_CH, CHANNEL); //set channel #
pillsburydoughboy	0:da73b7c64384	86	configRegRX(RF_SETUP,regRF_SETUP); //no continuos carrier, 250Kbps, 0dBm
pillsburydoughboy	0:da73b7c64384	87
pillsburydoughboy	0:da73b7c64384	88	rx_cs =0;
pillsburydoughboy	0:da73b7c64384	89	spi.write(WRITE\|RX_ADDR_P0);
pillsburydoughboy	0:da73b7c64384	90	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	91	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	92	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	93	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	94	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	95	rx_cs =1;
pillsburydoughboy	0:da73b7c64384	96
pillsburydoughboy	0:da73b7c64384	97	regConfig =readRegRX(CONFIG);
pillsburydoughboy	0:da73b7c64384	98	regRfChan =readRegRX(RF_CH);
pillsburydoughboy	0:da73b7c64384	99	regRfSetup =readRegRX(RF_SETUP);
pillsburydoughboy	0:da73b7c64384	100
pillsburydoughboy	0:da73b7c64384	101	rx_cs =0;
pillsburydoughboy	0:da73b7c64384	102	spi.write(READ\|RX_ADDR_P0);
pillsburydoughboy	0:da73b7c64384	103	temp_byte1=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	104	temp_byte2=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	105	temp_byte3=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	106	temp_byte4=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	107	temp_byte5=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	108	rx_cs =1;
pillsburydoughboy	0:da73b7c64384	109
pillsburydoughboy	0:da73b7c64384	110	rx_cs =0;
pillsburydoughboy	0:da73b7c64384	111	spi.write(FLUSH_RX);
pillsburydoughboy	0:da73b7c64384	112	rx_cs =1;
pillsburydoughboy	0:da73b7c64384	113
pillsburydoughboy	0:da73b7c64384	114	status=getStatusRX();
pillsburydoughboy	0:da73b7c64384	115	configRegRX(STATUS, status\|(1 << TX_DS) \| (1 << MAX_RT));
pillsburydoughboy	0:da73b7c64384	116	status=getStatusRX();
pillsburydoughboy	0:da73b7c64384	117
pillsburydoughboy	0:da73b7c64384	118	pc.printf("RX Config Register = %x \n RX Channel # = %x \n RX RF Setup Reg = %x \n RX Status Reg = %x \n ", regConfig, regRfChan, regRfSetup, status);
pillsburydoughboy	0:da73b7c64384	119	pc.printf("RX address = %x%x%x%x%x \n", temp_byte5,temp_byte4,temp_byte3,temp_byte2,temp_byte1);
pillsburydoughboy	0:da73b7c64384	120	rx_ce=1; //set to recieve mode
pillsburydoughboy	0:da73b7c64384	121	return;
pillsburydoughboy	0:da73b7c64384	122	}
pillsburydoughboy	0:da73b7c64384	123
pillsburydoughboy	0:da73b7c64384	124	void setup_tx() {
pillsburydoughboy	0:da73b7c64384	125	uint8_t regConfig =0, regRfChan=0, regRfSetup=0, status=0;
pillsburydoughboy	0:da73b7c64384	126
pillsburydoughboy	0:da73b7c64384	127	configRegTX(CONFIG,regCONFIG\|(1<<PWR_UP)\|(0<<PRIM_RX));
pillsburydoughboy	0:da73b7c64384	128	configRegTX(RF_CH,CHANNEL);
pillsburydoughboy	0:da73b7c64384	129	configRegTX(RF_SETUP,regRF_SETUP);
pillsburydoughboy	0:da73b7c64384	130
pillsburydoughboy	0:da73b7c64384	131	regConfig =readRegTX(CONFIG);
pillsburydoughboy	0:da73b7c64384	132	regRfChan =readRegTX(RF_CH);
pillsburydoughboy	0:da73b7c64384	133	regRfSetup =readRegTX(RF_SETUP);
pillsburydoughboy	0:da73b7c64384	134
pillsburydoughboy	0:da73b7c64384	135	tx_cs =0;
pillsburydoughboy	0:da73b7c64384	136	spi.write(WRITE\|TX_ADDR);
pillsburydoughboy	0:da73b7c64384	137	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	138	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	139	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	140	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	141	spi.write(0x51);
pillsburydoughboy	0:da73b7c64384	142	tx_cs =1;
pillsburydoughboy	0:da73b7c64384	143
pillsburydoughboy	0:da73b7c64384	144	tx_cs =0;
pillsburydoughboy	0:da73b7c64384	145	spi.write(READ\|TX_ADDR);
pillsburydoughboy	0:da73b7c64384	146	temp_byte1=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	147	temp_byte2=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	148	temp_byte3=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	149	temp_byte4=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	150	temp_byte5=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	151	tx_cs =1;
pillsburydoughboy	0:da73b7c64384	152
pillsburydoughboy	0:da73b7c64384	153	status=getStatusTX();
pillsburydoughboy	0:da73b7c64384	154	configRegTX(STATUS, status\|(1 << TX_DS) \| (1 << MAX_RT));
pillsburydoughboy	0:da73b7c64384	155
pillsburydoughboy	0:da73b7c64384	156	tx_cs =0;
pillsburydoughboy	0:da73b7c64384	157	spi.write(FLUSH_TX);
pillsburydoughboy	0:da73b7c64384	158	tx_cs =1;
pillsburydoughboy	0:da73b7c64384	159
pillsburydoughboy	0:da73b7c64384	160	status=getStatusTX();
pillsburydoughboy	0:da73b7c64384	161
pillsburydoughboy	0:da73b7c64384	162	pc.printf("TX Config Register = %x \n TX Channel # = %x \n TX RF Setup Reg = %x \n TX Status Reg = %x \n ", regConfig, regRfChan, regRfSetup, status);
pillsburydoughboy	0:da73b7c64384	163	pc.printf("TX address = %x%x%x%x%x \n", temp_byte5,temp_byte4,temp_byte3,temp_byte2,temp_byte1);
pillsburydoughboy	0:da73b7c64384	164
pillsburydoughboy	0:da73b7c64384	165	tx_ce=0;
pillsburydoughboy	0:da73b7c64384	166	return;
pillsburydoughboy	0:da73b7c64384	167	}
pillsburydoughboy	0:da73b7c64384	168
pillsburydoughboy	0:da73b7c64384	169	uint8_t getStatusTX() {
pillsburydoughboy	0:da73b7c64384	170	uint8_t status=0;
pillsburydoughboy	0:da73b7c64384	171	tx_cs = 0;
pillsburydoughboy	0:da73b7c64384	172	spi.write(READ\|STATUS);
pillsburydoughboy	0:da73b7c64384	173	status =spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	174	tx_cs =1;
pillsburydoughboy	0:da73b7c64384	175	return status;
pillsburydoughboy	0:da73b7c64384	176	}
pillsburydoughboy	0:da73b7c64384	177	uint8_t getStatusRX() {
pillsburydoughboy	0:da73b7c64384	178	uint8_t status=0;
pillsburydoughboy	0:da73b7c64384	179	rx_cs = 0;
pillsburydoughboy	0:da73b7c64384	180	spi.write(READ\|STATUS);
pillsburydoughboy	0:da73b7c64384	181	status =spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	182	rx_cs =1;
pillsburydoughboy	0:da73b7c64384	183	return status;
pillsburydoughboy	0:da73b7c64384	184	}
pillsburydoughboy	0:da73b7c64384	185	bool dataReady() {
pillsburydoughboy	0:da73b7c64384	186	uint8_t status = getStatusRX();
pillsburydoughboy	0:da73b7c64384	187	return (status & (1 << RX_DR));
pillsburydoughboy	0:da73b7c64384	188	}
pillsburydoughboy	0:da73b7c64384	189	void configRegTX(uint8_t reg, uint8_t value) {
pillsburydoughboy	0:da73b7c64384	190	tx_cs=0;
pillsburydoughboy	0:da73b7c64384	191	spi.write(WRITE\|reg);
pillsburydoughboy	0:da73b7c64384	192	spi.write(WRITE\|value);
pillsburydoughboy	0:da73b7c64384	193	tx_cs=1;
pillsburydoughboy	0:da73b7c64384	194	}
pillsburydoughboy	0:da73b7c64384	195	void configRegRX(uint8_t reg, uint8_t value) {
pillsburydoughboy	0:da73b7c64384	196	rx_cs=0;
pillsburydoughboy	0:da73b7c64384	197	spi.write(WRITE\|reg);
pillsburydoughboy	0:da73b7c64384	198	spi.write(WRITE\|value);
pillsburydoughboy	0:da73b7c64384	199	rx_cs=1;
pillsburydoughboy	0:da73b7c64384	200	}
pillsburydoughboy	0:da73b7c64384	201	void sendData(uint8_t data) {
pillsburydoughboy	0:da73b7c64384	202	uint8_t status;
pillsburydoughboy	0:da73b7c64384	203	status = getStatusTX();
pillsburydoughboy	0:da73b7c64384	204	PTX1=1;
pillsburydoughboy	0:da73b7c64384	205	while (PTX1) {
pillsburydoughboy	0:da73b7c64384	206	status = getStatusTX();
pillsburydoughboy	0:da73b7c64384	207
pillsburydoughboy	0:da73b7c64384	208	if ((status & ((1 << TX_DS) \| (1 << MAX_RT)))) {
pillsburydoughboy	0:da73b7c64384	209	PTX1 = 0;
pillsburydoughboy	0:da73b7c64384	210	break;
pillsburydoughboy	0:da73b7c64384	211	}
pillsburydoughboy	0:da73b7c64384	212	tx_ce=0;
pillsburydoughboy	0:da73b7c64384	213
pillsburydoughboy	0:da73b7c64384	214	PTX1 = 1;
pillsburydoughboy	0:da73b7c64384	215	configRegTX(CONFIG, regCONFIG \| ( (1<<PWR_UP) \| (0<<PRIM_RX) ) ); // Set to transmitter mode , Power up
pillsburydoughboy	0:da73b7c64384	216
pillsburydoughboy	0:da73b7c64384	217	tx_cs = 0; // Pull down chip select
pillsburydoughboy	0:da73b7c64384	218	spi.write( FLUSH_TX ); // Write cmd to flush tx fifo
pillsburydoughboy	0:da73b7c64384	219	tx_cs = 1; // Pull up chip select
pillsburydoughboy	0:da73b7c64384	220
pillsburydoughboy	0:da73b7c64384	221	//pc.printf("TX status before = %x \n", getStatusTX());
pillsburydoughboy	0:da73b7c64384	222	//pc.printf("data to be sent = %x \n", data);
pillsburydoughboy	0:da73b7c64384	223	tx_cs = 0; // Pull down chip select
pillsburydoughboy	0:da73b7c64384	224	spi.write(W_TX_PAYLOAD); // Write cmd to write payload
pillsburydoughboy	0:da73b7c64384	225	spi.write(data); // Write payload
pillsburydoughboy	0:da73b7c64384	226	tx_cs = 1; // Pull up chip select
pillsburydoughboy	0:da73b7c64384	227	// pc.printf("TX FIFO status = %x \n", readRegTX(FIFO_STATUS));//
pillsburydoughboy	0:da73b7c64384	228	tx_ce=1; // Start transmission
pillsburydoughboy	0:da73b7c64384	229	wait(.005); //50uS delay
pillsburydoughboy	0:da73b7c64384	230	tx_ce=0;
pillsburydoughboy	0:da73b7c64384	231	// wait(1);//
pillsburydoughboy	0:da73b7c64384	232	// pc.printf("TX FIFO status = %x \n", readRegTX(FIFO_STATUS));//
pillsburydoughboy	0:da73b7c64384	233	// pc.printf("TX status after = %x \n", getStatusTX());
pillsburydoughboy	0:da73b7c64384	234	configRegTX(STATUS,getStatusTX()\|(1 << TX_DS) \| (1 << MAX_RT)); //clear sent bit
pillsburydoughboy	0:da73b7c64384	235	return;
pillsburydoughboy	0:da73b7c64384	236	}
pillsburydoughboy	0:da73b7c64384	237	}
pillsburydoughboy	0:da73b7c64384	238	void transmitSync(uint8_t * dataout,uint8_t len) { //later....
pillsburydoughboy	0:da73b7c64384	239	uint8_t i; //test me!
pillsburydoughboy	0:da73b7c64384	240	pc.printf("length = %i \n", len);
pillsburydoughboy	0:da73b7c64384	241	for (i = 0;i < len;i++) {
pillsburydoughboy	0:da73b7c64384	242	spi.write(dataout[i]);
pillsburydoughboy	0:da73b7c64384	243
pillsburydoughboy	0:da73b7c64384	244	}
pillsburydoughboy	0:da73b7c64384	245	pc.printf("i = %i \n",i);
pillsburydoughboy	0:da73b7c64384	246	return;
pillsburydoughboy	0:da73b7c64384	247	}
pillsburydoughboy	0:da73b7c64384	248	uint8_t getData()
pillsburydoughboy	0:da73b7c64384	249	// Reads payload bytes into data array
pillsburydoughboy	0:da73b7c64384	250	{
pillsburydoughboy	0:da73b7c64384	251	uint8_t data_byte=0;
pillsburydoughboy	0:da73b7c64384	252	rx_cs = 0; // Pull down chip select
pillsburydoughboy	0:da73b7c64384	253	spi.write(R_RX_PAYLOAD); // Send cmd to read rx payload
pillsburydoughboy	0:da73b7c64384	254	data_byte=spi.write(NOP); // Read payload
pillsburydoughboy	0:da73b7c64384	255	rx_cs = 1; // Pull up chip select
pillsburydoughboy	0:da73b7c64384	256	configRegTX(STATUS,(1<<RX_DR)); // Reset status register
pillsburydoughboy	0:da73b7c64384	257	return data_byte;
pillsburydoughboy	0:da73b7c64384	258	}
pillsburydoughboy	0:da73b7c64384	259	uint8_t readRegTX(uint8_t reg)
pillsburydoughboy	0:da73b7c64384	260	{
pillsburydoughboy	0:da73b7c64384	261	uint8_t reg_value=0;
pillsburydoughboy	0:da73b7c64384	262	tx_cs = 0;
pillsburydoughboy	0:da73b7c64384	263	spi.write(READ\|reg);
pillsburydoughboy	0:da73b7c64384	264	reg_value=spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	265	tx_cs = 1;
pillsburydoughboy	0:da73b7c64384	266	return reg_value;
pillsburydoughboy	0:da73b7c64384	267	}
pillsburydoughboy	0:da73b7c64384	268	uint8_t readRegRX(uint8_t reg)
pillsburydoughboy	0:da73b7c64384	269	{
pillsburydoughboy	0:da73b7c64384	270	uint8_t reg_value=0;
pillsburydoughboy	0:da73b7c64384	271	rx_cs = 0;
pillsburydoughboy	0:da73b7c64384	272	spi.write(READ\|reg);
pillsburydoughboy	0:da73b7c64384	273	reg_value = spi.write(NOP);
pillsburydoughboy	0:da73b7c64384	274	rx_cs = 1;
pillsburydoughboy	0:da73b7c64384	275	return reg_value;
pillsburydoughboy	0:da73b7c64384	276	}
pillsburydoughboy	0:da73b7c64384	277	//************************************************************************
pillsburydoughboy	0:da73b7c64384	278	int main() {
pillsburydoughboy	0:da73b7c64384	279	uint8_t data_to_send =0x55;
pillsburydoughboy	0:da73b7c64384	280	setup();
pillsburydoughboy	0:da73b7c64384	281	setup_rx();
pillsburydoughboy	0:da73b7c64384	282	setup_tx();
pillsburydoughboy	0:da73b7c64384	283	wait(.1);
pillsburydoughboy	0:da73b7c64384	284	pc.printf("Setup Complete \n");
pillsburydoughboy	0:da73b7c64384	285
pillsburydoughboy	0:da73b7c64384	286	configRegRX(RX_PW_P0,PAYLOAD_LENGTH);
pillsburydoughboy	0:da73b7c64384	287	configRegRX(RX_PW_P1,PAYLOAD_LENGTH);
pillsburydoughboy	0:da73b7c64384	288	//address widths
pillsburydoughboy	0:da73b7c64384	289	configRegTX(SETUP_AW,0x03);
pillsburydoughboy	0:da73b7c64384	290	configRegRX(SETUP_AW,0x03);
pillsburydoughboy	0:da73b7c64384	291
pillsburydoughboy	0:da73b7c64384	292	configRegTX(SETUP_RETR,0<<ARC);
pillsburydoughboy	0:da73b7c64384	293	configRegRX(ENAA_P0,0x00); //Disable all AA
pillsburydoughboy	0:da73b7c64384	294	configRegRX(EN_RXADDR, 0x3F); //ENable only pipe 0
pillsburydoughboy	0:da73b7c64384	295
pillsburydoughboy	0:da73b7c64384	296
pillsburydoughboy	0:da73b7c64384	297	//send some data
pillsburydoughboy	0:da73b7c64384	298	//pc.printf("data sent \n\n");
pillsburydoughboy	0:da73b7c64384	299	configRegTX(RF_CH,0x00);
pillsburydoughboy	0:da73b7c64384	300	uint8_t i =0;
pillsburydoughboy	0:da73b7c64384	301	while (!dataReady()) {
pillsburydoughboy	0:da73b7c64384	302	pc.printf("FIFO status = %x \n i = %i \n", readRegRX(FIFO_STATUS), i);
pillsburydoughboy	0:da73b7c64384	303	wait(.01);
pillsburydoughboy	0:da73b7c64384	304	sendData(data_to_send);
pillsburydoughboy	0:da73b7c64384	305	++i;
pillsburydoughboy	0:da73b7c64384	306	configRegTX(RF_CH,i);
pillsburydoughboy	0:da73b7c64384	307	}
pillsburydoughboy	0:da73b7c64384	308	led1=1;
pillsburydoughboy	0:da73b7c64384	309	pc.printf("This is data recieved: %x \n", getData());
pillsburydoughboy	0:da73b7c64384	310	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	06 Oct 2010
Imports:	23
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	3

main.cpp@0:da73b7c64384, 2010-10-06 (annotated)

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