Pierre Provent / USBHost

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Dependents:   TEST_USB_Nucleo_F429ZI Essais_USB_Nucleo_F429ZI SID_V3_Nucleo_F429ZI SID_V4_Nucleo_F429ZI_copy

targets/TARGET_RENESAS/USBHALHost_RZ_A1.cpp@0:77ca32e8e04e, 2020-09-25 (annotated)

Committer:
pierreprovent
Date:
Fri Sep 25 10:17:49 2020 +0000
Revision:
0:77ca32e8e04e
Programme acquisition en enregistrement sur clef USB carte Nucleo F429ZI cours ELE118 Cnam

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pierreprovent 0:77ca32e8e04e 1 /* mbed USBHost Library
pierreprovent 0:77ca32e8e04e 2 * Copyright (c) 2006-2013 ARM Limited
pierreprovent 0:77ca32e8e04e 3 *
pierreprovent 0:77ca32e8e04e 4 * Licensed under the Apache License, Version 2.0 (the "License");
pierreprovent 0:77ca32e8e04e 5 * you may not use this file except in compliance with the License.
pierreprovent 0:77ca32e8e04e 6 * You may obtain a copy of the License at
pierreprovent 0:77ca32e8e04e 7 *
pierreprovent 0:77ca32e8e04e 8 * http://www.apache.org/licenses/LICENSE-2.0
pierreprovent 0:77ca32e8e04e 9 *
pierreprovent 0:77ca32e8e04e 10 * Unless required by applicable law or agreed to in writing, software
pierreprovent 0:77ca32e8e04e 11 * distributed under the License is distributed on an "AS IS" BASIS,
pierreprovent 0:77ca32e8e04e 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
pierreprovent 0:77ca32e8e04e 13 * See the License for the specific language governing permissions and
pierreprovent 0:77ca32e8e04e 14 * limitations under the License.
pierreprovent 0:77ca32e8e04e 15 */
pierreprovent 0:77ca32e8e04e 16
pierreprovent 0:77ca32e8e04e 17 #if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
pierreprovent 0:77ca32e8e04e 18
pierreprovent 0:77ca32e8e04e 19 #include "mbed.h"
pierreprovent 0:77ca32e8e04e 20 #include "USBHALHost.h"
pierreprovent 0:77ca32e8e04e 21 #include "dbg.h"
pierreprovent 0:77ca32e8e04e 22
pierreprovent 0:77ca32e8e04e 23 #include "ohci_wrapp_RZ_A1.h"
pierreprovent 0:77ca32e8e04e 24
pierreprovent 0:77ca32e8e04e 25
pierreprovent 0:77ca32e8e04e 26 #define HCCA_SIZE sizeof(HCCA)
pierreprovent 0:77ca32e8e04e 27 #define ED_SIZE sizeof(HCED)
pierreprovent 0:77ca32e8e04e 28 #define TD_SIZE sizeof(HCTD)
pierreprovent 0:77ca32e8e04e 29
pierreprovent 0:77ca32e8e04e 30 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
pierreprovent 0:77ca32e8e04e 31 #define ALIGNE_MSK (0x0000000F)
pierreprovent 0:77ca32e8e04e 32
pierreprovent 0:77ca32e8e04e 33 static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned!
pierreprovent 0:77ca32e8e04e 34
pierreprovent 0:77ca32e8e04e 35 USBHALHost * USBHALHost::instHost;
pierreprovent 0:77ca32e8e04e 36
pierreprovent 0:77ca32e8e04e 37 USBHALHost::USBHALHost() {
pierreprovent 0:77ca32e8e04e 38 instHost = this;
pierreprovent 0:77ca32e8e04e 39 memInit();
pierreprovent 0:77ca32e8e04e 40 memset((void*)usb_hcca, 0, HCCA_SIZE);
pierreprovent 0:77ca32e8e04e 41 for (int i = 0; i < MAX_ENDPOINT; i++) {
pierreprovent 0:77ca32e8e04e 42 edBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 43 }
pierreprovent 0:77ca32e8e04e 44 for (int i = 0; i < MAX_TD; i++) {
pierreprovent 0:77ca32e8e04e 45 tdBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 46 }
pierreprovent 0:77ca32e8e04e 47 }
pierreprovent 0:77ca32e8e04e 48
pierreprovent 0:77ca32e8e04e 49 void USBHALHost::init() {
pierreprovent 0:77ca32e8e04e 50 ohciwrapp_init(&_usbisr);
pierreprovent 0:77ca32e8e04e 51
pierreprovent 0:77ca32e8e04e 52 ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET
pierreprovent 0:77ca32e8e04e 53 ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
pierreprovent 0:77ca32e8e04e 54 ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero
pierreprovent 0:77ca32e8e04e 55
pierreprovent 0:77ca32e8e04e 56 // Wait 100 ms before apply reset
pierreprovent 0:77ca32e8e04e 57 wait_ms(100);
pierreprovent 0:77ca32e8e04e 58
pierreprovent 0:77ca32e8e04e 59 // software reset
pierreprovent 0:77ca32e8e04e 60 ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
pierreprovent 0:77ca32e8e04e 61
pierreprovent 0:77ca32e8e04e 62 // Write Fm Interval and Largest Data Packet Counter
pierreprovent 0:77ca32e8e04e 63 ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
pierreprovent 0:77ca32e8e04e 64 ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100);
pierreprovent 0:77ca32e8e04e 65
pierreprovent 0:77ca32e8e04e 66 // Put HC in operational state
pierreprovent 0:77ca32e8e04e 67 ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
pierreprovent 0:77ca32e8e04e 68 // Set Global Power
pierreprovent 0:77ca32e8e04e 69 ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
pierreprovent 0:77ca32e8e04e 70
pierreprovent 0:77ca32e8e04e 71 ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
pierreprovent 0:77ca32e8e04e 72
pierreprovent 0:77ca32e8e04e 73 // Clear Interrrupt Status
pierreprovent 0:77ca32e8e04e 74 ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
pierreprovent 0:77ca32e8e04e 75
pierreprovent 0:77ca32e8e04e 76 ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
pierreprovent 0:77ca32e8e04e 77
pierreprovent 0:77ca32e8e04e 78 // Enable the USB Interrupt
pierreprovent 0:77ca32e8e04e 79 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
pierreprovent 0:77ca32e8e04e 80 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
pierreprovent 0:77ca32e8e04e 81
pierreprovent 0:77ca32e8e04e 82 // Check for any connected devices
pierreprovent 0:77ca32e8e04e 83 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
pierreprovent 0:77ca32e8e04e 84 //Device connected
pierreprovent 0:77ca32e8e04e 85 wait_ms(150);
pierreprovent 0:77ca32e8e04e 86 USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
pierreprovent 0:77ca32e8e04e 87 deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
pierreprovent 0:77ca32e8e04e 88 }
pierreprovent 0:77ca32e8e04e 89 }
pierreprovent 0:77ca32e8e04e 90
pierreprovent 0:77ca32e8e04e 91 uint32_t USBHALHost::controlHeadED() {
pierreprovent 0:77ca32e8e04e 92 return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
pierreprovent 0:77ca32e8e04e 93 }
pierreprovent 0:77ca32e8e04e 94
pierreprovent 0:77ca32e8e04e 95 uint32_t USBHALHost::bulkHeadED() {
pierreprovent 0:77ca32e8e04e 96 return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
pierreprovent 0:77ca32e8e04e 97 }
pierreprovent 0:77ca32e8e04e 98
pierreprovent 0:77ca32e8e04e 99 uint32_t USBHALHost::interruptHeadED() {
pierreprovent 0:77ca32e8e04e 100 return usb_hcca->IntTable[0];
pierreprovent 0:77ca32e8e04e 101 }
pierreprovent 0:77ca32e8e04e 102
pierreprovent 0:77ca32e8e04e 103 void USBHALHost::updateBulkHeadED(uint32_t addr) {
pierreprovent 0:77ca32e8e04e 104 ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
pierreprovent 0:77ca32e8e04e 105 }
pierreprovent 0:77ca32e8e04e 106
pierreprovent 0:77ca32e8e04e 107
pierreprovent 0:77ca32e8e04e 108 void USBHALHost::updateControlHeadED(uint32_t addr) {
pierreprovent 0:77ca32e8e04e 109 ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
pierreprovent 0:77ca32e8e04e 110 }
pierreprovent 0:77ca32e8e04e 111
pierreprovent 0:77ca32e8e04e 112 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
pierreprovent 0:77ca32e8e04e 113 usb_hcca->IntTable[0] = addr;
pierreprovent 0:77ca32e8e04e 114 }
pierreprovent 0:77ca32e8e04e 115
pierreprovent 0:77ca32e8e04e 116
pierreprovent 0:77ca32e8e04e 117 void USBHALHost::enableList(ENDPOINT_TYPE type) {
pierreprovent 0:77ca32e8e04e 118 uint32_t wk_data;
pierreprovent 0:77ca32e8e04e 119
pierreprovent 0:77ca32e8e04e 120 switch(type) {
pierreprovent 0:77ca32e8e04e 121 case CONTROL_ENDPOINT:
pierreprovent 0:77ca32e8e04e 122 ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
pierreprovent 0:77ca32e8e04e 123 wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
pierreprovent 0:77ca32e8e04e 124 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
pierreprovent 0:77ca32e8e04e 125 break;
pierreprovent 0:77ca32e8e04e 126 case ISOCHRONOUS_ENDPOINT:
pierreprovent 0:77ca32e8e04e 127 break;
pierreprovent 0:77ca32e8e04e 128 case BULK_ENDPOINT:
pierreprovent 0:77ca32e8e04e 129 ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
pierreprovent 0:77ca32e8e04e 130 wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
pierreprovent 0:77ca32e8e04e 131 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
pierreprovent 0:77ca32e8e04e 132 break;
pierreprovent 0:77ca32e8e04e 133 case INTERRUPT_ENDPOINT:
pierreprovent 0:77ca32e8e04e 134 wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
pierreprovent 0:77ca32e8e04e 135 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
pierreprovent 0:77ca32e8e04e 136 break;
pierreprovent 0:77ca32e8e04e 137 }
pierreprovent 0:77ca32e8e04e 138 }
pierreprovent 0:77ca32e8e04e 139
pierreprovent 0:77ca32e8e04e 140
pierreprovent 0:77ca32e8e04e 141 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
pierreprovent 0:77ca32e8e04e 142 uint32_t wk_data;
pierreprovent 0:77ca32e8e04e 143
pierreprovent 0:77ca32e8e04e 144 switch(type) {
pierreprovent 0:77ca32e8e04e 145 case CONTROL_ENDPOINT:
pierreprovent 0:77ca32e8e04e 146 wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
pierreprovent 0:77ca32e8e04e 147 if(wk_data & OR_CONTROL_CLE) {
pierreprovent 0:77ca32e8e04e 148 wk_data &= ~OR_CONTROL_CLE;
pierreprovent 0:77ca32e8e04e 149 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
pierreprovent 0:77ca32e8e04e 150 return true;
pierreprovent 0:77ca32e8e04e 151 }
pierreprovent 0:77ca32e8e04e 152 return false;
pierreprovent 0:77ca32e8e04e 153 case ISOCHRONOUS_ENDPOINT:
pierreprovent 0:77ca32e8e04e 154 return false;
pierreprovent 0:77ca32e8e04e 155 case BULK_ENDPOINT:
pierreprovent 0:77ca32e8e04e 156 wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
pierreprovent 0:77ca32e8e04e 157 if(wk_data & OR_CONTROL_BLE) {
pierreprovent 0:77ca32e8e04e 158 wk_data &= ~OR_CONTROL_BLE;
pierreprovent 0:77ca32e8e04e 159 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
pierreprovent 0:77ca32e8e04e 160 return true;
pierreprovent 0:77ca32e8e04e 161 }
pierreprovent 0:77ca32e8e04e 162 return false;
pierreprovent 0:77ca32e8e04e 163 case INTERRUPT_ENDPOINT:
pierreprovent 0:77ca32e8e04e 164 wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
pierreprovent 0:77ca32e8e04e 165 if(wk_data & OR_CONTROL_PLE) {
pierreprovent 0:77ca32e8e04e 166 wk_data &= ~OR_CONTROL_PLE;
pierreprovent 0:77ca32e8e04e 167 ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
pierreprovent 0:77ca32e8e04e 168 return true;
pierreprovent 0:77ca32e8e04e 169 }
pierreprovent 0:77ca32e8e04e 170 return false;
pierreprovent 0:77ca32e8e04e 171 }
pierreprovent 0:77ca32e8e04e 172 return false;
pierreprovent 0:77ca32e8e04e 173 }
pierreprovent 0:77ca32e8e04e 174
pierreprovent 0:77ca32e8e04e 175
pierreprovent 0:77ca32e8e04e 176 void USBHALHost::memInit() {
pierreprovent 0:77ca32e8e04e 177 volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
pierreprovent 0:77ca32e8e04e 178
pierreprovent 0:77ca32e8e04e 179 usb_hcca = (volatile HCCA *)p_wk_buf;
pierreprovent 0:77ca32e8e04e 180 usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
pierreprovent 0:77ca32e8e04e 181 usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
pierreprovent 0:77ca32e8e04e 182 }
pierreprovent 0:77ca32e8e04e 183
pierreprovent 0:77ca32e8e04e 184 volatile uint8_t * USBHALHost::getED() {
pierreprovent 0:77ca32e8e04e 185 for (int i = 0; i < MAX_ENDPOINT; i++) {
pierreprovent 0:77ca32e8e04e 186 if ( !edBufAlloc[i] ) {
pierreprovent 0:77ca32e8e04e 187 edBufAlloc[i] = true;
pierreprovent 0:77ca32e8e04e 188 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
pierreprovent 0:77ca32e8e04e 189 }
pierreprovent 0:77ca32e8e04e 190 }
pierreprovent 0:77ca32e8e04e 191 perror("Could not allocate ED\r\n");
pierreprovent 0:77ca32e8e04e 192 return NULL; //Could not alloc ED
pierreprovent 0:77ca32e8e04e 193 }
pierreprovent 0:77ca32e8e04e 194
pierreprovent 0:77ca32e8e04e 195 volatile uint8_t * USBHALHost::getTD() {
pierreprovent 0:77ca32e8e04e 196 int i;
pierreprovent 0:77ca32e8e04e 197 for (i = 0; i < MAX_TD; i++) {
pierreprovent 0:77ca32e8e04e 198 if ( !tdBufAlloc[i] ) {
pierreprovent 0:77ca32e8e04e 199 tdBufAlloc[i] = true;
pierreprovent 0:77ca32e8e04e 200 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
pierreprovent 0:77ca32e8e04e 201 }
pierreprovent 0:77ca32e8e04e 202 }
pierreprovent 0:77ca32e8e04e 203 perror("Could not allocate TD\r\n");
pierreprovent 0:77ca32e8e04e 204 return NULL; //Could not alloc TD
pierreprovent 0:77ca32e8e04e 205 }
pierreprovent 0:77ca32e8e04e 206
pierreprovent 0:77ca32e8e04e 207
pierreprovent 0:77ca32e8e04e 208 void USBHALHost::freeED(volatile uint8_t * ed) {
pierreprovent 0:77ca32e8e04e 209 int i;
pierreprovent 0:77ca32e8e04e 210 i = (ed - usb_edBuf) / ED_SIZE;
pierreprovent 0:77ca32e8e04e 211 edBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 212 }
pierreprovent 0:77ca32e8e04e 213
pierreprovent 0:77ca32e8e04e 214 void USBHALHost::freeTD(volatile uint8_t * td) {
pierreprovent 0:77ca32e8e04e 215 int i;
pierreprovent 0:77ca32e8e04e 216 i = (td - usb_tdBuf) / TD_SIZE;
pierreprovent 0:77ca32e8e04e 217 tdBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 218 }
pierreprovent 0:77ca32e8e04e 219
pierreprovent 0:77ca32e8e04e 220
pierreprovent 0:77ca32e8e04e 221 void USBHALHost::resetRootHub() {
pierreprovent 0:77ca32e8e04e 222 // Initiate port reset
pierreprovent 0:77ca32e8e04e 223 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
pierreprovent 0:77ca32e8e04e 224
pierreprovent 0:77ca32e8e04e 225 while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
pierreprovent 0:77ca32e8e04e 226
pierreprovent 0:77ca32e8e04e 227 // ...and clear port reset signal
pierreprovent 0:77ca32e8e04e 228 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
pierreprovent 0:77ca32e8e04e 229 }
pierreprovent 0:77ca32e8e04e 230
pierreprovent 0:77ca32e8e04e 231
pierreprovent 0:77ca32e8e04e 232 void USBHALHost::_usbisr(void) {
pierreprovent 0:77ca32e8e04e 233 if (instHost) {
pierreprovent 0:77ca32e8e04e 234 instHost->UsbIrqhandler();
pierreprovent 0:77ca32e8e04e 235 }
pierreprovent 0:77ca32e8e04e 236 }
pierreprovent 0:77ca32e8e04e 237
pierreprovent 0:77ca32e8e04e 238 void USBHALHost::UsbIrqhandler() {
pierreprovent 0:77ca32e8e04e 239 uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
pierreprovent 0:77ca32e8e04e 240 uint32_t data;
pierreprovent 0:77ca32e8e04e 241
pierreprovent 0:77ca32e8e04e 242 if (int_status != 0) { //Is there something to actually process?
pierreprovent 0:77ca32e8e04e 243 // Root hub status change interrupt
pierreprovent 0:77ca32e8e04e 244 if (int_status & OR_INTR_STATUS_RHSC) {
pierreprovent 0:77ca32e8e04e 245 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
pierreprovent 0:77ca32e8e04e 246 if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
pierreprovent 0:77ca32e8e04e 247 // When DRWE is on, Connect Status Change
pierreprovent 0:77ca32e8e04e 248 // means a remote wakeup event.
pierreprovent 0:77ca32e8e04e 249 } else {
pierreprovent 0:77ca32e8e04e 250
pierreprovent 0:77ca32e8e04e 251 //Root device connected
pierreprovent 0:77ca32e8e04e 252 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
pierreprovent 0:77ca32e8e04e 253
pierreprovent 0:77ca32e8e04e 254 // wait 150ms to avoid bounce
pierreprovent 0:77ca32e8e04e 255 wait_ms(150);
pierreprovent 0:77ca32e8e04e 256
pierreprovent 0:77ca32e8e04e 257 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
pierreprovent 0:77ca32e8e04e 258 data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
pierreprovent 0:77ca32e8e04e 259 deviceConnected(0, 1, data);
pierreprovent 0:77ca32e8e04e 260 }
pierreprovent 0:77ca32e8e04e 261
pierreprovent 0:77ca32e8e04e 262 //Root device disconnected
pierreprovent 0:77ca32e8e04e 263 else {
pierreprovent 0:77ca32e8e04e 264 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
pierreprovent 0:77ca32e8e04e 265 }
pierreprovent 0:77ca32e8e04e 266 }
pierreprovent 0:77ca32e8e04e 267 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
pierreprovent 0:77ca32e8e04e 268 }
pierreprovent 0:77ca32e8e04e 269 if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
pierreprovent 0:77ca32e8e04e 270 ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
pierreprovent 0:77ca32e8e04e 271 }
pierreprovent 0:77ca32e8e04e 272 ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
pierreprovent 0:77ca32e8e04e 273 }
pierreprovent 0:77ca32e8e04e 274
pierreprovent 0:77ca32e8e04e 275 // Writeback Done Head interrupt
pierreprovent 0:77ca32e8e04e 276 if (int_status & OR_INTR_STATUS_WDH) {
pierreprovent 0:77ca32e8e04e 277 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
pierreprovent 0:77ca32e8e04e 278 ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
pierreprovent 0:77ca32e8e04e 279 }
pierreprovent 0:77ca32e8e04e 280 }
pierreprovent 0:77ca32e8e04e 281 }
pierreprovent 0:77ca32e8e04e 282 #endif