Pierre Provent / USBHost

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Dependents:   TEST_USB_Nucleo_F429ZI Essais_USB_Nucleo_F429ZI SID_V3_Nucleo_F429ZI SID_V4_Nucleo_F429ZI_copy

targets/TARGET_NXP/USBHALHost_LPC17.cpp@0:77ca32e8e04e, 2020-09-25 (annotated)

Committer:
pierreprovent
Date:
Fri Sep 25 10:17:49 2020 +0000
Revision:
0:77ca32e8e04e
Programme acquisition en enregistrement sur clef USB carte Nucleo F429ZI cours ELE118 Cnam

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pierreprovent 0:77ca32e8e04e 1 /* mbed USBHost Library
pierreprovent 0:77ca32e8e04e 2 * Copyright (c) 2006-2013 ARM Limited
pierreprovent 0:77ca32e8e04e 3 *
pierreprovent 0:77ca32e8e04e 4 * Licensed under the Apache License, Version 2.0 (the "License");
pierreprovent 0:77ca32e8e04e 5 * you may not use this file except in compliance with the License.
pierreprovent 0:77ca32e8e04e 6 * You may obtain a copy of the License at
pierreprovent 0:77ca32e8e04e 7 *
pierreprovent 0:77ca32e8e04e 8 * http://www.apache.org/licenses/LICENSE-2.0
pierreprovent 0:77ca32e8e04e 9 *
pierreprovent 0:77ca32e8e04e 10 * Unless required by applicable law or agreed to in writing, software
pierreprovent 0:77ca32e8e04e 11 * distributed under the License is distributed on an "AS IS" BASIS,
pierreprovent 0:77ca32e8e04e 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
pierreprovent 0:77ca32e8e04e 13 * See the License for the specific language governing permissions and
pierreprovent 0:77ca32e8e04e 14 * limitations under the License.
pierreprovent 0:77ca32e8e04e 15 */
pierreprovent 0:77ca32e8e04e 16
pierreprovent 0:77ca32e8e04e 17 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2460)
pierreprovent 0:77ca32e8e04e 18
pierreprovent 0:77ca32e8e04e 19 #include "mbed.h"
pierreprovent 0:77ca32e8e04e 20 #include "USBHALHost.h"
pierreprovent 0:77ca32e8e04e 21 #include "dbg.h"
pierreprovent 0:77ca32e8e04e 22
pierreprovent 0:77ca32e8e04e 23 // bits of the USB/OTG clock control register
pierreprovent 0:77ca32e8e04e 24 #define HOST_CLK_EN (1<<0)
pierreprovent 0:77ca32e8e04e 25 #define DEV_CLK_EN (1<<1)
pierreprovent 0:77ca32e8e04e 26 #define PORTSEL_CLK_EN (1<<3)
pierreprovent 0:77ca32e8e04e 27 #define AHB_CLK_EN (1<<4)
pierreprovent 0:77ca32e8e04e 28
pierreprovent 0:77ca32e8e04e 29 // bits of the USB/OTG clock status register
pierreprovent 0:77ca32e8e04e 30 #define HOST_CLK_ON (1<<0)
pierreprovent 0:77ca32e8e04e 31 #define DEV_CLK_ON (1<<1)
pierreprovent 0:77ca32e8e04e 32 #define PORTSEL_CLK_ON (1<<3)
pierreprovent 0:77ca32e8e04e 33 #define AHB_CLK_ON (1<<4)
pierreprovent 0:77ca32e8e04e 34
pierreprovent 0:77ca32e8e04e 35 // we need host clock, OTG/portsel clock and AHB clock
pierreprovent 0:77ca32e8e04e 36 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
pierreprovent 0:77ca32e8e04e 37
pierreprovent 0:77ca32e8e04e 38 #define HCCA_SIZE sizeof(HCCA)
pierreprovent 0:77ca32e8e04e 39 #define ED_SIZE sizeof(HCED)
pierreprovent 0:77ca32e8e04e 40 #define TD_SIZE sizeof(HCTD)
pierreprovent 0:77ca32e8e04e 41
pierreprovent 0:77ca32e8e04e 42 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
pierreprovent 0:77ca32e8e04e 43
pierreprovent 0:77ca32e8e04e 44 static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
pierreprovent 0:77ca32e8e04e 45
pierreprovent 0:77ca32e8e04e 46 USBHALHost * USBHALHost::instHost;
pierreprovent 0:77ca32e8e04e 47
pierreprovent 0:77ca32e8e04e 48 USBHALHost::USBHALHost() {
pierreprovent 0:77ca32e8e04e 49 instHost = this;
pierreprovent 0:77ca32e8e04e 50 memInit();
pierreprovent 0:77ca32e8e04e 51 memset((void*)usb_hcca, 0, HCCA_SIZE);
pierreprovent 0:77ca32e8e04e 52 for (int i = 0; i < MAX_ENDPOINT; i++) {
pierreprovent 0:77ca32e8e04e 53 edBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 54 }
pierreprovent 0:77ca32e8e04e 55 for (int i = 0; i < MAX_TD; i++) {
pierreprovent 0:77ca32e8e04e 56 tdBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 57 }
pierreprovent 0:77ca32e8e04e 58 }
pierreprovent 0:77ca32e8e04e 59
pierreprovent 0:77ca32e8e04e 60 void USBHALHost::init() {
pierreprovent 0:77ca32e8e04e 61 NVIC_DisableIRQ(USB_IRQn);
pierreprovent 0:77ca32e8e04e 62
pierreprovent 0:77ca32e8e04e 63 //Cut power
pierreprovent 0:77ca32e8e04e 64 LPC_SC->PCONP &= ~(1UL<<31);
pierreprovent 0:77ca32e8e04e 65 wait_ms(100);
pierreprovent 0:77ca32e8e04e 66
pierreprovent 0:77ca32e8e04e 67 // turn on power for USB
pierreprovent 0:77ca32e8e04e 68 LPC_SC->PCONP |= (1UL<<31);
pierreprovent 0:77ca32e8e04e 69
pierreprovent 0:77ca32e8e04e 70 // Enable USB host clock, port selection and AHB clock
pierreprovent 0:77ca32e8e04e 71 LPC_USB->USBClkCtrl |= CLOCK_MASK;
pierreprovent 0:77ca32e8e04e 72
pierreprovent 0:77ca32e8e04e 73 // Wait for clocks to become available
pierreprovent 0:77ca32e8e04e 74 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
pierreprovent 0:77ca32e8e04e 75
pierreprovent 0:77ca32e8e04e 76 // it seems the bits[0:1] mean the following
pierreprovent 0:77ca32e8e04e 77 // 0: U1=device, U2=host
pierreprovent 0:77ca32e8e04e 78 // 1: U1=host, U2=host
pierreprovent 0:77ca32e8e04e 79 // 2: reserved
pierreprovent 0:77ca32e8e04e 80 // 3: U1=host, U2=device
pierreprovent 0:77ca32e8e04e 81 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
pierreprovent 0:77ca32e8e04e 82 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
pierreprovent 0:77ca32e8e04e 83 LPC_USB->OTGStCtrl |= 1;
pierreprovent 0:77ca32e8e04e 84
pierreprovent 0:77ca32e8e04e 85 // now that we've configured the ports, we can turn off the portsel clock
pierreprovent 0:77ca32e8e04e 86 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
pierreprovent 0:77ca32e8e04e 87
pierreprovent 0:77ca32e8e04e 88 // configure USB D+/D- pins
pierreprovent 0:77ca32e8e04e 89 // P0[29] = USB_D+, 01
pierreprovent 0:77ca32e8e04e 90 // P0[30] = USB_D-, 01
pierreprovent 0:77ca32e8e04e 91 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
pierreprovent 0:77ca32e8e04e 92 LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
pierreprovent 0:77ca32e8e04e 93
pierreprovent 0:77ca32e8e04e 94 LPC_USB->HcControl = 0; // HARDWARE RESET
pierreprovent 0:77ca32e8e04e 95 LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
pierreprovent 0:77ca32e8e04e 96 LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
pierreprovent 0:77ca32e8e04e 97
pierreprovent 0:77ca32e8e04e 98 // Wait 100 ms before apply reset
pierreprovent 0:77ca32e8e04e 99 wait_ms(100);
pierreprovent 0:77ca32e8e04e 100
pierreprovent 0:77ca32e8e04e 101 // software reset
pierreprovent 0:77ca32e8e04e 102 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
pierreprovent 0:77ca32e8e04e 103
pierreprovent 0:77ca32e8e04e 104 // Write Fm Interval and Largest Data Packet Counter
pierreprovent 0:77ca32e8e04e 105 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
pierreprovent 0:77ca32e8e04e 106 LPC_USB->HcPeriodicStart = FI * 90 / 100;
pierreprovent 0:77ca32e8e04e 107
pierreprovent 0:77ca32e8e04e 108 // Put HC in operational state
pierreprovent 0:77ca32e8e04e 109 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
pierreprovent 0:77ca32e8e04e 110 // Set Global Power
pierreprovent 0:77ca32e8e04e 111 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
pierreprovent 0:77ca32e8e04e 112
pierreprovent 0:77ca32e8e04e 113 LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
pierreprovent 0:77ca32e8e04e 114
pierreprovent 0:77ca32e8e04e 115 // Clear Interrrupt Status
pierreprovent 0:77ca32e8e04e 116 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
pierreprovent 0:77ca32e8e04e 117
pierreprovent 0:77ca32e8e04e 118 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
pierreprovent 0:77ca32e8e04e 119
pierreprovent 0:77ca32e8e04e 120 // Enable the USB Interrupt
pierreprovent 0:77ca32e8e04e 121 NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
pierreprovent 0:77ca32e8e04e 122 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
pierreprovent 0:77ca32e8e04e 123 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
pierreprovent 0:77ca32e8e04e 124
pierreprovent 0:77ca32e8e04e 125 NVIC_EnableIRQ(USB_IRQn);
pierreprovent 0:77ca32e8e04e 126
pierreprovent 0:77ca32e8e04e 127 // Check for any connected devices
pierreprovent 0:77ca32e8e04e 128 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
pierreprovent 0:77ca32e8e04e 129 //Device connected
pierreprovent 0:77ca32e8e04e 130 wait_ms(150);
pierreprovent 0:77ca32e8e04e 131 USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
pierreprovent 0:77ca32e8e04e 132 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
pierreprovent 0:77ca32e8e04e 133 }
pierreprovent 0:77ca32e8e04e 134 }
pierreprovent 0:77ca32e8e04e 135
pierreprovent 0:77ca32e8e04e 136 uint32_t USBHALHost::controlHeadED() {
pierreprovent 0:77ca32e8e04e 137 return LPC_USB->HcControlHeadED;
pierreprovent 0:77ca32e8e04e 138 }
pierreprovent 0:77ca32e8e04e 139
pierreprovent 0:77ca32e8e04e 140 uint32_t USBHALHost::bulkHeadED() {
pierreprovent 0:77ca32e8e04e 141 return LPC_USB->HcBulkHeadED;
pierreprovent 0:77ca32e8e04e 142 }
pierreprovent 0:77ca32e8e04e 143
pierreprovent 0:77ca32e8e04e 144 uint32_t USBHALHost::interruptHeadED() {
pierreprovent 0:77ca32e8e04e 145 return usb_hcca->IntTable[0];
pierreprovent 0:77ca32e8e04e 146 }
pierreprovent 0:77ca32e8e04e 147
pierreprovent 0:77ca32e8e04e 148 void USBHALHost::updateBulkHeadED(uint32_t addr) {
pierreprovent 0:77ca32e8e04e 149 LPC_USB->HcBulkHeadED = addr;
pierreprovent 0:77ca32e8e04e 150 }
pierreprovent 0:77ca32e8e04e 151
pierreprovent 0:77ca32e8e04e 152
pierreprovent 0:77ca32e8e04e 153 void USBHALHost::updateControlHeadED(uint32_t addr) {
pierreprovent 0:77ca32e8e04e 154 LPC_USB->HcControlHeadED = addr;
pierreprovent 0:77ca32e8e04e 155 }
pierreprovent 0:77ca32e8e04e 156
pierreprovent 0:77ca32e8e04e 157 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
pierreprovent 0:77ca32e8e04e 158 usb_hcca->IntTable[0] = addr;
pierreprovent 0:77ca32e8e04e 159 }
pierreprovent 0:77ca32e8e04e 160
pierreprovent 0:77ca32e8e04e 161
pierreprovent 0:77ca32e8e04e 162 void USBHALHost::enableList(ENDPOINT_TYPE type) {
pierreprovent 0:77ca32e8e04e 163 switch(type) {
pierreprovent 0:77ca32e8e04e 164 case CONTROL_ENDPOINT:
pierreprovent 0:77ca32e8e04e 165 LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
pierreprovent 0:77ca32e8e04e 166 LPC_USB->HcControl |= OR_CONTROL_CLE;
pierreprovent 0:77ca32e8e04e 167 break;
pierreprovent 0:77ca32e8e04e 168 case ISOCHRONOUS_ENDPOINT:
pierreprovent 0:77ca32e8e04e 169 break;
pierreprovent 0:77ca32e8e04e 170 case BULK_ENDPOINT:
pierreprovent 0:77ca32e8e04e 171 LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
pierreprovent 0:77ca32e8e04e 172 LPC_USB->HcControl |= OR_CONTROL_BLE;
pierreprovent 0:77ca32e8e04e 173 break;
pierreprovent 0:77ca32e8e04e 174 case INTERRUPT_ENDPOINT:
pierreprovent 0:77ca32e8e04e 175 LPC_USB->HcControl |= OR_CONTROL_PLE;
pierreprovent 0:77ca32e8e04e 176 break;
pierreprovent 0:77ca32e8e04e 177 }
pierreprovent 0:77ca32e8e04e 178 }
pierreprovent 0:77ca32e8e04e 179
pierreprovent 0:77ca32e8e04e 180
pierreprovent 0:77ca32e8e04e 181 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
pierreprovent 0:77ca32e8e04e 182 switch(type) {
pierreprovent 0:77ca32e8e04e 183 case CONTROL_ENDPOINT:
pierreprovent 0:77ca32e8e04e 184 if(LPC_USB->HcControl & OR_CONTROL_CLE) {
pierreprovent 0:77ca32e8e04e 185 LPC_USB->HcControl &= ~OR_CONTROL_CLE;
pierreprovent 0:77ca32e8e04e 186 return true;
pierreprovent 0:77ca32e8e04e 187 }
pierreprovent 0:77ca32e8e04e 188 return false;
pierreprovent 0:77ca32e8e04e 189 case ISOCHRONOUS_ENDPOINT:
pierreprovent 0:77ca32e8e04e 190 return false;
pierreprovent 0:77ca32e8e04e 191 case BULK_ENDPOINT:
pierreprovent 0:77ca32e8e04e 192 if(LPC_USB->HcControl & OR_CONTROL_BLE){
pierreprovent 0:77ca32e8e04e 193 LPC_USB->HcControl &= ~OR_CONTROL_BLE;
pierreprovent 0:77ca32e8e04e 194 return true;
pierreprovent 0:77ca32e8e04e 195 }
pierreprovent 0:77ca32e8e04e 196 return false;
pierreprovent 0:77ca32e8e04e 197 case INTERRUPT_ENDPOINT:
pierreprovent 0:77ca32e8e04e 198 if(LPC_USB->HcControl & OR_CONTROL_PLE) {
pierreprovent 0:77ca32e8e04e 199 LPC_USB->HcControl &= ~OR_CONTROL_PLE;
pierreprovent 0:77ca32e8e04e 200 return true;
pierreprovent 0:77ca32e8e04e 201 }
pierreprovent 0:77ca32e8e04e 202 return false;
pierreprovent 0:77ca32e8e04e 203 }
pierreprovent 0:77ca32e8e04e 204 return false;
pierreprovent 0:77ca32e8e04e 205 }
pierreprovent 0:77ca32e8e04e 206
pierreprovent 0:77ca32e8e04e 207
pierreprovent 0:77ca32e8e04e 208 void USBHALHost::memInit() {
pierreprovent 0:77ca32e8e04e 209 usb_hcca = (volatile HCCA *)usb_buf;
pierreprovent 0:77ca32e8e04e 210 usb_edBuf = usb_buf + HCCA_SIZE;
pierreprovent 0:77ca32e8e04e 211 usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
pierreprovent 0:77ca32e8e04e 212 }
pierreprovent 0:77ca32e8e04e 213
pierreprovent 0:77ca32e8e04e 214 volatile uint8_t * USBHALHost::getED() {
pierreprovent 0:77ca32e8e04e 215 for (int i = 0; i < MAX_ENDPOINT; i++) {
pierreprovent 0:77ca32e8e04e 216 if ( !edBufAlloc[i] ) {
pierreprovent 0:77ca32e8e04e 217 edBufAlloc[i] = true;
pierreprovent 0:77ca32e8e04e 218 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
pierreprovent 0:77ca32e8e04e 219 }
pierreprovent 0:77ca32e8e04e 220 }
pierreprovent 0:77ca32e8e04e 221 perror("Could not allocate ED\r\n");
pierreprovent 0:77ca32e8e04e 222 return NULL; //Could not alloc ED
pierreprovent 0:77ca32e8e04e 223 }
pierreprovent 0:77ca32e8e04e 224
pierreprovent 0:77ca32e8e04e 225 volatile uint8_t * USBHALHost::getTD() {
pierreprovent 0:77ca32e8e04e 226 int i;
pierreprovent 0:77ca32e8e04e 227 for (i = 0; i < MAX_TD; i++) {
pierreprovent 0:77ca32e8e04e 228 if ( !tdBufAlloc[i] ) {
pierreprovent 0:77ca32e8e04e 229 tdBufAlloc[i] = true;
pierreprovent 0:77ca32e8e04e 230 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
pierreprovent 0:77ca32e8e04e 231 }
pierreprovent 0:77ca32e8e04e 232 }
pierreprovent 0:77ca32e8e04e 233 perror("Could not allocate TD\r\n");
pierreprovent 0:77ca32e8e04e 234 return NULL; //Could not alloc TD
pierreprovent 0:77ca32e8e04e 235 }
pierreprovent 0:77ca32e8e04e 236
pierreprovent 0:77ca32e8e04e 237
pierreprovent 0:77ca32e8e04e 238 void USBHALHost::freeED(volatile uint8_t * ed) {
pierreprovent 0:77ca32e8e04e 239 int i;
pierreprovent 0:77ca32e8e04e 240 i = (ed - usb_edBuf) / ED_SIZE;
pierreprovent 0:77ca32e8e04e 241 edBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 242 }
pierreprovent 0:77ca32e8e04e 243
pierreprovent 0:77ca32e8e04e 244 void USBHALHost::freeTD(volatile uint8_t * td) {
pierreprovent 0:77ca32e8e04e 245 int i;
pierreprovent 0:77ca32e8e04e 246 i = (td - usb_tdBuf) / TD_SIZE;
pierreprovent 0:77ca32e8e04e 247 tdBufAlloc[i] = false;
pierreprovent 0:77ca32e8e04e 248 }
pierreprovent 0:77ca32e8e04e 249
pierreprovent 0:77ca32e8e04e 250
pierreprovent 0:77ca32e8e04e 251 void USBHALHost::resetRootHub() {
pierreprovent 0:77ca32e8e04e 252 // Initiate port reset
pierreprovent 0:77ca32e8e04e 253 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
pierreprovent 0:77ca32e8e04e 254
pierreprovent 0:77ca32e8e04e 255 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
pierreprovent 0:77ca32e8e04e 256
pierreprovent 0:77ca32e8e04e 257 // ...and clear port reset signal
pierreprovent 0:77ca32e8e04e 258 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
pierreprovent 0:77ca32e8e04e 259 }
pierreprovent 0:77ca32e8e04e 260
pierreprovent 0:77ca32e8e04e 261
pierreprovent 0:77ca32e8e04e 262 void USBHALHost::_usbisr(void) {
pierreprovent 0:77ca32e8e04e 263 if (instHost) {
pierreprovent 0:77ca32e8e04e 264 instHost->UsbIrqhandler();
pierreprovent 0:77ca32e8e04e 265 }
pierreprovent 0:77ca32e8e04e 266 }
pierreprovent 0:77ca32e8e04e 267
pierreprovent 0:77ca32e8e04e 268 void USBHALHost::UsbIrqhandler() {
pierreprovent 0:77ca32e8e04e 269 if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
pierreprovent 0:77ca32e8e04e 270 {
pierreprovent 0:77ca32e8e04e 271
pierreprovent 0:77ca32e8e04e 272 uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
pierreprovent 0:77ca32e8e04e 273
pierreprovent 0:77ca32e8e04e 274 // Root hub status change interrupt
pierreprovent 0:77ca32e8e04e 275 if (int_status & OR_INTR_STATUS_RHSC) {
pierreprovent 0:77ca32e8e04e 276 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
pierreprovent 0:77ca32e8e04e 277 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
pierreprovent 0:77ca32e8e04e 278 // When DRWE is on, Connect Status Change
pierreprovent 0:77ca32e8e04e 279 // means a remote wakeup event.
pierreprovent 0:77ca32e8e04e 280 } else {
pierreprovent 0:77ca32e8e04e 281
pierreprovent 0:77ca32e8e04e 282 //Root device connected
pierreprovent 0:77ca32e8e04e 283 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
pierreprovent 0:77ca32e8e04e 284
pierreprovent 0:77ca32e8e04e 285 // wait 150ms to avoid bounce
pierreprovent 0:77ca32e8e04e 286 wait_ms(150);
pierreprovent 0:77ca32e8e04e 287
pierreprovent 0:77ca32e8e04e 288 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
pierreprovent 0:77ca32e8e04e 289 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
pierreprovent 0:77ca32e8e04e 290 }
pierreprovent 0:77ca32e8e04e 291
pierreprovent 0:77ca32e8e04e 292 //Root device disconnected
pierreprovent 0:77ca32e8e04e 293 else {
pierreprovent 0:77ca32e8e04e 294
pierreprovent 0:77ca32e8e04e 295 if (!(int_status & OR_INTR_STATUS_WDH)) {
pierreprovent 0:77ca32e8e04e 296 usb_hcca->DoneHead = 0;
pierreprovent 0:77ca32e8e04e 297 }
pierreprovent 0:77ca32e8e04e 298
pierreprovent 0:77ca32e8e04e 299 // wait 200ms to avoid bounce
pierreprovent 0:77ca32e8e04e 300 wait_ms(200);
pierreprovent 0:77ca32e8e04e 301
pierreprovent 0:77ca32e8e04e 302 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
pierreprovent 0:77ca32e8e04e 303
pierreprovent 0:77ca32e8e04e 304 if (int_status & OR_INTR_STATUS_WDH) {
pierreprovent 0:77ca32e8e04e 305 usb_hcca->DoneHead = 0;
pierreprovent 0:77ca32e8e04e 306 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
pierreprovent 0:77ca32e8e04e 307 }
pierreprovent 0:77ca32e8e04e 308 }
pierreprovent 0:77ca32e8e04e 309 }
pierreprovent 0:77ca32e8e04e 310 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
pierreprovent 0:77ca32e8e04e 311 }
pierreprovent 0:77ca32e8e04e 312 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
pierreprovent 0:77ca32e8e04e 313 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
pierreprovent 0:77ca32e8e04e 314 }
pierreprovent 0:77ca32e8e04e 315 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
pierreprovent 0:77ca32e8e04e 316 }
pierreprovent 0:77ca32e8e04e 317
pierreprovent 0:77ca32e8e04e 318 // Writeback Done Head interrupt
pierreprovent 0:77ca32e8e04e 319 if (int_status & OR_INTR_STATUS_WDH) {
pierreprovent 0:77ca32e8e04e 320 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
pierreprovent 0:77ca32e8e04e 321 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
pierreprovent 0:77ca32e8e04e 322 }
pierreprovent 0:77ca32e8e04e 323 }
pierreprovent 0:77ca32e8e04e 324 }
pierreprovent 0:77ca32e8e04e 325 #endif