Pierre Provent / USBHost

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Dependents:   TEST_USB_Nucleo_F429ZI Essais_USB_Nucleo_F429ZI SID_V3_Nucleo_F429ZI SID_V4_Nucleo_F429ZI_copy

mbed-rtos/rtx/TARGET_ARM7/rt_HAL_CM.h@0:77ca32e8e04e, 2020-09-25 (annotated)

Committer:
pierreprovent
Date:
Fri Sep 25 10:17:49 2020 +0000
Revision:
0:77ca32e8e04e
Programme acquisition en enregistrement sur clef USB carte Nucleo F429ZI cours ELE118 Cnam

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pierreprovent 0:77ca32e8e04e 1 /*----------------------------------------------------------------------------
pierreprovent 0:77ca32e8e04e 2 * RL-ARM - RTX
pierreprovent 0:77ca32e8e04e 3 *----------------------------------------------------------------------------
pierreprovent 0:77ca32e8e04e 4 * Name: RT_HAL_CM.H
pierreprovent 0:77ca32e8e04e 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
pierreprovent 0:77ca32e8e04e 6 * Rev.: V4.60
pierreprovent 0:77ca32e8e04e 7 *----------------------------------------------------------------------------
pierreprovent 0:77ca32e8e04e 8 *
pierreprovent 0:77ca32e8e04e 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
pierreprovent 0:77ca32e8e04e 10 * All rights reserved.
pierreprovent 0:77ca32e8e04e 11 * Redistribution and use in source and binary forms, with or without
pierreprovent 0:77ca32e8e04e 12 * modification, are permitted provided that the following conditions are met:
pierreprovent 0:77ca32e8e04e 13 * - Redistributions of source code must retain the above copyright
pierreprovent 0:77ca32e8e04e 14 * notice, this list of conditions and the following disclaimer.
pierreprovent 0:77ca32e8e04e 15 * - Redistributions in binary form must reproduce the above copyright
pierreprovent 0:77ca32e8e04e 16 * notice, this list of conditions and the following disclaimer in the
pierreprovent 0:77ca32e8e04e 17 * documentation and/or other materials provided with the distribution.
pierreprovent 0:77ca32e8e04e 18 * - Neither the name of ARM nor the names of its contributors may be used
pierreprovent 0:77ca32e8e04e 19 * to endorse or promote products derived from this software without
pierreprovent 0:77ca32e8e04e 20 * specific prior written permission.
pierreprovent 0:77ca32e8e04e 21 *
pierreprovent 0:77ca32e8e04e 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
pierreprovent 0:77ca32e8e04e 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
pierreprovent 0:77ca32e8e04e 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
pierreprovent 0:77ca32e8e04e 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
pierreprovent 0:77ca32e8e04e 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
pierreprovent 0:77ca32e8e04e 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
pierreprovent 0:77ca32e8e04e 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
pierreprovent 0:77ca32e8e04e 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
pierreprovent 0:77ca32e8e04e 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
pierreprovent 0:77ca32e8e04e 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
pierreprovent 0:77ca32e8e04e 32 * POSSIBILITY OF SUCH DAMAGE.
pierreprovent 0:77ca32e8e04e 33 *---------------------------------------------------------------------------*/
pierreprovent 0:77ca32e8e04e 34
pierreprovent 0:77ca32e8e04e 35 #include "cmsis.h"
pierreprovent 0:77ca32e8e04e 36 /* Definitions */
pierreprovent 0:77ca32e8e04e 37 #define INITIAL_xPSR 0x10000000
pierreprovent 0:77ca32e8e04e 38 #define DEMCR_TRCENA 0x01000000
pierreprovent 0:77ca32e8e04e 39 #define ITM_ITMENA 0x00000001
pierreprovent 0:77ca32e8e04e 40 #define MAGIC_WORD 0xE25A2EA5
pierreprovent 0:77ca32e8e04e 41
pierreprovent 0:77ca32e8e04e 42 #define SYS_TICK_IRQn TIMER0_IRQn
pierreprovent 0:77ca32e8e04e 43
pierreprovent 0:77ca32e8e04e 44 extern void rt_set_PSP (U32 stack);
pierreprovent 0:77ca32e8e04e 45 extern U32 rt_get_PSP (void);
pierreprovent 0:77ca32e8e04e 46 extern void os_set_env (void);
pierreprovent 0:77ca32e8e04e 47 extern void SysTick_Handler (void);
pierreprovent 0:77ca32e8e04e 48 extern void *_alloc_box (void *box_mem);
pierreprovent 0:77ca32e8e04e 49 extern int _free_box (void *box_mem, void *box);
pierreprovent 0:77ca32e8e04e 50
pierreprovent 0:77ca32e8e04e 51 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
pierreprovent 0:77ca32e8e04e 52 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
pierreprovent 0:77ca32e8e04e 53 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
pierreprovent 0:77ca32e8e04e 54
pierreprovent 0:77ca32e8e04e 55 extern void dbg_init (void);
pierreprovent 0:77ca32e8e04e 56 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
pierreprovent 0:77ca32e8e04e 57 extern void dbg_task_switch (U32 task_id);
pierreprovent 0:77ca32e8e04e 58
pierreprovent 0:77ca32e8e04e 59
pierreprovent 0:77ca32e8e04e 60 #if defined (__CC_ARM) /* ARM Compiler */
pierreprovent 0:77ca32e8e04e 61
pierreprovent 0:77ca32e8e04e 62 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
pierreprovent 0:77ca32e8e04e 63 #define __USE_EXCLUSIVE_ACCESS
pierreprovent 0:77ca32e8e04e 64 #else
pierreprovent 0:77ca32e8e04e 65 #undef __USE_EXCLUSIVE_ACCESS
pierreprovent 0:77ca32e8e04e 66 #endif
pierreprovent 0:77ca32e8e04e 67
pierreprovent 0:77ca32e8e04e 68 #elif defined (__GNUC__) /* GNU Compiler */
pierreprovent 0:77ca32e8e04e 69
pierreprovent 0:77ca32e8e04e 70 #undef __USE_EXCLUSIVE_ACCESS
pierreprovent 0:77ca32e8e04e 71
pierreprovent 0:77ca32e8e04e 72 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
pierreprovent 0:77ca32e8e04e 73 #define __TARGET_ARCH_6S_M 1
pierreprovent 0:77ca32e8e04e 74 #else
pierreprovent 0:77ca32e8e04e 75 #define __TARGET_ARCH_6S_M 0
pierreprovent 0:77ca32e8e04e 76 #endif
pierreprovent 0:77ca32e8e04e 77
pierreprovent 0:77ca32e8e04e 78 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
pierreprovent 0:77ca32e8e04e 79 #define __TARGET_FPU_VFP 1
pierreprovent 0:77ca32e8e04e 80 #else
pierreprovent 0:77ca32e8e04e 81 #define __TARGET_FPU_VFP 0
pierreprovent 0:77ca32e8e04e 82 #endif
pierreprovent 0:77ca32e8e04e 83
pierreprovent 0:77ca32e8e04e 84 #define __inline inline
pierreprovent 0:77ca32e8e04e 85 #define __weak __attribute__((weak))
pierreprovent 0:77ca32e8e04e 86
pierreprovent 0:77ca32e8e04e 87
pierreprovent 0:77ca32e8e04e 88 #elif defined (__ICCARM__) /* IAR Compiler */
pierreprovent 0:77ca32e8e04e 89
pierreprovent 0:77ca32e8e04e 90 #undef __USE_EXCLUSIVE_ACCESS
pierreprovent 0:77ca32e8e04e 91
pierreprovent 0:77ca32e8e04e 92 #if (__CORE__ == __ARM6M__)
pierreprovent 0:77ca32e8e04e 93 #define __TARGET_ARCH_6S_M 1
pierreprovent 0:77ca32e8e04e 94 #else
pierreprovent 0:77ca32e8e04e 95 #define __TARGET_ARCH_6S_M 0
pierreprovent 0:77ca32e8e04e 96 #endif
pierreprovent 0:77ca32e8e04e 97
pierreprovent 0:77ca32e8e04e 98 #if defined __ARMVFP__
pierreprovent 0:77ca32e8e04e 99 #define __TARGET_FPU_VFP 1
pierreprovent 0:77ca32e8e04e 100 #else
pierreprovent 0:77ca32e8e04e 101 #define __TARGET_FPU_VFP 0
pierreprovent 0:77ca32e8e04e 102 #endif
pierreprovent 0:77ca32e8e04e 103
pierreprovent 0:77ca32e8e04e 104 #define __inline inline
pierreprovent 0:77ca32e8e04e 105
pierreprovent 0:77ca32e8e04e 106 #endif
pierreprovent 0:77ca32e8e04e 107
pierreprovent 0:77ca32e8e04e 108
pierreprovent 0:77ca32e8e04e 109 /* NVIC registers */
pierreprovent 0:77ca32e8e04e 110
pierreprovent 0:77ca32e8e04e 111 #define OS_PEND_IRQ() NVIC_PendIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 112 #define OS_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 113 #define OS_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 114 #define OS_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 115 #define OS_LOCK() NVIC_DisableIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 116 #define OS_UNLOCK() NVIC_EnableIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 117
pierreprovent 0:77ca32e8e04e 118 #define OS_X_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 119 #define OS_X_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 120 #define OS_X_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
pierreprovent 0:77ca32e8e04e 121
pierreprovent 0:77ca32e8e04e 122 #define OS_X_INIT(n) NVIC_EnableIRQ(n)
pierreprovent 0:77ca32e8e04e 123 #define OS_X_LOCK(n) NVIC_DisableIRQ(n)
pierreprovent 0:77ca32e8e04e 124 #define OS_X_UNLOCK(n) NVIC_EnableIRQ(n)
pierreprovent 0:77ca32e8e04e 125
pierreprovent 0:77ca32e8e04e 126 /* Variables */
pierreprovent 0:77ca32e8e04e 127 extern BIT dbg_msg;
pierreprovent 0:77ca32e8e04e 128
pierreprovent 0:77ca32e8e04e 129 /* Functions */
pierreprovent 0:77ca32e8e04e 130 #ifdef __USE_EXCLUSIVE_ACCESS
pierreprovent 0:77ca32e8e04e 131 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
pierreprovent 0:77ca32e8e04e 132 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
pierreprovent 0:77ca32e8e04e 133 #else
pierreprovent 0:77ca32e8e04e 134 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
pierreprovent 0:77ca32e8e04e 135 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
pierreprovent 0:77ca32e8e04e 136 #endif
pierreprovent 0:77ca32e8e04e 137
pierreprovent 0:77ca32e8e04e 138 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
pierreprovent 0:77ca32e8e04e 139 U32 cnt,c2;
pierreprovent 0:77ca32e8e04e 140 #ifdef __USE_EXCLUSIVE_ACCESS
pierreprovent 0:77ca32e8e04e 141 do {
pierreprovent 0:77ca32e8e04e 142 if ((cnt = __ldrex(count)) == size) {
pierreprovent 0:77ca32e8e04e 143 __clrex();
pierreprovent 0:77ca32e8e04e 144 return (cnt); }
pierreprovent 0:77ca32e8e04e 145 } while (__strex(cnt+1, count));
pierreprovent 0:77ca32e8e04e 146 do {
pierreprovent 0:77ca32e8e04e 147 c2 = (cnt = __ldrex(first)) + 1;
pierreprovent 0:77ca32e8e04e 148 if (c2 == size) c2 = 0;
pierreprovent 0:77ca32e8e04e 149 } while (__strex(c2, first));
pierreprovent 0:77ca32e8e04e 150 #else
pierreprovent 0:77ca32e8e04e 151 __disable_irq();
pierreprovent 0:77ca32e8e04e 152 if ((cnt = *count) < size) {
pierreprovent 0:77ca32e8e04e 153 *count = cnt+1;
pierreprovent 0:77ca32e8e04e 154 c2 = (cnt = *first) + 1;
pierreprovent 0:77ca32e8e04e 155 if (c2 == size) c2 = 0;
pierreprovent 0:77ca32e8e04e 156 *first = c2;
pierreprovent 0:77ca32e8e04e 157 }
pierreprovent 0:77ca32e8e04e 158 __enable_irq ();
pierreprovent 0:77ca32e8e04e 159 #endif
pierreprovent 0:77ca32e8e04e 160 return (cnt);
pierreprovent 0:77ca32e8e04e 161 }
pierreprovent 0:77ca32e8e04e 162
pierreprovent 0:77ca32e8e04e 163 __inline static void rt_systick_init (void) {
pierreprovent 0:77ca32e8e04e 164 #if SYS_TICK_IRQn == TIMER0_IRQn
pierreprovent 0:77ca32e8e04e 165 #define SYS_TICK_TIMER LPC_TIM0
pierreprovent 0:77ca32e8e04e 166 LPC_SC->PCONP |= (1 << PCTIM0);
pierreprovent 0:77ca32e8e04e 167 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<3))) | (1<<2); //PCLK == CPUCLK
pierreprovent 0:77ca32e8e04e 168 #elif SYS_TICK_IRQn == TIMER1_IRQn
pierreprovent 0:77ca32e8e04e 169 #define SYS_TICK_TIMER LPC_TIM1
pierreprovent 0:77ca32e8e04e 170 LPC_SC->PCONP |= (1 << PCTIM1);
pierreprovent 0:77ca32e8e04e 171 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<5))) | (1<<4); //PCLK == CPUCLK
pierreprovent 0:77ca32e8e04e 172 #elif SYS_TICK_IRQn == TIMER2_IRQn
pierreprovent 0:77ca32e8e04e 173 #define SYS_TICK_TIMER LPC_TIM2
pierreprovent 0:77ca32e8e04e 174 LPC_SC->PCONP |= (1 << PCTIM2);
pierreprovent 0:77ca32e8e04e 175 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<13))) | (1<<12); //PCLK == CPUCLK
pierreprovent 0:77ca32e8e04e 176 #else
pierreprovent 0:77ca32e8e04e 177 #define SYS_TICK_TIMER LPC_TIM3
pierreprovent 0:77ca32e8e04e 178 LPC_SC->PCONP |= (1 << PCTIM3);
pierreprovent 0:77ca32e8e04e 179 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<15))) | (1<<14); //PCLK == CPUCLK
pierreprovent 0:77ca32e8e04e 180 #endif
pierreprovent 0:77ca32e8e04e 181
pierreprovent 0:77ca32e8e04e 182 // setup Timer to count forever
pierreprovent 0:77ca32e8e04e 183 //interrupt_reg
pierreprovent 0:77ca32e8e04e 184 SYS_TICK_TIMER->TCR = 2; // reset & disable timer 0
pierreprovent 0:77ca32e8e04e 185 SYS_TICK_TIMER->TC = os_trv;
pierreprovent 0:77ca32e8e04e 186 SYS_TICK_TIMER->PR = 0; // set the prescale divider
pierreprovent 0:77ca32e8e04e 187 //Reset of TC and Interrupt when MR3 MR2 matches TC
pierreprovent 0:77ca32e8e04e 188 SYS_TICK_TIMER->MCR = (1 << 9) |(1 << 10); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk
pierreprovent 0:77ca32e8e04e 189 SYS_TICK_TIMER->MR3 = os_trv; // match registers
pierreprovent 0:77ca32e8e04e 190 SYS_TICK_TIMER->CCR = 0; // disable compare registers
pierreprovent 0:77ca32e8e04e 191 SYS_TICK_TIMER->EMR = 0; // disable external match register
pierreprovent 0:77ca32e8e04e 192 // initialize the interrupt vector
pierreprovent 0:77ca32e8e04e 193 NVIC_SetVector(SYS_TICK_IRQn, (uint32_t)&SysTick_Handler);
pierreprovent 0:77ca32e8e04e 194 SYS_TICK_TIMER->TCR = 1; // enable timer 0
pierreprovent 0:77ca32e8e04e 195 }
pierreprovent 0:77ca32e8e04e 196
pierreprovent 0:77ca32e8e04e 197 __inline static void rt_svc_init (void) {
pierreprovent 0:77ca32e8e04e 198 // TODO: add svcInit
pierreprovent 0:77ca32e8e04e 199
pierreprovent 0:77ca32e8e04e 200 }
pierreprovent 0:77ca32e8e04e 201
pierreprovent 0:77ca32e8e04e 202 #ifdef DBG_MSG
pierreprovent 0:77ca32e8e04e 203 #define DBG_INIT() dbg_init()
pierreprovent 0:77ca32e8e04e 204 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
pierreprovent 0:77ca32e8e04e 205 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
pierreprovent 0:77ca32e8e04e 206 dbg_task_switch(task_id)
pierreprovent 0:77ca32e8e04e 207 #else
pierreprovent 0:77ca32e8e04e 208 #define DBG_INIT()
pierreprovent 0:77ca32e8e04e 209 #define DBG_TASK_NOTIFY(p_tcb,create)
pierreprovent 0:77ca32e8e04e 210 #define DBG_TASK_SWITCH(task_id)
pierreprovent 0:77ca32e8e04e 211 #endif
pierreprovent 0:77ca32e8e04e 212
pierreprovent 0:77ca32e8e04e 213 /*----------------------------------------------------------------------------
pierreprovent 0:77ca32e8e04e 214 * end of file
pierreprovent 0:77ca32e8e04e 215 *---------------------------------------------------------------------------*/
pierreprovent 0:77ca32e8e04e 216