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targets/cmsis/core_cm0plus.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

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phungductung 0:e87aa4c49e95 1 /**************************************************************************//**
phungductung 0:e87aa4c49e95 2 * @file core_cm0plus.h
phungductung 0:e87aa4c49e95 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
phungductung 0:e87aa4c49e95 4 * @version V4.10
phungductung 0:e87aa4c49e95 5 * @date 18. March 2015
phungductung 0:e87aa4c49e95 6 *
phungductung 0:e87aa4c49e95 7 * @note
phungductung 0:e87aa4c49e95 8 *
phungductung 0:e87aa4c49e95 9 ******************************************************************************/
phungductung 0:e87aa4c49e95 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
phungductung 0:e87aa4c49e95 11
phungductung 0:e87aa4c49e95 12 All rights reserved.
phungductung 0:e87aa4c49e95 13 Redistribution and use in source and binary forms, with or without
phungductung 0:e87aa4c49e95 14 modification, are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 15 - Redistributions of source code must retain the above copyright
phungductung 0:e87aa4c49e95 16 notice, this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 17 - Redistributions in binary form must reproduce the above copyright
phungductung 0:e87aa4c49e95 18 notice, this list of conditions and the following disclaimer in the
phungductung 0:e87aa4c49e95 19 documentation and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 20 - Neither the name of ARM nor the names of its contributors may be used
phungductung 0:e87aa4c49e95 21 to endorse or promote products derived from this software without
phungductung 0:e87aa4c49e95 22 specific prior written permission.
phungductung 0:e87aa4c49e95 23 *
phungductung 0:e87aa4c49e95 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
phungductung 0:e87aa4c49e95 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
phungductung 0:e87aa4c49e95 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
phungductung 0:e87aa4c49e95 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
phungductung 0:e87aa4c49e95 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
phungductung 0:e87aa4c49e95 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
phungductung 0:e87aa4c49e95 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
phungductung 0:e87aa4c49e95 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
phungductung 0:e87aa4c49e95 34 POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 35 ---------------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 36
phungductung 0:e87aa4c49e95 37
phungductung 0:e87aa4c49e95 38 #if defined ( __ICCARM__ )
phungductung 0:e87aa4c49e95 39 #pragma system_include /* treat file as system include file for MISRA check */
phungductung 0:e87aa4c49e95 40 #endif
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 #ifndef __CORE_CM0PLUS_H_GENERIC
phungductung 0:e87aa4c49e95 43 #define __CORE_CM0PLUS_H_GENERIC
phungductung 0:e87aa4c49e95 44
phungductung 0:e87aa4c49e95 45 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 46 extern "C" {
phungductung 0:e87aa4c49e95 47 #endif
phungductung 0:e87aa4c49e95 48
phungductung 0:e87aa4c49e95 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
phungductung 0:e87aa4c49e95 50 CMSIS violates the following MISRA-C:2004 rules:
phungductung 0:e87aa4c49e95 51
phungductung 0:e87aa4c49e95 52 \li Required Rule 8.5, object/function definition in header file.<br>
phungductung 0:e87aa4c49e95 53 Function definitions in header files are used to allow 'inlining'.
phungductung 0:e87aa4c49e95 54
phungductung 0:e87aa4c49e95 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
phungductung 0:e87aa4c49e95 56 Unions are used for effective representation of core registers.
phungductung 0:e87aa4c49e95 57
phungductung 0:e87aa4c49e95 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
phungductung 0:e87aa4c49e95 59 Function-like macros are used to allow more efficient code.
phungductung 0:e87aa4c49e95 60 */
phungductung 0:e87aa4c49e95 61
phungductung 0:e87aa4c49e95 62
phungductung 0:e87aa4c49e95 63 /*******************************************************************************
phungductung 0:e87aa4c49e95 64 * CMSIS definitions
phungductung 0:e87aa4c49e95 65 ******************************************************************************/
phungductung 0:e87aa4c49e95 66 /** \ingroup Cortex-M0+
phungductung 0:e87aa4c49e95 67 @{
phungductung 0:e87aa4c49e95 68 */
phungductung 0:e87aa4c49e95 69
phungductung 0:e87aa4c49e95 70 /* CMSIS CM0P definitions */
phungductung 0:e87aa4c49e95 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
phungductung 0:e87aa4c49e95 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
phungductung 0:e87aa4c49e95 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
phungductung 0:e87aa4c49e95 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
phungductung 0:e87aa4c49e95 75
phungductung 0:e87aa4c49e95 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
phungductung 0:e87aa4c49e95 77
phungductung 0:e87aa4c49e95 78
phungductung 0:e87aa4c49e95 79 #if defined ( __CC_ARM )
phungductung 0:e87aa4c49e95 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
phungductung 0:e87aa4c49e95 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
phungductung 0:e87aa4c49e95 82 #define __STATIC_INLINE static __inline
phungductung 0:e87aa4c49e95 83
phungductung 0:e87aa4c49e95 84 #elif defined ( __GNUC__ )
phungductung 0:e87aa4c49e95 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
phungductung 0:e87aa4c49e95 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
phungductung 0:e87aa4c49e95 87 #define __STATIC_INLINE static inline
phungductung 0:e87aa4c49e95 88
phungductung 0:e87aa4c49e95 89 #elif defined ( __ICCARM__ )
phungductung 0:e87aa4c49e95 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
phungductung 0:e87aa4c49e95 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
phungductung 0:e87aa4c49e95 92 #define __STATIC_INLINE static inline
phungductung 0:e87aa4c49e95 93
phungductung 0:e87aa4c49e95 94 #elif defined ( __TMS470__ )
phungductung 0:e87aa4c49e95 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
phungductung 0:e87aa4c49e95 96 #define __STATIC_INLINE static inline
phungductung 0:e87aa4c49e95 97
phungductung 0:e87aa4c49e95 98 #elif defined ( __TASKING__ )
phungductung 0:e87aa4c49e95 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
phungductung 0:e87aa4c49e95 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
phungductung 0:e87aa4c49e95 101 #define __STATIC_INLINE static inline
phungductung 0:e87aa4c49e95 102
phungductung 0:e87aa4c49e95 103 #elif defined ( __CSMC__ )
phungductung 0:e87aa4c49e95 104 #define __packed
phungductung 0:e87aa4c49e95 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
phungductung 0:e87aa4c49e95 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
phungductung 0:e87aa4c49e95 107 #define __STATIC_INLINE static inline
phungductung 0:e87aa4c49e95 108
phungductung 0:e87aa4c49e95 109 #endif
phungductung 0:e87aa4c49e95 110
phungductung 0:e87aa4c49e95 111 /** __FPU_USED indicates whether an FPU is used or not.
phungductung 0:e87aa4c49e95 112 This core does not support an FPU at all
phungductung 0:e87aa4c49e95 113 */
phungductung 0:e87aa4c49e95 114 #define __FPU_USED 0
phungductung 0:e87aa4c49e95 115
phungductung 0:e87aa4c49e95 116 #if defined ( __CC_ARM )
phungductung 0:e87aa4c49e95 117 #if defined __TARGET_FPU_VFP
phungductung 0:e87aa4c49e95 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:e87aa4c49e95 119 #endif
phungductung 0:e87aa4c49e95 120
phungductung 0:e87aa4c49e95 121 #elif defined ( __GNUC__ )
phungductung 0:e87aa4c49e95 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
phungductung 0:e87aa4c49e95 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:e87aa4c49e95 124 #endif
phungductung 0:e87aa4c49e95 125
phungductung 0:e87aa4c49e95 126 #elif defined ( __ICCARM__ )
phungductung 0:e87aa4c49e95 127 #if defined __ARMVFP__
phungductung 0:e87aa4c49e95 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:e87aa4c49e95 129 #endif
phungductung 0:e87aa4c49e95 130
phungductung 0:e87aa4c49e95 131 #elif defined ( __TMS470__ )
phungductung 0:e87aa4c49e95 132 #if defined __TI__VFP_SUPPORT____
phungductung 0:e87aa4c49e95 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:e87aa4c49e95 134 #endif
phungductung 0:e87aa4c49e95 135
phungductung 0:e87aa4c49e95 136 #elif defined ( __TASKING__ )
phungductung 0:e87aa4c49e95 137 #if defined __FPU_VFP__
phungductung 0:e87aa4c49e95 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:e87aa4c49e95 139 #endif
phungductung 0:e87aa4c49e95 140
phungductung 0:e87aa4c49e95 141 #elif defined ( __CSMC__ ) /* Cosmic */
phungductung 0:e87aa4c49e95 142 #if ( __CSMC__ & 0x400) // FPU present for parser
phungductung 0:e87aa4c49e95 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:e87aa4c49e95 144 #endif
phungductung 0:e87aa4c49e95 145 #endif
phungductung 0:e87aa4c49e95 146
phungductung 0:e87aa4c49e95 147 #include <stdint.h> /* standard types definitions */
phungductung 0:e87aa4c49e95 148 #include <core_cmInstr.h> /* Core Instruction Access */
phungductung 0:e87aa4c49e95 149 #include <core_cmFunc.h> /* Core Function Access */
phungductung 0:e87aa4c49e95 150
phungductung 0:e87aa4c49e95 151 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 152 }
phungductung 0:e87aa4c49e95 153 #endif
phungductung 0:e87aa4c49e95 154
phungductung 0:e87aa4c49e95 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
phungductung 0:e87aa4c49e95 156
phungductung 0:e87aa4c49e95 157 #ifndef __CMSIS_GENERIC
phungductung 0:e87aa4c49e95 158
phungductung 0:e87aa4c49e95 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
phungductung 0:e87aa4c49e95 160 #define __CORE_CM0PLUS_H_DEPENDANT
phungductung 0:e87aa4c49e95 161
phungductung 0:e87aa4c49e95 162 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 163 extern "C" {
phungductung 0:e87aa4c49e95 164 #endif
phungductung 0:e87aa4c49e95 165
phungductung 0:e87aa4c49e95 166 /* check device defines and use defaults */
phungductung 0:e87aa4c49e95 167 #if defined __CHECK_DEVICE_DEFINES
phungductung 0:e87aa4c49e95 168 #ifndef __CM0PLUS_REV
phungductung 0:e87aa4c49e95 169 #define __CM0PLUS_REV 0x0000
phungductung 0:e87aa4c49e95 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
phungductung 0:e87aa4c49e95 171 #endif
phungductung 0:e87aa4c49e95 172
phungductung 0:e87aa4c49e95 173 #ifndef __MPU_PRESENT
phungductung 0:e87aa4c49e95 174 #define __MPU_PRESENT 0
phungductung 0:e87aa4c49e95 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
phungductung 0:e87aa4c49e95 176 #endif
phungductung 0:e87aa4c49e95 177
phungductung 0:e87aa4c49e95 178 #ifndef __VTOR_PRESENT
phungductung 0:e87aa4c49e95 179 #define __VTOR_PRESENT 0
phungductung 0:e87aa4c49e95 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
phungductung 0:e87aa4c49e95 181 #endif
phungductung 0:e87aa4c49e95 182
phungductung 0:e87aa4c49e95 183 #ifndef __NVIC_PRIO_BITS
phungductung 0:e87aa4c49e95 184 #define __NVIC_PRIO_BITS 2
phungductung 0:e87aa4c49e95 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
phungductung 0:e87aa4c49e95 186 #endif
phungductung 0:e87aa4c49e95 187
phungductung 0:e87aa4c49e95 188 #ifndef __Vendor_SysTickConfig
phungductung 0:e87aa4c49e95 189 #define __Vendor_SysTickConfig 0
phungductung 0:e87aa4c49e95 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
phungductung 0:e87aa4c49e95 191 #endif
phungductung 0:e87aa4c49e95 192 #endif
phungductung 0:e87aa4c49e95 193
phungductung 0:e87aa4c49e95 194 /* IO definitions (access restrictions to peripheral registers) */
phungductung 0:e87aa4c49e95 195 /**
phungductung 0:e87aa4c49e95 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
phungductung 0:e87aa4c49e95 197
phungductung 0:e87aa4c49e95 198 <strong>IO Type Qualifiers</strong> are used
phungductung 0:e87aa4c49e95 199 \li to specify the access to peripheral variables.
phungductung 0:e87aa4c49e95 200 \li for automatic generation of peripheral register debug information.
phungductung 0:e87aa4c49e95 201 */
phungductung 0:e87aa4c49e95 202 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 203 #define __I volatile /*!< Defines 'read only' permissions */
phungductung 0:e87aa4c49e95 204 #else
phungductung 0:e87aa4c49e95 205 #define __I volatile const /*!< Defines 'read only' permissions */
phungductung 0:e87aa4c49e95 206 #endif
phungductung 0:e87aa4c49e95 207 #define __O volatile /*!< Defines 'write only' permissions */
phungductung 0:e87aa4c49e95 208 #define __IO volatile /*!< Defines 'read / write' permissions */
phungductung 0:e87aa4c49e95 209
phungductung 0:e87aa4c49e95 210 /*@} end of group Cortex-M0+ */
phungductung 0:e87aa4c49e95 211
phungductung 0:e87aa4c49e95 212
phungductung 0:e87aa4c49e95 213
phungductung 0:e87aa4c49e95 214 /*******************************************************************************
phungductung 0:e87aa4c49e95 215 * Register Abstraction
phungductung 0:e87aa4c49e95 216 Core Register contain:
phungductung 0:e87aa4c49e95 217 - Core Register
phungductung 0:e87aa4c49e95 218 - Core NVIC Register
phungductung 0:e87aa4c49e95 219 - Core SCB Register
phungductung 0:e87aa4c49e95 220 - Core SysTick Register
phungductung 0:e87aa4c49e95 221 - Core MPU Register
phungductung 0:e87aa4c49e95 222 ******************************************************************************/
phungductung 0:e87aa4c49e95 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
phungductung 0:e87aa4c49e95 224 \brief Type definitions and defines for Cortex-M processor based devices.
phungductung 0:e87aa4c49e95 225 */
phungductung 0:e87aa4c49e95 226
phungductung 0:e87aa4c49e95 227 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 228 \defgroup CMSIS_CORE Status and Control Registers
phungductung 0:e87aa4c49e95 229 \brief Core Register type definitions.
phungductung 0:e87aa4c49e95 230 @{
phungductung 0:e87aa4c49e95 231 */
phungductung 0:e87aa4c49e95 232
phungductung 0:e87aa4c49e95 233 /** \brief Union type to access the Application Program Status Register (APSR).
phungductung 0:e87aa4c49e95 234 */
phungductung 0:e87aa4c49e95 235 typedef union
phungductung 0:e87aa4c49e95 236 {
phungductung 0:e87aa4c49e95 237 struct
phungductung 0:e87aa4c49e95 238 {
phungductung 0:e87aa4c49e95 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
phungductung 0:e87aa4c49e95 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
phungductung 0:e87aa4c49e95 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
phungductung 0:e87aa4c49e95 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
phungductung 0:e87aa4c49e95 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
phungductung 0:e87aa4c49e95 244 } b; /*!< Structure used for bit access */
phungductung 0:e87aa4c49e95 245 uint32_t w; /*!< Type used for word access */
phungductung 0:e87aa4c49e95 246 } APSR_Type;
phungductung 0:e87aa4c49e95 247
phungductung 0:e87aa4c49e95 248 /* APSR Register Definitions */
phungductung 0:e87aa4c49e95 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
phungductung 0:e87aa4c49e95 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
phungductung 0:e87aa4c49e95 251
phungductung 0:e87aa4c49e95 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
phungductung 0:e87aa4c49e95 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
phungductung 0:e87aa4c49e95 254
phungductung 0:e87aa4c49e95 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
phungductung 0:e87aa4c49e95 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
phungductung 0:e87aa4c49e95 257
phungductung 0:e87aa4c49e95 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
phungductung 0:e87aa4c49e95 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
phungductung 0:e87aa4c49e95 260
phungductung 0:e87aa4c49e95 261
phungductung 0:e87aa4c49e95 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
phungductung 0:e87aa4c49e95 263 */
phungductung 0:e87aa4c49e95 264 typedef union
phungductung 0:e87aa4c49e95 265 {
phungductung 0:e87aa4c49e95 266 struct
phungductung 0:e87aa4c49e95 267 {
phungductung 0:e87aa4c49e95 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
phungductung 0:e87aa4c49e95 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
phungductung 0:e87aa4c49e95 270 } b; /*!< Structure used for bit access */
phungductung 0:e87aa4c49e95 271 uint32_t w; /*!< Type used for word access */
phungductung 0:e87aa4c49e95 272 } IPSR_Type;
phungductung 0:e87aa4c49e95 273
phungductung 0:e87aa4c49e95 274 /* IPSR Register Definitions */
phungductung 0:e87aa4c49e95 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
phungductung 0:e87aa4c49e95 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
phungductung 0:e87aa4c49e95 277
phungductung 0:e87aa4c49e95 278
phungductung 0:e87aa4c49e95 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
phungductung 0:e87aa4c49e95 280 */
phungductung 0:e87aa4c49e95 281 typedef union
phungductung 0:e87aa4c49e95 282 {
phungductung 0:e87aa4c49e95 283 struct
phungductung 0:e87aa4c49e95 284 {
phungductung 0:e87aa4c49e95 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
phungductung 0:e87aa4c49e95 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
phungductung 0:e87aa4c49e95 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
phungductung 0:e87aa4c49e95 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
phungductung 0:e87aa4c49e95 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
phungductung 0:e87aa4c49e95 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
phungductung 0:e87aa4c49e95 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
phungductung 0:e87aa4c49e95 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
phungductung 0:e87aa4c49e95 293 } b; /*!< Structure used for bit access */
phungductung 0:e87aa4c49e95 294 uint32_t w; /*!< Type used for word access */
phungductung 0:e87aa4c49e95 295 } xPSR_Type;
phungductung 0:e87aa4c49e95 296
phungductung 0:e87aa4c49e95 297 /* xPSR Register Definitions */
phungductung 0:e87aa4c49e95 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
phungductung 0:e87aa4c49e95 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
phungductung 0:e87aa4c49e95 300
phungductung 0:e87aa4c49e95 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
phungductung 0:e87aa4c49e95 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
phungductung 0:e87aa4c49e95 303
phungductung 0:e87aa4c49e95 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
phungductung 0:e87aa4c49e95 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
phungductung 0:e87aa4c49e95 306
phungductung 0:e87aa4c49e95 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
phungductung 0:e87aa4c49e95 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
phungductung 0:e87aa4c49e95 309
phungductung 0:e87aa4c49e95 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
phungductung 0:e87aa4c49e95 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
phungductung 0:e87aa4c49e95 312
phungductung 0:e87aa4c49e95 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
phungductung 0:e87aa4c49e95 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
phungductung 0:e87aa4c49e95 315
phungductung 0:e87aa4c49e95 316
phungductung 0:e87aa4c49e95 317 /** \brief Union type to access the Control Registers (CONTROL).
phungductung 0:e87aa4c49e95 318 */
phungductung 0:e87aa4c49e95 319 typedef union
phungductung 0:e87aa4c49e95 320 {
phungductung 0:e87aa4c49e95 321 struct
phungductung 0:e87aa4c49e95 322 {
phungductung 0:e87aa4c49e95 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
phungductung 0:e87aa4c49e95 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
phungductung 0:e87aa4c49e95 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
phungductung 0:e87aa4c49e95 326 } b; /*!< Structure used for bit access */
phungductung 0:e87aa4c49e95 327 uint32_t w; /*!< Type used for word access */
phungductung 0:e87aa4c49e95 328 } CONTROL_Type;
phungductung 0:e87aa4c49e95 329
phungductung 0:e87aa4c49e95 330 /* CONTROL Register Definitions */
phungductung 0:e87aa4c49e95 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
phungductung 0:e87aa4c49e95 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
phungductung 0:e87aa4c49e95 333
phungductung 0:e87aa4c49e95 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
phungductung 0:e87aa4c49e95 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
phungductung 0:e87aa4c49e95 336
phungductung 0:e87aa4c49e95 337 /*@} end of group CMSIS_CORE */
phungductung 0:e87aa4c49e95 338
phungductung 0:e87aa4c49e95 339
phungductung 0:e87aa4c49e95 340 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
phungductung 0:e87aa4c49e95 342 \brief Type definitions for the NVIC Registers
phungductung 0:e87aa4c49e95 343 @{
phungductung 0:e87aa4c49e95 344 */
phungductung 0:e87aa4c49e95 345
phungductung 0:e87aa4c49e95 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
phungductung 0:e87aa4c49e95 347 */
phungductung 0:e87aa4c49e95 348 typedef struct
phungductung 0:e87aa4c49e95 349 {
phungductung 0:e87aa4c49e95 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
phungductung 0:e87aa4c49e95 351 uint32_t RESERVED0[31];
phungductung 0:e87aa4c49e95 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
phungductung 0:e87aa4c49e95 353 uint32_t RSERVED1[31];
phungductung 0:e87aa4c49e95 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
phungductung 0:e87aa4c49e95 355 uint32_t RESERVED2[31];
phungductung 0:e87aa4c49e95 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
phungductung 0:e87aa4c49e95 357 uint32_t RESERVED3[31];
phungductung 0:e87aa4c49e95 358 uint32_t RESERVED4[64];
phungductung 0:e87aa4c49e95 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
phungductung 0:e87aa4c49e95 360 } NVIC_Type;
phungductung 0:e87aa4c49e95 361
phungductung 0:e87aa4c49e95 362 /*@} end of group CMSIS_NVIC */
phungductung 0:e87aa4c49e95 363
phungductung 0:e87aa4c49e95 364
phungductung 0:e87aa4c49e95 365 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 366 \defgroup CMSIS_SCB System Control Block (SCB)
phungductung 0:e87aa4c49e95 367 \brief Type definitions for the System Control Block Registers
phungductung 0:e87aa4c49e95 368 @{
phungductung 0:e87aa4c49e95 369 */
phungductung 0:e87aa4c49e95 370
phungductung 0:e87aa4c49e95 371 /** \brief Structure type to access the System Control Block (SCB).
phungductung 0:e87aa4c49e95 372 */
phungductung 0:e87aa4c49e95 373 typedef struct
phungductung 0:e87aa4c49e95 374 {
phungductung 0:e87aa4c49e95 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
phungductung 0:e87aa4c49e95 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
phungductung 0:e87aa4c49e95 377 #if (__VTOR_PRESENT == 1)
phungductung 0:e87aa4c49e95 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
phungductung 0:e87aa4c49e95 379 #else
phungductung 0:e87aa4c49e95 380 uint32_t RESERVED0;
phungductung 0:e87aa4c49e95 381 #endif
phungductung 0:e87aa4c49e95 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
phungductung 0:e87aa4c49e95 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
phungductung 0:e87aa4c49e95 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
phungductung 0:e87aa4c49e95 385 uint32_t RESERVED1;
phungductung 0:e87aa4c49e95 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
phungductung 0:e87aa4c49e95 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
phungductung 0:e87aa4c49e95 388 } SCB_Type;
phungductung 0:e87aa4c49e95 389
phungductung 0:e87aa4c49e95 390 /* SCB CPUID Register Definitions */
phungductung 0:e87aa4c49e95 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
phungductung 0:e87aa4c49e95 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
phungductung 0:e87aa4c49e95 393
phungductung 0:e87aa4c49e95 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
phungductung 0:e87aa4c49e95 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
phungductung 0:e87aa4c49e95 396
phungductung 0:e87aa4c49e95 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
phungductung 0:e87aa4c49e95 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
phungductung 0:e87aa4c49e95 399
phungductung 0:e87aa4c49e95 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
phungductung 0:e87aa4c49e95 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
phungductung 0:e87aa4c49e95 402
phungductung 0:e87aa4c49e95 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
phungductung 0:e87aa4c49e95 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
phungductung 0:e87aa4c49e95 405
phungductung 0:e87aa4c49e95 406 /* SCB Interrupt Control State Register Definitions */
phungductung 0:e87aa4c49e95 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
phungductung 0:e87aa4c49e95 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
phungductung 0:e87aa4c49e95 409
phungductung 0:e87aa4c49e95 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
phungductung 0:e87aa4c49e95 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
phungductung 0:e87aa4c49e95 412
phungductung 0:e87aa4c49e95 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
phungductung 0:e87aa4c49e95 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
phungductung 0:e87aa4c49e95 415
phungductung 0:e87aa4c49e95 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
phungductung 0:e87aa4c49e95 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
phungductung 0:e87aa4c49e95 418
phungductung 0:e87aa4c49e95 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
phungductung 0:e87aa4c49e95 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
phungductung 0:e87aa4c49e95 421
phungductung 0:e87aa4c49e95 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
phungductung 0:e87aa4c49e95 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
phungductung 0:e87aa4c49e95 424
phungductung 0:e87aa4c49e95 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
phungductung 0:e87aa4c49e95 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
phungductung 0:e87aa4c49e95 427
phungductung 0:e87aa4c49e95 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
phungductung 0:e87aa4c49e95 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
phungductung 0:e87aa4c49e95 430
phungductung 0:e87aa4c49e95 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
phungductung 0:e87aa4c49e95 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
phungductung 0:e87aa4c49e95 433
phungductung 0:e87aa4c49e95 434 #if (__VTOR_PRESENT == 1)
phungductung 0:e87aa4c49e95 435 /* SCB Interrupt Control State Register Definitions */
phungductung 0:e87aa4c49e95 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
phungductung 0:e87aa4c49e95 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
phungductung 0:e87aa4c49e95 438 #endif
phungductung 0:e87aa4c49e95 439
phungductung 0:e87aa4c49e95 440 /* SCB Application Interrupt and Reset Control Register Definitions */
phungductung 0:e87aa4c49e95 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
phungductung 0:e87aa4c49e95 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
phungductung 0:e87aa4c49e95 443
phungductung 0:e87aa4c49e95 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
phungductung 0:e87aa4c49e95 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
phungductung 0:e87aa4c49e95 446
phungductung 0:e87aa4c49e95 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
phungductung 0:e87aa4c49e95 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
phungductung 0:e87aa4c49e95 449
phungductung 0:e87aa4c49e95 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
phungductung 0:e87aa4c49e95 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
phungductung 0:e87aa4c49e95 452
phungductung 0:e87aa4c49e95 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
phungductung 0:e87aa4c49e95 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
phungductung 0:e87aa4c49e95 455
phungductung 0:e87aa4c49e95 456 /* SCB System Control Register Definitions */
phungductung 0:e87aa4c49e95 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
phungductung 0:e87aa4c49e95 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
phungductung 0:e87aa4c49e95 459
phungductung 0:e87aa4c49e95 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
phungductung 0:e87aa4c49e95 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
phungductung 0:e87aa4c49e95 462
phungductung 0:e87aa4c49e95 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
phungductung 0:e87aa4c49e95 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
phungductung 0:e87aa4c49e95 465
phungductung 0:e87aa4c49e95 466 /* SCB Configuration Control Register Definitions */
phungductung 0:e87aa4c49e95 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
phungductung 0:e87aa4c49e95 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
phungductung 0:e87aa4c49e95 469
phungductung 0:e87aa4c49e95 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
phungductung 0:e87aa4c49e95 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
phungductung 0:e87aa4c49e95 472
phungductung 0:e87aa4c49e95 473 /* SCB System Handler Control and State Register Definitions */
phungductung 0:e87aa4c49e95 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
phungductung 0:e87aa4c49e95 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
phungductung 0:e87aa4c49e95 476
phungductung 0:e87aa4c49e95 477 /*@} end of group CMSIS_SCB */
phungductung 0:e87aa4c49e95 478
phungductung 0:e87aa4c49e95 479
phungductung 0:e87aa4c49e95 480 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
phungductung 0:e87aa4c49e95 482 \brief Type definitions for the System Timer Registers.
phungductung 0:e87aa4c49e95 483 @{
phungductung 0:e87aa4c49e95 484 */
phungductung 0:e87aa4c49e95 485
phungductung 0:e87aa4c49e95 486 /** \brief Structure type to access the System Timer (SysTick).
phungductung 0:e87aa4c49e95 487 */
phungductung 0:e87aa4c49e95 488 typedef struct
phungductung 0:e87aa4c49e95 489 {
phungductung 0:e87aa4c49e95 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
phungductung 0:e87aa4c49e95 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
phungductung 0:e87aa4c49e95 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
phungductung 0:e87aa4c49e95 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
phungductung 0:e87aa4c49e95 494 } SysTick_Type;
phungductung 0:e87aa4c49e95 495
phungductung 0:e87aa4c49e95 496 /* SysTick Control / Status Register Definitions */
phungductung 0:e87aa4c49e95 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
phungductung 0:e87aa4c49e95 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
phungductung 0:e87aa4c49e95 499
phungductung 0:e87aa4c49e95 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
phungductung 0:e87aa4c49e95 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
phungductung 0:e87aa4c49e95 502
phungductung 0:e87aa4c49e95 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
phungductung 0:e87aa4c49e95 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
phungductung 0:e87aa4c49e95 505
phungductung 0:e87aa4c49e95 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
phungductung 0:e87aa4c49e95 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
phungductung 0:e87aa4c49e95 508
phungductung 0:e87aa4c49e95 509 /* SysTick Reload Register Definitions */
phungductung 0:e87aa4c49e95 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
phungductung 0:e87aa4c49e95 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
phungductung 0:e87aa4c49e95 512
phungductung 0:e87aa4c49e95 513 /* SysTick Current Register Definitions */
phungductung 0:e87aa4c49e95 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
phungductung 0:e87aa4c49e95 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
phungductung 0:e87aa4c49e95 516
phungductung 0:e87aa4c49e95 517 /* SysTick Calibration Register Definitions */
phungductung 0:e87aa4c49e95 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
phungductung 0:e87aa4c49e95 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
phungductung 0:e87aa4c49e95 520
phungductung 0:e87aa4c49e95 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
phungductung 0:e87aa4c49e95 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
phungductung 0:e87aa4c49e95 523
phungductung 0:e87aa4c49e95 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
phungductung 0:e87aa4c49e95 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
phungductung 0:e87aa4c49e95 526
phungductung 0:e87aa4c49e95 527 /*@} end of group CMSIS_SysTick */
phungductung 0:e87aa4c49e95 528
phungductung 0:e87aa4c49e95 529 #if (__MPU_PRESENT == 1)
phungductung 0:e87aa4c49e95 530 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
phungductung 0:e87aa4c49e95 532 \brief Type definitions for the Memory Protection Unit (MPU)
phungductung 0:e87aa4c49e95 533 @{
phungductung 0:e87aa4c49e95 534 */
phungductung 0:e87aa4c49e95 535
phungductung 0:e87aa4c49e95 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
phungductung 0:e87aa4c49e95 537 */
phungductung 0:e87aa4c49e95 538 typedef struct
phungductung 0:e87aa4c49e95 539 {
phungductung 0:e87aa4c49e95 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
phungductung 0:e87aa4c49e95 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
phungductung 0:e87aa4c49e95 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
phungductung 0:e87aa4c49e95 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
phungductung 0:e87aa4c49e95 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
phungductung 0:e87aa4c49e95 545 } MPU_Type;
phungductung 0:e87aa4c49e95 546
phungductung 0:e87aa4c49e95 547 /* MPU Type Register */
phungductung 0:e87aa4c49e95 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
phungductung 0:e87aa4c49e95 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
phungductung 0:e87aa4c49e95 550
phungductung 0:e87aa4c49e95 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
phungductung 0:e87aa4c49e95 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
phungductung 0:e87aa4c49e95 553
phungductung 0:e87aa4c49e95 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
phungductung 0:e87aa4c49e95 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
phungductung 0:e87aa4c49e95 556
phungductung 0:e87aa4c49e95 557 /* MPU Control Register */
phungductung 0:e87aa4c49e95 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
phungductung 0:e87aa4c49e95 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
phungductung 0:e87aa4c49e95 560
phungductung 0:e87aa4c49e95 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
phungductung 0:e87aa4c49e95 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
phungductung 0:e87aa4c49e95 563
phungductung 0:e87aa4c49e95 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
phungductung 0:e87aa4c49e95 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
phungductung 0:e87aa4c49e95 566
phungductung 0:e87aa4c49e95 567 /* MPU Region Number Register */
phungductung 0:e87aa4c49e95 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
phungductung 0:e87aa4c49e95 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
phungductung 0:e87aa4c49e95 570
phungductung 0:e87aa4c49e95 571 /* MPU Region Base Address Register */
phungductung 0:e87aa4c49e95 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
phungductung 0:e87aa4c49e95 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
phungductung 0:e87aa4c49e95 574
phungductung 0:e87aa4c49e95 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
phungductung 0:e87aa4c49e95 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
phungductung 0:e87aa4c49e95 577
phungductung 0:e87aa4c49e95 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
phungductung 0:e87aa4c49e95 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
phungductung 0:e87aa4c49e95 580
phungductung 0:e87aa4c49e95 581 /* MPU Region Attribute and Size Register */
phungductung 0:e87aa4c49e95 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
phungductung 0:e87aa4c49e95 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
phungductung 0:e87aa4c49e95 584
phungductung 0:e87aa4c49e95 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
phungductung 0:e87aa4c49e95 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
phungductung 0:e87aa4c49e95 587
phungductung 0:e87aa4c49e95 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
phungductung 0:e87aa4c49e95 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
phungductung 0:e87aa4c49e95 590
phungductung 0:e87aa4c49e95 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
phungductung 0:e87aa4c49e95 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
phungductung 0:e87aa4c49e95 593
phungductung 0:e87aa4c49e95 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
phungductung 0:e87aa4c49e95 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
phungductung 0:e87aa4c49e95 596
phungductung 0:e87aa4c49e95 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
phungductung 0:e87aa4c49e95 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
phungductung 0:e87aa4c49e95 599
phungductung 0:e87aa4c49e95 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
phungductung 0:e87aa4c49e95 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
phungductung 0:e87aa4c49e95 602
phungductung 0:e87aa4c49e95 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
phungductung 0:e87aa4c49e95 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
phungductung 0:e87aa4c49e95 605
phungductung 0:e87aa4c49e95 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
phungductung 0:e87aa4c49e95 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
phungductung 0:e87aa4c49e95 608
phungductung 0:e87aa4c49e95 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
phungductung 0:e87aa4c49e95 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
phungductung 0:e87aa4c49e95 611
phungductung 0:e87aa4c49e95 612 /*@} end of group CMSIS_MPU */
phungductung 0:e87aa4c49e95 613 #endif
phungductung 0:e87aa4c49e95 614
phungductung 0:e87aa4c49e95 615
phungductung 0:e87aa4c49e95 616 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
phungductung 0:e87aa4c49e95 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
phungductung 0:e87aa4c49e95 619 are only accessible over DAP and not via processor. Therefore
phungductung 0:e87aa4c49e95 620 they are not covered by the Cortex-M0 header file.
phungductung 0:e87aa4c49e95 621 @{
phungductung 0:e87aa4c49e95 622 */
phungductung 0:e87aa4c49e95 623 /*@} end of group CMSIS_CoreDebug */
phungductung 0:e87aa4c49e95 624
phungductung 0:e87aa4c49e95 625
phungductung 0:e87aa4c49e95 626 /** \ingroup CMSIS_core_register
phungductung 0:e87aa4c49e95 627 \defgroup CMSIS_core_base Core Definitions
phungductung 0:e87aa4c49e95 628 \brief Definitions for base addresses, unions, and structures.
phungductung 0:e87aa4c49e95 629 @{
phungductung 0:e87aa4c49e95 630 */
phungductung 0:e87aa4c49e95 631
phungductung 0:e87aa4c49e95 632 /* Memory mapping of Cortex-M0+ Hardware */
phungductung 0:e87aa4c49e95 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
phungductung 0:e87aa4c49e95 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
phungductung 0:e87aa4c49e95 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
phungductung 0:e87aa4c49e95 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
phungductung 0:e87aa4c49e95 637
phungductung 0:e87aa4c49e95 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
phungductung 0:e87aa4c49e95 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
phungductung 0:e87aa4c49e95 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
phungductung 0:e87aa4c49e95 641
phungductung 0:e87aa4c49e95 642 #if (__MPU_PRESENT == 1)
phungductung 0:e87aa4c49e95 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
phungductung 0:e87aa4c49e95 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
phungductung 0:e87aa4c49e95 645 #endif
phungductung 0:e87aa4c49e95 646
phungductung 0:e87aa4c49e95 647 /*@} */
phungductung 0:e87aa4c49e95 648
phungductung 0:e87aa4c49e95 649
phungductung 0:e87aa4c49e95 650
phungductung 0:e87aa4c49e95 651 /*******************************************************************************
phungductung 0:e87aa4c49e95 652 * Hardware Abstraction Layer
phungductung 0:e87aa4c49e95 653 Core Function Interface contains:
phungductung 0:e87aa4c49e95 654 - Core NVIC Functions
phungductung 0:e87aa4c49e95 655 - Core SysTick Functions
phungductung 0:e87aa4c49e95 656 - Core Register Access Functions
phungductung 0:e87aa4c49e95 657 ******************************************************************************/
phungductung 0:e87aa4c49e95 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
phungductung 0:e87aa4c49e95 659 */
phungductung 0:e87aa4c49e95 660
phungductung 0:e87aa4c49e95 661
phungductung 0:e87aa4c49e95 662
phungductung 0:e87aa4c49e95 663 /* ########################## NVIC functions #################################### */
phungductung 0:e87aa4c49e95 664 /** \ingroup CMSIS_Core_FunctionInterface
phungductung 0:e87aa4c49e95 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
phungductung 0:e87aa4c49e95 666 \brief Functions that manage interrupts and exceptions via the NVIC.
phungductung 0:e87aa4c49e95 667 @{
phungductung 0:e87aa4c49e95 668 */
phungductung 0:e87aa4c49e95 669
phungductung 0:e87aa4c49e95 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
phungductung 0:e87aa4c49e95 671 /* The following MACROS handle generation of the register offset and byte masks */
phungductung 0:e87aa4c49e95 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
phungductung 0:e87aa4c49e95 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
phungductung 0:e87aa4c49e95 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
phungductung 0:e87aa4c49e95 675
phungductung 0:e87aa4c49e95 676
phungductung 0:e87aa4c49e95 677 /** \brief Enable External Interrupt
phungductung 0:e87aa4c49e95 678
phungductung 0:e87aa4c49e95 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
phungductung 0:e87aa4c49e95 680
phungductung 0:e87aa4c49e95 681 \param [in] IRQn External interrupt number. Value cannot be negative.
phungductung 0:e87aa4c49e95 682 */
phungductung 0:e87aa4c49e95 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
phungductung 0:e87aa4c49e95 684 {
phungductung 0:e87aa4c49e95 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:e87aa4c49e95 686 }
phungductung 0:e87aa4c49e95 687
phungductung 0:e87aa4c49e95 688
phungductung 0:e87aa4c49e95 689 /** \brief Disable External Interrupt
phungductung 0:e87aa4c49e95 690
phungductung 0:e87aa4c49e95 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
phungductung 0:e87aa4c49e95 692
phungductung 0:e87aa4c49e95 693 \param [in] IRQn External interrupt number. Value cannot be negative.
phungductung 0:e87aa4c49e95 694 */
phungductung 0:e87aa4c49e95 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
phungductung 0:e87aa4c49e95 696 {
phungductung 0:e87aa4c49e95 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:e87aa4c49e95 698 }
phungductung 0:e87aa4c49e95 699
phungductung 0:e87aa4c49e95 700
phungductung 0:e87aa4c49e95 701 /** \brief Get Pending Interrupt
phungductung 0:e87aa4c49e95 702
phungductung 0:e87aa4c49e95 703 The function reads the pending register in the NVIC and returns the pending bit
phungductung 0:e87aa4c49e95 704 for the specified interrupt.
phungductung 0:e87aa4c49e95 705
phungductung 0:e87aa4c49e95 706 \param [in] IRQn Interrupt number.
phungductung 0:e87aa4c49e95 707
phungductung 0:e87aa4c49e95 708 \return 0 Interrupt status is not pending.
phungductung 0:e87aa4c49e95 709 \return 1 Interrupt status is pending.
phungductung 0:e87aa4c49e95 710 */
phungductung 0:e87aa4c49e95 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
phungductung 0:e87aa4c49e95 712 {
phungductung 0:e87aa4c49e95 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung 0:e87aa4c49e95 714 }
phungductung 0:e87aa4c49e95 715
phungductung 0:e87aa4c49e95 716
phungductung 0:e87aa4c49e95 717 /** \brief Set Pending Interrupt
phungductung 0:e87aa4c49e95 718
phungductung 0:e87aa4c49e95 719 The function sets the pending bit of an external interrupt.
phungductung 0:e87aa4c49e95 720
phungductung 0:e87aa4c49e95 721 \param [in] IRQn Interrupt number. Value cannot be negative.
phungductung 0:e87aa4c49e95 722 */
phungductung 0:e87aa4c49e95 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
phungductung 0:e87aa4c49e95 724 {
phungductung 0:e87aa4c49e95 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:e87aa4c49e95 726 }
phungductung 0:e87aa4c49e95 727
phungductung 0:e87aa4c49e95 728
phungductung 0:e87aa4c49e95 729 /** \brief Clear Pending Interrupt
phungductung 0:e87aa4c49e95 730
phungductung 0:e87aa4c49e95 731 The function clears the pending bit of an external interrupt.
phungductung 0:e87aa4c49e95 732
phungductung 0:e87aa4c49e95 733 \param [in] IRQn External interrupt number. Value cannot be negative.
phungductung 0:e87aa4c49e95 734 */
phungductung 0:e87aa4c49e95 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
phungductung 0:e87aa4c49e95 736 {
phungductung 0:e87aa4c49e95 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:e87aa4c49e95 738 }
phungductung 0:e87aa4c49e95 739
phungductung 0:e87aa4c49e95 740
phungductung 0:e87aa4c49e95 741 /** \brief Set Interrupt Priority
phungductung 0:e87aa4c49e95 742
phungductung 0:e87aa4c49e95 743 The function sets the priority of an interrupt.
phungductung 0:e87aa4c49e95 744
phungductung 0:e87aa4c49e95 745 \note The priority cannot be set for every core interrupt.
phungductung 0:e87aa4c49e95 746
phungductung 0:e87aa4c49e95 747 \param [in] IRQn Interrupt number.
phungductung 0:e87aa4c49e95 748 \param [in] priority Priority to set.
phungductung 0:e87aa4c49e95 749 */
phungductung 0:e87aa4c49e95 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
phungductung 0:e87aa4c49e95 751 {
phungductung 0:e87aa4c49e95 752 if((int32_t)(IRQn) < 0) {
phungductung 0:e87aa4c49e95 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
phungductung 0:e87aa4c49e95 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
phungductung 0:e87aa4c49e95 755 }
phungductung 0:e87aa4c49e95 756 else {
phungductung 0:e87aa4c49e95 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
phungductung 0:e87aa4c49e95 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
phungductung 0:e87aa4c49e95 759 }
phungductung 0:e87aa4c49e95 760 }
phungductung 0:e87aa4c49e95 761
phungductung 0:e87aa4c49e95 762
phungductung 0:e87aa4c49e95 763 /** \brief Get Interrupt Priority
phungductung 0:e87aa4c49e95 764
phungductung 0:e87aa4c49e95 765 The function reads the priority of an interrupt. The interrupt
phungductung 0:e87aa4c49e95 766 number can be positive to specify an external (device specific)
phungductung 0:e87aa4c49e95 767 interrupt, or negative to specify an internal (core) interrupt.
phungductung 0:e87aa4c49e95 768
phungductung 0:e87aa4c49e95 769
phungductung 0:e87aa4c49e95 770 \param [in] IRQn Interrupt number.
phungductung 0:e87aa4c49e95 771 \return Interrupt Priority. Value is aligned automatically to the implemented
phungductung 0:e87aa4c49e95 772 priority bits of the microcontroller.
phungductung 0:e87aa4c49e95 773 */
phungductung 0:e87aa4c49e95 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
phungductung 0:e87aa4c49e95 775 {
phungductung 0:e87aa4c49e95 776
phungductung 0:e87aa4c49e95 777 if((int32_t)(IRQn) < 0) {
phungductung 0:e87aa4c49e95 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
phungductung 0:e87aa4c49e95 779 }
phungductung 0:e87aa4c49e95 780 else {
phungductung 0:e87aa4c49e95 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
phungductung 0:e87aa4c49e95 782 }
phungductung 0:e87aa4c49e95 783 }
phungductung 0:e87aa4c49e95 784
phungductung 0:e87aa4c49e95 785
phungductung 0:e87aa4c49e95 786 /** \brief System Reset
phungductung 0:e87aa4c49e95 787
phungductung 0:e87aa4c49e95 788 The function initiates a system reset request to reset the MCU.
phungductung 0:e87aa4c49e95 789 */
phungductung 0:e87aa4c49e95 790 __STATIC_INLINE void NVIC_SystemReset(void)
phungductung 0:e87aa4c49e95 791 {
phungductung 0:e87aa4c49e95 792 __DSB(); /* Ensure all outstanding memory accesses included
phungductung 0:e87aa4c49e95 793 buffered write are completed before reset */
phungductung 0:e87aa4c49e95 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
phungductung 0:e87aa4c49e95 795 SCB_AIRCR_SYSRESETREQ_Msk);
phungductung 0:e87aa4c49e95 796 __DSB(); /* Ensure completion of memory access */
phungductung 0:e87aa4c49e95 797 while(1) { __NOP(); } /* wait until reset */
phungductung 0:e87aa4c49e95 798 }
phungductung 0:e87aa4c49e95 799
phungductung 0:e87aa4c49e95 800 /*@} end of CMSIS_Core_NVICFunctions */
phungductung 0:e87aa4c49e95 801
phungductung 0:e87aa4c49e95 802
phungductung 0:e87aa4c49e95 803
phungductung 0:e87aa4c49e95 804 /* ################################## SysTick function ############################################ */
phungductung 0:e87aa4c49e95 805 /** \ingroup CMSIS_Core_FunctionInterface
phungductung 0:e87aa4c49e95 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
phungductung 0:e87aa4c49e95 807 \brief Functions that configure the System.
phungductung 0:e87aa4c49e95 808 @{
phungductung 0:e87aa4c49e95 809 */
phungductung 0:e87aa4c49e95 810
phungductung 0:e87aa4c49e95 811 #if (__Vendor_SysTickConfig == 0)
phungductung 0:e87aa4c49e95 812
phungductung 0:e87aa4c49e95 813 /** \brief System Tick Configuration
phungductung 0:e87aa4c49e95 814
phungductung 0:e87aa4c49e95 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
phungductung 0:e87aa4c49e95 816 Counter is in free running mode to generate periodic interrupts.
phungductung 0:e87aa4c49e95 817
phungductung 0:e87aa4c49e95 818 \param [in] ticks Number of ticks between two interrupts.
phungductung 0:e87aa4c49e95 819
phungductung 0:e87aa4c49e95 820 \return 0 Function succeeded.
phungductung 0:e87aa4c49e95 821 \return 1 Function failed.
phungductung 0:e87aa4c49e95 822
phungductung 0:e87aa4c49e95 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
phungductung 0:e87aa4c49e95 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
phungductung 0:e87aa4c49e95 825 must contain a vendor-specific implementation of this function.
phungductung 0:e87aa4c49e95 826
phungductung 0:e87aa4c49e95 827 */
phungductung 0:e87aa4c49e95 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
phungductung 0:e87aa4c49e95 829 {
phungductung 0:e87aa4c49e95 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
phungductung 0:e87aa4c49e95 831
phungductung 0:e87aa4c49e95 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
phungductung 0:e87aa4c49e95 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
phungductung 0:e87aa4c49e95 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
phungductung 0:e87aa4c49e95 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
phungductung 0:e87aa4c49e95 836 SysTick_CTRL_TICKINT_Msk |
phungductung 0:e87aa4c49e95 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
phungductung 0:e87aa4c49e95 838 return (0UL); /* Function successful */
phungductung 0:e87aa4c49e95 839 }
phungductung 0:e87aa4c49e95 840
phungductung 0:e87aa4c49e95 841 #endif
phungductung 0:e87aa4c49e95 842
phungductung 0:e87aa4c49e95 843 /*@} end of CMSIS_Core_SysTickFunctions */
phungductung 0:e87aa4c49e95 844
phungductung 0:e87aa4c49e95 845
phungductung 0:e87aa4c49e95 846
phungductung 0:e87aa4c49e95 847
phungductung 0:e87aa4c49e95 848 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 849 }
phungductung 0:e87aa4c49e95 850 #endif
phungductung 0:e87aa4c49e95 851
phungductung 0:e87aa4c49e95 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
phungductung 0:e87aa4c49e95 853
phungductung 0:e87aa4c49e95 854 #endif /* __CMSIS_GENERIC */