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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

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User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/**
phungductung	0:e87aa4c49e95	2	******************************************************************************
phungductung	0:e87aa4c49e95	3	* @file stm32f7xx_hal_tim.c
phungductung	0:e87aa4c49e95	4	* @author MCD Application Team
phungductung	0:e87aa4c49e95	5	* @version V1.0.4
phungductung	0:e87aa4c49e95	6	* @date 09-December-2015
phungductung	0:e87aa4c49e95	7	* @brief TIM HAL module driver.
phungductung	0:e87aa4c49e95	8	* This file provides firmware functions to manage the following
phungductung	0:e87aa4c49e95	9	* functionalities of the Timer (TIM) peripheral:
phungductung	0:e87aa4c49e95	10	* + Time Base Initialization
phungductung	0:e87aa4c49e95	11	* + Time Base Start
phungductung	0:e87aa4c49e95	12	* + Time Base Start Interruption
phungductung	0:e87aa4c49e95	13	* + Time Base Start DMA
phungductung	0:e87aa4c49e95	14	* + Time Output Compare/PWM Initialization
phungductung	0:e87aa4c49e95	15	* + Time Output Compare/PWM Channel Configuration
phungductung	0:e87aa4c49e95	16	* + Time Output Compare/PWM Start
phungductung	0:e87aa4c49e95	17	* + Time Output Compare/PWM Start Interruption
phungductung	0:e87aa4c49e95	18	* + Time Output Compare/PWM Start DMA
phungductung	0:e87aa4c49e95	19	* + Time Input Capture Initialization
phungductung	0:e87aa4c49e95	20	* + Time Input Capture Channel Configuration
phungductung	0:e87aa4c49e95	21	* + Time Input Capture Start
phungductung	0:e87aa4c49e95	22	* + Time Input Capture Start Interruption
phungductung	0:e87aa4c49e95	23	* + Time Input Capture Start DMA
phungductung	0:e87aa4c49e95	24	* + Time One Pulse Initialization
phungductung	0:e87aa4c49e95	25	* + Time One Pulse Channel Configuration
phungductung	0:e87aa4c49e95	26	* + Time One Pulse Start
phungductung	0:e87aa4c49e95	27	* + Time Encoder Interface Initialization
phungductung	0:e87aa4c49e95	28	* + Time Encoder Interface Start
phungductung	0:e87aa4c49e95	29	* + Time Encoder Interface Start Interruption
phungductung	0:e87aa4c49e95	30	* + Time Encoder Interface Start DMA
phungductung	0:e87aa4c49e95	31	* + Commutation Event configuration with Interruption and DMA
phungductung	0:e87aa4c49e95	32	* + Time OCRef clear configuration
phungductung	0:e87aa4c49e95	33	* + Time External Clock configuration
phungductung	0:e87aa4c49e95	34	@verbatim
phungductung	0:e87aa4c49e95	35	==============================================================================
phungductung	0:e87aa4c49e95	36	##### TIMER Generic features #####
phungductung	0:e87aa4c49e95	37	==============================================================================
phungductung	0:e87aa4c49e95	38	[..] The Timer features include:
phungductung	0:e87aa4c49e95	39	(#) 16-bit up, down, up/down auto-reload counter.
phungductung	0:e87aa4c49e95	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
phungductung	0:e87aa4c49e95	41	counter clock frequency either by any factor between 1 and 65536.
phungductung	0:e87aa4c49e95	42	(#) Up to 4 independent channels for:
phungductung	0:e87aa4c49e95	43	(++) Input Capture
phungductung	0:e87aa4c49e95	44	(++) Output Compare
phungductung	0:e87aa4c49e95	45	(++) PWM generation (Edge and Center-aligned Mode)
phungductung	0:e87aa4c49e95	46	(++) One-pulse mode output
phungductung	0:e87aa4c49e95	47
phungductung	0:e87aa4c49e95	48	##### How to use this driver #####
phungductung	0:e87aa4c49e95	49	==============================================================================
phungductung	0:e87aa4c49e95	50	[..]
phungductung	0:e87aa4c49e95	51	(#) Initialize the TIM low level resources by implementing the following functions
phungductung	0:e87aa4c49e95	52	depending from feature used :
phungductung	0:e87aa4c49e95	53	(++) Time Base : HAL_TIM_Base_MspInit()
phungductung	0:e87aa4c49e95	54	(++) Input Capture : HAL_TIM_IC_MspInit()
phungductung	0:e87aa4c49e95	55	(++) Output Compare : HAL_TIM_OC_MspInit()
phungductung	0:e87aa4c49e95	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
phungductung	0:e87aa4c49e95	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
phungductung	0:e87aa4c49e95	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
phungductung	0:e87aa4c49e95	59
phungductung	0:e87aa4c49e95	60	(#) Initialize the TIM low level resources :
phungductung	0:e87aa4c49e95	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
phungductung	0:e87aa4c49e95	62	(##) TIM pins configuration
phungductung	0:e87aa4c49e95	63	(+++) Enable the clock for the TIM GPIOs using the following function:
phungductung	0:e87aa4c49e95	64	__GPIOx_CLK_ENABLE();
phungductung	0:e87aa4c49e95	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
phungductung	0:e87aa4c49e95	66
phungductung	0:e87aa4c49e95	67	(#) The external Clock can be configured, if needed (the default clock is the
phungductung	0:e87aa4c49e95	68	internal clock from the APBx), using the following function:
phungductung	0:e87aa4c49e95	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
phungductung	0:e87aa4c49e95	70	any start function.
phungductung	0:e87aa4c49e95	71
phungductung	0:e87aa4c49e95	72	(#) Configure the TIM in the desired functioning mode using one of the
phungductung	0:e87aa4c49e95	73	initialization function of this driver:
phungductung	0:e87aa4c49e95	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
phungductung	0:e87aa4c49e95	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
phungductung	0:e87aa4c49e95	76	Output Compare signal.
phungductung	0:e87aa4c49e95	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
phungductung	0:e87aa4c49e95	78	PWM signal.
phungductung	0:e87aa4c49e95	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
phungductung	0:e87aa4c49e95	80	external signal.
phungductung	0:e87aa4c49e95	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
phungductung	0:e87aa4c49e95	82	in One Pulse Mode.
phungductung	0:e87aa4c49e95	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
phungductung	0:e87aa4c49e95	84
phungductung	0:e87aa4c49e95	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
phungductung	0:e87aa4c49e95	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
phungductung	0:e87aa4c49e95	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
phungductung	0:e87aa4c49e95	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
phungductung	0:e87aa4c49e95	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
phungductung	0:e87aa4c49e95	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
phungductung	0:e87aa4c49e95	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
phungductung	0:e87aa4c49e95	92
phungductung	0:e87aa4c49e95	93	(#) The DMA Burst is managed with the two following functions:
phungductung	0:e87aa4c49e95	94	HAL_TIM_DMABurst_WriteStart()
phungductung	0:e87aa4c49e95	95	HAL_TIM_DMABurst_ReadStart()
phungductung	0:e87aa4c49e95	96
phungductung	0:e87aa4c49e95	97	@endverbatim
phungductung	0:e87aa4c49e95	98	******************************************************************************
phungductung	0:e87aa4c49e95	99	* @attention
phungductung	0:e87aa4c49e95	100	*
phungductung	0:e87aa4c49e95	101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung	0:e87aa4c49e95	102	*
phungductung	0:e87aa4c49e95	103	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:e87aa4c49e95	104	* are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	105	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:e87aa4c49e95	106	* this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:e87aa4c49e95	108	* this list of conditions and the following disclaimer in the documentation
phungductung	0:e87aa4c49e95	109	* and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:e87aa4c49e95	111	* may be used to endorse or promote products derived from this software
phungductung	0:e87aa4c49e95	112	* without specific prior written permission.
phungductung	0:e87aa4c49e95	113	*
phungductung	0:e87aa4c49e95	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:e87aa4c49e95	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:e87aa4c49e95	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:e87aa4c49e95	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:e87aa4c49e95	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:e87aa4c49e95	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:e87aa4c49e95	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:e87aa4c49e95	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	124	*
phungductung	0:e87aa4c49e95	125	******************************************************************************
phungductung	0:e87aa4c49e95	126	*/
phungductung	0:e87aa4c49e95	127
phungductung	0:e87aa4c49e95	128	/* Includes ------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	129	#include "stm32f7xx_hal.h"
phungductung	0:e87aa4c49e95	130
phungductung	0:e87aa4c49e95	131	/** @addtogroup STM32F7xx_HAL_Driver
phungductung	0:e87aa4c49e95	132	* @{
phungductung	0:e87aa4c49e95	133	*/
phungductung	0:e87aa4c49e95	134
phungductung	0:e87aa4c49e95	135	/** @defgroup TIM TIM
phungductung	0:e87aa4c49e95	136	* @brief TIM HAL module driver
phungductung	0:e87aa4c49e95	137	* @{
phungductung	0:e87aa4c49e95	138	*/
phungductung	0:e87aa4c49e95	139
phungductung	0:e87aa4c49e95	140	#ifdef HAL_TIM_MODULE_ENABLED
phungductung	0:e87aa4c49e95	141
phungductung	0:e87aa4c49e95	142	/* Private typedef -----------------------------------------------------------*/
phungductung	0:e87aa4c49e95	143	/* Private define ------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	144	/* Private macro -------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	145	/* Private variables ---------------------------------------------------------*/
phungductung	0:e87aa4c49e95	146	/** @addtogroup TIM_Private_Functions
phungductung	0:e87aa4c49e95	147	* @{
phungductung	0:e87aa4c49e95	148	*/
phungductung	0:e87aa4c49e95	149	/* Private function prototypes -----------------------------------------------*/
phungductung	0:e87aa4c49e95	150	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
phungductung	0:e87aa4c49e95	151	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	152	uint32_t TIM_ICFilter);
phungductung	0:e87aa4c49e95	153	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
phungductung	0:e87aa4c49e95	154	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	155	uint32_t TIM_ICFilter);
phungductung	0:e87aa4c49e95	156	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	157	uint32_t TIM_ICFilter);
phungductung	0:e87aa4c49e95	158
phungductung	0:e87aa4c49e95	159	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
phungductung	0:e87aa4c49e95	160	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	161	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	162	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
phungductung	0:e87aa4c49e95	163	TIM_SlaveConfigTypeDef * sSlaveConfig);
phungductung	0:e87aa4c49e95	164	/**
phungductung	0:e87aa4c49e95	165	* @}
phungductung	0:e87aa4c49e95	166	*/
phungductung	0:e87aa4c49e95	167
phungductung	0:e87aa4c49e95	168	/* Exported functions --------------------------------------------------------*/
phungductung	0:e87aa4c49e95	169	/** @defgroup TIM_Exported_Functions TIM Exported Functions
phungductung	0:e87aa4c49e95	170	* @{
phungductung	0:e87aa4c49e95	171	*/
phungductung	0:e87aa4c49e95	172
phungductung	0:e87aa4c49e95	173	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
phungductung	0:e87aa4c49e95	174	* @brief Time Base functions
phungductung	0:e87aa4c49e95	175	*
phungductung	0:e87aa4c49e95	176	@verbatim
phungductung	0:e87aa4c49e95	177	==============================================================================
phungductung	0:e87aa4c49e95	178	##### Time Base functions #####
phungductung	0:e87aa4c49e95	179	==============================================================================
phungductung	0:e87aa4c49e95	180	[..]
phungductung	0:e87aa4c49e95	181	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	182	(+) Initialize and configure the TIM base.
phungductung	0:e87aa4c49e95	183	(+) De-initialize the TIM base.
phungductung	0:e87aa4c49e95	184	(+) Start the Time Base.
phungductung	0:e87aa4c49e95	185	(+) Stop the Time Base.
phungductung	0:e87aa4c49e95	186	(+) Start the Time Base and enable interrupt.
phungductung	0:e87aa4c49e95	187	(+) Stop the Time Base and disable interrupt.
phungductung	0:e87aa4c49e95	188	(+) Start the Time Base and enable DMA transfer.
phungductung	0:e87aa4c49e95	189	(+) Stop the Time Base and disable DMA transfer.
phungductung	0:e87aa4c49e95	190
phungductung	0:e87aa4c49e95	191	@endverbatim
phungductung	0:e87aa4c49e95	192	* @{
phungductung	0:e87aa4c49e95	193	*/
phungductung	0:e87aa4c49e95	194	/**
phungductung	0:e87aa4c49e95	195	* @brief Initializes the TIM Time base Unit according to the specified
phungductung	0:e87aa4c49e95	196	* parameters in the TIM_HandleTypeDef and create the associated handle.
phungductung	0:e87aa4c49e95	197	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	198	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	199	* @retval HAL status
phungductung	0:e87aa4c49e95	200	*/
phungductung	0:e87aa4c49e95	201	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	202	{
phungductung	0:e87aa4c49e95	203	/* Check the TIM handle allocation */
phungductung	0:e87aa4c49e95	204	if(htim == NULL)
phungductung	0:e87aa4c49e95	205	{
phungductung	0:e87aa4c49e95	206	return HAL_ERROR;
phungductung	0:e87aa4c49e95	207	}
phungductung	0:e87aa4c49e95	208
phungductung	0:e87aa4c49e95	209	/* Check the parameters */
phungductung	0:e87aa4c49e95	210	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	211	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
phungductung	0:e87aa4c49e95	212	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
phungductung	0:e87aa4c49e95	213
phungductung	0:e87aa4c49e95	214	if(htim->State == HAL_TIM_STATE_RESET)
phungductung	0:e87aa4c49e95	215	{
phungductung	0:e87aa4c49e95	216	/* Init the low level hardware : GPIO, CLOCK, NVIC */
phungductung	0:e87aa4c49e95	217	HAL_TIM_Base_MspInit(htim);
phungductung	0:e87aa4c49e95	218	}
phungductung	0:e87aa4c49e95	219
phungductung	0:e87aa4c49e95	220	/* Set the TIM state */
phungductung	0:e87aa4c49e95	221	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	222
phungductung	0:e87aa4c49e95	223	/* Set the Time Base configuration */
phungductung	0:e87aa4c49e95	224	TIM_Base_SetConfig(htim->Instance, &htim->Init);
phungductung	0:e87aa4c49e95	225
phungductung	0:e87aa4c49e95	226	/* Initialize the TIM state*/
phungductung	0:e87aa4c49e95	227	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	228
phungductung	0:e87aa4c49e95	229	return HAL_OK;
phungductung	0:e87aa4c49e95	230	}
phungductung	0:e87aa4c49e95	231
phungductung	0:e87aa4c49e95	232	/**
phungductung	0:e87aa4c49e95	233	* @brief DeInitializes the TIM Base peripheral
phungductung	0:e87aa4c49e95	234	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	235	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	236	* @retval HAL status
phungductung	0:e87aa4c49e95	237	*/
phungductung	0:e87aa4c49e95	238	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	239	{
phungductung	0:e87aa4c49e95	240	/* Check the parameters */
phungductung	0:e87aa4c49e95	241	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	242
phungductung	0:e87aa4c49e95	243	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	244
phungductung	0:e87aa4c49e95	245	/* Disable the TIM Peripheral Clock */
phungductung	0:e87aa4c49e95	246	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	247
phungductung	0:e87aa4c49e95	248	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
phungductung	0:e87aa4c49e95	249	HAL_TIM_Base_MspDeInit(htim);
phungductung	0:e87aa4c49e95	250
phungductung	0:e87aa4c49e95	251	/* Change TIM state */
phungductung	0:e87aa4c49e95	252	htim->State = HAL_TIM_STATE_RESET;
phungductung	0:e87aa4c49e95	253
phungductung	0:e87aa4c49e95	254	/* Release Lock */
phungductung	0:e87aa4c49e95	255	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	256
phungductung	0:e87aa4c49e95	257	return HAL_OK;
phungductung	0:e87aa4c49e95	258	}
phungductung	0:e87aa4c49e95	259
phungductung	0:e87aa4c49e95	260	/**
phungductung	0:e87aa4c49e95	261	* @brief Initializes the TIM Base MSP.
phungductung	0:e87aa4c49e95	262	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	263	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	264	* @retval None
phungductung	0:e87aa4c49e95	265	*/
phungductung	0:e87aa4c49e95	266	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	267	{
phungductung	0:e87aa4c49e95	268	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	269	UNUSED(htim);
phungductung	0:e87aa4c49e95	270
phungductung	0:e87aa4c49e95	271	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	272	the HAL_TIM_Base_MspInit could be implemented in the user file
phungductung	0:e87aa4c49e95	273	*/
phungductung	0:e87aa4c49e95	274	}
phungductung	0:e87aa4c49e95	275
phungductung	0:e87aa4c49e95	276	/**
phungductung	0:e87aa4c49e95	277	* @brief DeInitializes TIM Base MSP.
phungductung	0:e87aa4c49e95	278	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	279	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	280	* @retval None
phungductung	0:e87aa4c49e95	281	*/
phungductung	0:e87aa4c49e95	282	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	283	{
phungductung	0:e87aa4c49e95	284	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	285	UNUSED(htim);
phungductung	0:e87aa4c49e95	286
phungductung	0:e87aa4c49e95	287	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	288	the HAL_TIM_Base_MspDeInit could be implemented in the user file
phungductung	0:e87aa4c49e95	289	*/
phungductung	0:e87aa4c49e95	290	}
phungductung	0:e87aa4c49e95	291
phungductung	0:e87aa4c49e95	292	/**
phungductung	0:e87aa4c49e95	293	* @brief Starts the TIM Base generation.
phungductung	0:e87aa4c49e95	294	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	295	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	296	* @retval HAL status
phungductung	0:e87aa4c49e95	297	*/
phungductung	0:e87aa4c49e95	298	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	299	{
phungductung	0:e87aa4c49e95	300	/* Check the parameters */
phungductung	0:e87aa4c49e95	301	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	302
phungductung	0:e87aa4c49e95	303	/* Set the TIM state */
phungductung	0:e87aa4c49e95	304	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	305
phungductung	0:e87aa4c49e95	306	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	307	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	308
phungductung	0:e87aa4c49e95	309	/* Change the TIM state*/
phungductung	0:e87aa4c49e95	310	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	311
phungductung	0:e87aa4c49e95	312	/* Return function status */
phungductung	0:e87aa4c49e95	313	return HAL_OK;
phungductung	0:e87aa4c49e95	314	}
phungductung	0:e87aa4c49e95	315
phungductung	0:e87aa4c49e95	316	/**
phungductung	0:e87aa4c49e95	317	* @brief Stops the TIM Base generation.
phungductung	0:e87aa4c49e95	318	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	319	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	320	* @retval HAL status
phungductung	0:e87aa4c49e95	321	*/
phungductung	0:e87aa4c49e95	322	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	323	{
phungductung	0:e87aa4c49e95	324	/* Check the parameters */
phungductung	0:e87aa4c49e95	325	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	326
phungductung	0:e87aa4c49e95	327	/* Set the TIM state */
phungductung	0:e87aa4c49e95	328	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	329
phungductung	0:e87aa4c49e95	330	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	331	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	332
phungductung	0:e87aa4c49e95	333	/* Change the TIM state*/
phungductung	0:e87aa4c49e95	334	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	335
phungductung	0:e87aa4c49e95	336	/* Return function status */
phungductung	0:e87aa4c49e95	337	return HAL_OK;
phungductung	0:e87aa4c49e95	338	}
phungductung	0:e87aa4c49e95	339
phungductung	0:e87aa4c49e95	340	/**
phungductung	0:e87aa4c49e95	341	* @brief Starts the TIM Base generation in interrupt mode.
phungductung	0:e87aa4c49e95	342	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	343	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	344	* @retval HAL status
phungductung	0:e87aa4c49e95	345	*/
phungductung	0:e87aa4c49e95	346	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	347	{
phungductung	0:e87aa4c49e95	348	/* Check the parameters */
phungductung	0:e87aa4c49e95	349	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	350
phungductung	0:e87aa4c49e95	351	/* Enable the TIM Update interrupt */
phungductung	0:e87aa4c49e95	352	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
phungductung	0:e87aa4c49e95	353
phungductung	0:e87aa4c49e95	354	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	355	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	356
phungductung	0:e87aa4c49e95	357	/* Return function status */
phungductung	0:e87aa4c49e95	358	return HAL_OK;
phungductung	0:e87aa4c49e95	359	}
phungductung	0:e87aa4c49e95	360
phungductung	0:e87aa4c49e95	361	/**
phungductung	0:e87aa4c49e95	362	* @brief Stops the TIM Base generation in interrupt mode.
phungductung	0:e87aa4c49e95	363	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	364	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	365	* @retval HAL status
phungductung	0:e87aa4c49e95	366	*/
phungductung	0:e87aa4c49e95	367	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	368	{
phungductung	0:e87aa4c49e95	369	/* Check the parameters */
phungductung	0:e87aa4c49e95	370	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	371	/* Disable the TIM Update interrupt */
phungductung	0:e87aa4c49e95	372	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
phungductung	0:e87aa4c49e95	373
phungductung	0:e87aa4c49e95	374	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	375	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	376
phungductung	0:e87aa4c49e95	377	/* Return function status */
phungductung	0:e87aa4c49e95	378	return HAL_OK;
phungductung	0:e87aa4c49e95	379	}
phungductung	0:e87aa4c49e95	380
phungductung	0:e87aa4c49e95	381	/**
phungductung	0:e87aa4c49e95	382	* @brief Starts the TIM Base generation in DMA mode.
phungductung	0:e87aa4c49e95	383	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	384	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	385	* @param pData: The source Buffer address.
phungductung	0:e87aa4c49e95	386	* @param Length: The length of data to be transferred from memory to peripheral.
phungductung	0:e87aa4c49e95	387	* @retval HAL status
phungductung	0:e87aa4c49e95	388	*/
phungductung	0:e87aa4c49e95	389	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
phungductung	0:e87aa4c49e95	390	{
phungductung	0:e87aa4c49e95	391	/* Check the parameters */
phungductung	0:e87aa4c49e95	392	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	393
phungductung	0:e87aa4c49e95	394	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	395	{
phungductung	0:e87aa4c49e95	396	return HAL_BUSY;
phungductung	0:e87aa4c49e95	397	}
phungductung	0:e87aa4c49e95	398	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	399	{
phungductung	0:e87aa4c49e95	400	if((pData == 0 ) && (Length > 0))
phungductung	0:e87aa4c49e95	401	{
phungductung	0:e87aa4c49e95	402	return HAL_ERROR;
phungductung	0:e87aa4c49e95	403	}
phungductung	0:e87aa4c49e95	404	else
phungductung	0:e87aa4c49e95	405	{
phungductung	0:e87aa4c49e95	406	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	407	}
phungductung	0:e87aa4c49e95	408	}
phungductung	0:e87aa4c49e95	409	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	410	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
phungductung	0:e87aa4c49e95	411
phungductung	0:e87aa4c49e95	412	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	413	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	414
phungductung	0:e87aa4c49e95	415	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	416	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
phungductung	0:e87aa4c49e95	417
phungductung	0:e87aa4c49e95	418	/* Enable the TIM Update DMA request */
phungductung	0:e87aa4c49e95	419	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
phungductung	0:e87aa4c49e95	420
phungductung	0:e87aa4c49e95	421	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	422	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	423
phungductung	0:e87aa4c49e95	424	/* Return function status */
phungductung	0:e87aa4c49e95	425	return HAL_OK;
phungductung	0:e87aa4c49e95	426	}
phungductung	0:e87aa4c49e95	427
phungductung	0:e87aa4c49e95	428	/**
phungductung	0:e87aa4c49e95	429	* @brief Stops the TIM Base generation in DMA mode.
phungductung	0:e87aa4c49e95	430	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	431	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	432	* @retval HAL status
phungductung	0:e87aa4c49e95	433	*/
phungductung	0:e87aa4c49e95	434	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	435	{
phungductung	0:e87aa4c49e95	436	/* Check the parameters */
phungductung	0:e87aa4c49e95	437	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	438
phungductung	0:e87aa4c49e95	439	/* Disable the TIM Update DMA request */
phungductung	0:e87aa4c49e95	440	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
phungductung	0:e87aa4c49e95	441
phungductung	0:e87aa4c49e95	442	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	443	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	444
phungductung	0:e87aa4c49e95	445	/* Change the htim state */
phungductung	0:e87aa4c49e95	446	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	447
phungductung	0:e87aa4c49e95	448	/* Return function status */
phungductung	0:e87aa4c49e95	449	return HAL_OK;
phungductung	0:e87aa4c49e95	450	}
phungductung	0:e87aa4c49e95	451
phungductung	0:e87aa4c49e95	452	/**
phungductung	0:e87aa4c49e95	453	* @}
phungductung	0:e87aa4c49e95	454	*/
phungductung	0:e87aa4c49e95	455
phungductung	0:e87aa4c49e95	456	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
phungductung	0:e87aa4c49e95	457	* @brief Time Output Compare functions
phungductung	0:e87aa4c49e95	458	*
phungductung	0:e87aa4c49e95	459	@verbatim
phungductung	0:e87aa4c49e95	460	==============================================================================
phungductung	0:e87aa4c49e95	461	##### Time Output Compare functions #####
phungductung	0:e87aa4c49e95	462	==============================================================================
phungductung	0:e87aa4c49e95	463	[..]
phungductung	0:e87aa4c49e95	464	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	465	(+) Initialize and configure the TIM Output Compare.
phungductung	0:e87aa4c49e95	466	(+) De-initialize the TIM Output Compare.
phungductung	0:e87aa4c49e95	467	(+) Start the Time Output Compare.
phungductung	0:e87aa4c49e95	468	(+) Stop the Time Output Compare.
phungductung	0:e87aa4c49e95	469	(+) Start the Time Output Compare and enable interrupt.
phungductung	0:e87aa4c49e95	470	(+) Stop the Time Output Compare and disable interrupt.
phungductung	0:e87aa4c49e95	471	(+) Start the Time Output Compare and enable DMA transfer.
phungductung	0:e87aa4c49e95	472	(+) Stop the Time Output Compare and disable DMA transfer.
phungductung	0:e87aa4c49e95	473
phungductung	0:e87aa4c49e95	474	@endverbatim
phungductung	0:e87aa4c49e95	475	* @{
phungductung	0:e87aa4c49e95	476	*/
phungductung	0:e87aa4c49e95	477	/**
phungductung	0:e87aa4c49e95	478	* @brief Initializes the TIM Output Compare according to the specified
phungductung	0:e87aa4c49e95	479	* parameters in the TIM_HandleTypeDef and create the associated handle.
phungductung	0:e87aa4c49e95	480	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	481	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	482	* @retval HAL status
phungductung	0:e87aa4c49e95	483	*/
phungductung	0:e87aa4c49e95	484	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
phungductung	0:e87aa4c49e95	485	{
phungductung	0:e87aa4c49e95	486	/* Check the TIM handle allocation */
phungductung	0:e87aa4c49e95	487	if(htim == NULL)
phungductung	0:e87aa4c49e95	488	{
phungductung	0:e87aa4c49e95	489	return HAL_ERROR;
phungductung	0:e87aa4c49e95	490	}
phungductung	0:e87aa4c49e95	491
phungductung	0:e87aa4c49e95	492	/* Check the parameters */
phungductung	0:e87aa4c49e95	493	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	494	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
phungductung	0:e87aa4c49e95	495	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
phungductung	0:e87aa4c49e95	496
phungductung	0:e87aa4c49e95	497	if(htim->State == HAL_TIM_STATE_RESET)
phungductung	0:e87aa4c49e95	498	{
phungductung	0:e87aa4c49e95	499	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	500	htim->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	501	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	502	HAL_TIM_OC_MspInit(htim);
phungductung	0:e87aa4c49e95	503	}
phungductung	0:e87aa4c49e95	504
phungductung	0:e87aa4c49e95	505	/* Set the TIM state */
phungductung	0:e87aa4c49e95	506	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	507
phungductung	0:e87aa4c49e95	508	/* Init the base time for the Output Compare */
phungductung	0:e87aa4c49e95	509	TIM_Base_SetConfig(htim->Instance, &htim->Init);
phungductung	0:e87aa4c49e95	510
phungductung	0:e87aa4c49e95	511	/* Initialize the TIM state*/
phungductung	0:e87aa4c49e95	512	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	513
phungductung	0:e87aa4c49e95	514	return HAL_OK;
phungductung	0:e87aa4c49e95	515	}
phungductung	0:e87aa4c49e95	516
phungductung	0:e87aa4c49e95	517	/**
phungductung	0:e87aa4c49e95	518	* @brief DeInitializes the TIM peripheral
phungductung	0:e87aa4c49e95	519	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	520	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	521	* @retval HAL status
phungductung	0:e87aa4c49e95	522	*/
phungductung	0:e87aa4c49e95	523	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	524	{
phungductung	0:e87aa4c49e95	525	/* Check the parameters */
phungductung	0:e87aa4c49e95	526	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	527
phungductung	0:e87aa4c49e95	528	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	529
phungductung	0:e87aa4c49e95	530	/* Disable the TIM Peripheral Clock */
phungductung	0:e87aa4c49e95	531	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	532
phungductung	0:e87aa4c49e95	533	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	534	HAL_TIM_OC_MspDeInit(htim);
phungductung	0:e87aa4c49e95	535
phungductung	0:e87aa4c49e95	536	/* Change TIM state */
phungductung	0:e87aa4c49e95	537	htim->State = HAL_TIM_STATE_RESET;
phungductung	0:e87aa4c49e95	538
phungductung	0:e87aa4c49e95	539	/* Release Lock */
phungductung	0:e87aa4c49e95	540	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	541
phungductung	0:e87aa4c49e95	542	return HAL_OK;
phungductung	0:e87aa4c49e95	543	}
phungductung	0:e87aa4c49e95	544
phungductung	0:e87aa4c49e95	545	/**
phungductung	0:e87aa4c49e95	546	* @brief Initializes the TIM Output Compare MSP.
phungductung	0:e87aa4c49e95	547	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	548	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	549	* @retval None
phungductung	0:e87aa4c49e95	550	*/
phungductung	0:e87aa4c49e95	551	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	552	{
phungductung	0:e87aa4c49e95	553	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	554	UNUSED(htim);
phungductung	0:e87aa4c49e95	555
phungductung	0:e87aa4c49e95	556	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	557	the HAL_TIM_OC_MspInit could be implemented in the user file
phungductung	0:e87aa4c49e95	558	*/
phungductung	0:e87aa4c49e95	559	}
phungductung	0:e87aa4c49e95	560
phungductung	0:e87aa4c49e95	561	/**
phungductung	0:e87aa4c49e95	562	* @brief DeInitializes TIM Output Compare MSP.
phungductung	0:e87aa4c49e95	563	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	564	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	565	* @retval None
phungductung	0:e87aa4c49e95	566	*/
phungductung	0:e87aa4c49e95	567	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	568	{
phungductung	0:e87aa4c49e95	569	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	570	UNUSED(htim);
phungductung	0:e87aa4c49e95	571
phungductung	0:e87aa4c49e95	572	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	573	the HAL_TIM_OC_MspDeInit could be implemented in the user file
phungductung	0:e87aa4c49e95	574	*/
phungductung	0:e87aa4c49e95	575	}
phungductung	0:e87aa4c49e95	576
phungductung	0:e87aa4c49e95	577	/**
phungductung	0:e87aa4c49e95	578	* @brief Starts the TIM Output Compare signal generation.
phungductung	0:e87aa4c49e95	579	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	580	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	581	* @param Channel: TIM Channel to be enabled.
phungductung	0:e87aa4c49e95	582	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	583	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	584	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	585	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	586	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	587	* @retval HAL status
phungductung	0:e87aa4c49e95	588	*/
phungductung	0:e87aa4c49e95	589	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	590	{
phungductung	0:e87aa4c49e95	591	/* Check the parameters */
phungductung	0:e87aa4c49e95	592	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	593
phungductung	0:e87aa4c49e95	594	/* Enable the Output compare channel */
phungductung	0:e87aa4c49e95	595	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	596
phungductung	0:e87aa4c49e95	597	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	598	{
phungductung	0:e87aa4c49e95	599	/* Enable the main output */
phungductung	0:e87aa4c49e95	600	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	601	}
phungductung	0:e87aa4c49e95	602
phungductung	0:e87aa4c49e95	603	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	604	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	605
phungductung	0:e87aa4c49e95	606	/* Return function status */
phungductung	0:e87aa4c49e95	607	return HAL_OK;
phungductung	0:e87aa4c49e95	608	}
phungductung	0:e87aa4c49e95	609
phungductung	0:e87aa4c49e95	610	/**
phungductung	0:e87aa4c49e95	611	* @brief Stops the TIM Output Compare signal generation.
phungductung	0:e87aa4c49e95	612	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	613	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	614	* @param Channel: TIM Channel to be disabled.
phungductung	0:e87aa4c49e95	615	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	616	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	617	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	618	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	619	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	620	* @retval HAL status
phungductung	0:e87aa4c49e95	621	*/
phungductung	0:e87aa4c49e95	622	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	623	{
phungductung	0:e87aa4c49e95	624	/* Check the parameters */
phungductung	0:e87aa4c49e95	625	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	626
phungductung	0:e87aa4c49e95	627	/* Disable the Output compare channel */
phungductung	0:e87aa4c49e95	628	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	629
phungductung	0:e87aa4c49e95	630	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	631	{
phungductung	0:e87aa4c49e95	632	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	633	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	634	}
phungductung	0:e87aa4c49e95	635
phungductung	0:e87aa4c49e95	636	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	637	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	638
phungductung	0:e87aa4c49e95	639	/* Return function status */
phungductung	0:e87aa4c49e95	640	return HAL_OK;
phungductung	0:e87aa4c49e95	641	}
phungductung	0:e87aa4c49e95	642
phungductung	0:e87aa4c49e95	643	/**
phungductung	0:e87aa4c49e95	644	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
phungductung	0:e87aa4c49e95	645	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	646	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	647	* @param Channel: TIM Channel to be enabled.
phungductung	0:e87aa4c49e95	648	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	649	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	650	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	651	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	652	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	653	* @retval HAL status
phungductung	0:e87aa4c49e95	654	*/
phungductung	0:e87aa4c49e95	655	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	656	{
phungductung	0:e87aa4c49e95	657	/* Check the parameters */
phungductung	0:e87aa4c49e95	658	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	659
phungductung	0:e87aa4c49e95	660	switch (Channel)
phungductung	0:e87aa4c49e95	661	{
phungductung	0:e87aa4c49e95	662	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	663	{
phungductung	0:e87aa4c49e95	664	/* Enable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	665	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	666	}
phungductung	0:e87aa4c49e95	667	break;
phungductung	0:e87aa4c49e95	668
phungductung	0:e87aa4c49e95	669	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	670	{
phungductung	0:e87aa4c49e95	671	/* Enable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	672	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	673	}
phungductung	0:e87aa4c49e95	674	break;
phungductung	0:e87aa4c49e95	675
phungductung	0:e87aa4c49e95	676	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	677	{
phungductung	0:e87aa4c49e95	678	/* Enable the TIM Capture/Compare 3 interrupt */
phungductung	0:e87aa4c49e95	679	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	680	}
phungductung	0:e87aa4c49e95	681	break;
phungductung	0:e87aa4c49e95	682
phungductung	0:e87aa4c49e95	683	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	684	{
phungductung	0:e87aa4c49e95	685	/* Enable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	686	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	687	}
phungductung	0:e87aa4c49e95	688	break;
phungductung	0:e87aa4c49e95	689
phungductung	0:e87aa4c49e95	690	default:
phungductung	0:e87aa4c49e95	691	break;
phungductung	0:e87aa4c49e95	692	}
phungductung	0:e87aa4c49e95	693
phungductung	0:e87aa4c49e95	694	/* Enable the Output compare channel */
phungductung	0:e87aa4c49e95	695	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	696
phungductung	0:e87aa4c49e95	697	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	698	{
phungductung	0:e87aa4c49e95	699	/* Enable the main output */
phungductung	0:e87aa4c49e95	700	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	701	}
phungductung	0:e87aa4c49e95	702
phungductung	0:e87aa4c49e95	703	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	704	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	705
phungductung	0:e87aa4c49e95	706	/* Return function status */
phungductung	0:e87aa4c49e95	707	return HAL_OK;
phungductung	0:e87aa4c49e95	708	}
phungductung	0:e87aa4c49e95	709
phungductung	0:e87aa4c49e95	710	/**
phungductung	0:e87aa4c49e95	711	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
phungductung	0:e87aa4c49e95	712	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	713	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	714	* @param Channel: TIM Channel to be disabled.
phungductung	0:e87aa4c49e95	715	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	716	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	717	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	718	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	719	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	720	* @retval HAL status
phungductung	0:e87aa4c49e95	721	*/
phungductung	0:e87aa4c49e95	722	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	723	{
phungductung	0:e87aa4c49e95	724	/* Check the parameters */
phungductung	0:e87aa4c49e95	725	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	726
phungductung	0:e87aa4c49e95	727	switch (Channel)
phungductung	0:e87aa4c49e95	728	{
phungductung	0:e87aa4c49e95	729	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	730	{
phungductung	0:e87aa4c49e95	731	/* Disable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	732	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	733	}
phungductung	0:e87aa4c49e95	734	break;
phungductung	0:e87aa4c49e95	735
phungductung	0:e87aa4c49e95	736	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	737	{
phungductung	0:e87aa4c49e95	738	/* Disable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	739	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	740	}
phungductung	0:e87aa4c49e95	741	break;
phungductung	0:e87aa4c49e95	742
phungductung	0:e87aa4c49e95	743	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	744	{
phungductung	0:e87aa4c49e95	745	/* Disable the TIM Capture/Compare 3 interrupt */
phungductung	0:e87aa4c49e95	746	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	747	}
phungductung	0:e87aa4c49e95	748	break;
phungductung	0:e87aa4c49e95	749
phungductung	0:e87aa4c49e95	750	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	751	{
phungductung	0:e87aa4c49e95	752	/* Disable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	753	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	754	}
phungductung	0:e87aa4c49e95	755	break;
phungductung	0:e87aa4c49e95	756
phungductung	0:e87aa4c49e95	757	default:
phungductung	0:e87aa4c49e95	758	break;
phungductung	0:e87aa4c49e95	759	}
phungductung	0:e87aa4c49e95	760
phungductung	0:e87aa4c49e95	761	/* Disable the Output compare channel */
phungductung	0:e87aa4c49e95	762	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	763
phungductung	0:e87aa4c49e95	764	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	765	{
phungductung	0:e87aa4c49e95	766	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	767	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	768	}
phungductung	0:e87aa4c49e95	769
phungductung	0:e87aa4c49e95	770	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	771	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	772
phungductung	0:e87aa4c49e95	773	/* Return function status */
phungductung	0:e87aa4c49e95	774	return HAL_OK;
phungductung	0:e87aa4c49e95	775	}
phungductung	0:e87aa4c49e95	776
phungductung	0:e87aa4c49e95	777	/**
phungductung	0:e87aa4c49e95	778	* @brief Starts the TIM Output Compare signal generation in DMA mode.
phungductung	0:e87aa4c49e95	779	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	780	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	781	* @param Channel: TIM Channel to be enabled.
phungductung	0:e87aa4c49e95	782	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	783	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	784	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	785	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	786	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	787	* @param pData: The source Buffer address.
phungductung	0:e87aa4c49e95	788	* @param Length: The length of data to be transferred from memory to TIM peripheral
phungductung	0:e87aa4c49e95	789	* @retval HAL status
phungductung	0:e87aa4c49e95	790	*/
phungductung	0:e87aa4c49e95	791	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
phungductung	0:e87aa4c49e95	792	{
phungductung	0:e87aa4c49e95	793	/* Check the parameters */
phungductung	0:e87aa4c49e95	794	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	795
phungductung	0:e87aa4c49e95	796	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	797	{
phungductung	0:e87aa4c49e95	798	return HAL_BUSY;
phungductung	0:e87aa4c49e95	799	}
phungductung	0:e87aa4c49e95	800	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	801	{
phungductung	0:e87aa4c49e95	802	if(((uint32_t)pData == 0 ) && (Length > 0))
phungductung	0:e87aa4c49e95	803	{
phungductung	0:e87aa4c49e95	804	return HAL_ERROR;
phungductung	0:e87aa4c49e95	805	}
phungductung	0:e87aa4c49e95	806	else
phungductung	0:e87aa4c49e95	807	{
phungductung	0:e87aa4c49e95	808	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	809	}
phungductung	0:e87aa4c49e95	810	}
phungductung	0:e87aa4c49e95	811	switch (Channel)
phungductung	0:e87aa4c49e95	812	{
phungductung	0:e87aa4c49e95	813	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	814	{
phungductung	0:e87aa4c49e95	815	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	816	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	817
phungductung	0:e87aa4c49e95	818	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	819	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	820
phungductung	0:e87aa4c49e95	821	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	822	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
phungductung	0:e87aa4c49e95	823
phungductung	0:e87aa4c49e95	824	/* Enable the TIM Capture/Compare 1 DMA request */
phungductung	0:e87aa4c49e95	825	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	826	}
phungductung	0:e87aa4c49e95	827	break;
phungductung	0:e87aa4c49e95	828
phungductung	0:e87aa4c49e95	829	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	830	{
phungductung	0:e87aa4c49e95	831	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	832	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	833
phungductung	0:e87aa4c49e95	834	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	835	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	836
phungductung	0:e87aa4c49e95	837	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	838	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
phungductung	0:e87aa4c49e95	839
phungductung	0:e87aa4c49e95	840	/* Enable the TIM Capture/Compare 2 DMA request */
phungductung	0:e87aa4c49e95	841	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	842	}
phungductung	0:e87aa4c49e95	843	break;
phungductung	0:e87aa4c49e95	844
phungductung	0:e87aa4c49e95	845	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	846	{
phungductung	0:e87aa4c49e95	847	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	848	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	849
phungductung	0:e87aa4c49e95	850	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	851	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	852
phungductung	0:e87aa4c49e95	853	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	854	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
phungductung	0:e87aa4c49e95	855
phungductung	0:e87aa4c49e95	856	/* Enable the TIM Capture/Compare 3 DMA request */
phungductung	0:e87aa4c49e95	857	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
phungductung	0:e87aa4c49e95	858	}
phungductung	0:e87aa4c49e95	859	break;
phungductung	0:e87aa4c49e95	860
phungductung	0:e87aa4c49e95	861	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	862	{
phungductung	0:e87aa4c49e95	863	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	864	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	865
phungductung	0:e87aa4c49e95	866	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	867	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	868
phungductung	0:e87aa4c49e95	869	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	870	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
phungductung	0:e87aa4c49e95	871
phungductung	0:e87aa4c49e95	872	/* Enable the TIM Capture/Compare 4 DMA request */
phungductung	0:e87aa4c49e95	873	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
phungductung	0:e87aa4c49e95	874	}
phungductung	0:e87aa4c49e95	875	break;
phungductung	0:e87aa4c49e95	876
phungductung	0:e87aa4c49e95	877	default:
phungductung	0:e87aa4c49e95	878	break;
phungductung	0:e87aa4c49e95	879	}
phungductung	0:e87aa4c49e95	880
phungductung	0:e87aa4c49e95	881	/* Enable the Output compare channel */
phungductung	0:e87aa4c49e95	882	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	883
phungductung	0:e87aa4c49e95	884	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	885	{
phungductung	0:e87aa4c49e95	886	/* Enable the main output */
phungductung	0:e87aa4c49e95	887	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	888	}
phungductung	0:e87aa4c49e95	889
phungductung	0:e87aa4c49e95	890	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	891	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	892
phungductung	0:e87aa4c49e95	893	/* Return function status */
phungductung	0:e87aa4c49e95	894	return HAL_OK;
phungductung	0:e87aa4c49e95	895	}
phungductung	0:e87aa4c49e95	896
phungductung	0:e87aa4c49e95	897	/**
phungductung	0:e87aa4c49e95	898	* @brief Stops the TIM Output Compare signal generation in DMA mode.
phungductung	0:e87aa4c49e95	899	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	900	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	901	* @param Channel: TIM Channel to be disabled.
phungductung	0:e87aa4c49e95	902	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	903	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	904	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	905	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	906	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	907	* @retval HAL status
phungductung	0:e87aa4c49e95	908	*/
phungductung	0:e87aa4c49e95	909	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	910	{
phungductung	0:e87aa4c49e95	911	/* Check the parameters */
phungductung	0:e87aa4c49e95	912	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	913
phungductung	0:e87aa4c49e95	914	switch (Channel)
phungductung	0:e87aa4c49e95	915	{
phungductung	0:e87aa4c49e95	916	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	917	{
phungductung	0:e87aa4c49e95	918	/* Disable the TIM Capture/Compare 1 DMA request */
phungductung	0:e87aa4c49e95	919	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	920	}
phungductung	0:e87aa4c49e95	921	break;
phungductung	0:e87aa4c49e95	922
phungductung	0:e87aa4c49e95	923	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	924	{
phungductung	0:e87aa4c49e95	925	/* Disable the TIM Capture/Compare 2 DMA request */
phungductung	0:e87aa4c49e95	926	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	927	}
phungductung	0:e87aa4c49e95	928	break;
phungductung	0:e87aa4c49e95	929
phungductung	0:e87aa4c49e95	930	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	931	{
phungductung	0:e87aa4c49e95	932	/* Disable the TIM Capture/Compare 3 DMA request */
phungductung	0:e87aa4c49e95	933	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
phungductung	0:e87aa4c49e95	934	}
phungductung	0:e87aa4c49e95	935	break;
phungductung	0:e87aa4c49e95	936
phungductung	0:e87aa4c49e95	937	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	938	{
phungductung	0:e87aa4c49e95	939	/* Disable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	940	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
phungductung	0:e87aa4c49e95	941	}
phungductung	0:e87aa4c49e95	942	break;
phungductung	0:e87aa4c49e95	943
phungductung	0:e87aa4c49e95	944	default:
phungductung	0:e87aa4c49e95	945	break;
phungductung	0:e87aa4c49e95	946	}
phungductung	0:e87aa4c49e95	947
phungductung	0:e87aa4c49e95	948	/* Disable the Output compare channel */
phungductung	0:e87aa4c49e95	949	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	950
phungductung	0:e87aa4c49e95	951	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	952	{
phungductung	0:e87aa4c49e95	953	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	954	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	955	}
phungductung	0:e87aa4c49e95	956
phungductung	0:e87aa4c49e95	957	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	958	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	959
phungductung	0:e87aa4c49e95	960	/* Change the htim state */
phungductung	0:e87aa4c49e95	961	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	962
phungductung	0:e87aa4c49e95	963	/* Return function status */
phungductung	0:e87aa4c49e95	964	return HAL_OK;
phungductung	0:e87aa4c49e95	965	}
phungductung	0:e87aa4c49e95	966
phungductung	0:e87aa4c49e95	967	/**
phungductung	0:e87aa4c49e95	968	* @}
phungductung	0:e87aa4c49e95	969	*/
phungductung	0:e87aa4c49e95	970
phungductung	0:e87aa4c49e95	971	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
phungductung	0:e87aa4c49e95	972	* @brief Time PWM functions
phungductung	0:e87aa4c49e95	973	*
phungductung	0:e87aa4c49e95	974	@verbatim
phungductung	0:e87aa4c49e95	975	==============================================================================
phungductung	0:e87aa4c49e95	976	##### Time PWM functions #####
phungductung	0:e87aa4c49e95	977	==============================================================================
phungductung	0:e87aa4c49e95	978	[..]
phungductung	0:e87aa4c49e95	979	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	980	(+) Initialize and configure the TIM OPWM.
phungductung	0:e87aa4c49e95	981	(+) De-initialize the TIM PWM.
phungductung	0:e87aa4c49e95	982	(+) Start the Time PWM.
phungductung	0:e87aa4c49e95	983	(+) Stop the Time PWM.
phungductung	0:e87aa4c49e95	984	(+) Start the Time PWM and enable interrupt.
phungductung	0:e87aa4c49e95	985	(+) Stop the Time PWM and disable interrupt.
phungductung	0:e87aa4c49e95	986	(+) Start the Time PWM and enable DMA transfer.
phungductung	0:e87aa4c49e95	987	(+) Stop the Time PWM and disable DMA transfer.
phungductung	0:e87aa4c49e95	988
phungductung	0:e87aa4c49e95	989	@endverbatim
phungductung	0:e87aa4c49e95	990	* @{
phungductung	0:e87aa4c49e95	991	*/
phungductung	0:e87aa4c49e95	992	/**
phungductung	0:e87aa4c49e95	993	* @brief Initializes the TIM PWM Time Base according to the specified
phungductung	0:e87aa4c49e95	994	* parameters in the TIM_HandleTypeDef and create the associated handle.
phungductung	0:e87aa4c49e95	995	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	996	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	997	* @retval HAL status
phungductung	0:e87aa4c49e95	998	*/
phungductung	0:e87aa4c49e95	999	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1000	{
phungductung	0:e87aa4c49e95	1001	/* Check the TIM handle allocation */
phungductung	0:e87aa4c49e95	1002	if(htim == NULL)
phungductung	0:e87aa4c49e95	1003	{
phungductung	0:e87aa4c49e95	1004	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1005	}
phungductung	0:e87aa4c49e95	1006
phungductung	0:e87aa4c49e95	1007	/* Check the parameters */
phungductung	0:e87aa4c49e95	1008	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	1009	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
phungductung	0:e87aa4c49e95	1010	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
phungductung	0:e87aa4c49e95	1011
phungductung	0:e87aa4c49e95	1012	if(htim->State == HAL_TIM_STATE_RESET)
phungductung	0:e87aa4c49e95	1013	{
phungductung	0:e87aa4c49e95	1014	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	1015	htim->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	1016	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	1017	HAL_TIM_PWM_MspInit(htim);
phungductung	0:e87aa4c49e95	1018	}
phungductung	0:e87aa4c49e95	1019
phungductung	0:e87aa4c49e95	1020	/* Set the TIM state */
phungductung	0:e87aa4c49e95	1021	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	1022
phungductung	0:e87aa4c49e95	1023	/* Init the base time for the PWM */
phungductung	0:e87aa4c49e95	1024	TIM_Base_SetConfig(htim->Instance, &htim->Init);
phungductung	0:e87aa4c49e95	1025
phungductung	0:e87aa4c49e95	1026	/* Initialize the TIM state*/
phungductung	0:e87aa4c49e95	1027	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	1028
phungductung	0:e87aa4c49e95	1029	return HAL_OK;
phungductung	0:e87aa4c49e95	1030	}
phungductung	0:e87aa4c49e95	1031
phungductung	0:e87aa4c49e95	1032	/**
phungductung	0:e87aa4c49e95	1033	* @brief DeInitializes the TIM peripheral
phungductung	0:e87aa4c49e95	1034	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1035	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1036	* @retval HAL status
phungductung	0:e87aa4c49e95	1037	*/
phungductung	0:e87aa4c49e95	1038	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1039	{
phungductung	0:e87aa4c49e95	1040	/* Check the parameters */
phungductung	0:e87aa4c49e95	1041	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	1042
phungductung	0:e87aa4c49e95	1043	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	1044
phungductung	0:e87aa4c49e95	1045	/* Disable the TIM Peripheral Clock */
phungductung	0:e87aa4c49e95	1046	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1047
phungductung	0:e87aa4c49e95	1048	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	1049	HAL_TIM_PWM_MspDeInit(htim);
phungductung	0:e87aa4c49e95	1050
phungductung	0:e87aa4c49e95	1051	/* Change TIM state */
phungductung	0:e87aa4c49e95	1052	htim->State = HAL_TIM_STATE_RESET;
phungductung	0:e87aa4c49e95	1053
phungductung	0:e87aa4c49e95	1054	/* Release Lock */
phungductung	0:e87aa4c49e95	1055	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	1056
phungductung	0:e87aa4c49e95	1057	return HAL_OK;
phungductung	0:e87aa4c49e95	1058	}
phungductung	0:e87aa4c49e95	1059
phungductung	0:e87aa4c49e95	1060	/**
phungductung	0:e87aa4c49e95	1061	* @brief Initializes the TIM PWM MSP.
phungductung	0:e87aa4c49e95	1062	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1063	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1064	* @retval None
phungductung	0:e87aa4c49e95	1065	*/
phungductung	0:e87aa4c49e95	1066	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1067	{
phungductung	0:e87aa4c49e95	1068	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1069	UNUSED(htim);
phungductung	0:e87aa4c49e95	1070
phungductung	0:e87aa4c49e95	1071	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1072	the HAL_TIM_PWM_MspInit could be implemented in the user file
phungductung	0:e87aa4c49e95	1073	*/
phungductung	0:e87aa4c49e95	1074	}
phungductung	0:e87aa4c49e95	1075
phungductung	0:e87aa4c49e95	1076	/**
phungductung	0:e87aa4c49e95	1077	* @brief DeInitializes TIM PWM MSP.
phungductung	0:e87aa4c49e95	1078	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1079	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1080	* @retval None
phungductung	0:e87aa4c49e95	1081	*/
phungductung	0:e87aa4c49e95	1082	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1083	{
phungductung	0:e87aa4c49e95	1084	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1085	UNUSED(htim);
phungductung	0:e87aa4c49e95	1086
phungductung	0:e87aa4c49e95	1087	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1088	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
phungductung	0:e87aa4c49e95	1089	*/
phungductung	0:e87aa4c49e95	1090	}
phungductung	0:e87aa4c49e95	1091
phungductung	0:e87aa4c49e95	1092	/**
phungductung	0:e87aa4c49e95	1093	* @brief Starts the PWM signal generation.
phungductung	0:e87aa4c49e95	1094	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1095	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1096	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	1097	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1098	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1099	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1100	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1101	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1102	* @retval HAL status
phungductung	0:e87aa4c49e95	1103	*/
phungductung	0:e87aa4c49e95	1104	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1105	{
phungductung	0:e87aa4c49e95	1106	/* Check the parameters */
phungductung	0:e87aa4c49e95	1107	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1108
phungductung	0:e87aa4c49e95	1109	/* Enable the Capture compare channel */
phungductung	0:e87aa4c49e95	1110	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	1111
phungductung	0:e87aa4c49e95	1112	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	1113	{
phungductung	0:e87aa4c49e95	1114	/* Enable the main output */
phungductung	0:e87aa4c49e95	1115	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	1116	}
phungductung	0:e87aa4c49e95	1117
phungductung	0:e87aa4c49e95	1118	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	1119	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	1120
phungductung	0:e87aa4c49e95	1121	/* Return function status */
phungductung	0:e87aa4c49e95	1122	return HAL_OK;
phungductung	0:e87aa4c49e95	1123	}
phungductung	0:e87aa4c49e95	1124
phungductung	0:e87aa4c49e95	1125	/**
phungductung	0:e87aa4c49e95	1126	* @brief Stops the PWM signal generation.
phungductung	0:e87aa4c49e95	1127	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1128	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1129	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	1130	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1131	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1132	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1133	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1134	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1135	* @retval HAL status
phungductung	0:e87aa4c49e95	1136	*/
phungductung	0:e87aa4c49e95	1137	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1138	{
phungductung	0:e87aa4c49e95	1139	/* Check the parameters */
phungductung	0:e87aa4c49e95	1140	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1141
phungductung	0:e87aa4c49e95	1142	/* Disable the Capture compare channel */
phungductung	0:e87aa4c49e95	1143	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	1144
phungductung	0:e87aa4c49e95	1145	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	1146	{
phungductung	0:e87aa4c49e95	1147	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	1148	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	1149	}
phungductung	0:e87aa4c49e95	1150
phungductung	0:e87aa4c49e95	1151	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	1152	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1153
phungductung	0:e87aa4c49e95	1154	/* Change the htim state */
phungductung	0:e87aa4c49e95	1155	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	1156
phungductung	0:e87aa4c49e95	1157	/* Return function status */
phungductung	0:e87aa4c49e95	1158	return HAL_OK;
phungductung	0:e87aa4c49e95	1159	}
phungductung	0:e87aa4c49e95	1160
phungductung	0:e87aa4c49e95	1161	/**
phungductung	0:e87aa4c49e95	1162	* @brief Starts the PWM signal generation in interrupt mode.
phungductung	0:e87aa4c49e95	1163	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1164	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1165	* @param Channel: TIM Channel to be disabled.
phungductung	0:e87aa4c49e95	1166	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1167	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1168	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1169	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1170	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1171	* @retval HAL status
phungductung	0:e87aa4c49e95	1172	*/
phungductung	0:e87aa4c49e95	1173	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1174	{
phungductung	0:e87aa4c49e95	1175	/* Check the parameters */
phungductung	0:e87aa4c49e95	1176	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1177
phungductung	0:e87aa4c49e95	1178	switch (Channel)
phungductung	0:e87aa4c49e95	1179	{
phungductung	0:e87aa4c49e95	1180	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1181	{
phungductung	0:e87aa4c49e95	1182	/* Enable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	1183	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	1184	}
phungductung	0:e87aa4c49e95	1185	break;
phungductung	0:e87aa4c49e95	1186
phungductung	0:e87aa4c49e95	1187	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1188	{
phungductung	0:e87aa4c49e95	1189	/* Enable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	1190	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	1191	}
phungductung	0:e87aa4c49e95	1192	break;
phungductung	0:e87aa4c49e95	1193
phungductung	0:e87aa4c49e95	1194	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1195	{
phungductung	0:e87aa4c49e95	1196	/* Enable the TIM Capture/Compare 3 interrupt */
phungductung	0:e87aa4c49e95	1197	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	1198	}
phungductung	0:e87aa4c49e95	1199	break;
phungductung	0:e87aa4c49e95	1200
phungductung	0:e87aa4c49e95	1201	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1202	{
phungductung	0:e87aa4c49e95	1203	/* Enable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	1204	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	1205	}
phungductung	0:e87aa4c49e95	1206	break;
phungductung	0:e87aa4c49e95	1207
phungductung	0:e87aa4c49e95	1208	default:
phungductung	0:e87aa4c49e95	1209	break;
phungductung	0:e87aa4c49e95	1210	}
phungductung	0:e87aa4c49e95	1211
phungductung	0:e87aa4c49e95	1212	/* Enable the Capture compare channel */
phungductung	0:e87aa4c49e95	1213	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	1214
phungductung	0:e87aa4c49e95	1215	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	1216	{
phungductung	0:e87aa4c49e95	1217	/* Enable the main output */
phungductung	0:e87aa4c49e95	1218	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	1219	}
phungductung	0:e87aa4c49e95	1220
phungductung	0:e87aa4c49e95	1221	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	1222	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	1223
phungductung	0:e87aa4c49e95	1224	/* Return function status */
phungductung	0:e87aa4c49e95	1225	return HAL_OK;
phungductung	0:e87aa4c49e95	1226	}
phungductung	0:e87aa4c49e95	1227
phungductung	0:e87aa4c49e95	1228	/**
phungductung	0:e87aa4c49e95	1229	* @brief Stops the PWM signal generation in interrupt mode.
phungductung	0:e87aa4c49e95	1230	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1231	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1232	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	1233	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1234	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1235	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1236	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1237	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1238	* @retval HAL status
phungductung	0:e87aa4c49e95	1239	*/
phungductung	0:e87aa4c49e95	1240	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1241	{
phungductung	0:e87aa4c49e95	1242	/* Check the parameters */
phungductung	0:e87aa4c49e95	1243	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1244
phungductung	0:e87aa4c49e95	1245	switch (Channel)
phungductung	0:e87aa4c49e95	1246	{
phungductung	0:e87aa4c49e95	1247	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1248	{
phungductung	0:e87aa4c49e95	1249	/* Disable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	1250	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	1251	}
phungductung	0:e87aa4c49e95	1252	break;
phungductung	0:e87aa4c49e95	1253
phungductung	0:e87aa4c49e95	1254	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1255	{
phungductung	0:e87aa4c49e95	1256	/* Disable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	1257	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	1258	}
phungductung	0:e87aa4c49e95	1259	break;
phungductung	0:e87aa4c49e95	1260
phungductung	0:e87aa4c49e95	1261	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1262	{
phungductung	0:e87aa4c49e95	1263	/* Disable the TIM Capture/Compare 3 interrupt */
phungductung	0:e87aa4c49e95	1264	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	1265	}
phungductung	0:e87aa4c49e95	1266	break;
phungductung	0:e87aa4c49e95	1267
phungductung	0:e87aa4c49e95	1268	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1269	{
phungductung	0:e87aa4c49e95	1270	/* Disable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	1271	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	1272	}
phungductung	0:e87aa4c49e95	1273	break;
phungductung	0:e87aa4c49e95	1274
phungductung	0:e87aa4c49e95	1275	default:
phungductung	0:e87aa4c49e95	1276	break;
phungductung	0:e87aa4c49e95	1277	}
phungductung	0:e87aa4c49e95	1278
phungductung	0:e87aa4c49e95	1279	/* Disable the Capture compare channel */
phungductung	0:e87aa4c49e95	1280	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	1281
phungductung	0:e87aa4c49e95	1282	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	1283	{
phungductung	0:e87aa4c49e95	1284	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	1285	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	1286	}
phungductung	0:e87aa4c49e95	1287
phungductung	0:e87aa4c49e95	1288	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	1289	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1290
phungductung	0:e87aa4c49e95	1291	/* Return function status */
phungductung	0:e87aa4c49e95	1292	return HAL_OK;
phungductung	0:e87aa4c49e95	1293	}
phungductung	0:e87aa4c49e95	1294
phungductung	0:e87aa4c49e95	1295	/**
phungductung	0:e87aa4c49e95	1296	* @brief Starts the TIM PWM signal generation in DMA mode.
phungductung	0:e87aa4c49e95	1297	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1298	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1299	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	1300	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1301	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1302	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1303	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1304	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1305	* @param pData: The source Buffer address.
phungductung	0:e87aa4c49e95	1306	* @param Length: The length of data to be transferred from memory to TIM peripheral
phungductung	0:e87aa4c49e95	1307	* @retval HAL status
phungductung	0:e87aa4c49e95	1308	*/
phungductung	0:e87aa4c49e95	1309	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
phungductung	0:e87aa4c49e95	1310	{
phungductung	0:e87aa4c49e95	1311	/* Check the parameters */
phungductung	0:e87aa4c49e95	1312	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1313
phungductung	0:e87aa4c49e95	1314	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	1315	{
phungductung	0:e87aa4c49e95	1316	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1317	}
phungductung	0:e87aa4c49e95	1318	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	1319	{
phungductung	0:e87aa4c49e95	1320	if(((uint32_t)pData == 0 ) && (Length > 0))
phungductung	0:e87aa4c49e95	1321	{
phungductung	0:e87aa4c49e95	1322	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1323	}
phungductung	0:e87aa4c49e95	1324	else
phungductung	0:e87aa4c49e95	1325	{
phungductung	0:e87aa4c49e95	1326	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	1327	}
phungductung	0:e87aa4c49e95	1328	}
phungductung	0:e87aa4c49e95	1329	switch (Channel)
phungductung	0:e87aa4c49e95	1330	{
phungductung	0:e87aa4c49e95	1331	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1332	{
phungductung	0:e87aa4c49e95	1333	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1334	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	1335
phungductung	0:e87aa4c49e95	1336	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1337	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1338
phungductung	0:e87aa4c49e95	1339	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1340	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
phungductung	0:e87aa4c49e95	1341
phungductung	0:e87aa4c49e95	1342	/* Enable the TIM Capture/Compare 1 DMA request */
phungductung	0:e87aa4c49e95	1343	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	1344	}
phungductung	0:e87aa4c49e95	1345	break;
phungductung	0:e87aa4c49e95	1346
phungductung	0:e87aa4c49e95	1347	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1348	{
phungductung	0:e87aa4c49e95	1349	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1350	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	1351
phungductung	0:e87aa4c49e95	1352	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1353	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1354
phungductung	0:e87aa4c49e95	1355	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1356	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
phungductung	0:e87aa4c49e95	1357
phungductung	0:e87aa4c49e95	1358	/* Enable the TIM Capture/Compare 2 DMA request */
phungductung	0:e87aa4c49e95	1359	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	1360	}
phungductung	0:e87aa4c49e95	1361	break;
phungductung	0:e87aa4c49e95	1362
phungductung	0:e87aa4c49e95	1363	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1364	{
phungductung	0:e87aa4c49e95	1365	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1366	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	1367
phungductung	0:e87aa4c49e95	1368	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1369	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1370
phungductung	0:e87aa4c49e95	1371	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1372	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
phungductung	0:e87aa4c49e95	1373
phungductung	0:e87aa4c49e95	1374	/* Enable the TIM Output Capture/Compare 3 request */
phungductung	0:e87aa4c49e95	1375	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
phungductung	0:e87aa4c49e95	1376	}
phungductung	0:e87aa4c49e95	1377	break;
phungductung	0:e87aa4c49e95	1378
phungductung	0:e87aa4c49e95	1379	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1380	{
phungductung	0:e87aa4c49e95	1381	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1382	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	1383
phungductung	0:e87aa4c49e95	1384	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1385	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1386
phungductung	0:e87aa4c49e95	1387	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1388	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
phungductung	0:e87aa4c49e95	1389
phungductung	0:e87aa4c49e95	1390	/* Enable the TIM Capture/Compare 4 DMA request */
phungductung	0:e87aa4c49e95	1391	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
phungductung	0:e87aa4c49e95	1392	}
phungductung	0:e87aa4c49e95	1393	break;
phungductung	0:e87aa4c49e95	1394
phungductung	0:e87aa4c49e95	1395	default:
phungductung	0:e87aa4c49e95	1396	break;
phungductung	0:e87aa4c49e95	1397	}
phungductung	0:e87aa4c49e95	1398
phungductung	0:e87aa4c49e95	1399	/* Enable the Capture compare channel */
phungductung	0:e87aa4c49e95	1400	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	1401
phungductung	0:e87aa4c49e95	1402	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	1403	{
phungductung	0:e87aa4c49e95	1404	/* Enable the main output */
phungductung	0:e87aa4c49e95	1405	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	1406	}
phungductung	0:e87aa4c49e95	1407
phungductung	0:e87aa4c49e95	1408	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	1409	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	1410
phungductung	0:e87aa4c49e95	1411	/* Return function status */
phungductung	0:e87aa4c49e95	1412	return HAL_OK;
phungductung	0:e87aa4c49e95	1413	}
phungductung	0:e87aa4c49e95	1414
phungductung	0:e87aa4c49e95	1415	/**
phungductung	0:e87aa4c49e95	1416	* @brief Stops the TIM PWM signal generation in DMA mode.
phungductung	0:e87aa4c49e95	1417	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1418	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1419	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	1420	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1421	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1422	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1423	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1424	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1425	* @retval HAL status
phungductung	0:e87aa4c49e95	1426	*/
phungductung	0:e87aa4c49e95	1427	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1428	{
phungductung	0:e87aa4c49e95	1429	/* Check the parameters */
phungductung	0:e87aa4c49e95	1430	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1431
phungductung	0:e87aa4c49e95	1432	switch (Channel)
phungductung	0:e87aa4c49e95	1433	{
phungductung	0:e87aa4c49e95	1434	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1435	{
phungductung	0:e87aa4c49e95	1436	/* Disable the TIM Capture/Compare 1 DMA request */
phungductung	0:e87aa4c49e95	1437	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	1438	}
phungductung	0:e87aa4c49e95	1439	break;
phungductung	0:e87aa4c49e95	1440
phungductung	0:e87aa4c49e95	1441	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1442	{
phungductung	0:e87aa4c49e95	1443	/* Disable the TIM Capture/Compare 2 DMA request */
phungductung	0:e87aa4c49e95	1444	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	1445	}
phungductung	0:e87aa4c49e95	1446	break;
phungductung	0:e87aa4c49e95	1447
phungductung	0:e87aa4c49e95	1448	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1449	{
phungductung	0:e87aa4c49e95	1450	/* Disable the TIM Capture/Compare 3 DMA request */
phungductung	0:e87aa4c49e95	1451	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
phungductung	0:e87aa4c49e95	1452	}
phungductung	0:e87aa4c49e95	1453	break;
phungductung	0:e87aa4c49e95	1454
phungductung	0:e87aa4c49e95	1455	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1456	{
phungductung	0:e87aa4c49e95	1457	/* Disable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	1458	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
phungductung	0:e87aa4c49e95	1459	}
phungductung	0:e87aa4c49e95	1460	break;
phungductung	0:e87aa4c49e95	1461
phungductung	0:e87aa4c49e95	1462	default:
phungductung	0:e87aa4c49e95	1463	break;
phungductung	0:e87aa4c49e95	1464	}
phungductung	0:e87aa4c49e95	1465
phungductung	0:e87aa4c49e95	1466	/* Disable the Capture compare channel */
phungductung	0:e87aa4c49e95	1467	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	1468
phungductung	0:e87aa4c49e95	1469	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	1470	{
phungductung	0:e87aa4c49e95	1471	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	1472	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	1473	}
phungductung	0:e87aa4c49e95	1474
phungductung	0:e87aa4c49e95	1475	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	1476	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1477
phungductung	0:e87aa4c49e95	1478	/* Change the htim state */
phungductung	0:e87aa4c49e95	1479	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	1480
phungductung	0:e87aa4c49e95	1481	/* Return function status */
phungductung	0:e87aa4c49e95	1482	return HAL_OK;
phungductung	0:e87aa4c49e95	1483	}
phungductung	0:e87aa4c49e95	1484
phungductung	0:e87aa4c49e95	1485	/**
phungductung	0:e87aa4c49e95	1486	* @}
phungductung	0:e87aa4c49e95	1487	*/
phungductung	0:e87aa4c49e95	1488
phungductung	0:e87aa4c49e95	1489	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
phungductung	0:e87aa4c49e95	1490	* @brief Time Input Capture functions
phungductung	0:e87aa4c49e95	1491	*
phungductung	0:e87aa4c49e95	1492	@verbatim
phungductung	0:e87aa4c49e95	1493	==============================================================================
phungductung	0:e87aa4c49e95	1494	##### Time Input Capture functions #####
phungductung	0:e87aa4c49e95	1495	==============================================================================
phungductung	0:e87aa4c49e95	1496	[..]
phungductung	0:e87aa4c49e95	1497	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	1498	(+) Initialize and configure the TIM Input Capture.
phungductung	0:e87aa4c49e95	1499	(+) De-initialize the TIM Input Capture.
phungductung	0:e87aa4c49e95	1500	(+) Start the Time Input Capture.
phungductung	0:e87aa4c49e95	1501	(+) Stop the Time Input Capture.
phungductung	0:e87aa4c49e95	1502	(+) Start the Time Input Capture and enable interrupt.
phungductung	0:e87aa4c49e95	1503	(+) Stop the Time Input Capture and disable interrupt.
phungductung	0:e87aa4c49e95	1504	(+) Start the Time Input Capture and enable DMA transfer.
phungductung	0:e87aa4c49e95	1505	(+) Stop the Time Input Capture and disable DMA transfer.
phungductung	0:e87aa4c49e95	1506
phungductung	0:e87aa4c49e95	1507	@endverbatim
phungductung	0:e87aa4c49e95	1508	* @{
phungductung	0:e87aa4c49e95	1509	*/
phungductung	0:e87aa4c49e95	1510	/**
phungductung	0:e87aa4c49e95	1511	* @brief Initializes the TIM Input Capture Time base according to the specified
phungductung	0:e87aa4c49e95	1512	* parameters in the TIM_HandleTypeDef and create the associated handle.
phungductung	0:e87aa4c49e95	1513	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1514	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1515	* @retval HAL status
phungductung	0:e87aa4c49e95	1516	*/
phungductung	0:e87aa4c49e95	1517	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1518	{
phungductung	0:e87aa4c49e95	1519	/* Check the TIM handle allocation */
phungductung	0:e87aa4c49e95	1520	if(htim == NULL)
phungductung	0:e87aa4c49e95	1521	{
phungductung	0:e87aa4c49e95	1522	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1523	}
phungductung	0:e87aa4c49e95	1524
phungductung	0:e87aa4c49e95	1525	/* Check the parameters */
phungductung	0:e87aa4c49e95	1526	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	1527	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
phungductung	0:e87aa4c49e95	1528	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
phungductung	0:e87aa4c49e95	1529
phungductung	0:e87aa4c49e95	1530	if(htim->State == HAL_TIM_STATE_RESET)
phungductung	0:e87aa4c49e95	1531	{
phungductung	0:e87aa4c49e95	1532	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	1533	htim->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	1534	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	1535	HAL_TIM_IC_MspInit(htim);
phungductung	0:e87aa4c49e95	1536	}
phungductung	0:e87aa4c49e95	1537
phungductung	0:e87aa4c49e95	1538	/* Set the TIM state */
phungductung	0:e87aa4c49e95	1539	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	1540
phungductung	0:e87aa4c49e95	1541	/* Init the base time for the input capture */
phungductung	0:e87aa4c49e95	1542	TIM_Base_SetConfig(htim->Instance, &htim->Init);
phungductung	0:e87aa4c49e95	1543
phungductung	0:e87aa4c49e95	1544	/* Initialize the TIM state*/
phungductung	0:e87aa4c49e95	1545	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	1546
phungductung	0:e87aa4c49e95	1547	return HAL_OK;
phungductung	0:e87aa4c49e95	1548	}
phungductung	0:e87aa4c49e95	1549
phungductung	0:e87aa4c49e95	1550	/**
phungductung	0:e87aa4c49e95	1551	* @brief DeInitializes the TIM peripheral
phungductung	0:e87aa4c49e95	1552	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1553	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1554	* @retval HAL status
phungductung	0:e87aa4c49e95	1555	*/
phungductung	0:e87aa4c49e95	1556	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1557	{
phungductung	0:e87aa4c49e95	1558	/* Check the parameters */
phungductung	0:e87aa4c49e95	1559	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	1560
phungductung	0:e87aa4c49e95	1561	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	1562
phungductung	0:e87aa4c49e95	1563	/* Disable the TIM Peripheral Clock */
phungductung	0:e87aa4c49e95	1564	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1565
phungductung	0:e87aa4c49e95	1566	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	1567	HAL_TIM_IC_MspDeInit(htim);
phungductung	0:e87aa4c49e95	1568
phungductung	0:e87aa4c49e95	1569	/* Change TIM state */
phungductung	0:e87aa4c49e95	1570	htim->State = HAL_TIM_STATE_RESET;
phungductung	0:e87aa4c49e95	1571
phungductung	0:e87aa4c49e95	1572	/* Release Lock */
phungductung	0:e87aa4c49e95	1573	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	1574
phungductung	0:e87aa4c49e95	1575	return HAL_OK;
phungductung	0:e87aa4c49e95	1576	}
phungductung	0:e87aa4c49e95	1577
phungductung	0:e87aa4c49e95	1578	/**
phungductung	0:e87aa4c49e95	1579	* @brief Initializes the TIM INput Capture MSP.
phungductung	0:e87aa4c49e95	1580	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1581	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1582	* @retval None
phungductung	0:e87aa4c49e95	1583	*/
phungductung	0:e87aa4c49e95	1584	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1585	{
phungductung	0:e87aa4c49e95	1586	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1587	UNUSED(htim);
phungductung	0:e87aa4c49e95	1588
phungductung	0:e87aa4c49e95	1589	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1590	the HAL_TIM_IC_MspInit could be implemented in the user file
phungductung	0:e87aa4c49e95	1591	*/
phungductung	0:e87aa4c49e95	1592	}
phungductung	0:e87aa4c49e95	1593
phungductung	0:e87aa4c49e95	1594	/**
phungductung	0:e87aa4c49e95	1595	* @brief DeInitializes TIM Input Capture MSP.
phungductung	0:e87aa4c49e95	1596	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1597	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1598	* @retval None
phungductung	0:e87aa4c49e95	1599	*/
phungductung	0:e87aa4c49e95	1600	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	1601	{
phungductung	0:e87aa4c49e95	1602	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1603	UNUSED(htim);
phungductung	0:e87aa4c49e95	1604
phungductung	0:e87aa4c49e95	1605	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1606	the HAL_TIM_IC_MspDeInit could be implemented in the user file
phungductung	0:e87aa4c49e95	1607	*/
phungductung	0:e87aa4c49e95	1608	}
phungductung	0:e87aa4c49e95	1609
phungductung	0:e87aa4c49e95	1610	/**
phungductung	0:e87aa4c49e95	1611	* @brief Starts the TIM Input Capture measurement.
phungductung	0:e87aa4c49e95	1612	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1613	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1614	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	1615	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1616	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1617	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1618	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1619	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1620	* @retval HAL status
phungductung	0:e87aa4c49e95	1621	*/
phungductung	0:e87aa4c49e95	1622	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1623	{
phungductung	0:e87aa4c49e95	1624	/* Check the parameters */
phungductung	0:e87aa4c49e95	1625	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1626
phungductung	0:e87aa4c49e95	1627	/* Enable the Input Capture channel */
phungductung	0:e87aa4c49e95	1628	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	1629
phungductung	0:e87aa4c49e95	1630	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	1631	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	1632
phungductung	0:e87aa4c49e95	1633	/* Return function status */
phungductung	0:e87aa4c49e95	1634	return HAL_OK;
phungductung	0:e87aa4c49e95	1635	}
phungductung	0:e87aa4c49e95	1636
phungductung	0:e87aa4c49e95	1637	/**
phungductung	0:e87aa4c49e95	1638	* @brief Stops the TIM Input Capture measurement.
phungductung	0:e87aa4c49e95	1639	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1640	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1641	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	1642	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1643	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1644	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1645	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1646	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1647	* @retval HAL status
phungductung	0:e87aa4c49e95	1648	*/
phungductung	0:e87aa4c49e95	1649	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1650	{
phungductung	0:e87aa4c49e95	1651	/* Check the parameters */
phungductung	0:e87aa4c49e95	1652	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1653
phungductung	0:e87aa4c49e95	1654	/* Disable the Input Capture channel */
phungductung	0:e87aa4c49e95	1655	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	1656
phungductung	0:e87aa4c49e95	1657	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	1658	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1659
phungductung	0:e87aa4c49e95	1660	/* Return function status */
phungductung	0:e87aa4c49e95	1661	return HAL_OK;
phungductung	0:e87aa4c49e95	1662	}
phungductung	0:e87aa4c49e95	1663
phungductung	0:e87aa4c49e95	1664	/**
phungductung	0:e87aa4c49e95	1665	* @brief Starts the TIM Input Capture measurement in interrupt mode.
phungductung	0:e87aa4c49e95	1666	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1667	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1668	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	1669	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1670	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1671	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1672	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1673	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1674	* @retval HAL status
phungductung	0:e87aa4c49e95	1675	*/
phungductung	0:e87aa4c49e95	1676	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1677	{
phungductung	0:e87aa4c49e95	1678	/* Check the parameters */
phungductung	0:e87aa4c49e95	1679	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1680
phungductung	0:e87aa4c49e95	1681	switch (Channel)
phungductung	0:e87aa4c49e95	1682	{
phungductung	0:e87aa4c49e95	1683	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1684	{
phungductung	0:e87aa4c49e95	1685	/* Enable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	1686	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	1687	}
phungductung	0:e87aa4c49e95	1688	break;
phungductung	0:e87aa4c49e95	1689
phungductung	0:e87aa4c49e95	1690	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1691	{
phungductung	0:e87aa4c49e95	1692	/* Enable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	1693	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	1694	}
phungductung	0:e87aa4c49e95	1695	break;
phungductung	0:e87aa4c49e95	1696
phungductung	0:e87aa4c49e95	1697	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1698	{
phungductung	0:e87aa4c49e95	1699	/* Enable the TIM Capture/Compare 3 interrupt */
phungductung	0:e87aa4c49e95	1700	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	1701	}
phungductung	0:e87aa4c49e95	1702	break;
phungductung	0:e87aa4c49e95	1703
phungductung	0:e87aa4c49e95	1704	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1705	{
phungductung	0:e87aa4c49e95	1706	/* Enable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	1707	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	1708	}
phungductung	0:e87aa4c49e95	1709	break;
phungductung	0:e87aa4c49e95	1710
phungductung	0:e87aa4c49e95	1711	default:
phungductung	0:e87aa4c49e95	1712	break;
phungductung	0:e87aa4c49e95	1713	}
phungductung	0:e87aa4c49e95	1714	/* Enable the Input Capture channel */
phungductung	0:e87aa4c49e95	1715	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	1716
phungductung	0:e87aa4c49e95	1717	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	1718	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	1719
phungductung	0:e87aa4c49e95	1720	/* Return function status */
phungductung	0:e87aa4c49e95	1721	return HAL_OK;
phungductung	0:e87aa4c49e95	1722	}
phungductung	0:e87aa4c49e95	1723
phungductung	0:e87aa4c49e95	1724	/**
phungductung	0:e87aa4c49e95	1725	* @brief Stops the TIM Input Capture measurement in interrupt mode.
phungductung	0:e87aa4c49e95	1726	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1727	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1728	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	1729	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1730	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1731	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1732	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1733	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1734	* @retval HAL status
phungductung	0:e87aa4c49e95	1735	*/
phungductung	0:e87aa4c49e95	1736	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1737	{
phungductung	0:e87aa4c49e95	1738	/* Check the parameters */
phungductung	0:e87aa4c49e95	1739	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1740
phungductung	0:e87aa4c49e95	1741	switch (Channel)
phungductung	0:e87aa4c49e95	1742	{
phungductung	0:e87aa4c49e95	1743	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1744	{
phungductung	0:e87aa4c49e95	1745	/* Disable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	1746	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	1747	}
phungductung	0:e87aa4c49e95	1748	break;
phungductung	0:e87aa4c49e95	1749
phungductung	0:e87aa4c49e95	1750	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1751	{
phungductung	0:e87aa4c49e95	1752	/* Disable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	1753	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	1754	}
phungductung	0:e87aa4c49e95	1755	break;
phungductung	0:e87aa4c49e95	1756
phungductung	0:e87aa4c49e95	1757	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1758	{
phungductung	0:e87aa4c49e95	1759	/* Disable the TIM Capture/Compare 3 interrupt */
phungductung	0:e87aa4c49e95	1760	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	1761	}
phungductung	0:e87aa4c49e95	1762	break;
phungductung	0:e87aa4c49e95	1763
phungductung	0:e87aa4c49e95	1764	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1765	{
phungductung	0:e87aa4c49e95	1766	/* Disable the TIM Capture/Compare 4 interrupt */
phungductung	0:e87aa4c49e95	1767	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	1768	}
phungductung	0:e87aa4c49e95	1769	break;
phungductung	0:e87aa4c49e95	1770
phungductung	0:e87aa4c49e95	1771	default:
phungductung	0:e87aa4c49e95	1772	break;
phungductung	0:e87aa4c49e95	1773	}
phungductung	0:e87aa4c49e95	1774
phungductung	0:e87aa4c49e95	1775	/* Disable the Input Capture channel */
phungductung	0:e87aa4c49e95	1776	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	1777
phungductung	0:e87aa4c49e95	1778	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	1779	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1780
phungductung	0:e87aa4c49e95	1781	/* Return function status */
phungductung	0:e87aa4c49e95	1782	return HAL_OK;
phungductung	0:e87aa4c49e95	1783	}
phungductung	0:e87aa4c49e95	1784
phungductung	0:e87aa4c49e95	1785	/**
phungductung	0:e87aa4c49e95	1786	* @brief Starts the TIM Input Capture measurement on in DMA mode.
phungductung	0:e87aa4c49e95	1787	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1788	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1789	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	1790	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1791	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1792	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1793	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1794	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1795	* @param pData: The destination Buffer address.
phungductung	0:e87aa4c49e95	1796	* @param Length: The length of data to be transferred from TIM peripheral to memory.
phungductung	0:e87aa4c49e95	1797	* @retval HAL status
phungductung	0:e87aa4c49e95	1798	*/
phungductung	0:e87aa4c49e95	1799	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
phungductung	0:e87aa4c49e95	1800	{
phungductung	0:e87aa4c49e95	1801	/* Check the parameters */
phungductung	0:e87aa4c49e95	1802	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1803	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	1804
phungductung	0:e87aa4c49e95	1805	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	1806	{
phungductung	0:e87aa4c49e95	1807	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1808	}
phungductung	0:e87aa4c49e95	1809	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	1810	{
phungductung	0:e87aa4c49e95	1811	if((pData == 0 ) && (Length > 0))
phungductung	0:e87aa4c49e95	1812	{
phungductung	0:e87aa4c49e95	1813	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1814	}
phungductung	0:e87aa4c49e95	1815	else
phungductung	0:e87aa4c49e95	1816	{
phungductung	0:e87aa4c49e95	1817	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	1818	}
phungductung	0:e87aa4c49e95	1819	}
phungductung	0:e87aa4c49e95	1820
phungductung	0:e87aa4c49e95	1821	switch (Channel)
phungductung	0:e87aa4c49e95	1822	{
phungductung	0:e87aa4c49e95	1823	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1824	{
phungductung	0:e87aa4c49e95	1825	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1826	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	1827
phungductung	0:e87aa4c49e95	1828	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1829	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1830
phungductung	0:e87aa4c49e95	1831	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1832	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
phungductung	0:e87aa4c49e95	1833
phungductung	0:e87aa4c49e95	1834	/* Enable the TIM Capture/Compare 1 DMA request */
phungductung	0:e87aa4c49e95	1835	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	1836	}
phungductung	0:e87aa4c49e95	1837	break;
phungductung	0:e87aa4c49e95	1838
phungductung	0:e87aa4c49e95	1839	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1840	{
phungductung	0:e87aa4c49e95	1841	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1842	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	1843
phungductung	0:e87aa4c49e95	1844	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1845	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1846
phungductung	0:e87aa4c49e95	1847	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1848	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
phungductung	0:e87aa4c49e95	1849
phungductung	0:e87aa4c49e95	1850	/* Enable the TIM Capture/Compare 2 DMA request */
phungductung	0:e87aa4c49e95	1851	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	1852	}
phungductung	0:e87aa4c49e95	1853	break;
phungductung	0:e87aa4c49e95	1854
phungductung	0:e87aa4c49e95	1855	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1856	{
phungductung	0:e87aa4c49e95	1857	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1858	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	1859
phungductung	0:e87aa4c49e95	1860	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1861	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1862
phungductung	0:e87aa4c49e95	1863	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1864	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
phungductung	0:e87aa4c49e95	1865
phungductung	0:e87aa4c49e95	1866	/* Enable the TIM Capture/Compare 3 DMA request */
phungductung	0:e87aa4c49e95	1867	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
phungductung	0:e87aa4c49e95	1868	}
phungductung	0:e87aa4c49e95	1869	break;
phungductung	0:e87aa4c49e95	1870
phungductung	0:e87aa4c49e95	1871	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1872	{
phungductung	0:e87aa4c49e95	1873	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	1874	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	1875
phungductung	0:e87aa4c49e95	1876	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1877	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	1878
phungductung	0:e87aa4c49e95	1879	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	1880	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
phungductung	0:e87aa4c49e95	1881
phungductung	0:e87aa4c49e95	1882	/* Enable the TIM Capture/Compare 4 DMA request */
phungductung	0:e87aa4c49e95	1883	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
phungductung	0:e87aa4c49e95	1884	}
phungductung	0:e87aa4c49e95	1885	break;
phungductung	0:e87aa4c49e95	1886
phungductung	0:e87aa4c49e95	1887	default:
phungductung	0:e87aa4c49e95	1888	break;
phungductung	0:e87aa4c49e95	1889	}
phungductung	0:e87aa4c49e95	1890
phungductung	0:e87aa4c49e95	1891	/* Enable the Input Capture channel */
phungductung	0:e87aa4c49e95	1892	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	1893
phungductung	0:e87aa4c49e95	1894	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	1895	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	1896
phungductung	0:e87aa4c49e95	1897	/* Return function status */
phungductung	0:e87aa4c49e95	1898	return HAL_OK;
phungductung	0:e87aa4c49e95	1899	}
phungductung	0:e87aa4c49e95	1900
phungductung	0:e87aa4c49e95	1901	/**
phungductung	0:e87aa4c49e95	1902	* @brief Stops the TIM Input Capture measurement on in DMA mode.
phungductung	0:e87aa4c49e95	1903	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1904	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1905	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	1906	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1907	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	1908	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	1909	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	1910	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	1911	* @retval HAL status
phungductung	0:e87aa4c49e95	1912	*/
phungductung	0:e87aa4c49e95	1913	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	1914	{
phungductung	0:e87aa4c49e95	1915	/* Check the parameters */
phungductung	0:e87aa4c49e95	1916	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
phungductung	0:e87aa4c49e95	1917	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	1918
phungductung	0:e87aa4c49e95	1919	switch (Channel)
phungductung	0:e87aa4c49e95	1920	{
phungductung	0:e87aa4c49e95	1921	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	1922	{
phungductung	0:e87aa4c49e95	1923	/* Disable the TIM Capture/Compare 1 DMA request */
phungductung	0:e87aa4c49e95	1924	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	1925	}
phungductung	0:e87aa4c49e95	1926	break;
phungductung	0:e87aa4c49e95	1927
phungductung	0:e87aa4c49e95	1928	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	1929	{
phungductung	0:e87aa4c49e95	1930	/* Disable the TIM Capture/Compare 2 DMA request */
phungductung	0:e87aa4c49e95	1931	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	1932	}
phungductung	0:e87aa4c49e95	1933	break;
phungductung	0:e87aa4c49e95	1934
phungductung	0:e87aa4c49e95	1935	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	1936	{
phungductung	0:e87aa4c49e95	1937	/* Disable the TIM Capture/Compare 3 DMA request */
phungductung	0:e87aa4c49e95	1938	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
phungductung	0:e87aa4c49e95	1939	}
phungductung	0:e87aa4c49e95	1940	break;
phungductung	0:e87aa4c49e95	1941
phungductung	0:e87aa4c49e95	1942	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	1943	{
phungductung	0:e87aa4c49e95	1944	/* Disable the TIM Capture/Compare 4 DMA request */
phungductung	0:e87aa4c49e95	1945	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
phungductung	0:e87aa4c49e95	1946	}
phungductung	0:e87aa4c49e95	1947	break;
phungductung	0:e87aa4c49e95	1948
phungductung	0:e87aa4c49e95	1949	default:
phungductung	0:e87aa4c49e95	1950	break;
phungductung	0:e87aa4c49e95	1951	}
phungductung	0:e87aa4c49e95	1952
phungductung	0:e87aa4c49e95	1953	/* Disable the Input Capture channel */
phungductung	0:e87aa4c49e95	1954	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	1955
phungductung	0:e87aa4c49e95	1956	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	1957	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	1958
phungductung	0:e87aa4c49e95	1959	/* Change the htim state */
phungductung	0:e87aa4c49e95	1960	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	1961
phungductung	0:e87aa4c49e95	1962	/* Return function status */
phungductung	0:e87aa4c49e95	1963	return HAL_OK;
phungductung	0:e87aa4c49e95	1964	}
phungductung	0:e87aa4c49e95	1965	/**
phungductung	0:e87aa4c49e95	1966	* @}
phungductung	0:e87aa4c49e95	1967	*/
phungductung	0:e87aa4c49e95	1968
phungductung	0:e87aa4c49e95	1969	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
phungductung	0:e87aa4c49e95	1970	* @brief Time One Pulse functions
phungductung	0:e87aa4c49e95	1971	*
phungductung	0:e87aa4c49e95	1972	@verbatim
phungductung	0:e87aa4c49e95	1973	==============================================================================
phungductung	0:e87aa4c49e95	1974	##### Time One Pulse functions #####
phungductung	0:e87aa4c49e95	1975	==============================================================================
phungductung	0:e87aa4c49e95	1976	[..]
phungductung	0:e87aa4c49e95	1977	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	1978	(+) Initialize and configure the TIM One Pulse.
phungductung	0:e87aa4c49e95	1979	(+) De-initialize the TIM One Pulse.
phungductung	0:e87aa4c49e95	1980	(+) Start the Time One Pulse.
phungductung	0:e87aa4c49e95	1981	(+) Stop the Time One Pulse.
phungductung	0:e87aa4c49e95	1982	(+) Start the Time One Pulse and enable interrupt.
phungductung	0:e87aa4c49e95	1983	(+) Stop the Time One Pulse and disable interrupt.
phungductung	0:e87aa4c49e95	1984	(+) Start the Time One Pulse and enable DMA transfer.
phungductung	0:e87aa4c49e95	1985	(+) Stop the Time One Pulse and disable DMA transfer.
phungductung	0:e87aa4c49e95	1986
phungductung	0:e87aa4c49e95	1987	@endverbatim
phungductung	0:e87aa4c49e95	1988	* @{
phungductung	0:e87aa4c49e95	1989	*/
phungductung	0:e87aa4c49e95	1990	/**
phungductung	0:e87aa4c49e95	1991	* @brief Initializes the TIM One Pulse Time Base according to the specified
phungductung	0:e87aa4c49e95	1992	* parameters in the TIM_HandleTypeDef and create the associated handle.
phungductung	0:e87aa4c49e95	1993	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1994	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	1995	* @param OnePulseMode: Select the One pulse mode.
phungductung	0:e87aa4c49e95	1996	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1997	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
phungductung	0:e87aa4c49e95	1998	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
phungductung	0:e87aa4c49e95	1999	* @retval HAL status
phungductung	0:e87aa4c49e95	2000	*/
phungductung	0:e87aa4c49e95	2001	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
phungductung	0:e87aa4c49e95	2002	{
phungductung	0:e87aa4c49e95	2003	/* Check the TIM handle allocation */
phungductung	0:e87aa4c49e95	2004	if(htim == NULL)
phungductung	0:e87aa4c49e95	2005	{
phungductung	0:e87aa4c49e95	2006	return HAL_ERROR;
phungductung	0:e87aa4c49e95	2007	}
phungductung	0:e87aa4c49e95	2008
phungductung	0:e87aa4c49e95	2009	/* Check the parameters */
phungductung	0:e87aa4c49e95	2010	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2011	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
phungductung	0:e87aa4c49e95	2012	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
phungductung	0:e87aa4c49e95	2013	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
phungductung	0:e87aa4c49e95	2014
phungductung	0:e87aa4c49e95	2015	if(htim->State == HAL_TIM_STATE_RESET)
phungductung	0:e87aa4c49e95	2016	{
phungductung	0:e87aa4c49e95	2017	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	2018	htim->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	2019	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	2020	HAL_TIM_OnePulse_MspInit(htim);
phungductung	0:e87aa4c49e95	2021	}
phungductung	0:e87aa4c49e95	2022
phungductung	0:e87aa4c49e95	2023	/* Set the TIM state */
phungductung	0:e87aa4c49e95	2024	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	2025
phungductung	0:e87aa4c49e95	2026	/* Configure the Time base in the One Pulse Mode */
phungductung	0:e87aa4c49e95	2027	TIM_Base_SetConfig(htim->Instance, &htim->Init);
phungductung	0:e87aa4c49e95	2028
phungductung	0:e87aa4c49e95	2029	/* Reset the OPM Bit */
phungductung	0:e87aa4c49e95	2030	htim->Instance->CR1 &= ~TIM_CR1_OPM;
phungductung	0:e87aa4c49e95	2031
phungductung	0:e87aa4c49e95	2032	/* Configure the OPM Mode */
phungductung	0:e87aa4c49e95	2033	htim->Instance->CR1 \|= OnePulseMode;
phungductung	0:e87aa4c49e95	2034
phungductung	0:e87aa4c49e95	2035	/* Initialize the TIM state*/
phungductung	0:e87aa4c49e95	2036	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	2037
phungductung	0:e87aa4c49e95	2038	return HAL_OK;
phungductung	0:e87aa4c49e95	2039	}
phungductung	0:e87aa4c49e95	2040
phungductung	0:e87aa4c49e95	2041	/**
phungductung	0:e87aa4c49e95	2042	* @brief DeInitializes the TIM One Pulse
phungductung	0:e87aa4c49e95	2043	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2044	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2045	* @retval HAL status
phungductung	0:e87aa4c49e95	2046	*/
phungductung	0:e87aa4c49e95	2047	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2048	{
phungductung	0:e87aa4c49e95	2049	/* Check the parameters */
phungductung	0:e87aa4c49e95	2050	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2051
phungductung	0:e87aa4c49e95	2052	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	2053
phungductung	0:e87aa4c49e95	2054	/* Disable the TIM Peripheral Clock */
phungductung	0:e87aa4c49e95	2055	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2056
phungductung	0:e87aa4c49e95	2057	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
phungductung	0:e87aa4c49e95	2058	HAL_TIM_OnePulse_MspDeInit(htim);
phungductung	0:e87aa4c49e95	2059
phungductung	0:e87aa4c49e95	2060	/* Change TIM state */
phungductung	0:e87aa4c49e95	2061	htim->State = HAL_TIM_STATE_RESET;
phungductung	0:e87aa4c49e95	2062
phungductung	0:e87aa4c49e95	2063	/* Release Lock */
phungductung	0:e87aa4c49e95	2064	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	2065
phungductung	0:e87aa4c49e95	2066	return HAL_OK;
phungductung	0:e87aa4c49e95	2067	}
phungductung	0:e87aa4c49e95	2068
phungductung	0:e87aa4c49e95	2069	/**
phungductung	0:e87aa4c49e95	2070	* @brief Initializes the TIM One Pulse MSP.
phungductung	0:e87aa4c49e95	2071	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2072	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2073	* @retval None
phungductung	0:e87aa4c49e95	2074	*/
phungductung	0:e87aa4c49e95	2075	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2076	{
phungductung	0:e87aa4c49e95	2077	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	2078	UNUSED(htim);
phungductung	0:e87aa4c49e95	2079
phungductung	0:e87aa4c49e95	2080	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	2081	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
phungductung	0:e87aa4c49e95	2082	*/
phungductung	0:e87aa4c49e95	2083	}
phungductung	0:e87aa4c49e95	2084
phungductung	0:e87aa4c49e95	2085	/**
phungductung	0:e87aa4c49e95	2086	* @brief DeInitializes TIM One Pulse MSP.
phungductung	0:e87aa4c49e95	2087	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2088	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2089	* @retval None
phungductung	0:e87aa4c49e95	2090	*/
phungductung	0:e87aa4c49e95	2091	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2092	{
phungductung	0:e87aa4c49e95	2093	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	2094	UNUSED(htim);
phungductung	0:e87aa4c49e95	2095
phungductung	0:e87aa4c49e95	2096	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	2097	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
phungductung	0:e87aa4c49e95	2098	*/
phungductung	0:e87aa4c49e95	2099	}
phungductung	0:e87aa4c49e95	2100
phungductung	0:e87aa4c49e95	2101	/**
phungductung	0:e87aa4c49e95	2102	* @brief Starts the TIM One Pulse signal generation.
phungductung	0:e87aa4c49e95	2103	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2104	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2105	* @param OutputChannel : TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2106	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2107	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2108	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2109	* @retval HAL status
phungductung	0:e87aa4c49e95	2110	*/
phungductung	0:e87aa4c49e95	2111	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
phungductung	0:e87aa4c49e95	2112	{
phungductung	0:e87aa4c49e95	2113	/* Enable the Capture compare and the Input Capture channels
phungductung	0:e87aa4c49e95	2114	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	2115	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
phungductung	0:e87aa4c49e95	2116	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
phungductung	0:e87aa4c49e95	2117	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
phungductung	0:e87aa4c49e95	2118
phungductung	0:e87aa4c49e95	2119	No need to enable the counter, it's enabled automatically by hardware
phungductung	0:e87aa4c49e95	2120	(the counter starts in response to a stimulus and generate a pulse */
phungductung	0:e87aa4c49e95	2121
phungductung	0:e87aa4c49e95	2122	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2123	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2124
phungductung	0:e87aa4c49e95	2125	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	2126	{
phungductung	0:e87aa4c49e95	2127	/* Enable the main output */
phungductung	0:e87aa4c49e95	2128	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	2129	}
phungductung	0:e87aa4c49e95	2130
phungductung	0:e87aa4c49e95	2131	/* Return function status */
phungductung	0:e87aa4c49e95	2132	return HAL_OK;
phungductung	0:e87aa4c49e95	2133	}
phungductung	0:e87aa4c49e95	2134
phungductung	0:e87aa4c49e95	2135	/**
phungductung	0:e87aa4c49e95	2136	* @brief Stops the TIM One Pulse signal generation.
phungductung	0:e87aa4c49e95	2137	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2138	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2139	* @param OutputChannel : TIM Channels to be disable.
phungductung	0:e87aa4c49e95	2140	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2141	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2142	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2143	* @retval HAL status
phungductung	0:e87aa4c49e95	2144	*/
phungductung	0:e87aa4c49e95	2145	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
phungductung	0:e87aa4c49e95	2146	{
phungductung	0:e87aa4c49e95	2147	/* Disable the Capture compare and the Input Capture channels
phungductung	0:e87aa4c49e95	2148	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	2149	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
phungductung	0:e87aa4c49e95	2150	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
phungductung	0:e87aa4c49e95	2151	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
phungductung	0:e87aa4c49e95	2152
phungductung	0:e87aa4c49e95	2153	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2154	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2155
phungductung	0:e87aa4c49e95	2156	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	2157	{
phungductung	0:e87aa4c49e95	2158	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	2159	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	2160	}
phungductung	0:e87aa4c49e95	2161
phungductung	0:e87aa4c49e95	2162	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	2163	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2164
phungductung	0:e87aa4c49e95	2165	/* Return function status */
phungductung	0:e87aa4c49e95	2166	return HAL_OK;
phungductung	0:e87aa4c49e95	2167	}
phungductung	0:e87aa4c49e95	2168
phungductung	0:e87aa4c49e95	2169	/**
phungductung	0:e87aa4c49e95	2170	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
phungductung	0:e87aa4c49e95	2171	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2172	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2173	* @param OutputChannel : TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2174	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2175	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2176	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2177	* @retval HAL status
phungductung	0:e87aa4c49e95	2178	*/
phungductung	0:e87aa4c49e95	2179	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
phungductung	0:e87aa4c49e95	2180	{
phungductung	0:e87aa4c49e95	2181	/* Enable the Capture compare and the Input Capture channels
phungductung	0:e87aa4c49e95	2182	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	2183	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
phungductung	0:e87aa4c49e95	2184	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
phungductung	0:e87aa4c49e95	2185	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
phungductung	0:e87aa4c49e95	2186
phungductung	0:e87aa4c49e95	2187	No need to enable the counter, it's enabled automatically by hardware
phungductung	0:e87aa4c49e95	2188	(the counter starts in response to a stimulus and generate a pulse */
phungductung	0:e87aa4c49e95	2189
phungductung	0:e87aa4c49e95	2190	/* Enable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	2191	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2192
phungductung	0:e87aa4c49e95	2193	/* Enable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	2194	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2195
phungductung	0:e87aa4c49e95	2196	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2197	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2198
phungductung	0:e87aa4c49e95	2199	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	2200	{
phungductung	0:e87aa4c49e95	2201	/* Enable the main output */
phungductung	0:e87aa4c49e95	2202	__HAL_TIM_MOE_ENABLE(htim);
phungductung	0:e87aa4c49e95	2203	}
phungductung	0:e87aa4c49e95	2204
phungductung	0:e87aa4c49e95	2205	/* Return function status */
phungductung	0:e87aa4c49e95	2206	return HAL_OK;
phungductung	0:e87aa4c49e95	2207	}
phungductung	0:e87aa4c49e95	2208
phungductung	0:e87aa4c49e95	2209	/**
phungductung	0:e87aa4c49e95	2210	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
phungductung	0:e87aa4c49e95	2211	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2212	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2213	* @param OutputChannel : TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2214	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2215	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2216	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2217	* @retval HAL status
phungductung	0:e87aa4c49e95	2218	*/
phungductung	0:e87aa4c49e95	2219	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
phungductung	0:e87aa4c49e95	2220	{
phungductung	0:e87aa4c49e95	2221	/* Disable the TIM Capture/Compare 1 interrupt */
phungductung	0:e87aa4c49e95	2222	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2223
phungductung	0:e87aa4c49e95	2224	/* Disable the TIM Capture/Compare 2 interrupt */
phungductung	0:e87aa4c49e95	2225	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2226
phungductung	0:e87aa4c49e95	2227	/* Disable the Capture compare and the Input Capture channels
phungductung	0:e87aa4c49e95	2228	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	2229	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
phungductung	0:e87aa4c49e95	2230	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
phungductung	0:e87aa4c49e95	2231	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
phungductung	0:e87aa4c49e95	2232	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2233	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2234
phungductung	0:e87aa4c49e95	2235	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
phungductung	0:e87aa4c49e95	2236	{
phungductung	0:e87aa4c49e95	2237	/* Disable the Main Output */
phungductung	0:e87aa4c49e95	2238	__HAL_TIM_MOE_DISABLE(htim);
phungductung	0:e87aa4c49e95	2239	}
phungductung	0:e87aa4c49e95	2240
phungductung	0:e87aa4c49e95	2241	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	2242	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2243
phungductung	0:e87aa4c49e95	2244	/* Return function status */
phungductung	0:e87aa4c49e95	2245	return HAL_OK;
phungductung	0:e87aa4c49e95	2246	}
phungductung	0:e87aa4c49e95	2247
phungductung	0:e87aa4c49e95	2248	/**
phungductung	0:e87aa4c49e95	2249	* @}
phungductung	0:e87aa4c49e95	2250	*/
phungductung	0:e87aa4c49e95	2251
phungductung	0:e87aa4c49e95	2252	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
phungductung	0:e87aa4c49e95	2253	* @brief Time Encoder functions
phungductung	0:e87aa4c49e95	2254	*
phungductung	0:e87aa4c49e95	2255	@verbatim
phungductung	0:e87aa4c49e95	2256	==============================================================================
phungductung	0:e87aa4c49e95	2257	##### Time Encoder functions #####
phungductung	0:e87aa4c49e95	2258	==============================================================================
phungductung	0:e87aa4c49e95	2259	[..]
phungductung	0:e87aa4c49e95	2260	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	2261	(+) Initialize and configure the TIM Encoder.
phungductung	0:e87aa4c49e95	2262	(+) De-initialize the TIM Encoder.
phungductung	0:e87aa4c49e95	2263	(+) Start the Time Encoder.
phungductung	0:e87aa4c49e95	2264	(+) Stop the Time Encoder.
phungductung	0:e87aa4c49e95	2265	(+) Start the Time Encoder and enable interrupt.
phungductung	0:e87aa4c49e95	2266	(+) Stop the Time Encoder and disable interrupt.
phungductung	0:e87aa4c49e95	2267	(+) Start the Time Encoder and enable DMA transfer.
phungductung	0:e87aa4c49e95	2268	(+) Stop the Time Encoder and disable DMA transfer.
phungductung	0:e87aa4c49e95	2269
phungductung	0:e87aa4c49e95	2270	@endverbatim
phungductung	0:e87aa4c49e95	2271	* @{
phungductung	0:e87aa4c49e95	2272	*/
phungductung	0:e87aa4c49e95	2273	/**
phungductung	0:e87aa4c49e95	2274	* @brief Initializes the TIM Encoder Interface and create the associated handle.
phungductung	0:e87aa4c49e95	2275	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2276	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2277	* @param sConfig: TIM Encoder Interface configuration structure
phungductung	0:e87aa4c49e95	2278	* @retval HAL status
phungductung	0:e87aa4c49e95	2279	*/
phungductung	0:e87aa4c49e95	2280	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
phungductung	0:e87aa4c49e95	2281	{
phungductung	0:e87aa4c49e95	2282	uint32_t tmpsmcr = 0;
phungductung	0:e87aa4c49e95	2283	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	2284	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	2285
phungductung	0:e87aa4c49e95	2286	/* Check the TIM handle allocation */
phungductung	0:e87aa4c49e95	2287	if(htim == NULL)
phungductung	0:e87aa4c49e95	2288	{
phungductung	0:e87aa4c49e95	2289	return HAL_ERROR;
phungductung	0:e87aa4c49e95	2290	}
phungductung	0:e87aa4c49e95	2291
phungductung	0:e87aa4c49e95	2292	/* Check the parameters */
phungductung	0:e87aa4c49e95	2293	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2294	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
phungductung	0:e87aa4c49e95	2295	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
phungductung	0:e87aa4c49e95	2296	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
phungductung	0:e87aa4c49e95	2297	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
phungductung	0:e87aa4c49e95	2298	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
phungductung	0:e87aa4c49e95	2299	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
phungductung	0:e87aa4c49e95	2300	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
phungductung	0:e87aa4c49e95	2301	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
phungductung	0:e87aa4c49e95	2302	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
phungductung	0:e87aa4c49e95	2303
phungductung	0:e87aa4c49e95	2304	if(htim->State == HAL_TIM_STATE_RESET)
phungductung	0:e87aa4c49e95	2305	{
phungductung	0:e87aa4c49e95	2306	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	2307	htim->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	2308	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
phungductung	0:e87aa4c49e95	2309	HAL_TIM_Encoder_MspInit(htim);
phungductung	0:e87aa4c49e95	2310	}
phungductung	0:e87aa4c49e95	2311
phungductung	0:e87aa4c49e95	2312	/* Set the TIM state */
phungductung	0:e87aa4c49e95	2313	htim->State= HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	2314
phungductung	0:e87aa4c49e95	2315	/* Reset the SMS bits */
phungductung	0:e87aa4c49e95	2316	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
phungductung	0:e87aa4c49e95	2317
phungductung	0:e87aa4c49e95	2318	/* Configure the Time base in the Encoder Mode */
phungductung	0:e87aa4c49e95	2319	TIM_Base_SetConfig(htim->Instance, &htim->Init);
phungductung	0:e87aa4c49e95	2320
phungductung	0:e87aa4c49e95	2321	/* Get the TIMx SMCR register value */
phungductung	0:e87aa4c49e95	2322	tmpsmcr = htim->Instance->SMCR;
phungductung	0:e87aa4c49e95	2323
phungductung	0:e87aa4c49e95	2324	/* Get the TIMx CCMR1 register value */
phungductung	0:e87aa4c49e95	2325	tmpccmr1 = htim->Instance->CCMR1;
phungductung	0:e87aa4c49e95	2326
phungductung	0:e87aa4c49e95	2327	/* Get the TIMx CCER register value */
phungductung	0:e87aa4c49e95	2328	tmpccer = htim->Instance->CCER;
phungductung	0:e87aa4c49e95	2329
phungductung	0:e87aa4c49e95	2330	/* Set the encoder Mode */
phungductung	0:e87aa4c49e95	2331	tmpsmcr \|= sConfig->EncoderMode;
phungductung	0:e87aa4c49e95	2332
phungductung	0:e87aa4c49e95	2333	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
phungductung	0:e87aa4c49e95	2334	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
phungductung	0:e87aa4c49e95	2335	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
phungductung	0:e87aa4c49e95	2336
phungductung	0:e87aa4c49e95	2337	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
phungductung	0:e87aa4c49e95	2338	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
phungductung	0:e87aa4c49e95	2339	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
phungductung	0:e87aa4c49e95	2340	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
phungductung	0:e87aa4c49e95	2341	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
phungductung	0:e87aa4c49e95	2342
phungductung	0:e87aa4c49e95	2343	/* Set the TI1 and the TI2 Polarities */
phungductung	0:e87aa4c49e95	2344	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
phungductung	0:e87aa4c49e95	2345	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
phungductung	0:e87aa4c49e95	2346	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
phungductung	0:e87aa4c49e95	2347
phungductung	0:e87aa4c49e95	2348	/* Write to TIMx SMCR */
phungductung	0:e87aa4c49e95	2349	htim->Instance->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	2350
phungductung	0:e87aa4c49e95	2351	/* Write to TIMx CCMR1 */
phungductung	0:e87aa4c49e95	2352	htim->Instance->CCMR1 = tmpccmr1;
phungductung	0:e87aa4c49e95	2353
phungductung	0:e87aa4c49e95	2354	/* Write to TIMx CCER */
phungductung	0:e87aa4c49e95	2355	htim->Instance->CCER = tmpccer;
phungductung	0:e87aa4c49e95	2356
phungductung	0:e87aa4c49e95	2357	/* Initialize the TIM state*/
phungductung	0:e87aa4c49e95	2358	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	2359
phungductung	0:e87aa4c49e95	2360	return HAL_OK;
phungductung	0:e87aa4c49e95	2361	}
phungductung	0:e87aa4c49e95	2362
phungductung	0:e87aa4c49e95	2363	/**
phungductung	0:e87aa4c49e95	2364	* @brief DeInitializes the TIM Encoder interface
phungductung	0:e87aa4c49e95	2365	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2366	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2367	* @retval HAL status
phungductung	0:e87aa4c49e95	2368	*/
phungductung	0:e87aa4c49e95	2369	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2370	{
phungductung	0:e87aa4c49e95	2371	/* Check the parameters */
phungductung	0:e87aa4c49e95	2372	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2373
phungductung	0:e87aa4c49e95	2374	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	2375
phungductung	0:e87aa4c49e95	2376	/* Disable the TIM Peripheral Clock */
phungductung	0:e87aa4c49e95	2377	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2378
phungductung	0:e87aa4c49e95	2379	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
phungductung	0:e87aa4c49e95	2380	HAL_TIM_Encoder_MspDeInit(htim);
phungductung	0:e87aa4c49e95	2381
phungductung	0:e87aa4c49e95	2382	/* Change TIM state */
phungductung	0:e87aa4c49e95	2383	htim->State = HAL_TIM_STATE_RESET;
phungductung	0:e87aa4c49e95	2384
phungductung	0:e87aa4c49e95	2385	/* Release Lock */
phungductung	0:e87aa4c49e95	2386	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	2387
phungductung	0:e87aa4c49e95	2388	return HAL_OK;
phungductung	0:e87aa4c49e95	2389	}
phungductung	0:e87aa4c49e95	2390
phungductung	0:e87aa4c49e95	2391	/**
phungductung	0:e87aa4c49e95	2392	* @brief Initializes the TIM Encoder Interface MSP.
phungductung	0:e87aa4c49e95	2393	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2394	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2395	* @retval None
phungductung	0:e87aa4c49e95	2396	*/
phungductung	0:e87aa4c49e95	2397	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2398	{
phungductung	0:e87aa4c49e95	2399	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	2400	UNUSED(htim);
phungductung	0:e87aa4c49e95	2401
phungductung	0:e87aa4c49e95	2402	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	2403	the HAL_TIM_Encoder_MspInit could be implemented in the user file
phungductung	0:e87aa4c49e95	2404	*/
phungductung	0:e87aa4c49e95	2405	}
phungductung	0:e87aa4c49e95	2406
phungductung	0:e87aa4c49e95	2407	/**
phungductung	0:e87aa4c49e95	2408	* @brief DeInitializes TIM Encoder Interface MSP.
phungductung	0:e87aa4c49e95	2409	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2410	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2411	* @retval None
phungductung	0:e87aa4c49e95	2412	*/
phungductung	0:e87aa4c49e95	2413	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2414	{
phungductung	0:e87aa4c49e95	2415	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	2416	UNUSED(htim);
phungductung	0:e87aa4c49e95	2417
phungductung	0:e87aa4c49e95	2418	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	2419	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
phungductung	0:e87aa4c49e95	2420	*/
phungductung	0:e87aa4c49e95	2421	}
phungductung	0:e87aa4c49e95	2422
phungductung	0:e87aa4c49e95	2423	/**
phungductung	0:e87aa4c49e95	2424	* @brief Starts the TIM Encoder Interface.
phungductung	0:e87aa4c49e95	2425	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2426	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2427	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2428	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2429	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2430	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2431	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
phungductung	0:e87aa4c49e95	2432	* @retval HAL status
phungductung	0:e87aa4c49e95	2433	*/
phungductung	0:e87aa4c49e95	2434	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	2435	{
phungductung	0:e87aa4c49e95	2436	/* Check the parameters */
phungductung	0:e87aa4c49e95	2437	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2438
phungductung	0:e87aa4c49e95	2439	/* Enable the encoder interface channels */
phungductung	0:e87aa4c49e95	2440	switch (Channel)
phungductung	0:e87aa4c49e95	2441	{
phungductung	0:e87aa4c49e95	2442	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	2443	{
phungductung	0:e87aa4c49e95	2444	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2445	break;
phungductung	0:e87aa4c49e95	2446	}
phungductung	0:e87aa4c49e95	2447	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	2448	{
phungductung	0:e87aa4c49e95	2449	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2450	break;
phungductung	0:e87aa4c49e95	2451	}
phungductung	0:e87aa4c49e95	2452	default :
phungductung	0:e87aa4c49e95	2453	{
phungductung	0:e87aa4c49e95	2454	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2455	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2456	break;
phungductung	0:e87aa4c49e95	2457	}
phungductung	0:e87aa4c49e95	2458	}
phungductung	0:e87aa4c49e95	2459	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	2460	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	2461
phungductung	0:e87aa4c49e95	2462	/* Return function status */
phungductung	0:e87aa4c49e95	2463	return HAL_OK;
phungductung	0:e87aa4c49e95	2464	}
phungductung	0:e87aa4c49e95	2465
phungductung	0:e87aa4c49e95	2466	/**
phungductung	0:e87aa4c49e95	2467	* @brief Stops the TIM Encoder Interface.
phungductung	0:e87aa4c49e95	2468	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2469	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2470	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	2471	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2472	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2473	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2474	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
phungductung	0:e87aa4c49e95	2475	* @retval HAL status
phungductung	0:e87aa4c49e95	2476	*/
phungductung	0:e87aa4c49e95	2477	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	2478	{
phungductung	0:e87aa4c49e95	2479	/* Check the parameters */
phungductung	0:e87aa4c49e95	2480	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2481
phungductung	0:e87aa4c49e95	2482	/* Disable the Input Capture channels 1 and 2
phungductung	0:e87aa4c49e95	2483	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
phungductung	0:e87aa4c49e95	2484	switch (Channel)
phungductung	0:e87aa4c49e95	2485	{
phungductung	0:e87aa4c49e95	2486	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	2487	{
phungductung	0:e87aa4c49e95	2488	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2489	break;
phungductung	0:e87aa4c49e95	2490	}
phungductung	0:e87aa4c49e95	2491	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	2492	{
phungductung	0:e87aa4c49e95	2493	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2494	break;
phungductung	0:e87aa4c49e95	2495	}
phungductung	0:e87aa4c49e95	2496	default :
phungductung	0:e87aa4c49e95	2497	{
phungductung	0:e87aa4c49e95	2498	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2499	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2500	break;
phungductung	0:e87aa4c49e95	2501	}
phungductung	0:e87aa4c49e95	2502	}
phungductung	0:e87aa4c49e95	2503	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	2504	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2505
phungductung	0:e87aa4c49e95	2506	/* Return function status */
phungductung	0:e87aa4c49e95	2507	return HAL_OK;
phungductung	0:e87aa4c49e95	2508	}
phungductung	0:e87aa4c49e95	2509
phungductung	0:e87aa4c49e95	2510	/**
phungductung	0:e87aa4c49e95	2511	* @brief Starts the TIM Encoder Interface in interrupt mode.
phungductung	0:e87aa4c49e95	2512	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2513	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2514	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2515	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2516	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2517	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2518	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
phungductung	0:e87aa4c49e95	2519	* @retval HAL status
phungductung	0:e87aa4c49e95	2520	*/
phungductung	0:e87aa4c49e95	2521	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	2522	{
phungductung	0:e87aa4c49e95	2523	/* Check the parameters */
phungductung	0:e87aa4c49e95	2524	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2525
phungductung	0:e87aa4c49e95	2526	/* Enable the encoder interface channels */
phungductung	0:e87aa4c49e95	2527	/* Enable the capture compare Interrupts 1 and/or 2 */
phungductung	0:e87aa4c49e95	2528	switch (Channel)
phungductung	0:e87aa4c49e95	2529	{
phungductung	0:e87aa4c49e95	2530	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	2531	{
phungductung	0:e87aa4c49e95	2532	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2533	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2534	break;
phungductung	0:e87aa4c49e95	2535	}
phungductung	0:e87aa4c49e95	2536	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	2537	{
phungductung	0:e87aa4c49e95	2538	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2539	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2540	break;
phungductung	0:e87aa4c49e95	2541	}
phungductung	0:e87aa4c49e95	2542	default :
phungductung	0:e87aa4c49e95	2543	{
phungductung	0:e87aa4c49e95	2544	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2545	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2546	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2547	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2548	break;
phungductung	0:e87aa4c49e95	2549	}
phungductung	0:e87aa4c49e95	2550	}
phungductung	0:e87aa4c49e95	2551
phungductung	0:e87aa4c49e95	2552	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	2553	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	2554
phungductung	0:e87aa4c49e95	2555	/* Return function status */
phungductung	0:e87aa4c49e95	2556	return HAL_OK;
phungductung	0:e87aa4c49e95	2557	}
phungductung	0:e87aa4c49e95	2558
phungductung	0:e87aa4c49e95	2559	/**
phungductung	0:e87aa4c49e95	2560	* @brief Stops the TIM Encoder Interface in interrupt mode.
phungductung	0:e87aa4c49e95	2561	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2562	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2563	* @param Channel: TIM Channels to be disabled.
phungductung	0:e87aa4c49e95	2564	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2565	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2566	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2567	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
phungductung	0:e87aa4c49e95	2568	* @retval HAL status
phungductung	0:e87aa4c49e95	2569	*/
phungductung	0:e87aa4c49e95	2570	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	2571	{
phungductung	0:e87aa4c49e95	2572	/* Check the parameters */
phungductung	0:e87aa4c49e95	2573	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2574
phungductung	0:e87aa4c49e95	2575	/* Disable the Input Capture channels 1 and 2
phungductung	0:e87aa4c49e95	2576	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
phungductung	0:e87aa4c49e95	2577	if(Channel == TIM_CHANNEL_1)
phungductung	0:e87aa4c49e95	2578	{
phungductung	0:e87aa4c49e95	2579	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2580
phungductung	0:e87aa4c49e95	2581	/* Disable the capture compare Interrupts 1 */
phungductung	0:e87aa4c49e95	2582	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2583	}
phungductung	0:e87aa4c49e95	2584	else if(Channel == TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	2585	{
phungductung	0:e87aa4c49e95	2586	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2587
phungductung	0:e87aa4c49e95	2588	/* Disable the capture compare Interrupts 2 */
phungductung	0:e87aa4c49e95	2589	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2590	}
phungductung	0:e87aa4c49e95	2591	else
phungductung	0:e87aa4c49e95	2592	{
phungductung	0:e87aa4c49e95	2593	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2594	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2595
phungductung	0:e87aa4c49e95	2596	/* Disable the capture compare Interrupts 1 and 2 */
phungductung	0:e87aa4c49e95	2597	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2598	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2599	}
phungductung	0:e87aa4c49e95	2600
phungductung	0:e87aa4c49e95	2601	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	2602	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2603
phungductung	0:e87aa4c49e95	2604	/* Change the htim state */
phungductung	0:e87aa4c49e95	2605	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	2606
phungductung	0:e87aa4c49e95	2607	/* Return function status */
phungductung	0:e87aa4c49e95	2608	return HAL_OK;
phungductung	0:e87aa4c49e95	2609	}
phungductung	0:e87aa4c49e95	2610
phungductung	0:e87aa4c49e95	2611	/**
phungductung	0:e87aa4c49e95	2612	* @brief Starts the TIM Encoder Interface in DMA mode.
phungductung	0:e87aa4c49e95	2613	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2614	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2615	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2616	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2617	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2618	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2619	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
phungductung	0:e87aa4c49e95	2620	* @param pData1: The destination Buffer address for IC1.
phungductung	0:e87aa4c49e95	2621	* @param pData2: The destination Buffer address for IC2.
phungductung	0:e87aa4c49e95	2622	* @param Length: The length of data to be transferred from TIM peripheral to memory.
phungductung	0:e87aa4c49e95	2623	* @retval HAL status
phungductung	0:e87aa4c49e95	2624	*/
phungductung	0:e87aa4c49e95	2625	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
phungductung	0:e87aa4c49e95	2626	{
phungductung	0:e87aa4c49e95	2627	/* Check the parameters */
phungductung	0:e87aa4c49e95	2628	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2629
phungductung	0:e87aa4c49e95	2630	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	2631	{
phungductung	0:e87aa4c49e95	2632	return HAL_BUSY;
phungductung	0:e87aa4c49e95	2633	}
phungductung	0:e87aa4c49e95	2634	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	2635	{
phungductung	0:e87aa4c49e95	2636	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
phungductung	0:e87aa4c49e95	2637	{
phungductung	0:e87aa4c49e95	2638	return HAL_ERROR;
phungductung	0:e87aa4c49e95	2639	}
phungductung	0:e87aa4c49e95	2640	else
phungductung	0:e87aa4c49e95	2641	{
phungductung	0:e87aa4c49e95	2642	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	2643	}
phungductung	0:e87aa4c49e95	2644	}
phungductung	0:e87aa4c49e95	2645
phungductung	0:e87aa4c49e95	2646	switch (Channel)
phungductung	0:e87aa4c49e95	2647	{
phungductung	0:e87aa4c49e95	2648	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	2649	{
phungductung	0:e87aa4c49e95	2650	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	2651	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	2652
phungductung	0:e87aa4c49e95	2653	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	2654	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	2655
phungductung	0:e87aa4c49e95	2656	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	2657	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
phungductung	0:e87aa4c49e95	2658
phungductung	0:e87aa4c49e95	2659	/* Enable the TIM Input Capture DMA request */
phungductung	0:e87aa4c49e95	2660	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	2661
phungductung	0:e87aa4c49e95	2662	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	2663	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	2664
phungductung	0:e87aa4c49e95	2665	/* Enable the Capture compare channel */
phungductung	0:e87aa4c49e95	2666	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2667	}
phungductung	0:e87aa4c49e95	2668	break;
phungductung	0:e87aa4c49e95	2669
phungductung	0:e87aa4c49e95	2670	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	2671	{
phungductung	0:e87aa4c49e95	2672	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	2673	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	2674
phungductung	0:e87aa4c49e95	2675	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	2676	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
phungductung	0:e87aa4c49e95	2677	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	2678	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
phungductung	0:e87aa4c49e95	2679
phungductung	0:e87aa4c49e95	2680	/* Enable the TIM Input Capture DMA request */
phungductung	0:e87aa4c49e95	2681	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	2682
phungductung	0:e87aa4c49e95	2683	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	2684	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	2685
phungductung	0:e87aa4c49e95	2686	/* Enable the Capture compare channel */
phungductung	0:e87aa4c49e95	2687	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2688	}
phungductung	0:e87aa4c49e95	2689	break;
phungductung	0:e87aa4c49e95	2690
phungductung	0:e87aa4c49e95	2691	case TIM_CHANNEL_ALL:
phungductung	0:e87aa4c49e95	2692	{
phungductung	0:e87aa4c49e95	2693	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	2694	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	2695
phungductung	0:e87aa4c49e95	2696	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	2697	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	2698
phungductung	0:e87aa4c49e95	2699	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	2700	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
phungductung	0:e87aa4c49e95	2701
phungductung	0:e87aa4c49e95	2702	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	2703	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	2704
phungductung	0:e87aa4c49e95	2705	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	2706	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	2707
phungductung	0:e87aa4c49e95	2708	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	2709	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
phungductung	0:e87aa4c49e95	2710
phungductung	0:e87aa4c49e95	2711	/* Enable the Peripheral */
phungductung	0:e87aa4c49e95	2712	__HAL_TIM_ENABLE(htim);
phungductung	0:e87aa4c49e95	2713
phungductung	0:e87aa4c49e95	2714	/* Enable the Capture compare channel */
phungductung	0:e87aa4c49e95	2715	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2716	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
phungductung	0:e87aa4c49e95	2717
phungductung	0:e87aa4c49e95	2718	/* Enable the TIM Input Capture DMA request */
phungductung	0:e87aa4c49e95	2719	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	2720	/* Enable the TIM Input Capture DMA request */
phungductung	0:e87aa4c49e95	2721	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	2722	}
phungductung	0:e87aa4c49e95	2723	break;
phungductung	0:e87aa4c49e95	2724
phungductung	0:e87aa4c49e95	2725	default:
phungductung	0:e87aa4c49e95	2726	break;
phungductung	0:e87aa4c49e95	2727	}
phungductung	0:e87aa4c49e95	2728	/* Return function status */
phungductung	0:e87aa4c49e95	2729	return HAL_OK;
phungductung	0:e87aa4c49e95	2730	}
phungductung	0:e87aa4c49e95	2731
phungductung	0:e87aa4c49e95	2732	/**
phungductung	0:e87aa4c49e95	2733	* @brief Stops the TIM Encoder Interface in DMA mode.
phungductung	0:e87aa4c49e95	2734	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2735	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2736	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2737	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2738	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2739	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2740	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
phungductung	0:e87aa4c49e95	2741	* @retval HAL status
phungductung	0:e87aa4c49e95	2742	*/
phungductung	0:e87aa4c49e95	2743	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	2744	{
phungductung	0:e87aa4c49e95	2745	/* Check the parameters */
phungductung	0:e87aa4c49e95	2746	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2747
phungductung	0:e87aa4c49e95	2748	/* Disable the Input Capture channels 1 and 2
phungductung	0:e87aa4c49e95	2749	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
phungductung	0:e87aa4c49e95	2750	if(Channel == TIM_CHANNEL_1)
phungductung	0:e87aa4c49e95	2751	{
phungductung	0:e87aa4c49e95	2752	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2753
phungductung	0:e87aa4c49e95	2754	/* Disable the capture compare DMA Request 1 */
phungductung	0:e87aa4c49e95	2755	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	2756	}
phungductung	0:e87aa4c49e95	2757	else if(Channel == TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	2758	{
phungductung	0:e87aa4c49e95	2759	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2760
phungductung	0:e87aa4c49e95	2761	/* Disable the capture compare DMA Request 2 */
phungductung	0:e87aa4c49e95	2762	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	2763	}
phungductung	0:e87aa4c49e95	2764	else
phungductung	0:e87aa4c49e95	2765	{
phungductung	0:e87aa4c49e95	2766	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2767	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
phungductung	0:e87aa4c49e95	2768
phungductung	0:e87aa4c49e95	2769	/* Disable the capture compare DMA Request 1 and 2 */
phungductung	0:e87aa4c49e95	2770	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
phungductung	0:e87aa4c49e95	2771	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
phungductung	0:e87aa4c49e95	2772	}
phungductung	0:e87aa4c49e95	2773
phungductung	0:e87aa4c49e95	2774	/* Disable the Peripheral */
phungductung	0:e87aa4c49e95	2775	__HAL_TIM_DISABLE(htim);
phungductung	0:e87aa4c49e95	2776
phungductung	0:e87aa4c49e95	2777	/* Change the htim state */
phungductung	0:e87aa4c49e95	2778	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	2779
phungductung	0:e87aa4c49e95	2780	/* Return function status */
phungductung	0:e87aa4c49e95	2781	return HAL_OK;
phungductung	0:e87aa4c49e95	2782	}
phungductung	0:e87aa4c49e95	2783
phungductung	0:e87aa4c49e95	2784	/**
phungductung	0:e87aa4c49e95	2785	* @}
phungductung	0:e87aa4c49e95	2786	*/
phungductung	0:e87aa4c49e95	2787	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
phungductung	0:e87aa4c49e95	2788	* @brief IRQ handler management
phungductung	0:e87aa4c49e95	2789	*
phungductung	0:e87aa4c49e95	2790	@verbatim
phungductung	0:e87aa4c49e95	2791	==============================================================================
phungductung	0:e87aa4c49e95	2792	##### IRQ handler management #####
phungductung	0:e87aa4c49e95	2793	==============================================================================
phungductung	0:e87aa4c49e95	2794	[..]
phungductung	0:e87aa4c49e95	2795	This section provides Timer IRQ handler function.
phungductung	0:e87aa4c49e95	2796
phungductung	0:e87aa4c49e95	2797	@endverbatim
phungductung	0:e87aa4c49e95	2798	* @{
phungductung	0:e87aa4c49e95	2799	*/
phungductung	0:e87aa4c49e95	2800	/**
phungductung	0:e87aa4c49e95	2801	* @brief This function handles TIM interrupts requests.
phungductung	0:e87aa4c49e95	2802	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2803	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2804	* @retval None
phungductung	0:e87aa4c49e95	2805	*/
phungductung	0:e87aa4c49e95	2806	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	2807	{
phungductung	0:e87aa4c49e95	2808	/* Capture compare 1 event */
phungductung	0:e87aa4c49e95	2809	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
phungductung	0:e87aa4c49e95	2810	{
phungductung	0:e87aa4c49e95	2811	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
phungductung	0:e87aa4c49e95	2812	{
phungductung	0:e87aa4c49e95	2813	{
phungductung	0:e87aa4c49e95	2814	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
phungductung	0:e87aa4c49e95	2815	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
phungductung	0:e87aa4c49e95	2816
phungductung	0:e87aa4c49e95	2817	/* Input capture event */
phungductung	0:e87aa4c49e95	2818	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
phungductung	0:e87aa4c49e95	2819	{
phungductung	0:e87aa4c49e95	2820	HAL_TIM_IC_CaptureCallback(htim);
phungductung	0:e87aa4c49e95	2821	}
phungductung	0:e87aa4c49e95	2822	/* Output compare event */
phungductung	0:e87aa4c49e95	2823	else
phungductung	0:e87aa4c49e95	2824	{
phungductung	0:e87aa4c49e95	2825	HAL_TIM_OC_DelayElapsedCallback(htim);
phungductung	0:e87aa4c49e95	2826	HAL_TIM_PWM_PulseFinishedCallback(htim);
phungductung	0:e87aa4c49e95	2827	}
phungductung	0:e87aa4c49e95	2828	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
phungductung	0:e87aa4c49e95	2829	}
phungductung	0:e87aa4c49e95	2830	}
phungductung	0:e87aa4c49e95	2831	}
phungductung	0:e87aa4c49e95	2832	/* Capture compare 2 event */
phungductung	0:e87aa4c49e95	2833	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
phungductung	0:e87aa4c49e95	2834	{
phungductung	0:e87aa4c49e95	2835	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
phungductung	0:e87aa4c49e95	2836	{
phungductung	0:e87aa4c49e95	2837	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
phungductung	0:e87aa4c49e95	2838	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
phungductung	0:e87aa4c49e95	2839	/* Input capture event */
phungductung	0:e87aa4c49e95	2840	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
phungductung	0:e87aa4c49e95	2841	{
phungductung	0:e87aa4c49e95	2842	HAL_TIM_IC_CaptureCallback(htim);
phungductung	0:e87aa4c49e95	2843	}
phungductung	0:e87aa4c49e95	2844	/* Output compare event */
phungductung	0:e87aa4c49e95	2845	else
phungductung	0:e87aa4c49e95	2846	{
phungductung	0:e87aa4c49e95	2847	HAL_TIM_OC_DelayElapsedCallback(htim);
phungductung	0:e87aa4c49e95	2848	HAL_TIM_PWM_PulseFinishedCallback(htim);
phungductung	0:e87aa4c49e95	2849	}
phungductung	0:e87aa4c49e95	2850	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
phungductung	0:e87aa4c49e95	2851	}
phungductung	0:e87aa4c49e95	2852	}
phungductung	0:e87aa4c49e95	2853	/* Capture compare 3 event */
phungductung	0:e87aa4c49e95	2854	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
phungductung	0:e87aa4c49e95	2855	{
phungductung	0:e87aa4c49e95	2856	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
phungductung	0:e87aa4c49e95	2857	{
phungductung	0:e87aa4c49e95	2858	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
phungductung	0:e87aa4c49e95	2859	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
phungductung	0:e87aa4c49e95	2860	/* Input capture event */
phungductung	0:e87aa4c49e95	2861	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
phungductung	0:e87aa4c49e95	2862	{
phungductung	0:e87aa4c49e95	2863	HAL_TIM_IC_CaptureCallback(htim);
phungductung	0:e87aa4c49e95	2864	}
phungductung	0:e87aa4c49e95	2865	/* Output compare event */
phungductung	0:e87aa4c49e95	2866	else
phungductung	0:e87aa4c49e95	2867	{
phungductung	0:e87aa4c49e95	2868	HAL_TIM_OC_DelayElapsedCallback(htim);
phungductung	0:e87aa4c49e95	2869	HAL_TIM_PWM_PulseFinishedCallback(htim);
phungductung	0:e87aa4c49e95	2870	}
phungductung	0:e87aa4c49e95	2871	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
phungductung	0:e87aa4c49e95	2872	}
phungductung	0:e87aa4c49e95	2873	}
phungductung	0:e87aa4c49e95	2874	/* Capture compare 4 event */
phungductung	0:e87aa4c49e95	2875	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
phungductung	0:e87aa4c49e95	2876	{
phungductung	0:e87aa4c49e95	2877	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
phungductung	0:e87aa4c49e95	2878	{
phungductung	0:e87aa4c49e95	2879	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
phungductung	0:e87aa4c49e95	2880	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
phungductung	0:e87aa4c49e95	2881	/* Input capture event */
phungductung	0:e87aa4c49e95	2882	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
phungductung	0:e87aa4c49e95	2883	{
phungductung	0:e87aa4c49e95	2884	HAL_TIM_IC_CaptureCallback(htim);
phungductung	0:e87aa4c49e95	2885	}
phungductung	0:e87aa4c49e95	2886	/* Output compare event */
phungductung	0:e87aa4c49e95	2887	else
phungductung	0:e87aa4c49e95	2888	{
phungductung	0:e87aa4c49e95	2889	HAL_TIM_OC_DelayElapsedCallback(htim);
phungductung	0:e87aa4c49e95	2890	HAL_TIM_PWM_PulseFinishedCallback(htim);
phungductung	0:e87aa4c49e95	2891	}
phungductung	0:e87aa4c49e95	2892	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
phungductung	0:e87aa4c49e95	2893	}
phungductung	0:e87aa4c49e95	2894	}
phungductung	0:e87aa4c49e95	2895	/* TIM Update event */
phungductung	0:e87aa4c49e95	2896	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
phungductung	0:e87aa4c49e95	2897	{
phungductung	0:e87aa4c49e95	2898	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
phungductung	0:e87aa4c49e95	2899	{
phungductung	0:e87aa4c49e95	2900	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
phungductung	0:e87aa4c49e95	2901	HAL_TIM_PeriodElapsedCallback(htim);
phungductung	0:e87aa4c49e95	2902	}
phungductung	0:e87aa4c49e95	2903	}
phungductung	0:e87aa4c49e95	2904	/* TIM Break input event */
phungductung	0:e87aa4c49e95	2905	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
phungductung	0:e87aa4c49e95	2906	{
phungductung	0:e87aa4c49e95	2907	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
phungductung	0:e87aa4c49e95	2908	{
phungductung	0:e87aa4c49e95	2909	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
phungductung	0:e87aa4c49e95	2910	HAL_TIMEx_BreakCallback(htim);
phungductung	0:e87aa4c49e95	2911	}
phungductung	0:e87aa4c49e95	2912	}
phungductung	0:e87aa4c49e95	2913
phungductung	0:e87aa4c49e95	2914	/* TIM Break input event */
phungductung	0:e87aa4c49e95	2915	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
phungductung	0:e87aa4c49e95	2916	{
phungductung	0:e87aa4c49e95	2917	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
phungductung	0:e87aa4c49e95	2918	{
phungductung	0:e87aa4c49e95	2919	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
phungductung	0:e87aa4c49e95	2920	HAL_TIMEx_BreakCallback(htim);
phungductung	0:e87aa4c49e95	2921	}
phungductung	0:e87aa4c49e95	2922	}
phungductung	0:e87aa4c49e95	2923
phungductung	0:e87aa4c49e95	2924	/* TIM Trigger detection event */
phungductung	0:e87aa4c49e95	2925	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
phungductung	0:e87aa4c49e95	2926	{
phungductung	0:e87aa4c49e95	2927	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
phungductung	0:e87aa4c49e95	2928	{
phungductung	0:e87aa4c49e95	2929	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
phungductung	0:e87aa4c49e95	2930	HAL_TIM_TriggerCallback(htim);
phungductung	0:e87aa4c49e95	2931	}
phungductung	0:e87aa4c49e95	2932	}
phungductung	0:e87aa4c49e95	2933	/* TIM commutation event */
phungductung	0:e87aa4c49e95	2934	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
phungductung	0:e87aa4c49e95	2935	{
phungductung	0:e87aa4c49e95	2936	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
phungductung	0:e87aa4c49e95	2937	{
phungductung	0:e87aa4c49e95	2938	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
phungductung	0:e87aa4c49e95	2939	HAL_TIMEx_CommutationCallback(htim);
phungductung	0:e87aa4c49e95	2940	}
phungductung	0:e87aa4c49e95	2941	}
phungductung	0:e87aa4c49e95	2942	}
phungductung	0:e87aa4c49e95	2943
phungductung	0:e87aa4c49e95	2944	/**
phungductung	0:e87aa4c49e95	2945	* @}
phungductung	0:e87aa4c49e95	2946	*/
phungductung	0:e87aa4c49e95	2947
phungductung	0:e87aa4c49e95	2948	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
phungductung	0:e87aa4c49e95	2949	* @brief Peripheral Control functions
phungductung	0:e87aa4c49e95	2950	*
phungductung	0:e87aa4c49e95	2951	@verbatim
phungductung	0:e87aa4c49e95	2952	==============================================================================
phungductung	0:e87aa4c49e95	2953	##### Peripheral Control functions #####
phungductung	0:e87aa4c49e95	2954	==============================================================================
phungductung	0:e87aa4c49e95	2955	[..]
phungductung	0:e87aa4c49e95	2956	This section provides functions allowing to:
phungductung	0:e87aa4c49e95	2957	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
phungductung	0:e87aa4c49e95	2958	(+) Configure External Clock source.
phungductung	0:e87aa4c49e95	2959	(+) Configure Complementary channels, break features and dead time.
phungductung	0:e87aa4c49e95	2960	(+) Configure Master and the Slave synchronization.
phungductung	0:e87aa4c49e95	2961	(+) Configure the DMA Burst Mode.
phungductung	0:e87aa4c49e95	2962
phungductung	0:e87aa4c49e95	2963	@endverbatim
phungductung	0:e87aa4c49e95	2964	* @{
phungductung	0:e87aa4c49e95	2965	*/
phungductung	0:e87aa4c49e95	2966
phungductung	0:e87aa4c49e95	2967	/**
phungductung	0:e87aa4c49e95	2968	* @brief Initializes the TIM Output Compare Channels according to the specified
phungductung	0:e87aa4c49e95	2969	* parameters in the TIM_OC_InitTypeDef.
phungductung	0:e87aa4c49e95	2970	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2971	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	2972	* @param sConfig: TIM Output Compare configuration structure
phungductung	0:e87aa4c49e95	2973	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	2974	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2975	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	2976	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	2977	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	2978	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	2979	* @retval HAL status
phungductung	0:e87aa4c49e95	2980	*/
phungductung	0:e87aa4c49e95	2981	__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
phungductung	0:e87aa4c49e95	2982	{
phungductung	0:e87aa4c49e95	2983	/* Check the parameters */
phungductung	0:e87aa4c49e95	2984	assert_param(IS_TIM_CHANNELS(Channel));
phungductung	0:e87aa4c49e95	2985	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
phungductung	0:e87aa4c49e95	2986	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
phungductung	0:e87aa4c49e95	2987
phungductung	0:e87aa4c49e95	2988	/* Check input state */
phungductung	0:e87aa4c49e95	2989	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	2990
phungductung	0:e87aa4c49e95	2991	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	2992
phungductung	0:e87aa4c49e95	2993	switch (Channel)
phungductung	0:e87aa4c49e95	2994	{
phungductung	0:e87aa4c49e95	2995	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	2996	{
phungductung	0:e87aa4c49e95	2997	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	2998	/* Configure the TIM Channel 1 in Output Compare */
phungductung	0:e87aa4c49e95	2999	TIM_OC1_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3000	}
phungductung	0:e87aa4c49e95	3001	break;
phungductung	0:e87aa4c49e95	3002
phungductung	0:e87aa4c49e95	3003	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	3004	{
phungductung	0:e87aa4c49e95	3005	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3006	/* Configure the TIM Channel 2 in Output Compare */
phungductung	0:e87aa4c49e95	3007	TIM_OC2_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3008	}
phungductung	0:e87aa4c49e95	3009	break;
phungductung	0:e87aa4c49e95	3010
phungductung	0:e87aa4c49e95	3011	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	3012	{
phungductung	0:e87aa4c49e95	3013	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3014	/* Configure the TIM Channel 3 in Output Compare */
phungductung	0:e87aa4c49e95	3015	TIM_OC3_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3016	}
phungductung	0:e87aa4c49e95	3017	break;
phungductung	0:e87aa4c49e95	3018
phungductung	0:e87aa4c49e95	3019	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	3020	{
phungductung	0:e87aa4c49e95	3021	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3022	/* Configure the TIM Channel 4 in Output Compare */
phungductung	0:e87aa4c49e95	3023	TIM_OC4_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3024	}
phungductung	0:e87aa4c49e95	3025	break;
phungductung	0:e87aa4c49e95	3026
phungductung	0:e87aa4c49e95	3027	default:
phungductung	0:e87aa4c49e95	3028	break;
phungductung	0:e87aa4c49e95	3029	}
phungductung	0:e87aa4c49e95	3030	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3031
phungductung	0:e87aa4c49e95	3032	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	3033
phungductung	0:e87aa4c49e95	3034	return HAL_OK;
phungductung	0:e87aa4c49e95	3035	}
phungductung	0:e87aa4c49e95	3036
phungductung	0:e87aa4c49e95	3037	/**
phungductung	0:e87aa4c49e95	3038	* @brief Initializes the TIM Input Capture Channels according to the specified
phungductung	0:e87aa4c49e95	3039	* parameters in the TIM_IC_InitTypeDef.
phungductung	0:e87aa4c49e95	3040	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3041	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3042	* @param sConfig: TIM Input Capture configuration structure
phungductung	0:e87aa4c49e95	3043	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	3044	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	3045	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	3046	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	3047	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	3048	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	3049	* @retval HAL status
phungductung	0:e87aa4c49e95	3050	*/
phungductung	0:e87aa4c49e95	3051	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
phungductung	0:e87aa4c49e95	3052	{
phungductung	0:e87aa4c49e95	3053	/* Check the parameters */
phungductung	0:e87aa4c49e95	3054	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3055	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
phungductung	0:e87aa4c49e95	3056	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
phungductung	0:e87aa4c49e95	3057	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
phungductung	0:e87aa4c49e95	3058	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
phungductung	0:e87aa4c49e95	3059
phungductung	0:e87aa4c49e95	3060	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	3061
phungductung	0:e87aa4c49e95	3062	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3063
phungductung	0:e87aa4c49e95	3064	if (Channel == TIM_CHANNEL_1)
phungductung	0:e87aa4c49e95	3065	{
phungductung	0:e87aa4c49e95	3066	/* TI1 Configuration */
phungductung	0:e87aa4c49e95	3067	TIM_TI1_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	3068	sConfig->ICPolarity,
phungductung	0:e87aa4c49e95	3069	sConfig->ICSelection,
phungductung	0:e87aa4c49e95	3070	sConfig->ICFilter);
phungductung	0:e87aa4c49e95	3071
phungductung	0:e87aa4c49e95	3072	/* Reset the IC1PSC Bits */
phungductung	0:e87aa4c49e95	3073	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
phungductung	0:e87aa4c49e95	3074
phungductung	0:e87aa4c49e95	3075	/* Set the IC1PSC value */
phungductung	0:e87aa4c49e95	3076	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
phungductung	0:e87aa4c49e95	3077	}
phungductung	0:e87aa4c49e95	3078	else if (Channel == TIM_CHANNEL_2)
phungductung	0:e87aa4c49e95	3079	{
phungductung	0:e87aa4c49e95	3080	/* TI2 Configuration */
phungductung	0:e87aa4c49e95	3081	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3082
phungductung	0:e87aa4c49e95	3083	TIM_TI2_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	3084	sConfig->ICPolarity,
phungductung	0:e87aa4c49e95	3085	sConfig->ICSelection,
phungductung	0:e87aa4c49e95	3086	sConfig->ICFilter);
phungductung	0:e87aa4c49e95	3087
phungductung	0:e87aa4c49e95	3088	/* Reset the IC2PSC Bits */
phungductung	0:e87aa4c49e95	3089	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
phungductung	0:e87aa4c49e95	3090
phungductung	0:e87aa4c49e95	3091	/* Set the IC2PSC value */
phungductung	0:e87aa4c49e95	3092	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
phungductung	0:e87aa4c49e95	3093	}
phungductung	0:e87aa4c49e95	3094	else if (Channel == TIM_CHANNEL_3)
phungductung	0:e87aa4c49e95	3095	{
phungductung	0:e87aa4c49e95	3096	/* TI3 Configuration */
phungductung	0:e87aa4c49e95	3097	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3098
phungductung	0:e87aa4c49e95	3099	TIM_TI3_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	3100	sConfig->ICPolarity,
phungductung	0:e87aa4c49e95	3101	sConfig->ICSelection,
phungductung	0:e87aa4c49e95	3102	sConfig->ICFilter);
phungductung	0:e87aa4c49e95	3103
phungductung	0:e87aa4c49e95	3104	/* Reset the IC3PSC Bits */
phungductung	0:e87aa4c49e95	3105	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
phungductung	0:e87aa4c49e95	3106
phungductung	0:e87aa4c49e95	3107	/* Set the IC3PSC value */
phungductung	0:e87aa4c49e95	3108	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
phungductung	0:e87aa4c49e95	3109	}
phungductung	0:e87aa4c49e95	3110	else
phungductung	0:e87aa4c49e95	3111	{
phungductung	0:e87aa4c49e95	3112	/* TI4 Configuration */
phungductung	0:e87aa4c49e95	3113	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3114
phungductung	0:e87aa4c49e95	3115	TIM_TI4_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	3116	sConfig->ICPolarity,
phungductung	0:e87aa4c49e95	3117	sConfig->ICSelection,
phungductung	0:e87aa4c49e95	3118	sConfig->ICFilter);
phungductung	0:e87aa4c49e95	3119
phungductung	0:e87aa4c49e95	3120	/* Reset the IC4PSC Bits */
phungductung	0:e87aa4c49e95	3121	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
phungductung	0:e87aa4c49e95	3122
phungductung	0:e87aa4c49e95	3123	/* Set the IC4PSC value */
phungductung	0:e87aa4c49e95	3124	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
phungductung	0:e87aa4c49e95	3125	}
phungductung	0:e87aa4c49e95	3126
phungductung	0:e87aa4c49e95	3127	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3128
phungductung	0:e87aa4c49e95	3129	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	3130
phungductung	0:e87aa4c49e95	3131	return HAL_OK;
phungductung	0:e87aa4c49e95	3132	}
phungductung	0:e87aa4c49e95	3133
phungductung	0:e87aa4c49e95	3134	/**
phungductung	0:e87aa4c49e95	3135	* @brief Initializes the TIM PWM channels according to the specified
phungductung	0:e87aa4c49e95	3136	* parameters in the TIM_OC_InitTypeDef.
phungductung	0:e87aa4c49e95	3137	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3138	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3139	* @param sConfig: TIM PWM configuration structure
phungductung	0:e87aa4c49e95	3140	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	3141	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	3142	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	3143	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	3144	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	3145	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	3146	* @retval HAL status
phungductung	0:e87aa4c49e95	3147	*/
phungductung	0:e87aa4c49e95	3148	__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
phungductung	0:e87aa4c49e95	3149	{
phungductung	0:e87aa4c49e95	3150	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	3151
phungductung	0:e87aa4c49e95	3152	/* Check the parameters */
phungductung	0:e87aa4c49e95	3153	assert_param(IS_TIM_CHANNELS(Channel));
phungductung	0:e87aa4c49e95	3154	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
phungductung	0:e87aa4c49e95	3155	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
phungductung	0:e87aa4c49e95	3156	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
phungductung	0:e87aa4c49e95	3157
phungductung	0:e87aa4c49e95	3158	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3159
phungductung	0:e87aa4c49e95	3160	switch (Channel)
phungductung	0:e87aa4c49e95	3161	{
phungductung	0:e87aa4c49e95	3162	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	3163	{
phungductung	0:e87aa4c49e95	3164	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3165	/* Configure the Channel 1 in PWM mode */
phungductung	0:e87aa4c49e95	3166	TIM_OC1_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3167
phungductung	0:e87aa4c49e95	3168	/* Set the Preload enable bit for channel1 */
phungductung	0:e87aa4c49e95	3169	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
phungductung	0:e87aa4c49e95	3170
phungductung	0:e87aa4c49e95	3171	/* Configure the Output Fast mode */
phungductung	0:e87aa4c49e95	3172	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
phungductung	0:e87aa4c49e95	3173	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
phungductung	0:e87aa4c49e95	3174	}
phungductung	0:e87aa4c49e95	3175	break;
phungductung	0:e87aa4c49e95	3176
phungductung	0:e87aa4c49e95	3177	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	3178	{
phungductung	0:e87aa4c49e95	3179	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3180	/* Configure the Channel 2 in PWM mode */
phungductung	0:e87aa4c49e95	3181	TIM_OC2_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3182
phungductung	0:e87aa4c49e95	3183	/* Set the Preload enable bit for channel2 */
phungductung	0:e87aa4c49e95	3184	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
phungductung	0:e87aa4c49e95	3185
phungductung	0:e87aa4c49e95	3186	/* Configure the Output Fast mode */
phungductung	0:e87aa4c49e95	3187	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
phungductung	0:e87aa4c49e95	3188	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
phungductung	0:e87aa4c49e95	3189	}
phungductung	0:e87aa4c49e95	3190	break;
phungductung	0:e87aa4c49e95	3191
phungductung	0:e87aa4c49e95	3192	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	3193	{
phungductung	0:e87aa4c49e95	3194	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3195	/* Configure the Channel 3 in PWM mode */
phungductung	0:e87aa4c49e95	3196	TIM_OC3_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3197
phungductung	0:e87aa4c49e95	3198	/* Set the Preload enable bit for channel3 */
phungductung	0:e87aa4c49e95	3199	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
phungductung	0:e87aa4c49e95	3200
phungductung	0:e87aa4c49e95	3201	/* Configure the Output Fast mode */
phungductung	0:e87aa4c49e95	3202	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
phungductung	0:e87aa4c49e95	3203	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
phungductung	0:e87aa4c49e95	3204	}
phungductung	0:e87aa4c49e95	3205	break;
phungductung	0:e87aa4c49e95	3206
phungductung	0:e87aa4c49e95	3207	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	3208	{
phungductung	0:e87aa4c49e95	3209	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3210	/* Configure the Channel 4 in PWM mode */
phungductung	0:e87aa4c49e95	3211	TIM_OC4_SetConfig(htim->Instance, sConfig);
phungductung	0:e87aa4c49e95	3212
phungductung	0:e87aa4c49e95	3213	/* Set the Preload enable bit for channel4 */
phungductung	0:e87aa4c49e95	3214	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
phungductung	0:e87aa4c49e95	3215
phungductung	0:e87aa4c49e95	3216	/* Configure the Output Fast mode */
phungductung	0:e87aa4c49e95	3217	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
phungductung	0:e87aa4c49e95	3218	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
phungductung	0:e87aa4c49e95	3219	}
phungductung	0:e87aa4c49e95	3220	break;
phungductung	0:e87aa4c49e95	3221
phungductung	0:e87aa4c49e95	3222	default:
phungductung	0:e87aa4c49e95	3223	break;
phungductung	0:e87aa4c49e95	3224	}
phungductung	0:e87aa4c49e95	3225
phungductung	0:e87aa4c49e95	3226	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3227
phungductung	0:e87aa4c49e95	3228	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	3229
phungductung	0:e87aa4c49e95	3230	return HAL_OK;
phungductung	0:e87aa4c49e95	3231	}
phungductung	0:e87aa4c49e95	3232
phungductung	0:e87aa4c49e95	3233	/**
phungductung	0:e87aa4c49e95	3234	* @brief Initializes the TIM One Pulse Channels according to the specified
phungductung	0:e87aa4c49e95	3235	* parameters in the TIM_OnePulse_InitTypeDef.
phungductung	0:e87aa4c49e95	3236	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3237	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3238	* @param sConfig: TIM One Pulse configuration structure
phungductung	0:e87aa4c49e95	3239	* @param OutputChannel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	3240	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	3241	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	3242	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	3243	* @param InputChannel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	3244	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	3245	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	3246	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	3247	* @retval HAL status
phungductung	0:e87aa4c49e95	3248	*/
phungductung	0:e87aa4c49e95	3249	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
phungductung	0:e87aa4c49e95	3250	{
phungductung	0:e87aa4c49e95	3251	TIM_OC_InitTypeDef temp1;
phungductung	0:e87aa4c49e95	3252
phungductung	0:e87aa4c49e95	3253	/* Check the parameters */
phungductung	0:e87aa4c49e95	3254	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
phungductung	0:e87aa4c49e95	3255	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
phungductung	0:e87aa4c49e95	3256
phungductung	0:e87aa4c49e95	3257	if(OutputChannel != InputChannel)
phungductung	0:e87aa4c49e95	3258	{
phungductung	0:e87aa4c49e95	3259	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	3260
phungductung	0:e87aa4c49e95	3261	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3262
phungductung	0:e87aa4c49e95	3263	/* Extract the Output compare configuration from sConfig structure */
phungductung	0:e87aa4c49e95	3264	temp1.OCMode = sConfig->OCMode;
phungductung	0:e87aa4c49e95	3265	temp1.Pulse = sConfig->Pulse;
phungductung	0:e87aa4c49e95	3266	temp1.OCPolarity = sConfig->OCPolarity;
phungductung	0:e87aa4c49e95	3267	temp1.OCNPolarity = sConfig->OCNPolarity;
phungductung	0:e87aa4c49e95	3268	temp1.OCIdleState = sConfig->OCIdleState;
phungductung	0:e87aa4c49e95	3269	temp1.OCNIdleState = sConfig->OCNIdleState;
phungductung	0:e87aa4c49e95	3270
phungductung	0:e87aa4c49e95	3271	switch (OutputChannel)
phungductung	0:e87aa4c49e95	3272	{
phungductung	0:e87aa4c49e95	3273	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	3274	{
phungductung	0:e87aa4c49e95	3275	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3276
phungductung	0:e87aa4c49e95	3277	TIM_OC1_SetConfig(htim->Instance, &temp1);
phungductung	0:e87aa4c49e95	3278	}
phungductung	0:e87aa4c49e95	3279	break;
phungductung	0:e87aa4c49e95	3280	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	3281	{
phungductung	0:e87aa4c49e95	3282	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3283
phungductung	0:e87aa4c49e95	3284	TIM_OC2_SetConfig(htim->Instance, &temp1);
phungductung	0:e87aa4c49e95	3285	}
phungductung	0:e87aa4c49e95	3286	break;
phungductung	0:e87aa4c49e95	3287	default:
phungductung	0:e87aa4c49e95	3288	break;
phungductung	0:e87aa4c49e95	3289	}
phungductung	0:e87aa4c49e95	3290	switch (InputChannel)
phungductung	0:e87aa4c49e95	3291	{
phungductung	0:e87aa4c49e95	3292	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	3293	{
phungductung	0:e87aa4c49e95	3294	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3295
phungductung	0:e87aa4c49e95	3296	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
phungductung	0:e87aa4c49e95	3297	sConfig->ICSelection, sConfig->ICFilter);
phungductung	0:e87aa4c49e95	3298
phungductung	0:e87aa4c49e95	3299	/* Reset the IC1PSC Bits */
phungductung	0:e87aa4c49e95	3300	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
phungductung	0:e87aa4c49e95	3301
phungductung	0:e87aa4c49e95	3302	/* Select the Trigger source */
phungductung	0:e87aa4c49e95	3303	htim->Instance->SMCR &= ~TIM_SMCR_TS;
phungductung	0:e87aa4c49e95	3304	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
phungductung	0:e87aa4c49e95	3305
phungductung	0:e87aa4c49e95	3306	/* Select the Slave Mode */
phungductung	0:e87aa4c49e95	3307	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
phungductung	0:e87aa4c49e95	3308	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
phungductung	0:e87aa4c49e95	3309	}
phungductung	0:e87aa4c49e95	3310	break;
phungductung	0:e87aa4c49e95	3311	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	3312	{
phungductung	0:e87aa4c49e95	3313	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3314
phungductung	0:e87aa4c49e95	3315	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
phungductung	0:e87aa4c49e95	3316	sConfig->ICSelection, sConfig->ICFilter);
phungductung	0:e87aa4c49e95	3317
phungductung	0:e87aa4c49e95	3318	/* Reset the IC2PSC Bits */
phungductung	0:e87aa4c49e95	3319	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
phungductung	0:e87aa4c49e95	3320
phungductung	0:e87aa4c49e95	3321	/* Select the Trigger source */
phungductung	0:e87aa4c49e95	3322	htim->Instance->SMCR &= ~TIM_SMCR_TS;
phungductung	0:e87aa4c49e95	3323	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
phungductung	0:e87aa4c49e95	3324
phungductung	0:e87aa4c49e95	3325	/* Select the Slave Mode */
phungductung	0:e87aa4c49e95	3326	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
phungductung	0:e87aa4c49e95	3327	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
phungductung	0:e87aa4c49e95	3328	}
phungductung	0:e87aa4c49e95	3329	break;
phungductung	0:e87aa4c49e95	3330
phungductung	0:e87aa4c49e95	3331	default:
phungductung	0:e87aa4c49e95	3332	break;
phungductung	0:e87aa4c49e95	3333	}
phungductung	0:e87aa4c49e95	3334
phungductung	0:e87aa4c49e95	3335	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3336
phungductung	0:e87aa4c49e95	3337	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	3338
phungductung	0:e87aa4c49e95	3339	return HAL_OK;
phungductung	0:e87aa4c49e95	3340	}
phungductung	0:e87aa4c49e95	3341	else
phungductung	0:e87aa4c49e95	3342	{
phungductung	0:e87aa4c49e95	3343	return HAL_ERROR;
phungductung	0:e87aa4c49e95	3344	}
phungductung	0:e87aa4c49e95	3345	}
phungductung	0:e87aa4c49e95	3346
phungductung	0:e87aa4c49e95	3347	/**
phungductung	0:e87aa4c49e95	3348	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
phungductung	0:e87aa4c49e95	3349	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3350	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3351	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
phungductung	0:e87aa4c49e95	3352	* This parameters can be on of the following values:
phungductung	0:e87aa4c49e95	3353	* @arg TIM_DMABASE_CR1
phungductung	0:e87aa4c49e95	3354	* @arg TIM_DMABASE_CR2
phungductung	0:e87aa4c49e95	3355	* @arg TIM_DMABASE_SMCR
phungductung	0:e87aa4c49e95	3356	* @arg TIM_DMABASE_DIER
phungductung	0:e87aa4c49e95	3357	* @arg TIM_DMABASE_SR
phungductung	0:e87aa4c49e95	3358	* @arg TIM_DMABASE_EGR
phungductung	0:e87aa4c49e95	3359	* @arg TIM_DMABASE_CCMR1
phungductung	0:e87aa4c49e95	3360	* @arg TIM_DMABASE_CCMR2
phungductung	0:e87aa4c49e95	3361	* @arg TIM_DMABASE_CCER
phungductung	0:e87aa4c49e95	3362	* @arg TIM_DMABASE_CNT
phungductung	0:e87aa4c49e95	3363	* @arg TIM_DMABASE_PSC
phungductung	0:e87aa4c49e95	3364	* @arg TIM_DMABASE_ARR
phungductung	0:e87aa4c49e95	3365	* @arg TIM_DMABASE_RCR
phungductung	0:e87aa4c49e95	3366	* @arg TIM_DMABASE_CCR1
phungductung	0:e87aa4c49e95	3367	* @arg TIM_DMABASE_CCR2
phungductung	0:e87aa4c49e95	3368	* @arg TIM_DMABASE_CCR3
phungductung	0:e87aa4c49e95	3369	* @arg TIM_DMABASE_CCR4
phungductung	0:e87aa4c49e95	3370	* @arg TIM_DMABASE_BDTR
phungductung	0:e87aa4c49e95	3371	* @arg TIM_DMABASE_DCR
phungductung	0:e87aa4c49e95	3372	* @param BurstRequestSrc: TIM DMA Request sources.
phungductung	0:e87aa4c49e95	3373	* This parameters can be on of the following values:
phungductung	0:e87aa4c49e95	3374	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
phungductung	0:e87aa4c49e95	3375	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
phungductung	0:e87aa4c49e95	3376	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
phungductung	0:e87aa4c49e95	3377	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
phungductung	0:e87aa4c49e95	3378	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
phungductung	0:e87aa4c49e95	3379	* @arg TIM_DMA_COM: TIM Commutation DMA source
phungductung	0:e87aa4c49e95	3380	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
phungductung	0:e87aa4c49e95	3381	* @param BurstBuffer: The Buffer address.
phungductung	0:e87aa4c49e95	3382	* @param BurstLength: DMA Burst length. This parameter can be one value
phungductung	0:e87aa4c49e95	3383	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
phungductung	0:e87aa4c49e95	3384	* @retval HAL status
phungductung	0:e87aa4c49e95	3385	*/
phungductung	0:e87aa4c49e95	3386	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
phungductung	0:e87aa4c49e95	3387	uint32_t* BurstBuffer, uint32_t BurstLength)
phungductung	0:e87aa4c49e95	3388	{
phungductung	0:e87aa4c49e95	3389	/* Check the parameters */
phungductung	0:e87aa4c49e95	3390	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3391	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
phungductung	0:e87aa4c49e95	3392	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
phungductung	0:e87aa4c49e95	3393	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
phungductung	0:e87aa4c49e95	3394
phungductung	0:e87aa4c49e95	3395	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	3396	{
phungductung	0:e87aa4c49e95	3397	return HAL_BUSY;
phungductung	0:e87aa4c49e95	3398	}
phungductung	0:e87aa4c49e95	3399	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	3400	{
phungductung	0:e87aa4c49e95	3401	if((BurstBuffer == 0 ) && (BurstLength > 0))
phungductung	0:e87aa4c49e95	3402	{
phungductung	0:e87aa4c49e95	3403	return HAL_ERROR;
phungductung	0:e87aa4c49e95	3404	}
phungductung	0:e87aa4c49e95	3405	else
phungductung	0:e87aa4c49e95	3406	{
phungductung	0:e87aa4c49e95	3407	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3408	}
phungductung	0:e87aa4c49e95	3409	}
phungductung	0:e87aa4c49e95	3410	switch(BurstRequestSrc)
phungductung	0:e87aa4c49e95	3411	{
phungductung	0:e87aa4c49e95	3412	case TIM_DMA_UPDATE:
phungductung	0:e87aa4c49e95	3413	{
phungductung	0:e87aa4c49e95	3414	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3415	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
phungductung	0:e87aa4c49e95	3416
phungductung	0:e87aa4c49e95	3417	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3418	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3419
phungductung	0:e87aa4c49e95	3420	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3421	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3422	}
phungductung	0:e87aa4c49e95	3423	break;
phungductung	0:e87aa4c49e95	3424	case TIM_DMA_CC1:
phungductung	0:e87aa4c49e95	3425	{
phungductung	0:e87aa4c49e95	3426	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3427	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	3428
phungductung	0:e87aa4c49e95	3429	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3430	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3431
phungductung	0:e87aa4c49e95	3432	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3433	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3434	}
phungductung	0:e87aa4c49e95	3435	break;
phungductung	0:e87aa4c49e95	3436	case TIM_DMA_CC2:
phungductung	0:e87aa4c49e95	3437	{
phungductung	0:e87aa4c49e95	3438	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3439	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	3440
phungductung	0:e87aa4c49e95	3441	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3442	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3443
phungductung	0:e87aa4c49e95	3444	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3445	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3446	}
phungductung	0:e87aa4c49e95	3447	break;
phungductung	0:e87aa4c49e95	3448	case TIM_DMA_CC3:
phungductung	0:e87aa4c49e95	3449	{
phungductung	0:e87aa4c49e95	3450	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3451	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	3452
phungductung	0:e87aa4c49e95	3453	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3454	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3455
phungductung	0:e87aa4c49e95	3456	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3457	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3458	}
phungductung	0:e87aa4c49e95	3459	break;
phungductung	0:e87aa4c49e95	3460	case TIM_DMA_CC4:
phungductung	0:e87aa4c49e95	3461	{
phungductung	0:e87aa4c49e95	3462	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3463	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
phungductung	0:e87aa4c49e95	3464
phungductung	0:e87aa4c49e95	3465	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3466	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3467
phungductung	0:e87aa4c49e95	3468	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3469	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3470	}
phungductung	0:e87aa4c49e95	3471	break;
phungductung	0:e87aa4c49e95	3472	case TIM_DMA_COM:
phungductung	0:e87aa4c49e95	3473	{
phungductung	0:e87aa4c49e95	3474	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3475	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
phungductung	0:e87aa4c49e95	3476
phungductung	0:e87aa4c49e95	3477	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3478	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3479
phungductung	0:e87aa4c49e95	3480	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3481	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3482	}
phungductung	0:e87aa4c49e95	3483	break;
phungductung	0:e87aa4c49e95	3484	case TIM_DMA_TRIGGER:
phungductung	0:e87aa4c49e95	3485	{
phungductung	0:e87aa4c49e95	3486	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3487	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
phungductung	0:e87aa4c49e95	3488
phungductung	0:e87aa4c49e95	3489	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3490	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3491
phungductung	0:e87aa4c49e95	3492	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3493	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3494	}
phungductung	0:e87aa4c49e95	3495	break;
phungductung	0:e87aa4c49e95	3496	default:
phungductung	0:e87aa4c49e95	3497	break;
phungductung	0:e87aa4c49e95	3498	}
phungductung	0:e87aa4c49e95	3499	/* configure the DMA Burst Mode */
phungductung	0:e87aa4c49e95	3500	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
phungductung	0:e87aa4c49e95	3501
phungductung	0:e87aa4c49e95	3502	/* Enable the TIM DMA Request */
phungductung	0:e87aa4c49e95	3503	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
phungductung	0:e87aa4c49e95	3504
phungductung	0:e87aa4c49e95	3505	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3506
phungductung	0:e87aa4c49e95	3507	/* Return function status */
phungductung	0:e87aa4c49e95	3508	return HAL_OK;
phungductung	0:e87aa4c49e95	3509	}
phungductung	0:e87aa4c49e95	3510
phungductung	0:e87aa4c49e95	3511	/**
phungductung	0:e87aa4c49e95	3512	* @brief Stops the TIM DMA Burst mode
phungductung	0:e87aa4c49e95	3513	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3514	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3515	* @param BurstRequestSrc: TIM DMA Request sources to disable
phungductung	0:e87aa4c49e95	3516	* @retval HAL status
phungductung	0:e87aa4c49e95	3517	*/
phungductung	0:e87aa4c49e95	3518	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
phungductung	0:e87aa4c49e95	3519	{
phungductung	0:e87aa4c49e95	3520	/* Check the parameters */
phungductung	0:e87aa4c49e95	3521	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
phungductung	0:e87aa4c49e95	3522
phungductung	0:e87aa4c49e95	3523	/* Abort the DMA transfer (at least disable the DMA channel) */
phungductung	0:e87aa4c49e95	3524	switch(BurstRequestSrc)
phungductung	0:e87aa4c49e95	3525	{
phungductung	0:e87aa4c49e95	3526	case TIM_DMA_UPDATE:
phungductung	0:e87aa4c49e95	3527	{
phungductung	0:e87aa4c49e95	3528	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
phungductung	0:e87aa4c49e95	3529	}
phungductung	0:e87aa4c49e95	3530	break;
phungductung	0:e87aa4c49e95	3531	case TIM_DMA_CC1:
phungductung	0:e87aa4c49e95	3532	{
phungductung	0:e87aa4c49e95	3533	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
phungductung	0:e87aa4c49e95	3534	}
phungductung	0:e87aa4c49e95	3535	break;
phungductung	0:e87aa4c49e95	3536	case TIM_DMA_CC2:
phungductung	0:e87aa4c49e95	3537	{
phungductung	0:e87aa4c49e95	3538	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
phungductung	0:e87aa4c49e95	3539	}
phungductung	0:e87aa4c49e95	3540	break;
phungductung	0:e87aa4c49e95	3541	case TIM_DMA_CC3:
phungductung	0:e87aa4c49e95	3542	{
phungductung	0:e87aa4c49e95	3543	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
phungductung	0:e87aa4c49e95	3544	}
phungductung	0:e87aa4c49e95	3545	break;
phungductung	0:e87aa4c49e95	3546	case TIM_DMA_CC4:
phungductung	0:e87aa4c49e95	3547	{
phungductung	0:e87aa4c49e95	3548	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
phungductung	0:e87aa4c49e95	3549	}
phungductung	0:e87aa4c49e95	3550	break;
phungductung	0:e87aa4c49e95	3551	case TIM_DMA_COM:
phungductung	0:e87aa4c49e95	3552	{
phungductung	0:e87aa4c49e95	3553	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
phungductung	0:e87aa4c49e95	3554	}
phungductung	0:e87aa4c49e95	3555	break;
phungductung	0:e87aa4c49e95	3556	case TIM_DMA_TRIGGER:
phungductung	0:e87aa4c49e95	3557	{
phungductung	0:e87aa4c49e95	3558	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
phungductung	0:e87aa4c49e95	3559	}
phungductung	0:e87aa4c49e95	3560	break;
phungductung	0:e87aa4c49e95	3561	default:
phungductung	0:e87aa4c49e95	3562	break;
phungductung	0:e87aa4c49e95	3563	}
phungductung	0:e87aa4c49e95	3564
phungductung	0:e87aa4c49e95	3565	/* Disable the TIM Update DMA request */
phungductung	0:e87aa4c49e95	3566	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
phungductung	0:e87aa4c49e95	3567
phungductung	0:e87aa4c49e95	3568	/* Return function status */
phungductung	0:e87aa4c49e95	3569	return HAL_OK;
phungductung	0:e87aa4c49e95	3570	}
phungductung	0:e87aa4c49e95	3571
phungductung	0:e87aa4c49e95	3572	/**
phungductung	0:e87aa4c49e95	3573	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
phungductung	0:e87aa4c49e95	3574	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3575	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3576	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
phungductung	0:e87aa4c49e95	3577	* This parameters can be on of the following values:
phungductung	0:e87aa4c49e95	3578	* @arg TIM_DMABASE_CR1
phungductung	0:e87aa4c49e95	3579	* @arg TIM_DMABASE_CR2
phungductung	0:e87aa4c49e95	3580	* @arg TIM_DMABASE_SMCR
phungductung	0:e87aa4c49e95	3581	* @arg TIM_DMABASE_DIER
phungductung	0:e87aa4c49e95	3582	* @arg TIM_DMABASE_SR
phungductung	0:e87aa4c49e95	3583	* @arg TIM_DMABASE_EGR
phungductung	0:e87aa4c49e95	3584	* @arg TIM_DMABASE_CCMR1
phungductung	0:e87aa4c49e95	3585	* @arg TIM_DMABASE_CCMR2
phungductung	0:e87aa4c49e95	3586	* @arg TIM_DMABASE_CCER
phungductung	0:e87aa4c49e95	3587	* @arg TIM_DMABASE_CNT
phungductung	0:e87aa4c49e95	3588	* @arg TIM_DMABASE_PSC
phungductung	0:e87aa4c49e95	3589	* @arg TIM_DMABASE_ARR
phungductung	0:e87aa4c49e95	3590	* @arg TIM_DMABASE_RCR
phungductung	0:e87aa4c49e95	3591	* @arg TIM_DMABASE_CCR1
phungductung	0:e87aa4c49e95	3592	* @arg TIM_DMABASE_CCR2
phungductung	0:e87aa4c49e95	3593	* @arg TIM_DMABASE_CCR3
phungductung	0:e87aa4c49e95	3594	* @arg TIM_DMABASE_CCR4
phungductung	0:e87aa4c49e95	3595	* @arg TIM_DMABASE_BDTR
phungductung	0:e87aa4c49e95	3596	* @arg TIM_DMABASE_DCR
phungductung	0:e87aa4c49e95	3597	* @param BurstRequestSrc: TIM DMA Request sources.
phungductung	0:e87aa4c49e95	3598	* This parameters can be on of the following values:
phungductung	0:e87aa4c49e95	3599	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
phungductung	0:e87aa4c49e95	3600	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
phungductung	0:e87aa4c49e95	3601	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
phungductung	0:e87aa4c49e95	3602	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
phungductung	0:e87aa4c49e95	3603	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
phungductung	0:e87aa4c49e95	3604	* @arg TIM_DMA_COM: TIM Commutation DMA source
phungductung	0:e87aa4c49e95	3605	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
phungductung	0:e87aa4c49e95	3606	* @param BurstBuffer: The Buffer address.
phungductung	0:e87aa4c49e95	3607	* @param BurstLength: DMA Burst length. This parameter can be one value
phungductung	0:e87aa4c49e95	3608	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
phungductung	0:e87aa4c49e95	3609	* @retval HAL status
phungductung	0:e87aa4c49e95	3610	*/
phungductung	0:e87aa4c49e95	3611	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
phungductung	0:e87aa4c49e95	3612	uint32_t *BurstBuffer, uint32_t BurstLength)
phungductung	0:e87aa4c49e95	3613	{
phungductung	0:e87aa4c49e95	3614	/* Check the parameters */
phungductung	0:e87aa4c49e95	3615	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3616	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
phungductung	0:e87aa4c49e95	3617	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
phungductung	0:e87aa4c49e95	3618	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
phungductung	0:e87aa4c49e95	3619
phungductung	0:e87aa4c49e95	3620	if((htim->State == HAL_TIM_STATE_BUSY))
phungductung	0:e87aa4c49e95	3621	{
phungductung	0:e87aa4c49e95	3622	return HAL_BUSY;
phungductung	0:e87aa4c49e95	3623	}
phungductung	0:e87aa4c49e95	3624	else if((htim->State == HAL_TIM_STATE_READY))
phungductung	0:e87aa4c49e95	3625	{
phungductung	0:e87aa4c49e95	3626	if((BurstBuffer == 0 ) && (BurstLength > 0))
phungductung	0:e87aa4c49e95	3627	{
phungductung	0:e87aa4c49e95	3628	return HAL_ERROR;
phungductung	0:e87aa4c49e95	3629	}
phungductung	0:e87aa4c49e95	3630	else
phungductung	0:e87aa4c49e95	3631	{
phungductung	0:e87aa4c49e95	3632	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3633	}
phungductung	0:e87aa4c49e95	3634	}
phungductung	0:e87aa4c49e95	3635	switch(BurstRequestSrc)
phungductung	0:e87aa4c49e95	3636	{
phungductung	0:e87aa4c49e95	3637	case TIM_DMA_UPDATE:
phungductung	0:e87aa4c49e95	3638	{
phungductung	0:e87aa4c49e95	3639	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3640	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
phungductung	0:e87aa4c49e95	3641
phungductung	0:e87aa4c49e95	3642	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3643	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3644
phungductung	0:e87aa4c49e95	3645	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3646	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3647	}
phungductung	0:e87aa4c49e95	3648	break;
phungductung	0:e87aa4c49e95	3649	case TIM_DMA_CC1:
phungductung	0:e87aa4c49e95	3650	{
phungductung	0:e87aa4c49e95	3651	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3652	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	3653
phungductung	0:e87aa4c49e95	3654	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3655	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3656
phungductung	0:e87aa4c49e95	3657	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3658	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3659	}
phungductung	0:e87aa4c49e95	3660	break;
phungductung	0:e87aa4c49e95	3661	case TIM_DMA_CC2:
phungductung	0:e87aa4c49e95	3662	{
phungductung	0:e87aa4c49e95	3663	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3664	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	3665
phungductung	0:e87aa4c49e95	3666	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3667	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3668
phungductung	0:e87aa4c49e95	3669	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3670	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3671	}
phungductung	0:e87aa4c49e95	3672	break;
phungductung	0:e87aa4c49e95	3673	case TIM_DMA_CC3:
phungductung	0:e87aa4c49e95	3674	{
phungductung	0:e87aa4c49e95	3675	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3676	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	3677
phungductung	0:e87aa4c49e95	3678	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3679	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3680
phungductung	0:e87aa4c49e95	3681	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3682	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3683	}
phungductung	0:e87aa4c49e95	3684	break;
phungductung	0:e87aa4c49e95	3685	case TIM_DMA_CC4:
phungductung	0:e87aa4c49e95	3686	{
phungductung	0:e87aa4c49e95	3687	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3688	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
phungductung	0:e87aa4c49e95	3689
phungductung	0:e87aa4c49e95	3690	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3691	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3692
phungductung	0:e87aa4c49e95	3693	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3694	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3695	}
phungductung	0:e87aa4c49e95	3696	break;
phungductung	0:e87aa4c49e95	3697	case TIM_DMA_COM:
phungductung	0:e87aa4c49e95	3698	{
phungductung	0:e87aa4c49e95	3699	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3700	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
phungductung	0:e87aa4c49e95	3701
phungductung	0:e87aa4c49e95	3702	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3703	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3704
phungductung	0:e87aa4c49e95	3705	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3706	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3707	}
phungductung	0:e87aa4c49e95	3708	break;
phungductung	0:e87aa4c49e95	3709	case TIM_DMA_TRIGGER:
phungductung	0:e87aa4c49e95	3710	{
phungductung	0:e87aa4c49e95	3711	/* Set the DMA Period elapsed callback */
phungductung	0:e87aa4c49e95	3712	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
phungductung	0:e87aa4c49e95	3713
phungductung	0:e87aa4c49e95	3714	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	3715	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
phungductung	0:e87aa4c49e95	3716
phungductung	0:e87aa4c49e95	3717	/* Enable the DMA Stream */
phungductung	0:e87aa4c49e95	3718	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
phungductung	0:e87aa4c49e95	3719	}
phungductung	0:e87aa4c49e95	3720	break;
phungductung	0:e87aa4c49e95	3721	default:
phungductung	0:e87aa4c49e95	3722	break;
phungductung	0:e87aa4c49e95	3723	}
phungductung	0:e87aa4c49e95	3724
phungductung	0:e87aa4c49e95	3725	/* configure the DMA Burst Mode */
phungductung	0:e87aa4c49e95	3726	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
phungductung	0:e87aa4c49e95	3727
phungductung	0:e87aa4c49e95	3728	/* Enable the TIM DMA Request */
phungductung	0:e87aa4c49e95	3729	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
phungductung	0:e87aa4c49e95	3730
phungductung	0:e87aa4c49e95	3731	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3732
phungductung	0:e87aa4c49e95	3733	/* Return function status */
phungductung	0:e87aa4c49e95	3734	return HAL_OK;
phungductung	0:e87aa4c49e95	3735	}
phungductung	0:e87aa4c49e95	3736
phungductung	0:e87aa4c49e95	3737	/**
phungductung	0:e87aa4c49e95	3738	* @brief Stop the DMA burst reading
phungductung	0:e87aa4c49e95	3739	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3740	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3741	* @param BurstRequestSrc: TIM DMA Request sources to disable.
phungductung	0:e87aa4c49e95	3742	* @retval HAL status
phungductung	0:e87aa4c49e95	3743	*/
phungductung	0:e87aa4c49e95	3744	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
phungductung	0:e87aa4c49e95	3745	{
phungductung	0:e87aa4c49e95	3746	/* Check the parameters */
phungductung	0:e87aa4c49e95	3747	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
phungductung	0:e87aa4c49e95	3748
phungductung	0:e87aa4c49e95	3749	/* Abort the DMA transfer (at least disable the DMA channel) */
phungductung	0:e87aa4c49e95	3750	switch(BurstRequestSrc)
phungductung	0:e87aa4c49e95	3751	{
phungductung	0:e87aa4c49e95	3752	case TIM_DMA_UPDATE:
phungductung	0:e87aa4c49e95	3753	{
phungductung	0:e87aa4c49e95	3754	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
phungductung	0:e87aa4c49e95	3755	}
phungductung	0:e87aa4c49e95	3756	break;
phungductung	0:e87aa4c49e95	3757	case TIM_DMA_CC1:
phungductung	0:e87aa4c49e95	3758	{
phungductung	0:e87aa4c49e95	3759	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
phungductung	0:e87aa4c49e95	3760	}
phungductung	0:e87aa4c49e95	3761	break;
phungductung	0:e87aa4c49e95	3762	case TIM_DMA_CC2:
phungductung	0:e87aa4c49e95	3763	{
phungductung	0:e87aa4c49e95	3764	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
phungductung	0:e87aa4c49e95	3765	}
phungductung	0:e87aa4c49e95	3766	break;
phungductung	0:e87aa4c49e95	3767	case TIM_DMA_CC3:
phungductung	0:e87aa4c49e95	3768	{
phungductung	0:e87aa4c49e95	3769	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
phungductung	0:e87aa4c49e95	3770	}
phungductung	0:e87aa4c49e95	3771	break;
phungductung	0:e87aa4c49e95	3772	case TIM_DMA_CC4:
phungductung	0:e87aa4c49e95	3773	{
phungductung	0:e87aa4c49e95	3774	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
phungductung	0:e87aa4c49e95	3775	}
phungductung	0:e87aa4c49e95	3776	break;
phungductung	0:e87aa4c49e95	3777	case TIM_DMA_COM:
phungductung	0:e87aa4c49e95	3778	{
phungductung	0:e87aa4c49e95	3779	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
phungductung	0:e87aa4c49e95	3780	}
phungductung	0:e87aa4c49e95	3781	break;
phungductung	0:e87aa4c49e95	3782	case TIM_DMA_TRIGGER:
phungductung	0:e87aa4c49e95	3783	{
phungductung	0:e87aa4c49e95	3784	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
phungductung	0:e87aa4c49e95	3785	}
phungductung	0:e87aa4c49e95	3786	break;
phungductung	0:e87aa4c49e95	3787	default:
phungductung	0:e87aa4c49e95	3788	break;
phungductung	0:e87aa4c49e95	3789	}
phungductung	0:e87aa4c49e95	3790
phungductung	0:e87aa4c49e95	3791	/* Disable the TIM Update DMA request */
phungductung	0:e87aa4c49e95	3792	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
phungductung	0:e87aa4c49e95	3793
phungductung	0:e87aa4c49e95	3794	/* Return function status */
phungductung	0:e87aa4c49e95	3795	return HAL_OK;
phungductung	0:e87aa4c49e95	3796	}
phungductung	0:e87aa4c49e95	3797
phungductung	0:e87aa4c49e95	3798	/**
phungductung	0:e87aa4c49e95	3799	* @brief Generate a software event
phungductung	0:e87aa4c49e95	3800	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3801	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3802	* @param EventSource: specifies the event source.
phungductung	0:e87aa4c49e95	3803	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	3804	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
phungductung	0:e87aa4c49e95	3805	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
phungductung	0:e87aa4c49e95	3806	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
phungductung	0:e87aa4c49e95	3807	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
phungductung	0:e87aa4c49e95	3808	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
phungductung	0:e87aa4c49e95	3809	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
phungductung	0:e87aa4c49e95	3810	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
phungductung	0:e87aa4c49e95	3811	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
phungductung	0:e87aa4c49e95	3812	* @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
phungductung	0:e87aa4c49e95	3813	* @note TIM6 and TIM7 can only generate an update event.
phungductung	0:e87aa4c49e95	3814	* @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
phungductung	0:e87aa4c49e95	3815	* @retval HAL status
phungductung	0:e87aa4c49e95	3816	*/
phungductung	0:e87aa4c49e95	3817
phungductung	0:e87aa4c49e95	3818	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
phungductung	0:e87aa4c49e95	3819	{
phungductung	0:e87aa4c49e95	3820	/* Check the parameters */
phungductung	0:e87aa4c49e95	3821	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3822	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
phungductung	0:e87aa4c49e95	3823
phungductung	0:e87aa4c49e95	3824	/* Process Locked */
phungductung	0:e87aa4c49e95	3825	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	3826
phungductung	0:e87aa4c49e95	3827	/* Change the TIM state */
phungductung	0:e87aa4c49e95	3828	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3829
phungductung	0:e87aa4c49e95	3830	/* Set the event sources */
phungductung	0:e87aa4c49e95	3831	htim->Instance->EGR = EventSource;
phungductung	0:e87aa4c49e95	3832
phungductung	0:e87aa4c49e95	3833	/* Change the TIM state */
phungductung	0:e87aa4c49e95	3834	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3835
phungductung	0:e87aa4c49e95	3836	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	3837
phungductung	0:e87aa4c49e95	3838	/* Return function status */
phungductung	0:e87aa4c49e95	3839	return HAL_OK;
phungductung	0:e87aa4c49e95	3840	}
phungductung	0:e87aa4c49e95	3841
phungductung	0:e87aa4c49e95	3842	/**
phungductung	0:e87aa4c49e95	3843	* @brief Configures the OCRef clear feature
phungductung	0:e87aa4c49e95	3844	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3845	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3846	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
phungductung	0:e87aa4c49e95	3847	* contains the OCREF clear feature and parameters for the TIM peripheral.
phungductung	0:e87aa4c49e95	3848	* @param Channel: specifies the TIM Channel.
phungductung	0:e87aa4c49e95	3849	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	3850	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	3851	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	3852	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	3853	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	3854	* @retval HAL status
phungductung	0:e87aa4c49e95	3855	*/
phungductung	0:e87aa4c49e95	3856	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
phungductung	0:e87aa4c49e95	3857	{
phungductung	0:e87aa4c49e95	3858	/* Check the parameters */
phungductung	0:e87aa4c49e95	3859	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3860	assert_param(IS_TIM_CHANNELS(Channel));
phungductung	0:e87aa4c49e95	3861	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
phungductung	0:e87aa4c49e95	3862
phungductung	0:e87aa4c49e95	3863	/* Process Locked */
phungductung	0:e87aa4c49e95	3864	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	3865
phungductung	0:e87aa4c49e95	3866	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3867
phungductung	0:e87aa4c49e95	3868	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
phungductung	0:e87aa4c49e95	3869	{
phungductung	0:e87aa4c49e95	3870	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
phungductung	0:e87aa4c49e95	3871	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
phungductung	0:e87aa4c49e95	3872	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
phungductung	0:e87aa4c49e95	3873
phungductung	0:e87aa4c49e95	3874	TIM_ETR_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	3875	sClearInputConfig->ClearInputPrescaler,
phungductung	0:e87aa4c49e95	3876	sClearInputConfig->ClearInputPolarity,
phungductung	0:e87aa4c49e95	3877	sClearInputConfig->ClearInputFilter);
phungductung	0:e87aa4c49e95	3878	}
phungductung	0:e87aa4c49e95	3879
phungductung	0:e87aa4c49e95	3880	switch (Channel)
phungductung	0:e87aa4c49e95	3881	{
phungductung	0:e87aa4c49e95	3882	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	3883	{
phungductung	0:e87aa4c49e95	3884	if(sClearInputConfig->ClearInputState != RESET)
phungductung	0:e87aa4c49e95	3885	{
phungductung	0:e87aa4c49e95	3886	/* Enable the Ocref clear feature for Channel 1 */
phungductung	0:e87aa4c49e95	3887	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
phungductung	0:e87aa4c49e95	3888	}
phungductung	0:e87aa4c49e95	3889	else
phungductung	0:e87aa4c49e95	3890	{
phungductung	0:e87aa4c49e95	3891	/* Disable the Ocref clear feature for Channel 1 */
phungductung	0:e87aa4c49e95	3892	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
phungductung	0:e87aa4c49e95	3893	}
phungductung	0:e87aa4c49e95	3894	}
phungductung	0:e87aa4c49e95	3895	break;
phungductung	0:e87aa4c49e95	3896	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	3897	{
phungductung	0:e87aa4c49e95	3898	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3899	if(sClearInputConfig->ClearInputState != RESET)
phungductung	0:e87aa4c49e95	3900	{
phungductung	0:e87aa4c49e95	3901	/* Enable the Ocref clear feature for Channel 2 */
phungductung	0:e87aa4c49e95	3902	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
phungductung	0:e87aa4c49e95	3903	}
phungductung	0:e87aa4c49e95	3904	else
phungductung	0:e87aa4c49e95	3905	{
phungductung	0:e87aa4c49e95	3906	/* Disable the Ocref clear feature for Channel 2 */
phungductung	0:e87aa4c49e95	3907	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
phungductung	0:e87aa4c49e95	3908	}
phungductung	0:e87aa4c49e95	3909	}
phungductung	0:e87aa4c49e95	3910	break;
phungductung	0:e87aa4c49e95	3911	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	3912	{
phungductung	0:e87aa4c49e95	3913	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3914	if(sClearInputConfig->ClearInputState != RESET)
phungductung	0:e87aa4c49e95	3915	{
phungductung	0:e87aa4c49e95	3916	/* Enable the Ocref clear feature for Channel 3 */
phungductung	0:e87aa4c49e95	3917	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
phungductung	0:e87aa4c49e95	3918	}
phungductung	0:e87aa4c49e95	3919	else
phungductung	0:e87aa4c49e95	3920	{
phungductung	0:e87aa4c49e95	3921	/* Disable the Ocref clear feature for Channel 3 */
phungductung	0:e87aa4c49e95	3922	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
phungductung	0:e87aa4c49e95	3923	}
phungductung	0:e87aa4c49e95	3924	}
phungductung	0:e87aa4c49e95	3925	break;
phungductung	0:e87aa4c49e95	3926	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	3927	{
phungductung	0:e87aa4c49e95	3928	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3929	if(sClearInputConfig->ClearInputState != RESET)
phungductung	0:e87aa4c49e95	3930	{
phungductung	0:e87aa4c49e95	3931	/* Enable the Ocref clear feature for Channel 4 */
phungductung	0:e87aa4c49e95	3932	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
phungductung	0:e87aa4c49e95	3933	}
phungductung	0:e87aa4c49e95	3934	else
phungductung	0:e87aa4c49e95	3935	{
phungductung	0:e87aa4c49e95	3936	/* Disable the Ocref clear feature for Channel 4 */
phungductung	0:e87aa4c49e95	3937	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
phungductung	0:e87aa4c49e95	3938	}
phungductung	0:e87aa4c49e95	3939	}
phungductung	0:e87aa4c49e95	3940	break;
phungductung	0:e87aa4c49e95	3941	default:
phungductung	0:e87aa4c49e95	3942	break;
phungductung	0:e87aa4c49e95	3943	}
phungductung	0:e87aa4c49e95	3944
phungductung	0:e87aa4c49e95	3945	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	3946
phungductung	0:e87aa4c49e95	3947	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	3948
phungductung	0:e87aa4c49e95	3949	return HAL_OK;
phungductung	0:e87aa4c49e95	3950	}
phungductung	0:e87aa4c49e95	3951
phungductung	0:e87aa4c49e95	3952	/**
phungductung	0:e87aa4c49e95	3953	* @brief Configures the clock source to be used
phungductung	0:e87aa4c49e95	3954	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	3955	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	3956	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
phungductung	0:e87aa4c49e95	3957	* contains the clock source information for the TIM peripheral.
phungductung	0:e87aa4c49e95	3958	* @retval HAL status
phungductung	0:e87aa4c49e95	3959	*/
phungductung	0:e87aa4c49e95	3960	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
phungductung	0:e87aa4c49e95	3961	{
phungductung	0:e87aa4c49e95	3962	uint32_t tmpsmcr = 0;
phungductung	0:e87aa4c49e95	3963
phungductung	0:e87aa4c49e95	3964	/* Process Locked */
phungductung	0:e87aa4c49e95	3965	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	3966
phungductung	0:e87aa4c49e95	3967	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	3968
phungductung	0:e87aa4c49e95	3969	/* Check the parameters */
phungductung	0:e87aa4c49e95	3970	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
phungductung	0:e87aa4c49e95	3971
phungductung	0:e87aa4c49e95	3972	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
phungductung	0:e87aa4c49e95	3973	tmpsmcr = htim->Instance->SMCR;
phungductung	0:e87aa4c49e95	3974	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
phungductung	0:e87aa4c49e95	3975	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
phungductung	0:e87aa4c49e95	3976	htim->Instance->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	3977
phungductung	0:e87aa4c49e95	3978	switch (sClockSourceConfig->ClockSource)
phungductung	0:e87aa4c49e95	3979	{
phungductung	0:e87aa4c49e95	3980	case TIM_CLOCKSOURCE_INTERNAL:
phungductung	0:e87aa4c49e95	3981	{
phungductung	0:e87aa4c49e95	3982	assert_param(IS_TIM_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3983	/* Disable slave mode to clock the prescaler directly with the internal clock */
phungductung	0:e87aa4c49e95	3984	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
phungductung	0:e87aa4c49e95	3985	}
phungductung	0:e87aa4c49e95	3986	break;
phungductung	0:e87aa4c49e95	3987
phungductung	0:e87aa4c49e95	3988	case TIM_CLOCKSOURCE_ETRMODE1:
phungductung	0:e87aa4c49e95	3989	{
phungductung	0:e87aa4c49e95	3990	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	3991	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
phungductung	0:e87aa4c49e95	3992	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
phungductung	0:e87aa4c49e95	3993	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
phungductung	0:e87aa4c49e95	3994	/* Configure the ETR Clock source */
phungductung	0:e87aa4c49e95	3995	TIM_ETR_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	3996	sClockSourceConfig->ClockPrescaler,
phungductung	0:e87aa4c49e95	3997	sClockSourceConfig->ClockPolarity,
phungductung	0:e87aa4c49e95	3998	sClockSourceConfig->ClockFilter);
phungductung	0:e87aa4c49e95	3999	/* Get the TIMx SMCR register value */
phungductung	0:e87aa4c49e95	4000	tmpsmcr = htim->Instance->SMCR;
phungductung	0:e87aa4c49e95	4001	/* Reset the SMS and TS Bits */
phungductung	0:e87aa4c49e95	4002	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
phungductung	0:e87aa4c49e95	4003	/* Select the External clock mode1 and the ETRF trigger */
phungductung	0:e87aa4c49e95	4004	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
phungductung	0:e87aa4c49e95	4005	/* Write to TIMx SMCR */
phungductung	0:e87aa4c49e95	4006	htim->Instance->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	4007	}
phungductung	0:e87aa4c49e95	4008	break;
phungductung	0:e87aa4c49e95	4009
phungductung	0:e87aa4c49e95	4010	case TIM_CLOCKSOURCE_ETRMODE2:
phungductung	0:e87aa4c49e95	4011	{
phungductung	0:e87aa4c49e95	4012	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4013	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
phungductung	0:e87aa4c49e95	4014	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
phungductung	0:e87aa4c49e95	4015	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
phungductung	0:e87aa4c49e95	4016
phungductung	0:e87aa4c49e95	4017	/* Configure the ETR Clock source */
phungductung	0:e87aa4c49e95	4018	TIM_ETR_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	4019	sClockSourceConfig->ClockPrescaler,
phungductung	0:e87aa4c49e95	4020	sClockSourceConfig->ClockPolarity,
phungductung	0:e87aa4c49e95	4021	sClockSourceConfig->ClockFilter);
phungductung	0:e87aa4c49e95	4022	/* Enable the External clock mode2 */
phungductung	0:e87aa4c49e95	4023	htim->Instance->SMCR \|= TIM_SMCR_ECE;
phungductung	0:e87aa4c49e95	4024	}
phungductung	0:e87aa4c49e95	4025	break;
phungductung	0:e87aa4c49e95	4026
phungductung	0:e87aa4c49e95	4027	case TIM_CLOCKSOURCE_TI1:
phungductung	0:e87aa4c49e95	4028	{
phungductung	0:e87aa4c49e95	4029	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4030
phungductung	0:e87aa4c49e95	4031	/* Check TI1 input conditioning related parameters */
phungductung	0:e87aa4c49e95	4032	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
phungductung	0:e87aa4c49e95	4033	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
phungductung	0:e87aa4c49e95	4034
phungductung	0:e87aa4c49e95	4035	TIM_TI1_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	4036	sClockSourceConfig->ClockPolarity,
phungductung	0:e87aa4c49e95	4037	sClockSourceConfig->ClockFilter);
phungductung	0:e87aa4c49e95	4038	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
phungductung	0:e87aa4c49e95	4039	}
phungductung	0:e87aa4c49e95	4040	break;
phungductung	0:e87aa4c49e95	4041	case TIM_CLOCKSOURCE_TI2:
phungductung	0:e87aa4c49e95	4042	{
phungductung	0:e87aa4c49e95	4043	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4044
phungductung	0:e87aa4c49e95	4045	/* Check TI1 input conditioning related parameters */
phungductung	0:e87aa4c49e95	4046	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
phungductung	0:e87aa4c49e95	4047	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
phungductung	0:e87aa4c49e95	4048
phungductung	0:e87aa4c49e95	4049	TIM_TI2_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	4050	sClockSourceConfig->ClockPolarity,
phungductung	0:e87aa4c49e95	4051	sClockSourceConfig->ClockFilter);
phungductung	0:e87aa4c49e95	4052	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
phungductung	0:e87aa4c49e95	4053	}
phungductung	0:e87aa4c49e95	4054	break;
phungductung	0:e87aa4c49e95	4055	case TIM_CLOCKSOURCE_TI1ED:
phungductung	0:e87aa4c49e95	4056	{
phungductung	0:e87aa4c49e95	4057	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4058	/* Check TI1 input conditioning related parameters */
phungductung	0:e87aa4c49e95	4059	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
phungductung	0:e87aa4c49e95	4060	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
phungductung	0:e87aa4c49e95	4061
phungductung	0:e87aa4c49e95	4062	TIM_TI1_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	4063	sClockSourceConfig->ClockPolarity,
phungductung	0:e87aa4c49e95	4064	sClockSourceConfig->ClockFilter);
phungductung	0:e87aa4c49e95	4065	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
phungductung	0:e87aa4c49e95	4066	}
phungductung	0:e87aa4c49e95	4067	break;
phungductung	0:e87aa4c49e95	4068	case TIM_CLOCKSOURCE_ITR0:
phungductung	0:e87aa4c49e95	4069	{
phungductung	0:e87aa4c49e95	4070	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4071	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
phungductung	0:e87aa4c49e95	4072	}
phungductung	0:e87aa4c49e95	4073	break;
phungductung	0:e87aa4c49e95	4074	case TIM_CLOCKSOURCE_ITR1:
phungductung	0:e87aa4c49e95	4075	{
phungductung	0:e87aa4c49e95	4076	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4077	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
phungductung	0:e87aa4c49e95	4078	}
phungductung	0:e87aa4c49e95	4079	break;
phungductung	0:e87aa4c49e95	4080	case TIM_CLOCKSOURCE_ITR2:
phungductung	0:e87aa4c49e95	4081	{
phungductung	0:e87aa4c49e95	4082	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4083	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
phungductung	0:e87aa4c49e95	4084	}
phungductung	0:e87aa4c49e95	4085	break;
phungductung	0:e87aa4c49e95	4086	case TIM_CLOCKSOURCE_ITR3:
phungductung	0:e87aa4c49e95	4087	{
phungductung	0:e87aa4c49e95	4088	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4089	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
phungductung	0:e87aa4c49e95	4090	}
phungductung	0:e87aa4c49e95	4091	break;
phungductung	0:e87aa4c49e95	4092
phungductung	0:e87aa4c49e95	4093	default:
phungductung	0:e87aa4c49e95	4094	break;
phungductung	0:e87aa4c49e95	4095	}
phungductung	0:e87aa4c49e95	4096	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4097
phungductung	0:e87aa4c49e95	4098	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	4099
phungductung	0:e87aa4c49e95	4100	return HAL_OK;
phungductung	0:e87aa4c49e95	4101	}
phungductung	0:e87aa4c49e95	4102
phungductung	0:e87aa4c49e95	4103	/**
phungductung	0:e87aa4c49e95	4104	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
phungductung	0:e87aa4c49e95	4105	* or a XOR combination between CH1_input, CH2_input & CH3_input
phungductung	0:e87aa4c49e95	4106	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4107	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4108	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
phungductung	0:e87aa4c49e95	4109	* output of a XOR gate.
phungductung	0:e87aa4c49e95	4110	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	4111	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
phungductung	0:e87aa4c49e95	4112	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
phungductung	0:e87aa4c49e95	4113	* pins are connected to the TI1 input (XOR combination)
phungductung	0:e87aa4c49e95	4114	* @retval HAL status
phungductung	0:e87aa4c49e95	4115	*/
phungductung	0:e87aa4c49e95	4116	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
phungductung	0:e87aa4c49e95	4117	{
phungductung	0:e87aa4c49e95	4118	uint32_t tmpcr2 = 0;
phungductung	0:e87aa4c49e95	4119
phungductung	0:e87aa4c49e95	4120	/* Check the parameters */
phungductung	0:e87aa4c49e95	4121	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4122	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
phungductung	0:e87aa4c49e95	4123
phungductung	0:e87aa4c49e95	4124	/* Get the TIMx CR2 register value */
phungductung	0:e87aa4c49e95	4125	tmpcr2 = htim->Instance->CR2;
phungductung	0:e87aa4c49e95	4126
phungductung	0:e87aa4c49e95	4127	/* Reset the TI1 selection */
phungductung	0:e87aa4c49e95	4128	tmpcr2 &= ~TIM_CR2_TI1S;
phungductung	0:e87aa4c49e95	4129
phungductung	0:e87aa4c49e95	4130	/* Set the TI1 selection */
phungductung	0:e87aa4c49e95	4131	tmpcr2 \|= TI1_Selection;
phungductung	0:e87aa4c49e95	4132
phungductung	0:e87aa4c49e95	4133	/* Write to TIMxCR2 */
phungductung	0:e87aa4c49e95	4134	htim->Instance->CR2 = tmpcr2;
phungductung	0:e87aa4c49e95	4135
phungductung	0:e87aa4c49e95	4136	return HAL_OK;
phungductung	0:e87aa4c49e95	4137	}
phungductung	0:e87aa4c49e95	4138
phungductung	0:e87aa4c49e95	4139	/**
phungductung	0:e87aa4c49e95	4140	* @brief Configures the TIM in Slave mode
phungductung	0:e87aa4c49e95	4141	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4142	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4143	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
phungductung	0:e87aa4c49e95	4144	* contains the selected trigger (internal trigger input, filtered
phungductung	0:e87aa4c49e95	4145	* timer input or external trigger input) and the ) and the Slave
phungductung	0:e87aa4c49e95	4146	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
phungductung	0:e87aa4c49e95	4147	* @retval HAL status
phungductung	0:e87aa4c49e95	4148	*/
phungductung	0:e87aa4c49e95	4149	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
phungductung	0:e87aa4c49e95	4150	{
phungductung	0:e87aa4c49e95	4151	uint32_t tmpsmcr = 0;
phungductung	0:e87aa4c49e95	4152	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	4153	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	4154
phungductung	0:e87aa4c49e95	4155	/* Check the parameters */
phungductung	0:e87aa4c49e95	4156	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4157	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
phungductung	0:e87aa4c49e95	4158	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
phungductung	0:e87aa4c49e95	4159
phungductung	0:e87aa4c49e95	4160	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	4161
phungductung	0:e87aa4c49e95	4162	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	4163
phungductung	0:e87aa4c49e95	4164	/* Get the TIMx SMCR register value */
phungductung	0:e87aa4c49e95	4165	tmpsmcr = htim->Instance->SMCR;
phungductung	0:e87aa4c49e95	4166
phungductung	0:e87aa4c49e95	4167	/* Reset the Trigger Selection Bits */
phungductung	0:e87aa4c49e95	4168	tmpsmcr &= ~TIM_SMCR_TS;
phungductung	0:e87aa4c49e95	4169	/* Set the Input Trigger source */
phungductung	0:e87aa4c49e95	4170	tmpsmcr \|= sSlaveConfig->InputTrigger;
phungductung	0:e87aa4c49e95	4171
phungductung	0:e87aa4c49e95	4172	/* Reset the slave mode Bits */
phungductung	0:e87aa4c49e95	4173	tmpsmcr &= ~TIM_SMCR_SMS;
phungductung	0:e87aa4c49e95	4174	/* Set the slave mode */
phungductung	0:e87aa4c49e95	4175	tmpsmcr \|= sSlaveConfig->SlaveMode;
phungductung	0:e87aa4c49e95	4176
phungductung	0:e87aa4c49e95	4177	/* Write to TIMx SMCR */
phungductung	0:e87aa4c49e95	4178	htim->Instance->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	4179
phungductung	0:e87aa4c49e95	4180	/* Configure the trigger prescaler, filter, and polarity */
phungductung	0:e87aa4c49e95	4181	switch (sSlaveConfig->InputTrigger)
phungductung	0:e87aa4c49e95	4182	{
phungductung	0:e87aa4c49e95	4183	case TIM_TS_ETRF:
phungductung	0:e87aa4c49e95	4184	{
phungductung	0:e87aa4c49e95	4185	/* Check the parameters */
phungductung	0:e87aa4c49e95	4186	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4187	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
phungductung	0:e87aa4c49e95	4188	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	4189	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	4190	/* Configure the ETR Trigger source */
phungductung	0:e87aa4c49e95	4191	TIM_ETR_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	4192	sSlaveConfig->TriggerPrescaler,
phungductung	0:e87aa4c49e95	4193	sSlaveConfig->TriggerPolarity,
phungductung	0:e87aa4c49e95	4194	sSlaveConfig->TriggerFilter);
phungductung	0:e87aa4c49e95	4195	}
phungductung	0:e87aa4c49e95	4196	break;
phungductung	0:e87aa4c49e95	4197
phungductung	0:e87aa4c49e95	4198	case TIM_TS_TI1F_ED:
phungductung	0:e87aa4c49e95	4199	{
phungductung	0:e87aa4c49e95	4200	/* Check the parameters */
phungductung	0:e87aa4c49e95	4201	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4202	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	4203
phungductung	0:e87aa4c49e95	4204	/* Disable the Channel 1: Reset the CC1E Bit */
phungductung	0:e87aa4c49e95	4205	tmpccer = htim->Instance->CCER;
phungductung	0:e87aa4c49e95	4206	htim->Instance->CCER &= ~TIM_CCER_CC1E;
phungductung	0:e87aa4c49e95	4207	tmpccmr1 = htim->Instance->CCMR1;
phungductung	0:e87aa4c49e95	4208
phungductung	0:e87aa4c49e95	4209	/* Set the filter */
phungductung	0:e87aa4c49e95	4210	tmpccmr1 &= ~TIM_CCMR1_IC1F;
phungductung	0:e87aa4c49e95	4211	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
phungductung	0:e87aa4c49e95	4212
phungductung	0:e87aa4c49e95	4213	/* Write to TIMx CCMR1 and CCER registers */
phungductung	0:e87aa4c49e95	4214	htim->Instance->CCMR1 = tmpccmr1;
phungductung	0:e87aa4c49e95	4215	htim->Instance->CCER = tmpccer;
phungductung	0:e87aa4c49e95	4216
phungductung	0:e87aa4c49e95	4217	}
phungductung	0:e87aa4c49e95	4218	break;
phungductung	0:e87aa4c49e95	4219
phungductung	0:e87aa4c49e95	4220	case TIM_TS_TI1FP1:
phungductung	0:e87aa4c49e95	4221	{
phungductung	0:e87aa4c49e95	4222	/* Check the parameters */
phungductung	0:e87aa4c49e95	4223	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4224	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	4225	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	4226
phungductung	0:e87aa4c49e95	4227	/* Configure TI1 Filter and Polarity */
phungductung	0:e87aa4c49e95	4228	TIM_TI1_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	4229	sSlaveConfig->TriggerPolarity,
phungductung	0:e87aa4c49e95	4230	sSlaveConfig->TriggerFilter);
phungductung	0:e87aa4c49e95	4231	}
phungductung	0:e87aa4c49e95	4232	break;
phungductung	0:e87aa4c49e95	4233
phungductung	0:e87aa4c49e95	4234	case TIM_TS_TI2FP2:
phungductung	0:e87aa4c49e95	4235	{
phungductung	0:e87aa4c49e95	4236	/* Check the parameters */
phungductung	0:e87aa4c49e95	4237	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4238	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	4239	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	4240
phungductung	0:e87aa4c49e95	4241	/* Configure TI2 Filter and Polarity */
phungductung	0:e87aa4c49e95	4242	TIM_TI2_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	4243	sSlaveConfig->TriggerPolarity,
phungductung	0:e87aa4c49e95	4244	sSlaveConfig->TriggerFilter);
phungductung	0:e87aa4c49e95	4245	}
phungductung	0:e87aa4c49e95	4246	break;
phungductung	0:e87aa4c49e95	4247
phungductung	0:e87aa4c49e95	4248	case TIM_TS_ITR0:
phungductung	0:e87aa4c49e95	4249	{
phungductung	0:e87aa4c49e95	4250	/* Check the parameter */
phungductung	0:e87aa4c49e95	4251	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4252	}
phungductung	0:e87aa4c49e95	4253	break;
phungductung	0:e87aa4c49e95	4254
phungductung	0:e87aa4c49e95	4255	case TIM_TS_ITR1:
phungductung	0:e87aa4c49e95	4256	{
phungductung	0:e87aa4c49e95	4257	/* Check the parameter */
phungductung	0:e87aa4c49e95	4258	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4259	}
phungductung	0:e87aa4c49e95	4260	break;
phungductung	0:e87aa4c49e95	4261
phungductung	0:e87aa4c49e95	4262	case TIM_TS_ITR2:
phungductung	0:e87aa4c49e95	4263	{
phungductung	0:e87aa4c49e95	4264	/* Check the parameter */
phungductung	0:e87aa4c49e95	4265	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4266	}
phungductung	0:e87aa4c49e95	4267	break;
phungductung	0:e87aa4c49e95	4268
phungductung	0:e87aa4c49e95	4269	case TIM_TS_ITR3:
phungductung	0:e87aa4c49e95	4270	{
phungductung	0:e87aa4c49e95	4271	/* Check the parameter */
phungductung	0:e87aa4c49e95	4272	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4273	}
phungductung	0:e87aa4c49e95	4274	break;
phungductung	0:e87aa4c49e95	4275
phungductung	0:e87aa4c49e95	4276	default:
phungductung	0:e87aa4c49e95	4277	break;
phungductung	0:e87aa4c49e95	4278	}
phungductung	0:e87aa4c49e95	4279
phungductung	0:e87aa4c49e95	4280	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4281
phungductung	0:e87aa4c49e95	4282	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	4283
phungductung	0:e87aa4c49e95	4284	return HAL_OK;
phungductung	0:e87aa4c49e95	4285	}
phungductung	0:e87aa4c49e95	4286
phungductung	0:e87aa4c49e95	4287	/**
phungductung	0:e87aa4c49e95	4288	* @brief Configures the TIM in Slave mode in interrupt mode
phungductung	0:e87aa4c49e95	4289	* @param htim: TIM handle.
phungductung	0:e87aa4c49e95	4290	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
phungductung	0:e87aa4c49e95	4291	* contains the selected trigger (internal trigger input, filtered
phungductung	0:e87aa4c49e95	4292	* timer input or external trigger input) and the ) and the Slave
phungductung	0:e87aa4c49e95	4293	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
phungductung	0:e87aa4c49e95	4294	* @retval HAL status
phungductung	0:e87aa4c49e95	4295	*/
phungductung	0:e87aa4c49e95	4296	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
phungductung	0:e87aa4c49e95	4297	TIM_SlaveConfigTypeDef * sSlaveConfig)
phungductung	0:e87aa4c49e95	4298	{
phungductung	0:e87aa4c49e95	4299	/* Check the parameters */
phungductung	0:e87aa4c49e95	4300	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4301	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
phungductung	0:e87aa4c49e95	4302	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
phungductung	0:e87aa4c49e95	4303
phungductung	0:e87aa4c49e95	4304	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	4305
phungductung	0:e87aa4c49e95	4306	htim->State = HAL_TIM_STATE_BUSY;
phungductung	0:e87aa4c49e95	4307
phungductung	0:e87aa4c49e95	4308	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
phungductung	0:e87aa4c49e95	4309
phungductung	0:e87aa4c49e95	4310	/* Enable Trigger Interrupt */
phungductung	0:e87aa4c49e95	4311	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
phungductung	0:e87aa4c49e95	4312
phungductung	0:e87aa4c49e95	4313	/* Disable Trigger DMA request */
phungductung	0:e87aa4c49e95	4314	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
phungductung	0:e87aa4c49e95	4315
phungductung	0:e87aa4c49e95	4316	htim->State = HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4317
phungductung	0:e87aa4c49e95	4318	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	4319
phungductung	0:e87aa4c49e95	4320	return HAL_OK;
phungductung	0:e87aa4c49e95	4321	}
phungductung	0:e87aa4c49e95	4322
phungductung	0:e87aa4c49e95	4323	/**
phungductung	0:e87aa4c49e95	4324	* @brief Read the captured value from Capture Compare unit
phungductung	0:e87aa4c49e95	4325	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4326	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4327	* @param Channel: TIM Channels to be enabled.
phungductung	0:e87aa4c49e95	4328	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	4329	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
phungductung	0:e87aa4c49e95	4330	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
phungductung	0:e87aa4c49e95	4331	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
phungductung	0:e87aa4c49e95	4332	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
phungductung	0:e87aa4c49e95	4333	* @retval Captured value
phungductung	0:e87aa4c49e95	4334	*/
phungductung	0:e87aa4c49e95	4335	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
phungductung	0:e87aa4c49e95	4336	{
phungductung	0:e87aa4c49e95	4337	uint32_t tmpreg = 0;
phungductung	0:e87aa4c49e95	4338
phungductung	0:e87aa4c49e95	4339	__HAL_LOCK(htim);
phungductung	0:e87aa4c49e95	4340
phungductung	0:e87aa4c49e95	4341	switch (Channel)
phungductung	0:e87aa4c49e95	4342	{
phungductung	0:e87aa4c49e95	4343	case TIM_CHANNEL_1:
phungductung	0:e87aa4c49e95	4344	{
phungductung	0:e87aa4c49e95	4345	/* Check the parameters */
phungductung	0:e87aa4c49e95	4346	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4347
phungductung	0:e87aa4c49e95	4348	/* Return the capture 1 value */
phungductung	0:e87aa4c49e95	4349	tmpreg = htim->Instance->CCR1;
phungductung	0:e87aa4c49e95	4350
phungductung	0:e87aa4c49e95	4351	break;
phungductung	0:e87aa4c49e95	4352	}
phungductung	0:e87aa4c49e95	4353	case TIM_CHANNEL_2:
phungductung	0:e87aa4c49e95	4354	{
phungductung	0:e87aa4c49e95	4355	/* Check the parameters */
phungductung	0:e87aa4c49e95	4356	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4357
phungductung	0:e87aa4c49e95	4358	/* Return the capture 2 value */
phungductung	0:e87aa4c49e95	4359	tmpreg = htim->Instance->CCR2;
phungductung	0:e87aa4c49e95	4360
phungductung	0:e87aa4c49e95	4361	break;
phungductung	0:e87aa4c49e95	4362	}
phungductung	0:e87aa4c49e95	4363
phungductung	0:e87aa4c49e95	4364	case TIM_CHANNEL_3:
phungductung	0:e87aa4c49e95	4365	{
phungductung	0:e87aa4c49e95	4366	/* Check the parameters */
phungductung	0:e87aa4c49e95	4367	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4368
phungductung	0:e87aa4c49e95	4369	/* Return the capture 3 value */
phungductung	0:e87aa4c49e95	4370	tmpreg = htim->Instance->CCR3;
phungductung	0:e87aa4c49e95	4371
phungductung	0:e87aa4c49e95	4372	break;
phungductung	0:e87aa4c49e95	4373	}
phungductung	0:e87aa4c49e95	4374
phungductung	0:e87aa4c49e95	4375	case TIM_CHANNEL_4:
phungductung	0:e87aa4c49e95	4376	{
phungductung	0:e87aa4c49e95	4377	/* Check the parameters */
phungductung	0:e87aa4c49e95	4378	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	4379
phungductung	0:e87aa4c49e95	4380	/* Return the capture 4 value */
phungductung	0:e87aa4c49e95	4381	tmpreg = htim->Instance->CCR4;
phungductung	0:e87aa4c49e95	4382
phungductung	0:e87aa4c49e95	4383	break;
phungductung	0:e87aa4c49e95	4384	}
phungductung	0:e87aa4c49e95	4385
phungductung	0:e87aa4c49e95	4386	default:
phungductung	0:e87aa4c49e95	4387	break;
phungductung	0:e87aa4c49e95	4388	}
phungductung	0:e87aa4c49e95	4389
phungductung	0:e87aa4c49e95	4390	__HAL_UNLOCK(htim);
phungductung	0:e87aa4c49e95	4391	return tmpreg;
phungductung	0:e87aa4c49e95	4392	}
phungductung	0:e87aa4c49e95	4393
phungductung	0:e87aa4c49e95	4394	/**
phungductung	0:e87aa4c49e95	4395	* @}
phungductung	0:e87aa4c49e95	4396	*/
phungductung	0:e87aa4c49e95	4397
phungductung	0:e87aa4c49e95	4398	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
phungductung	0:e87aa4c49e95	4399	* @brief TIM Callbacks functions
phungductung	0:e87aa4c49e95	4400	*
phungductung	0:e87aa4c49e95	4401	@verbatim
phungductung	0:e87aa4c49e95	4402	==============================================================================
phungductung	0:e87aa4c49e95	4403	##### TIM Callbacks functions #####
phungductung	0:e87aa4c49e95	4404	==============================================================================
phungductung	0:e87aa4c49e95	4405	[..]
phungductung	0:e87aa4c49e95	4406	This section provides TIM callback functions:
phungductung	0:e87aa4c49e95	4407	(+) Timer Period elapsed callback
phungductung	0:e87aa4c49e95	4408	(+) Timer Output Compare callback
phungductung	0:e87aa4c49e95	4409	(+) Timer Input capture callback
phungductung	0:e87aa4c49e95	4410	(+) Timer Trigger callback
phungductung	0:e87aa4c49e95	4411	(+) Timer Error callback
phungductung	0:e87aa4c49e95	4412
phungductung	0:e87aa4c49e95	4413	@endverbatim
phungductung	0:e87aa4c49e95	4414	* @{
phungductung	0:e87aa4c49e95	4415	*/
phungductung	0:e87aa4c49e95	4416
phungductung	0:e87aa4c49e95	4417	/**
phungductung	0:e87aa4c49e95	4418	* @brief Period elapsed callback in non blocking mode
phungductung	0:e87aa4c49e95	4419	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4420	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4421	* @retval None
phungductung	0:e87aa4c49e95	4422	*/
phungductung	0:e87aa4c49e95	4423	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4424	{
phungductung	0:e87aa4c49e95	4425	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	4426	UNUSED(htim);
phungductung	0:e87aa4c49e95	4427
phungductung	0:e87aa4c49e95	4428	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	4429	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	4430	*/
phungductung	0:e87aa4c49e95	4431
phungductung	0:e87aa4c49e95	4432	}
phungductung	0:e87aa4c49e95	4433	/**
phungductung	0:e87aa4c49e95	4434	* @brief Output Compare callback in non blocking mode
phungductung	0:e87aa4c49e95	4435	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4436	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4437	* @retval None
phungductung	0:e87aa4c49e95	4438	*/
phungductung	0:e87aa4c49e95	4439	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4440	{
phungductung	0:e87aa4c49e95	4441	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	4442	UNUSED(htim);
phungductung	0:e87aa4c49e95	4443
phungductung	0:e87aa4c49e95	4444	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	4445	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	4446	*/
phungductung	0:e87aa4c49e95	4447	}
phungductung	0:e87aa4c49e95	4448	/**
phungductung	0:e87aa4c49e95	4449	* @brief Input Capture callback in non blocking mode
phungductung	0:e87aa4c49e95	4450	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4451	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4452	* @retval None
phungductung	0:e87aa4c49e95	4453	*/
phungductung	0:e87aa4c49e95	4454	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4455	{
phungductung	0:e87aa4c49e95	4456	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	4457	UNUSED(htim);
phungductung	0:e87aa4c49e95	4458
phungductung	0:e87aa4c49e95	4459	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	4460	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	4461	*/
phungductung	0:e87aa4c49e95	4462	}
phungductung	0:e87aa4c49e95	4463
phungductung	0:e87aa4c49e95	4464	/**
phungductung	0:e87aa4c49e95	4465	* @brief PWM Pulse finished callback in non blocking mode
phungductung	0:e87aa4c49e95	4466	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4467	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4468	* @retval None
phungductung	0:e87aa4c49e95	4469	*/
phungductung	0:e87aa4c49e95	4470	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4471	{
phungductung	0:e87aa4c49e95	4472	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	4473	UNUSED(htim);
phungductung	0:e87aa4c49e95	4474
phungductung	0:e87aa4c49e95	4475	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	4476	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	4477	*/
phungductung	0:e87aa4c49e95	4478	}
phungductung	0:e87aa4c49e95	4479
phungductung	0:e87aa4c49e95	4480	/**
phungductung	0:e87aa4c49e95	4481	* @brief Hall Trigger detection callback in non blocking mode
phungductung	0:e87aa4c49e95	4482	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4483	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4484	* @retval None
phungductung	0:e87aa4c49e95	4485	*/
phungductung	0:e87aa4c49e95	4486	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4487	{
phungductung	0:e87aa4c49e95	4488	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	4489	UNUSED(htim);
phungductung	0:e87aa4c49e95	4490
phungductung	0:e87aa4c49e95	4491	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	4492	the HAL_TIM_TriggerCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	4493	*/
phungductung	0:e87aa4c49e95	4494	}
phungductung	0:e87aa4c49e95	4495
phungductung	0:e87aa4c49e95	4496	/**
phungductung	0:e87aa4c49e95	4497	* @brief Timer error callback in non blocking mode
phungductung	0:e87aa4c49e95	4498	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4499	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4500	* @retval None
phungductung	0:e87aa4c49e95	4501	*/
phungductung	0:e87aa4c49e95	4502	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4503	{
phungductung	0:e87aa4c49e95	4504	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	4505	UNUSED(htim);
phungductung	0:e87aa4c49e95	4506
phungductung	0:e87aa4c49e95	4507	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	4508	the HAL_TIM_ErrorCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	4509	*/
phungductung	0:e87aa4c49e95	4510	}
phungductung	0:e87aa4c49e95	4511
phungductung	0:e87aa4c49e95	4512	/**
phungductung	0:e87aa4c49e95	4513	* @}
phungductung	0:e87aa4c49e95	4514	*/
phungductung	0:e87aa4c49e95	4515
phungductung	0:e87aa4c49e95	4516	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
phungductung	0:e87aa4c49e95	4517	* @brief Peripheral State functions
phungductung	0:e87aa4c49e95	4518	*
phungductung	0:e87aa4c49e95	4519	@verbatim
phungductung	0:e87aa4c49e95	4520	==============================================================================
phungductung	0:e87aa4c49e95	4521	##### Peripheral State functions #####
phungductung	0:e87aa4c49e95	4522	==============================================================================
phungductung	0:e87aa4c49e95	4523	[..]
phungductung	0:e87aa4c49e95	4524	This subsection permits to get in run-time the status of the peripheral
phungductung	0:e87aa4c49e95	4525	and the data flow.
phungductung	0:e87aa4c49e95	4526
phungductung	0:e87aa4c49e95	4527	@endverbatim
phungductung	0:e87aa4c49e95	4528	* @{
phungductung	0:e87aa4c49e95	4529	*/
phungductung	0:e87aa4c49e95	4530
phungductung	0:e87aa4c49e95	4531	/**
phungductung	0:e87aa4c49e95	4532	* @brief Return the TIM Base state
phungductung	0:e87aa4c49e95	4533	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4534	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4535	* @retval HAL state
phungductung	0:e87aa4c49e95	4536	*/
phungductung	0:e87aa4c49e95	4537	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4538	{
phungductung	0:e87aa4c49e95	4539	return htim->State;
phungductung	0:e87aa4c49e95	4540	}
phungductung	0:e87aa4c49e95	4541
phungductung	0:e87aa4c49e95	4542	/**
phungductung	0:e87aa4c49e95	4543	* @brief Return the TIM OC state
phungductung	0:e87aa4c49e95	4544	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4545	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4546	* @retval HAL state
phungductung	0:e87aa4c49e95	4547	*/
phungductung	0:e87aa4c49e95	4548	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4549	{
phungductung	0:e87aa4c49e95	4550	return htim->State;
phungductung	0:e87aa4c49e95	4551	}
phungductung	0:e87aa4c49e95	4552
phungductung	0:e87aa4c49e95	4553	/**
phungductung	0:e87aa4c49e95	4554	* @brief Return the TIM PWM state
phungductung	0:e87aa4c49e95	4555	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4556	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4557	* @retval HAL state
phungductung	0:e87aa4c49e95	4558	*/
phungductung	0:e87aa4c49e95	4559	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4560	{
phungductung	0:e87aa4c49e95	4561	return htim->State;
phungductung	0:e87aa4c49e95	4562	}
phungductung	0:e87aa4c49e95	4563
phungductung	0:e87aa4c49e95	4564	/**
phungductung	0:e87aa4c49e95	4565	* @brief Return the TIM Input Capture state
phungductung	0:e87aa4c49e95	4566	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4567	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4568	* @retval HAL state
phungductung	0:e87aa4c49e95	4569	*/
phungductung	0:e87aa4c49e95	4570	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4571	{
phungductung	0:e87aa4c49e95	4572	return htim->State;
phungductung	0:e87aa4c49e95	4573	}
phungductung	0:e87aa4c49e95	4574
phungductung	0:e87aa4c49e95	4575	/**
phungductung	0:e87aa4c49e95	4576	* @brief Return the TIM One Pulse Mode state
phungductung	0:e87aa4c49e95	4577	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4578	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4579	* @retval HAL state
phungductung	0:e87aa4c49e95	4580	*/
phungductung	0:e87aa4c49e95	4581	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4582	{
phungductung	0:e87aa4c49e95	4583	return htim->State;
phungductung	0:e87aa4c49e95	4584	}
phungductung	0:e87aa4c49e95	4585
phungductung	0:e87aa4c49e95	4586	/**
phungductung	0:e87aa4c49e95	4587	* @brief Return the TIM Encoder Mode state
phungductung	0:e87aa4c49e95	4588	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4589	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	4590	* @retval HAL state
phungductung	0:e87aa4c49e95	4591	*/
phungductung	0:e87aa4c49e95	4592	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
phungductung	0:e87aa4c49e95	4593	{
phungductung	0:e87aa4c49e95	4594	return htim->State;
phungductung	0:e87aa4c49e95	4595	}
phungductung	0:e87aa4c49e95	4596
phungductung	0:e87aa4c49e95	4597	/**
phungductung	0:e87aa4c49e95	4598	* @}
phungductung	0:e87aa4c49e95	4599	*/
phungductung	0:e87aa4c49e95	4600
phungductung	0:e87aa4c49e95	4601	/**
phungductung	0:e87aa4c49e95	4602	* @brief TIM DMA error callback
phungductung	0:e87aa4c49e95	4603	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4604	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	4605	* @retval None
phungductung	0:e87aa4c49e95	4606	*/
phungductung	0:e87aa4c49e95	4607	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	4608	{
phungductung	0:e87aa4c49e95	4609	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	4610
phungductung	0:e87aa4c49e95	4611	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4612
phungductung	0:e87aa4c49e95	4613	HAL_TIM_ErrorCallback(htim);
phungductung	0:e87aa4c49e95	4614	}
phungductung	0:e87aa4c49e95	4615
phungductung	0:e87aa4c49e95	4616	/**
phungductung	0:e87aa4c49e95	4617	* @brief TIM DMA Delay Pulse complete callback.
phungductung	0:e87aa4c49e95	4618	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4619	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	4620	* @retval None
phungductung	0:e87aa4c49e95	4621	*/
phungductung	0:e87aa4c49e95	4622	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	4623	{
phungductung	0:e87aa4c49e95	4624	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	4625
phungductung	0:e87aa4c49e95	4626	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4627
phungductung	0:e87aa4c49e95	4628	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
phungductung	0:e87aa4c49e95	4629	{
phungductung	0:e87aa4c49e95	4630	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
phungductung	0:e87aa4c49e95	4631	}
phungductung	0:e87aa4c49e95	4632	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
phungductung	0:e87aa4c49e95	4633	{
phungductung	0:e87aa4c49e95	4634	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
phungductung	0:e87aa4c49e95	4635	}
phungductung	0:e87aa4c49e95	4636	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
phungductung	0:e87aa4c49e95	4637	{
phungductung	0:e87aa4c49e95	4638	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
phungductung	0:e87aa4c49e95	4639	}
phungductung	0:e87aa4c49e95	4640	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
phungductung	0:e87aa4c49e95	4641	{
phungductung	0:e87aa4c49e95	4642	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
phungductung	0:e87aa4c49e95	4643	}
phungductung	0:e87aa4c49e95	4644
phungductung	0:e87aa4c49e95	4645	HAL_TIM_PWM_PulseFinishedCallback(htim);
phungductung	0:e87aa4c49e95	4646
phungductung	0:e87aa4c49e95	4647	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
phungductung	0:e87aa4c49e95	4648	}
phungductung	0:e87aa4c49e95	4649	/**
phungductung	0:e87aa4c49e95	4650	* @brief TIM DMA Capture complete callback.
phungductung	0:e87aa4c49e95	4651	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4652	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	4653	* @retval None
phungductung	0:e87aa4c49e95	4654	*/
phungductung	0:e87aa4c49e95	4655	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	4656	{
phungductung	0:e87aa4c49e95	4657	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	4658
phungductung	0:e87aa4c49e95	4659	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4660
phungductung	0:e87aa4c49e95	4661	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
phungductung	0:e87aa4c49e95	4662	{
phungductung	0:e87aa4c49e95	4663	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
phungductung	0:e87aa4c49e95	4664	}
phungductung	0:e87aa4c49e95	4665	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
phungductung	0:e87aa4c49e95	4666	{
phungductung	0:e87aa4c49e95	4667	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
phungductung	0:e87aa4c49e95	4668	}
phungductung	0:e87aa4c49e95	4669	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
phungductung	0:e87aa4c49e95	4670	{
phungductung	0:e87aa4c49e95	4671	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
phungductung	0:e87aa4c49e95	4672	}
phungductung	0:e87aa4c49e95	4673	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
phungductung	0:e87aa4c49e95	4674	{
phungductung	0:e87aa4c49e95	4675	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
phungductung	0:e87aa4c49e95	4676	}
phungductung	0:e87aa4c49e95	4677
phungductung	0:e87aa4c49e95	4678	HAL_TIM_IC_CaptureCallback(htim);
phungductung	0:e87aa4c49e95	4679
phungductung	0:e87aa4c49e95	4680	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
phungductung	0:e87aa4c49e95	4681
phungductung	0:e87aa4c49e95	4682	}
phungductung	0:e87aa4c49e95	4683
phungductung	0:e87aa4c49e95	4684	/**
phungductung	0:e87aa4c49e95	4685	* @brief TIM DMA Period Elapse complete callback.
phungductung	0:e87aa4c49e95	4686	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4687	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	4688	* @retval None
phungductung	0:e87aa4c49e95	4689	*/
phungductung	0:e87aa4c49e95	4690	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	4691	{
phungductung	0:e87aa4c49e95	4692	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	4693
phungductung	0:e87aa4c49e95	4694	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4695
phungductung	0:e87aa4c49e95	4696	HAL_TIM_PeriodElapsedCallback(htim);
phungductung	0:e87aa4c49e95	4697	}
phungductung	0:e87aa4c49e95	4698
phungductung	0:e87aa4c49e95	4699	/**
phungductung	0:e87aa4c49e95	4700	* @brief TIM DMA Trigger callback.
phungductung	0:e87aa4c49e95	4701	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	4702	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	4703	* @retval None
phungductung	0:e87aa4c49e95	4704	*/
phungductung	0:e87aa4c49e95	4705	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	4706	{
phungductung	0:e87aa4c49e95	4707	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	4708
phungductung	0:e87aa4c49e95	4709	htim->State= HAL_TIM_STATE_READY;
phungductung	0:e87aa4c49e95	4710
phungductung	0:e87aa4c49e95	4711	HAL_TIM_TriggerCallback(htim);
phungductung	0:e87aa4c49e95	4712	}
phungductung	0:e87aa4c49e95	4713
phungductung	0:e87aa4c49e95	4714	/**
phungductung	0:e87aa4c49e95	4715	* @brief Time Base configuration
phungductung	0:e87aa4c49e95	4716	* @param TIMx: TIM peripheral
phungductung	0:e87aa4c49e95	4717	* @param Structure: pointer on TIM Time Base required parameters
phungductung	0:e87aa4c49e95	4718	* @retval None
phungductung	0:e87aa4c49e95	4719	*/
phungductung	0:e87aa4c49e95	4720	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
phungductung	0:e87aa4c49e95	4721	{
phungductung	0:e87aa4c49e95	4722	uint32_t tmpcr1 = 0;
phungductung	0:e87aa4c49e95	4723	tmpcr1 = TIMx->CR1;
phungductung	0:e87aa4c49e95	4724
phungductung	0:e87aa4c49e95	4725	/* Set TIM Time Base Unit parameters ---------------------------------------*/
phungductung	0:e87aa4c49e95	4726	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4727	{
phungductung	0:e87aa4c49e95	4728	/* Select the Counter Mode */
phungductung	0:e87aa4c49e95	4729	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
phungductung	0:e87aa4c49e95	4730	tmpcr1 \|= Structure->CounterMode;
phungductung	0:e87aa4c49e95	4731	}
phungductung	0:e87aa4c49e95	4732
phungductung	0:e87aa4c49e95	4733	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4734	{
phungductung	0:e87aa4c49e95	4735	/* Set the clock division */
phungductung	0:e87aa4c49e95	4736	tmpcr1 &= ~TIM_CR1_CKD;
phungductung	0:e87aa4c49e95	4737	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
phungductung	0:e87aa4c49e95	4738	}
phungductung	0:e87aa4c49e95	4739
phungductung	0:e87aa4c49e95	4740	TIMx->CR1 = tmpcr1;
phungductung	0:e87aa4c49e95	4741
phungductung	0:e87aa4c49e95	4742	/* Set the Auto-reload value */
phungductung	0:e87aa4c49e95	4743	TIMx->ARR = (uint32_t)Structure->Period ;
phungductung	0:e87aa4c49e95	4744
phungductung	0:e87aa4c49e95	4745	/* Set the Prescaler value */
phungductung	0:e87aa4c49e95	4746	TIMx->PSC = (uint32_t)Structure->Prescaler;
phungductung	0:e87aa4c49e95	4747
phungductung	0:e87aa4c49e95	4748	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4749	{
phungductung	0:e87aa4c49e95	4750	/* Set the Repetition Counter value */
phungductung	0:e87aa4c49e95	4751	TIMx->RCR = Structure->RepetitionCounter;
phungductung	0:e87aa4c49e95	4752	}
phungductung	0:e87aa4c49e95	4753
phungductung	0:e87aa4c49e95	4754	/* Generate an update event to reload the Prescaler
phungductung	0:e87aa4c49e95	4755	and the repetition counter(only for TIM1 and TIM8) value immediately */
phungductung	0:e87aa4c49e95	4756	TIMx->EGR = TIM_EGR_UG;
phungductung	0:e87aa4c49e95	4757	}
phungductung	0:e87aa4c49e95	4758
phungductung	0:e87aa4c49e95	4759	/**
phungductung	0:e87aa4c49e95	4760	* @brief Time Output Compare 1 configuration
phungductung	0:e87aa4c49e95	4761	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	4762	* @param OC_Config: The output configuration structure
phungductung	0:e87aa4c49e95	4763	* @retval None
phungductung	0:e87aa4c49e95	4764	*/
phungductung	0:e87aa4c49e95	4765	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
phungductung	0:e87aa4c49e95	4766	{
phungductung	0:e87aa4c49e95	4767	uint32_t tmpccmrx = 0;
phungductung	0:e87aa4c49e95	4768	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	4769	uint32_t tmpcr2 = 0;
phungductung	0:e87aa4c49e95	4770
phungductung	0:e87aa4c49e95	4771	/* Disable the Channel 1: Reset the CC1E Bit */
phungductung	0:e87aa4c49e95	4772	TIMx->CCER &= ~TIM_CCER_CC1E;
phungductung	0:e87aa4c49e95	4773
phungductung	0:e87aa4c49e95	4774	/* Get the TIMx CCER register value */
phungductung	0:e87aa4c49e95	4775	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	4776	/* Get the TIMx CR2 register value */
phungductung	0:e87aa4c49e95	4777	tmpcr2 = TIMx->CR2;
phungductung	0:e87aa4c49e95	4778
phungductung	0:e87aa4c49e95	4779	/* Get the TIMx CCMR1 register value */
phungductung	0:e87aa4c49e95	4780	tmpccmrx = TIMx->CCMR1;
phungductung	0:e87aa4c49e95	4781
phungductung	0:e87aa4c49e95	4782	/* Reset the Output Compare Mode Bits */
phungductung	0:e87aa4c49e95	4783	tmpccmrx &= ~TIM_CCMR1_OC1M;
phungductung	0:e87aa4c49e95	4784	tmpccmrx &= ~TIM_CCMR1_CC1S;
phungductung	0:e87aa4c49e95	4785	/* Select the Output Compare Mode */
phungductung	0:e87aa4c49e95	4786	tmpccmrx \|= OC_Config->OCMode;
phungductung	0:e87aa4c49e95	4787
phungductung	0:e87aa4c49e95	4788	/* Reset the Output Polarity level */
phungductung	0:e87aa4c49e95	4789	tmpccer &= ~TIM_CCER_CC1P;
phungductung	0:e87aa4c49e95	4790	/* Set the Output Compare Polarity */
phungductung	0:e87aa4c49e95	4791	tmpccer \|= OC_Config->OCPolarity;
phungductung	0:e87aa4c49e95	4792
phungductung	0:e87aa4c49e95	4793
phungductung	0:e87aa4c49e95	4794	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4795	{
phungductung	0:e87aa4c49e95	4796	/* Reset the Output N Polarity level */
phungductung	0:e87aa4c49e95	4797	tmpccer &= ~TIM_CCER_CC1NP;
phungductung	0:e87aa4c49e95	4798	/* Set the Output N Polarity */
phungductung	0:e87aa4c49e95	4799	tmpccer \|= OC_Config->OCNPolarity;
phungductung	0:e87aa4c49e95	4800	/* Reset the Output N State */
phungductung	0:e87aa4c49e95	4801	tmpccer &= ~TIM_CCER_CC1NE;
phungductung	0:e87aa4c49e95	4802
phungductung	0:e87aa4c49e95	4803	/* Reset the Output Compare and Output Compare N IDLE State */
phungductung	0:e87aa4c49e95	4804	tmpcr2 &= ~TIM_CR2_OIS1;
phungductung	0:e87aa4c49e95	4805	tmpcr2 &= ~TIM_CR2_OIS1N;
phungductung	0:e87aa4c49e95	4806	/* Set the Output Idle state */
phungductung	0:e87aa4c49e95	4807	tmpcr2 \|= OC_Config->OCIdleState;
phungductung	0:e87aa4c49e95	4808	/* Set the Output N Idle state */
phungductung	0:e87aa4c49e95	4809	tmpcr2 \|= OC_Config->OCNIdleState;
phungductung	0:e87aa4c49e95	4810	}
phungductung	0:e87aa4c49e95	4811	/* Write to TIMx CR2 */
phungductung	0:e87aa4c49e95	4812	TIMx->CR2 = tmpcr2;
phungductung	0:e87aa4c49e95	4813
phungductung	0:e87aa4c49e95	4814	/* Write to TIMx CCMR1 */
phungductung	0:e87aa4c49e95	4815	TIMx->CCMR1 = tmpccmrx;
phungductung	0:e87aa4c49e95	4816
phungductung	0:e87aa4c49e95	4817	/* Set the Capture Compare Register value */
phungductung	0:e87aa4c49e95	4818	TIMx->CCR1 = OC_Config->Pulse;
phungductung	0:e87aa4c49e95	4819
phungductung	0:e87aa4c49e95	4820	/* Write to TIMx CCER */
phungductung	0:e87aa4c49e95	4821	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	4822	}
phungductung	0:e87aa4c49e95	4823
phungductung	0:e87aa4c49e95	4824	/**
phungductung	0:e87aa4c49e95	4825	* @brief Time Output Compare 2 configuration
phungductung	0:e87aa4c49e95	4826	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	4827	* @param OC_Config: The output configuration structure
phungductung	0:e87aa4c49e95	4828	* @retval None
phungductung	0:e87aa4c49e95	4829	*/
phungductung	0:e87aa4c49e95	4830	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
phungductung	0:e87aa4c49e95	4831	{
phungductung	0:e87aa4c49e95	4832	uint32_t tmpccmrx = 0;
phungductung	0:e87aa4c49e95	4833	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	4834	uint32_t tmpcr2 = 0;
phungductung	0:e87aa4c49e95	4835
phungductung	0:e87aa4c49e95	4836	/* Disable the Channel 2: Reset the CC2E Bit */
phungductung	0:e87aa4c49e95	4837	TIMx->CCER &= ~TIM_CCER_CC2E;
phungductung	0:e87aa4c49e95	4838
phungductung	0:e87aa4c49e95	4839	/* Get the TIMx CCER register value */
phungductung	0:e87aa4c49e95	4840	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	4841	/* Get the TIMx CR2 register value */
phungductung	0:e87aa4c49e95	4842	tmpcr2 = TIMx->CR2;
phungductung	0:e87aa4c49e95	4843
phungductung	0:e87aa4c49e95	4844	/* Get the TIMx CCMR1 register value */
phungductung	0:e87aa4c49e95	4845	tmpccmrx = TIMx->CCMR1;
phungductung	0:e87aa4c49e95	4846
phungductung	0:e87aa4c49e95	4847	/* Reset the Output Compare mode and Capture/Compare selection Bits */
phungductung	0:e87aa4c49e95	4848	tmpccmrx &= ~TIM_CCMR1_OC2M;
phungductung	0:e87aa4c49e95	4849	tmpccmrx &= ~TIM_CCMR1_CC2S;
phungductung	0:e87aa4c49e95	4850
phungductung	0:e87aa4c49e95	4851	/* Select the Output Compare Mode */
phungductung	0:e87aa4c49e95	4852	tmpccmrx \|= (OC_Config->OCMode << 8);
phungductung	0:e87aa4c49e95	4853
phungductung	0:e87aa4c49e95	4854	/* Reset the Output Polarity level */
phungductung	0:e87aa4c49e95	4855	tmpccer &= ~TIM_CCER_CC2P;
phungductung	0:e87aa4c49e95	4856	/* Set the Output Compare Polarity */
phungductung	0:e87aa4c49e95	4857	tmpccer \|= (OC_Config->OCPolarity << 4);
phungductung	0:e87aa4c49e95	4858
phungductung	0:e87aa4c49e95	4859	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4860	{
phungductung	0:e87aa4c49e95	4861	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
phungductung	0:e87aa4c49e95	4862
phungductung	0:e87aa4c49e95	4863	/* Reset the Output N Polarity level */
phungductung	0:e87aa4c49e95	4864	tmpccer &= ~TIM_CCER_CC2NP;
phungductung	0:e87aa4c49e95	4865	/* Set the Output N Polarity */
phungductung	0:e87aa4c49e95	4866	tmpccer \|= (OC_Config->OCNPolarity << 4);
phungductung	0:e87aa4c49e95	4867	/* Reset the Output N State */
phungductung	0:e87aa4c49e95	4868	tmpccer &= ~TIM_CCER_CC2NE;
phungductung	0:e87aa4c49e95	4869
phungductung	0:e87aa4c49e95	4870	/* Reset the Output Compare and Output Compare N IDLE State */
phungductung	0:e87aa4c49e95	4871	tmpcr2 &= ~TIM_CR2_OIS2;
phungductung	0:e87aa4c49e95	4872	tmpcr2 &= ~TIM_CR2_OIS2N;
phungductung	0:e87aa4c49e95	4873	/* Set the Output Idle state */
phungductung	0:e87aa4c49e95	4874	tmpcr2 \|= (OC_Config->OCIdleState << 2);
phungductung	0:e87aa4c49e95	4875	/* Set the Output N Idle state */
phungductung	0:e87aa4c49e95	4876	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
phungductung	0:e87aa4c49e95	4877	}
phungductung	0:e87aa4c49e95	4878	/* Write to TIMx CR2 */
phungductung	0:e87aa4c49e95	4879	TIMx->CR2 = tmpcr2;
phungductung	0:e87aa4c49e95	4880
phungductung	0:e87aa4c49e95	4881	/* Write to TIMx CCMR1 */
phungductung	0:e87aa4c49e95	4882	TIMx->CCMR1 = tmpccmrx;
phungductung	0:e87aa4c49e95	4883
phungductung	0:e87aa4c49e95	4884	/* Set the Capture Compare Register value */
phungductung	0:e87aa4c49e95	4885	TIMx->CCR2 = OC_Config->Pulse;
phungductung	0:e87aa4c49e95	4886
phungductung	0:e87aa4c49e95	4887	/* Write to TIMx CCER */
phungductung	0:e87aa4c49e95	4888	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	4889	}
phungductung	0:e87aa4c49e95	4890
phungductung	0:e87aa4c49e95	4891	/**
phungductung	0:e87aa4c49e95	4892	* @brief Time Output Compare 3 configuration
phungductung	0:e87aa4c49e95	4893	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	4894	* @param OC_Config: The output configuration structure
phungductung	0:e87aa4c49e95	4895	* @retval None
phungductung	0:e87aa4c49e95	4896	*/
phungductung	0:e87aa4c49e95	4897	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
phungductung	0:e87aa4c49e95	4898	{
phungductung	0:e87aa4c49e95	4899	uint32_t tmpccmrx = 0;
phungductung	0:e87aa4c49e95	4900	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	4901	uint32_t tmpcr2 = 0;
phungductung	0:e87aa4c49e95	4902
phungductung	0:e87aa4c49e95	4903	/* Disable the Channel 3: Reset the CC2E Bit */
phungductung	0:e87aa4c49e95	4904	TIMx->CCER &= ~TIM_CCER_CC3E;
phungductung	0:e87aa4c49e95	4905
phungductung	0:e87aa4c49e95	4906	/* Get the TIMx CCER register value */
phungductung	0:e87aa4c49e95	4907	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	4908	/* Get the TIMx CR2 register value */
phungductung	0:e87aa4c49e95	4909	tmpcr2 = TIMx->CR2;
phungductung	0:e87aa4c49e95	4910
phungductung	0:e87aa4c49e95	4911	/* Get the TIMx CCMR2 register value */
phungductung	0:e87aa4c49e95	4912	tmpccmrx = TIMx->CCMR2;
phungductung	0:e87aa4c49e95	4913
phungductung	0:e87aa4c49e95	4914	/* Reset the Output Compare mode and Capture/Compare selection Bits */
phungductung	0:e87aa4c49e95	4915	tmpccmrx &= ~TIM_CCMR2_OC3M;
phungductung	0:e87aa4c49e95	4916	tmpccmrx &= ~TIM_CCMR2_CC3S;
phungductung	0:e87aa4c49e95	4917	/* Select the Output Compare Mode */
phungductung	0:e87aa4c49e95	4918	tmpccmrx \|= OC_Config->OCMode;
phungductung	0:e87aa4c49e95	4919
phungductung	0:e87aa4c49e95	4920	/* Reset the Output Polarity level */
phungductung	0:e87aa4c49e95	4921	tmpccer &= ~TIM_CCER_CC3P;
phungductung	0:e87aa4c49e95	4922	/* Set the Output Compare Polarity */
phungductung	0:e87aa4c49e95	4923	tmpccer \|= (OC_Config->OCPolarity << 8);
phungductung	0:e87aa4c49e95	4924
phungductung	0:e87aa4c49e95	4925	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4926	{
phungductung	0:e87aa4c49e95	4927	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
phungductung	0:e87aa4c49e95	4928
phungductung	0:e87aa4c49e95	4929	/* Reset the Output N Polarity level */
phungductung	0:e87aa4c49e95	4930	tmpccer &= ~TIM_CCER_CC3NP;
phungductung	0:e87aa4c49e95	4931	/* Set the Output N Polarity */
phungductung	0:e87aa4c49e95	4932	tmpccer \|= (OC_Config->OCNPolarity << 8);
phungductung	0:e87aa4c49e95	4933	/* Reset the Output N State */
phungductung	0:e87aa4c49e95	4934	tmpccer &= ~TIM_CCER_CC3NE;
phungductung	0:e87aa4c49e95	4935
phungductung	0:e87aa4c49e95	4936	/* Reset the Output Compare and Output Compare N IDLE State */
phungductung	0:e87aa4c49e95	4937	tmpcr2 &= ~TIM_CR2_OIS3;
phungductung	0:e87aa4c49e95	4938	tmpcr2 &= ~TIM_CR2_OIS3N;
phungductung	0:e87aa4c49e95	4939	/* Set the Output Idle state */
phungductung	0:e87aa4c49e95	4940	tmpcr2 \|= (OC_Config->OCIdleState << 4);
phungductung	0:e87aa4c49e95	4941	/* Set the Output N Idle state */
phungductung	0:e87aa4c49e95	4942	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
phungductung	0:e87aa4c49e95	4943	}
phungductung	0:e87aa4c49e95	4944	/* Write to TIMx CR2 */
phungductung	0:e87aa4c49e95	4945	TIMx->CR2 = tmpcr2;
phungductung	0:e87aa4c49e95	4946
phungductung	0:e87aa4c49e95	4947	/* Write to TIMx CCMR2 */
phungductung	0:e87aa4c49e95	4948	TIMx->CCMR2 = tmpccmrx;
phungductung	0:e87aa4c49e95	4949
phungductung	0:e87aa4c49e95	4950	/* Set the Capture Compare Register value */
phungductung	0:e87aa4c49e95	4951	TIMx->CCR3 = OC_Config->Pulse;
phungductung	0:e87aa4c49e95	4952
phungductung	0:e87aa4c49e95	4953	/* Write to TIMx CCER */
phungductung	0:e87aa4c49e95	4954	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	4955	}
phungductung	0:e87aa4c49e95	4956
phungductung	0:e87aa4c49e95	4957	/**
phungductung	0:e87aa4c49e95	4958	* @brief Time Output Compare 4 configuration
phungductung	0:e87aa4c49e95	4959	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	4960	* @param OC_Config: The output configuration structure
phungductung	0:e87aa4c49e95	4961	* @retval None
phungductung	0:e87aa4c49e95	4962	*/
phungductung	0:e87aa4c49e95	4963	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
phungductung	0:e87aa4c49e95	4964	{
phungductung	0:e87aa4c49e95	4965	uint32_t tmpccmrx = 0;
phungductung	0:e87aa4c49e95	4966	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	4967	uint32_t tmpcr2 = 0;
phungductung	0:e87aa4c49e95	4968
phungductung	0:e87aa4c49e95	4969	/* Disable the Channel 4: Reset the CC4E Bit */
phungductung	0:e87aa4c49e95	4970	TIMx->CCER &= ~TIM_CCER_CC4E;
phungductung	0:e87aa4c49e95	4971
phungductung	0:e87aa4c49e95	4972	/* Get the TIMx CCER register value */
phungductung	0:e87aa4c49e95	4973	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	4974	/* Get the TIMx CR2 register value */
phungductung	0:e87aa4c49e95	4975	tmpcr2 = TIMx->CR2;
phungductung	0:e87aa4c49e95	4976
phungductung	0:e87aa4c49e95	4977	/* Get the TIMx CCMR2 register value */
phungductung	0:e87aa4c49e95	4978	tmpccmrx = TIMx->CCMR2;
phungductung	0:e87aa4c49e95	4979
phungductung	0:e87aa4c49e95	4980	/* Reset the Output Compare mode and Capture/Compare selection Bits */
phungductung	0:e87aa4c49e95	4981	tmpccmrx &= ~TIM_CCMR2_OC4M;
phungductung	0:e87aa4c49e95	4982	tmpccmrx &= ~TIM_CCMR2_CC4S;
phungductung	0:e87aa4c49e95	4983
phungductung	0:e87aa4c49e95	4984	/* Select the Output Compare Mode */
phungductung	0:e87aa4c49e95	4985	tmpccmrx \|= (OC_Config->OCMode << 8);
phungductung	0:e87aa4c49e95	4986
phungductung	0:e87aa4c49e95	4987	/* Reset the Output Polarity level */
phungductung	0:e87aa4c49e95	4988	tmpccer &= ~TIM_CCER_CC4P;
phungductung	0:e87aa4c49e95	4989	/* Set the Output Compare Polarity */
phungductung	0:e87aa4c49e95	4990	tmpccer \|= (OC_Config->OCPolarity << 12);
phungductung	0:e87aa4c49e95	4991
phungductung	0:e87aa4c49e95	4992	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
phungductung	0:e87aa4c49e95	4993	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	4994	{
phungductung	0:e87aa4c49e95	4995	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
phungductung	0:e87aa4c49e95	4996	/* Reset the Output Compare IDLE State */
phungductung	0:e87aa4c49e95	4997	tmpcr2 &= ~TIM_CR2_OIS4;
phungductung	0:e87aa4c49e95	4998	/* Set the Output Idle state */
phungductung	0:e87aa4c49e95	4999	tmpcr2 \|= (OC_Config->OCIdleState << 6);
phungductung	0:e87aa4c49e95	5000	}
phungductung	0:e87aa4c49e95	5001	/* Write to TIMx CR2 */
phungductung	0:e87aa4c49e95	5002	TIMx->CR2 = tmpcr2;
phungductung	0:e87aa4c49e95	5003
phungductung	0:e87aa4c49e95	5004	/* Write to TIMx CCMR2 */
phungductung	0:e87aa4c49e95	5005	TIMx->CCMR2 = tmpccmrx;
phungductung	0:e87aa4c49e95	5006
phungductung	0:e87aa4c49e95	5007	/* Set the Capture Compare Register value */
phungductung	0:e87aa4c49e95	5008	TIMx->CCR4 = OC_Config->Pulse;
phungductung	0:e87aa4c49e95	5009
phungductung	0:e87aa4c49e95	5010	/* Write to TIMx CCER */
phungductung	0:e87aa4c49e95	5011	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5012	}
phungductung	0:e87aa4c49e95	5013
phungductung	0:e87aa4c49e95	5014	/**
phungductung	0:e87aa4c49e95	5015	* @brief Time Output Compare 4 configuration
phungductung	0:e87aa4c49e95	5016	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	5017	* the configuration information for TIM module.
phungductung	0:e87aa4c49e95	5018	* @param sSlaveConfig: The slave configuration structure
phungductung	0:e87aa4c49e95	5019	* @retval None
phungductung	0:e87aa4c49e95	5020	*/
phungductung	0:e87aa4c49e95	5021	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
phungductung	0:e87aa4c49e95	5022	TIM_SlaveConfigTypeDef * sSlaveConfig)
phungductung	0:e87aa4c49e95	5023	{
phungductung	0:e87aa4c49e95	5024	uint32_t tmpsmcr = 0;
phungductung	0:e87aa4c49e95	5025	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	5026	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5027
phungductung	0:e87aa4c49e95	5028	/* Get the TIMx SMCR register value */
phungductung	0:e87aa4c49e95	5029	tmpsmcr = htim->Instance->SMCR;
phungductung	0:e87aa4c49e95	5030
phungductung	0:e87aa4c49e95	5031	/* Reset the Trigger Selection Bits */
phungductung	0:e87aa4c49e95	5032	tmpsmcr &= ~TIM_SMCR_TS;
phungductung	0:e87aa4c49e95	5033	/* Set the Input Trigger source */
phungductung	0:e87aa4c49e95	5034	tmpsmcr \|= sSlaveConfig->InputTrigger;
phungductung	0:e87aa4c49e95	5035
phungductung	0:e87aa4c49e95	5036	/* Reset the slave mode Bits */
phungductung	0:e87aa4c49e95	5037	tmpsmcr &= ~TIM_SMCR_SMS;
phungductung	0:e87aa4c49e95	5038	/* Set the slave mode */
phungductung	0:e87aa4c49e95	5039	tmpsmcr \|= sSlaveConfig->SlaveMode;
phungductung	0:e87aa4c49e95	5040
phungductung	0:e87aa4c49e95	5041	/* Write to TIMx SMCR */
phungductung	0:e87aa4c49e95	5042	htim->Instance->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	5043
phungductung	0:e87aa4c49e95	5044	/* Configure the trigger prescaler, filter, and polarity */
phungductung	0:e87aa4c49e95	5045	switch (sSlaveConfig->InputTrigger)
phungductung	0:e87aa4c49e95	5046	{
phungductung	0:e87aa4c49e95	5047	case TIM_TS_ETRF:
phungductung	0:e87aa4c49e95	5048	{
phungductung	0:e87aa4c49e95	5049	/* Check the parameters */
phungductung	0:e87aa4c49e95	5050	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5051	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
phungductung	0:e87aa4c49e95	5052	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	5053	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	5054	/* Configure the ETR Trigger source */
phungductung	0:e87aa4c49e95	5055	TIM_ETR_SetConfig(htim->Instance,
phungductung	0:e87aa4c49e95	5056	sSlaveConfig->TriggerPrescaler,
phungductung	0:e87aa4c49e95	5057	sSlaveConfig->TriggerPolarity,
phungductung	0:e87aa4c49e95	5058	sSlaveConfig->TriggerFilter);
phungductung	0:e87aa4c49e95	5059	}
phungductung	0:e87aa4c49e95	5060	break;
phungductung	0:e87aa4c49e95	5061
phungductung	0:e87aa4c49e95	5062	case TIM_TS_TI1F_ED:
phungductung	0:e87aa4c49e95	5063	{
phungductung	0:e87aa4c49e95	5064	/* Check the parameters */
phungductung	0:e87aa4c49e95	5065	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5066	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	5067	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	5068
phungductung	0:e87aa4c49e95	5069	/* Disable the Channel 1: Reset the CC1E Bit */
phungductung	0:e87aa4c49e95	5070	tmpccer = htim->Instance->CCER;
phungductung	0:e87aa4c49e95	5071	htim->Instance->CCER &= ~TIM_CCER_CC1E;
phungductung	0:e87aa4c49e95	5072	tmpccmr1 = htim->Instance->CCMR1;
phungductung	0:e87aa4c49e95	5073
phungductung	0:e87aa4c49e95	5074	/* Set the filter */
phungductung	0:e87aa4c49e95	5075	tmpccmr1 &= ~TIM_CCMR1_IC1F;
phungductung	0:e87aa4c49e95	5076	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
phungductung	0:e87aa4c49e95	5077
phungductung	0:e87aa4c49e95	5078	/* Write to TIMx CCMR1 and CCER registers */
phungductung	0:e87aa4c49e95	5079	htim->Instance->CCMR1 = tmpccmr1;
phungductung	0:e87aa4c49e95	5080	htim->Instance->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5081
phungductung	0:e87aa4c49e95	5082	}
phungductung	0:e87aa4c49e95	5083	break;
phungductung	0:e87aa4c49e95	5084
phungductung	0:e87aa4c49e95	5085	case TIM_TS_TI1FP1:
phungductung	0:e87aa4c49e95	5086	{
phungductung	0:e87aa4c49e95	5087	/* Check the parameters */
phungductung	0:e87aa4c49e95	5088	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5089	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	5090	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	5091
phungductung	0:e87aa4c49e95	5092	/* Configure TI1 Filter and Polarity */
phungductung	0:e87aa4c49e95	5093	TIM_TI1_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	5094	sSlaveConfig->TriggerPolarity,
phungductung	0:e87aa4c49e95	5095	sSlaveConfig->TriggerFilter);
phungductung	0:e87aa4c49e95	5096	}
phungductung	0:e87aa4c49e95	5097	break;
phungductung	0:e87aa4c49e95	5098
phungductung	0:e87aa4c49e95	5099	case TIM_TS_TI2FP2:
phungductung	0:e87aa4c49e95	5100	{
phungductung	0:e87aa4c49e95	5101	/* Check the parameters */
phungductung	0:e87aa4c49e95	5102	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5103	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
phungductung	0:e87aa4c49e95	5104	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
phungductung	0:e87aa4c49e95	5105
phungductung	0:e87aa4c49e95	5106	/* Configure TI2 Filter and Polarity */
phungductung	0:e87aa4c49e95	5107	TIM_TI2_ConfigInputStage(htim->Instance,
phungductung	0:e87aa4c49e95	5108	sSlaveConfig->TriggerPolarity,
phungductung	0:e87aa4c49e95	5109	sSlaveConfig->TriggerFilter);
phungductung	0:e87aa4c49e95	5110	}
phungductung	0:e87aa4c49e95	5111	break;
phungductung	0:e87aa4c49e95	5112
phungductung	0:e87aa4c49e95	5113	case TIM_TS_ITR0:
phungductung	0:e87aa4c49e95	5114	{
phungductung	0:e87aa4c49e95	5115	/* Check the parameter */
phungductung	0:e87aa4c49e95	5116	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5117	}
phungductung	0:e87aa4c49e95	5118	break;
phungductung	0:e87aa4c49e95	5119
phungductung	0:e87aa4c49e95	5120	case TIM_TS_ITR1:
phungductung	0:e87aa4c49e95	5121	{
phungductung	0:e87aa4c49e95	5122	/* Check the parameter */
phungductung	0:e87aa4c49e95	5123	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5124	}
phungductung	0:e87aa4c49e95	5125	break;
phungductung	0:e87aa4c49e95	5126
phungductung	0:e87aa4c49e95	5127	case TIM_TS_ITR2:
phungductung	0:e87aa4c49e95	5128	{
phungductung	0:e87aa4c49e95	5129	/* Check the parameter */
phungductung	0:e87aa4c49e95	5130	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5131	}
phungductung	0:e87aa4c49e95	5132	break;
phungductung	0:e87aa4c49e95	5133
phungductung	0:e87aa4c49e95	5134	case TIM_TS_ITR3:
phungductung	0:e87aa4c49e95	5135	{
phungductung	0:e87aa4c49e95	5136	/* Check the parameter */
phungductung	0:e87aa4c49e95	5137	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
phungductung	0:e87aa4c49e95	5138	}
phungductung	0:e87aa4c49e95	5139	break;
phungductung	0:e87aa4c49e95	5140
phungductung	0:e87aa4c49e95	5141	default:
phungductung	0:e87aa4c49e95	5142	break;
phungductung	0:e87aa4c49e95	5143	}
phungductung	0:e87aa4c49e95	5144	}
phungductung	0:e87aa4c49e95	5145
phungductung	0:e87aa4c49e95	5146	/**
phungductung	0:e87aa4c49e95	5147	* @brief Configure the TI1 as Input.
phungductung	0:e87aa4c49e95	5148	* @param TIMx to select the TIM peripheral.
phungductung	0:e87aa4c49e95	5149	* @param TIM_ICPolarity : The Input Polarity.
phungductung	0:e87aa4c49e95	5150	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5151	* @arg TIM_ICPolarity_Rising
phungductung	0:e87aa4c49e95	5152	* @arg TIM_ICPolarity_Falling
phungductung	0:e87aa4c49e95	5153	* @arg TIM_ICPolarity_BothEdge
phungductung	0:e87aa4c49e95	5154	* @param TIM_ICSelection: specifies the input to be used.
phungductung	0:e87aa4c49e95	5155	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5156	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
phungductung	0:e87aa4c49e95	5157	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
phungductung	0:e87aa4c49e95	5158	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
phungductung	0:e87aa4c49e95	5159	* @param TIM_ICFilter: Specifies the Input Capture Filter.
phungductung	0:e87aa4c49e95	5160	* This parameter must be a value between 0x00 and 0x0F.
phungductung	0:e87aa4c49e95	5161	* @retval None
phungductung	0:e87aa4c49e95	5162	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
phungductung	0:e87aa4c49e95	5163	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
phungductung	0:e87aa4c49e95	5164	* protected against un-initialized filter and polarity values.
phungductung	0:e87aa4c49e95	5165	*/
phungductung	0:e87aa4c49e95	5166	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	5167	uint32_t TIM_ICFilter)
phungductung	0:e87aa4c49e95	5168	{
phungductung	0:e87aa4c49e95	5169	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	5170	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5171
phungductung	0:e87aa4c49e95	5172	/* Disable the Channel 1: Reset the CC1E Bit */
phungductung	0:e87aa4c49e95	5173	TIMx->CCER &= ~TIM_CCER_CC1E;
phungductung	0:e87aa4c49e95	5174	tmpccmr1 = TIMx->CCMR1;
phungductung	0:e87aa4c49e95	5175	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	5176
phungductung	0:e87aa4c49e95	5177	/* Select the Input */
phungductung	0:e87aa4c49e95	5178	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
phungductung	0:e87aa4c49e95	5179	{
phungductung	0:e87aa4c49e95	5180	tmpccmr1 &= ~TIM_CCMR1_CC1S;
phungductung	0:e87aa4c49e95	5181	tmpccmr1 \|= TIM_ICSelection;
phungductung	0:e87aa4c49e95	5182	}
phungductung	0:e87aa4c49e95	5183	else
phungductung	0:e87aa4c49e95	5184	{
phungductung	0:e87aa4c49e95	5185	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
phungductung	0:e87aa4c49e95	5186	}
phungductung	0:e87aa4c49e95	5187
phungductung	0:e87aa4c49e95	5188	/* Set the filter */
phungductung	0:e87aa4c49e95	5189	tmpccmr1 &= ~TIM_CCMR1_IC1F;
phungductung	0:e87aa4c49e95	5190	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
phungductung	0:e87aa4c49e95	5191
phungductung	0:e87aa4c49e95	5192	/* Select the Polarity and set the CC1E Bit */
phungductung	0:e87aa4c49e95	5193	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
phungductung	0:e87aa4c49e95	5194	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
phungductung	0:e87aa4c49e95	5195
phungductung	0:e87aa4c49e95	5196	/* Write to TIMx CCMR1 and CCER registers */
phungductung	0:e87aa4c49e95	5197	TIMx->CCMR1 = tmpccmr1;
phungductung	0:e87aa4c49e95	5198	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5199	}
phungductung	0:e87aa4c49e95	5200
phungductung	0:e87aa4c49e95	5201	/**
phungductung	0:e87aa4c49e95	5202	* @brief Configure the Polarity and Filter for TI1.
phungductung	0:e87aa4c49e95	5203	* @param TIMx to select the TIM peripheral.
phungductung	0:e87aa4c49e95	5204	* @param TIM_ICPolarity : The Input Polarity.
phungductung	0:e87aa4c49e95	5205	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5206	* @arg TIM_ICPolarity_Rising
phungductung	0:e87aa4c49e95	5207	* @arg TIM_ICPolarity_Falling
phungductung	0:e87aa4c49e95	5208	* @arg TIM_ICPolarity_BothEdge
phungductung	0:e87aa4c49e95	5209	* @param TIM_ICFilter: Specifies the Input Capture Filter.
phungductung	0:e87aa4c49e95	5210	* This parameter must be a value between 0x00 and 0x0F.
phungductung	0:e87aa4c49e95	5211	* @retval None
phungductung	0:e87aa4c49e95	5212	*/
phungductung	0:e87aa4c49e95	5213	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
phungductung	0:e87aa4c49e95	5214	{
phungductung	0:e87aa4c49e95	5215	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	5216	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5217
phungductung	0:e87aa4c49e95	5218	/* Disable the Channel 1: Reset the CC1E Bit */
phungductung	0:e87aa4c49e95	5219	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	5220	TIMx->CCER &= ~TIM_CCER_CC1E;
phungductung	0:e87aa4c49e95	5221	tmpccmr1 = TIMx->CCMR1;
phungductung	0:e87aa4c49e95	5222
phungductung	0:e87aa4c49e95	5223	/* Set the filter */
phungductung	0:e87aa4c49e95	5224	tmpccmr1 &= ~TIM_CCMR1_IC1F;
phungductung	0:e87aa4c49e95	5225	tmpccmr1 \|= (TIM_ICFilter << 4);
phungductung	0:e87aa4c49e95	5226
phungductung	0:e87aa4c49e95	5227	/* Select the Polarity and set the CC1E Bit */
phungductung	0:e87aa4c49e95	5228	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
phungductung	0:e87aa4c49e95	5229	tmpccer \|= TIM_ICPolarity;
phungductung	0:e87aa4c49e95	5230
phungductung	0:e87aa4c49e95	5231	/* Write to TIMx CCMR1 and CCER registers */
phungductung	0:e87aa4c49e95	5232	TIMx->CCMR1 = tmpccmr1;
phungductung	0:e87aa4c49e95	5233	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5234	}
phungductung	0:e87aa4c49e95	5235
phungductung	0:e87aa4c49e95	5236	/**
phungductung	0:e87aa4c49e95	5237	* @brief Configure the TI2 as Input.
phungductung	0:e87aa4c49e95	5238	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	5239	* @param TIM_ICPolarity : The Input Polarity.
phungductung	0:e87aa4c49e95	5240	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5241	* @arg TIM_ICPolarity_Rising
phungductung	0:e87aa4c49e95	5242	* @arg TIM_ICPolarity_Falling
phungductung	0:e87aa4c49e95	5243	* @arg TIM_ICPolarity_BothEdge
phungductung	0:e87aa4c49e95	5244	* @param TIM_ICSelection: specifies the input to be used.
phungductung	0:e87aa4c49e95	5245	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5246	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
phungductung	0:e87aa4c49e95	5247	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
phungductung	0:e87aa4c49e95	5248	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
phungductung	0:e87aa4c49e95	5249	* @param TIM_ICFilter: Specifies the Input Capture Filter.
phungductung	0:e87aa4c49e95	5250	* This parameter must be a value between 0x00 and 0x0F.
phungductung	0:e87aa4c49e95	5251	* @retval None
phungductung	0:e87aa4c49e95	5252	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
phungductung	0:e87aa4c49e95	5253	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
phungductung	0:e87aa4c49e95	5254	* protected against un-initialized filter and polarity values.
phungductung	0:e87aa4c49e95	5255	*/
phungductung	0:e87aa4c49e95	5256	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	5257	uint32_t TIM_ICFilter)
phungductung	0:e87aa4c49e95	5258	{
phungductung	0:e87aa4c49e95	5259	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	5260	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5261
phungductung	0:e87aa4c49e95	5262	/* Disable the Channel 2: Reset the CC2E Bit */
phungductung	0:e87aa4c49e95	5263	TIMx->CCER &= ~TIM_CCER_CC2E;
phungductung	0:e87aa4c49e95	5264	tmpccmr1 = TIMx->CCMR1;
phungductung	0:e87aa4c49e95	5265	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	5266
phungductung	0:e87aa4c49e95	5267	/* Select the Input */
phungductung	0:e87aa4c49e95	5268	tmpccmr1 &= ~TIM_CCMR1_CC2S;
phungductung	0:e87aa4c49e95	5269	tmpccmr1 \|= (TIM_ICSelection << 8);
phungductung	0:e87aa4c49e95	5270
phungductung	0:e87aa4c49e95	5271	/* Set the filter */
phungductung	0:e87aa4c49e95	5272	tmpccmr1 &= ~TIM_CCMR1_IC2F;
phungductung	0:e87aa4c49e95	5273	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
phungductung	0:e87aa4c49e95	5274
phungductung	0:e87aa4c49e95	5275	/* Select the Polarity and set the CC2E Bit */
phungductung	0:e87aa4c49e95	5276	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
phungductung	0:e87aa4c49e95	5277	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
phungductung	0:e87aa4c49e95	5278
phungductung	0:e87aa4c49e95	5279	/* Write to TIMx CCMR1 and CCER registers */
phungductung	0:e87aa4c49e95	5280	TIMx->CCMR1 = tmpccmr1 ;
phungductung	0:e87aa4c49e95	5281	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5282	}
phungductung	0:e87aa4c49e95	5283
phungductung	0:e87aa4c49e95	5284	/**
phungductung	0:e87aa4c49e95	5285	* @brief Configure the Polarity and Filter for TI2.
phungductung	0:e87aa4c49e95	5286	* @param TIMx to select the TIM peripheral.
phungductung	0:e87aa4c49e95	5287	* @param TIM_ICPolarity : The Input Polarity.
phungductung	0:e87aa4c49e95	5288	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5289	* @arg TIM_ICPolarity_Rising
phungductung	0:e87aa4c49e95	5290	* @arg TIM_ICPolarity_Falling
phungductung	0:e87aa4c49e95	5291	* @arg TIM_ICPolarity_BothEdge
phungductung	0:e87aa4c49e95	5292	* @param TIM_ICFilter: Specifies the Input Capture Filter.
phungductung	0:e87aa4c49e95	5293	* This parameter must be a value between 0x00 and 0x0F.
phungductung	0:e87aa4c49e95	5294	* @retval None
phungductung	0:e87aa4c49e95	5295	*/
phungductung	0:e87aa4c49e95	5296	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
phungductung	0:e87aa4c49e95	5297	{
phungductung	0:e87aa4c49e95	5298	uint32_t tmpccmr1 = 0;
phungductung	0:e87aa4c49e95	5299	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5300
phungductung	0:e87aa4c49e95	5301	/* Disable the Channel 2: Reset the CC2E Bit */
phungductung	0:e87aa4c49e95	5302	TIMx->CCER &= ~TIM_CCER_CC2E;
phungductung	0:e87aa4c49e95	5303	tmpccmr1 = TIMx->CCMR1;
phungductung	0:e87aa4c49e95	5304	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	5305
phungductung	0:e87aa4c49e95	5306	/* Set the filter */
phungductung	0:e87aa4c49e95	5307	tmpccmr1 &= ~TIM_CCMR1_IC2F;
phungductung	0:e87aa4c49e95	5308	tmpccmr1 \|= (TIM_ICFilter << 12);
phungductung	0:e87aa4c49e95	5309
phungductung	0:e87aa4c49e95	5310	/* Select the Polarity and set the CC2E Bit */
phungductung	0:e87aa4c49e95	5311	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
phungductung	0:e87aa4c49e95	5312	tmpccer \|= (TIM_ICPolarity << 4);
phungductung	0:e87aa4c49e95	5313
phungductung	0:e87aa4c49e95	5314	/* Write to TIMx CCMR1 and CCER registers */
phungductung	0:e87aa4c49e95	5315	TIMx->CCMR1 = tmpccmr1 ;
phungductung	0:e87aa4c49e95	5316	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5317	}
phungductung	0:e87aa4c49e95	5318
phungductung	0:e87aa4c49e95	5319	/**
phungductung	0:e87aa4c49e95	5320	* @brief Configure the TI3 as Input.
phungductung	0:e87aa4c49e95	5321	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	5322	* @param TIM_ICPolarity : The Input Polarity.
phungductung	0:e87aa4c49e95	5323	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5324	* @arg TIM_ICPolarity_Rising
phungductung	0:e87aa4c49e95	5325	* @arg TIM_ICPolarity_Falling
phungductung	0:e87aa4c49e95	5326	* @arg TIM_ICPolarity_BothEdge
phungductung	0:e87aa4c49e95	5327	* @param TIM_ICSelection: specifies the input to be used.
phungductung	0:e87aa4c49e95	5328	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5329	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
phungductung	0:e87aa4c49e95	5330	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
phungductung	0:e87aa4c49e95	5331	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
phungductung	0:e87aa4c49e95	5332	* @param TIM_ICFilter: Specifies the Input Capture Filter.
phungductung	0:e87aa4c49e95	5333	* This parameter must be a value between 0x00 and 0x0F.
phungductung	0:e87aa4c49e95	5334	* @retval None
phungductung	0:e87aa4c49e95	5335	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
phungductung	0:e87aa4c49e95	5336	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
phungductung	0:e87aa4c49e95	5337	* protected against un-initialized filter and polarity values.
phungductung	0:e87aa4c49e95	5338	*/
phungductung	0:e87aa4c49e95	5339	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	5340	uint32_t TIM_ICFilter)
phungductung	0:e87aa4c49e95	5341	{
phungductung	0:e87aa4c49e95	5342	uint32_t tmpccmr2 = 0;
phungductung	0:e87aa4c49e95	5343	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5344
phungductung	0:e87aa4c49e95	5345	/* Disable the Channel 3: Reset the CC3E Bit */
phungductung	0:e87aa4c49e95	5346	TIMx->CCER &= ~TIM_CCER_CC3E;
phungductung	0:e87aa4c49e95	5347	tmpccmr2 = TIMx->CCMR2;
phungductung	0:e87aa4c49e95	5348	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	5349
phungductung	0:e87aa4c49e95	5350	/* Select the Input */
phungductung	0:e87aa4c49e95	5351	tmpccmr2 &= ~TIM_CCMR2_CC3S;
phungductung	0:e87aa4c49e95	5352	tmpccmr2 \|= TIM_ICSelection;
phungductung	0:e87aa4c49e95	5353
phungductung	0:e87aa4c49e95	5354	/* Set the filter */
phungductung	0:e87aa4c49e95	5355	tmpccmr2 &= ~TIM_CCMR2_IC3F;
phungductung	0:e87aa4c49e95	5356	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
phungductung	0:e87aa4c49e95	5357
phungductung	0:e87aa4c49e95	5358	/* Select the Polarity and set the CC3E Bit */
phungductung	0:e87aa4c49e95	5359	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
phungductung	0:e87aa4c49e95	5360	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
phungductung	0:e87aa4c49e95	5361
phungductung	0:e87aa4c49e95	5362	/* Write to TIMx CCMR2 and CCER registers */
phungductung	0:e87aa4c49e95	5363	TIMx->CCMR2 = tmpccmr2;
phungductung	0:e87aa4c49e95	5364	TIMx->CCER = tmpccer;
phungductung	0:e87aa4c49e95	5365	}
phungductung	0:e87aa4c49e95	5366
phungductung	0:e87aa4c49e95	5367	/**
phungductung	0:e87aa4c49e95	5368	* @brief Configure the TI4 as Input.
phungductung	0:e87aa4c49e95	5369	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	5370	* @param TIM_ICPolarity : The Input Polarity.
phungductung	0:e87aa4c49e95	5371	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5372	* @arg TIM_ICPolarity_Rising
phungductung	0:e87aa4c49e95	5373	* @arg TIM_ICPolarity_Falling
phungductung	0:e87aa4c49e95	5374	* @arg TIM_ICPolarity_BothEdge
phungductung	0:e87aa4c49e95	5375	* @param TIM_ICSelection: specifies the input to be used.
phungductung	0:e87aa4c49e95	5376	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5377	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
phungductung	0:e87aa4c49e95	5378	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
phungductung	0:e87aa4c49e95	5379	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
phungductung	0:e87aa4c49e95	5380	* @param TIM_ICFilter: Specifies the Input Capture Filter.
phungductung	0:e87aa4c49e95	5381	* This parameter must be a value between 0x00 and 0x0F.
phungductung	0:e87aa4c49e95	5382	* @retval None
phungductung	0:e87aa4c49e95	5383	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
phungductung	0:e87aa4c49e95	5384	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
phungductung	0:e87aa4c49e95	5385	* protected against un-initialized filter and polarity values.
phungductung	0:e87aa4c49e95	5386	*/
phungductung	0:e87aa4c49e95	5387	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
phungductung	0:e87aa4c49e95	5388	uint32_t TIM_ICFilter)
phungductung	0:e87aa4c49e95	5389	{
phungductung	0:e87aa4c49e95	5390	uint32_t tmpccmr2 = 0;
phungductung	0:e87aa4c49e95	5391	uint32_t tmpccer = 0;
phungductung	0:e87aa4c49e95	5392
phungductung	0:e87aa4c49e95	5393	/* Disable the Channel 4: Reset the CC4E Bit */
phungductung	0:e87aa4c49e95	5394	TIMx->CCER &= ~TIM_CCER_CC4E;
phungductung	0:e87aa4c49e95	5395	tmpccmr2 = TIMx->CCMR2;
phungductung	0:e87aa4c49e95	5396	tmpccer = TIMx->CCER;
phungductung	0:e87aa4c49e95	5397
phungductung	0:e87aa4c49e95	5398	/* Select the Input */
phungductung	0:e87aa4c49e95	5399	tmpccmr2 &= ~TIM_CCMR2_CC4S;
phungductung	0:e87aa4c49e95	5400	tmpccmr2 \|= (TIM_ICSelection << 8);
phungductung	0:e87aa4c49e95	5401
phungductung	0:e87aa4c49e95	5402	/* Set the filter */
phungductung	0:e87aa4c49e95	5403	tmpccmr2 &= ~TIM_CCMR2_IC4F;
phungductung	0:e87aa4c49e95	5404	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
phungductung	0:e87aa4c49e95	5405
phungductung	0:e87aa4c49e95	5406	/* Select the Polarity and set the CC4E Bit */
phungductung	0:e87aa4c49e95	5407	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
phungductung	0:e87aa4c49e95	5408	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
phungductung	0:e87aa4c49e95	5409
phungductung	0:e87aa4c49e95	5410	/* Write to TIMx CCMR2 and CCER registers */
phungductung	0:e87aa4c49e95	5411	TIMx->CCMR2 = tmpccmr2;
phungductung	0:e87aa4c49e95	5412	TIMx->CCER = tmpccer ;
phungductung	0:e87aa4c49e95	5413	}
phungductung	0:e87aa4c49e95	5414
phungductung	0:e87aa4c49e95	5415	/**
phungductung	0:e87aa4c49e95	5416	* @brief Selects the Input Trigger source
phungductung	0:e87aa4c49e95	5417	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	5418	* @param TIM_ITRx: The Input Trigger source.
phungductung	0:e87aa4c49e95	5419	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5420	* @arg TIM_TS_ITR0: Internal Trigger 0
phungductung	0:e87aa4c49e95	5421	* @arg TIM_TS_ITR1: Internal Trigger 1
phungductung	0:e87aa4c49e95	5422	* @arg TIM_TS_ITR2: Internal Trigger 2
phungductung	0:e87aa4c49e95	5423	* @arg TIM_TS_ITR3: Internal Trigger 3
phungductung	0:e87aa4c49e95	5424	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
phungductung	0:e87aa4c49e95	5425	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
phungductung	0:e87aa4c49e95	5426	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
phungductung	0:e87aa4c49e95	5427	* @arg TIM_TS_ETRF: External Trigger input
phungductung	0:e87aa4c49e95	5428	* @retval None
phungductung	0:e87aa4c49e95	5429	*/
phungductung	0:e87aa4c49e95	5430	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
phungductung	0:e87aa4c49e95	5431	{
phungductung	0:e87aa4c49e95	5432	uint32_t tmpsmcr = 0;
phungductung	0:e87aa4c49e95	5433
phungductung	0:e87aa4c49e95	5434	/* Get the TIMx SMCR register value */
phungductung	0:e87aa4c49e95	5435	tmpsmcr = TIMx->SMCR;
phungductung	0:e87aa4c49e95	5436	/* Reset the TS Bits */
phungductung	0:e87aa4c49e95	5437	tmpsmcr &= ~TIM_SMCR_TS;
phungductung	0:e87aa4c49e95	5438	/* Set the Input Trigger source and the slave mode*/
phungductung	0:e87aa4c49e95	5439	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
phungductung	0:e87aa4c49e95	5440	/* Write to TIMx SMCR */
phungductung	0:e87aa4c49e95	5441	TIMx->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	5442	}
phungductung	0:e87aa4c49e95	5443
phungductung	0:e87aa4c49e95	5444	/**
phungductung	0:e87aa4c49e95	5445	* @brief Configures the TIMx External Trigger (ETR).
phungductung	0:e87aa4c49e95	5446	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	5447	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
phungductung	0:e87aa4c49e95	5448	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5449	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
phungductung	0:e87aa4c49e95	5450	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
phungductung	0:e87aa4c49e95	5451	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
phungductung	0:e87aa4c49e95	5452	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
phungductung	0:e87aa4c49e95	5453	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
phungductung	0:e87aa4c49e95	5454	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5455	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
phungductung	0:e87aa4c49e95	5456	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
phungductung	0:e87aa4c49e95	5457	* @param ExtTRGFilter: External Trigger Filter.
phungductung	0:e87aa4c49e95	5458	* This parameter must be a value between 0x00 and 0x0F
phungductung	0:e87aa4c49e95	5459	* @retval None
phungductung	0:e87aa4c49e95	5460	*/
phungductung	0:e87aa4c49e95	5461	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
phungductung	0:e87aa4c49e95	5462	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
phungductung	0:e87aa4c49e95	5463	{
phungductung	0:e87aa4c49e95	5464	uint32_t tmpsmcr = 0;
phungductung	0:e87aa4c49e95	5465
phungductung	0:e87aa4c49e95	5466	tmpsmcr = TIMx->SMCR;
phungductung	0:e87aa4c49e95	5467
phungductung	0:e87aa4c49e95	5468	/* Reset the ETR Bits */
phungductung	0:e87aa4c49e95	5469	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
phungductung	0:e87aa4c49e95	5470
phungductung	0:e87aa4c49e95	5471	/* Set the Prescaler, the Filter value and the Polarity */
phungductung	0:e87aa4c49e95	5472	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
phungductung	0:e87aa4c49e95	5473
phungductung	0:e87aa4c49e95	5474	/* Write to TIMx SMCR */
phungductung	0:e87aa4c49e95	5475	TIMx->SMCR = tmpsmcr;
phungductung	0:e87aa4c49e95	5476	}
phungductung	0:e87aa4c49e95	5477
phungductung	0:e87aa4c49e95	5478	/**
phungductung	0:e87aa4c49e95	5479	* @brief Enables or disables the TIM Capture Compare Channel x.
phungductung	0:e87aa4c49e95	5480	* @param TIMx to select the TIM peripheral
phungductung	0:e87aa4c49e95	5481	* @param Channel: specifies the TIM Channel
phungductung	0:e87aa4c49e95	5482	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	5483	* @arg TIM_Channel_1: TIM Channel 1
phungductung	0:e87aa4c49e95	5484	* @arg TIM_Channel_2: TIM Channel 2
phungductung	0:e87aa4c49e95	5485	* @arg TIM_Channel_3: TIM Channel 3
phungductung	0:e87aa4c49e95	5486	* @arg TIM_Channel_4: TIM Channel 4
phungductung	0:e87aa4c49e95	5487	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
phungductung	0:e87aa4c49e95	5488	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
phungductung	0:e87aa4c49e95	5489	* @retval None
phungductung	0:e87aa4c49e95	5490	*/
phungductung	0:e87aa4c49e95	5491	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
phungductung	0:e87aa4c49e95	5492	{
phungductung	0:e87aa4c49e95	5493	uint32_t tmp = 0;
phungductung	0:e87aa4c49e95	5494
phungductung	0:e87aa4c49e95	5495	/* Check the parameters */
phungductung	0:e87aa4c49e95	5496	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
phungductung	0:e87aa4c49e95	5497	assert_param(IS_TIM_CHANNELS(Channel));
phungductung	0:e87aa4c49e95	5498
phungductung	0:e87aa4c49e95	5499	tmp = TIM_CCER_CC1E << Channel;
phungductung	0:e87aa4c49e95	5500
phungductung	0:e87aa4c49e95	5501	/* Reset the CCxE Bit */
phungductung	0:e87aa4c49e95	5502	TIMx->CCER &= ~tmp;
phungductung	0:e87aa4c49e95	5503
phungductung	0:e87aa4c49e95	5504	/* Set or reset the CCxE Bit */
phungductung	0:e87aa4c49e95	5505	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
phungductung	0:e87aa4c49e95	5506	}
phungductung	0:e87aa4c49e95	5507
phungductung	0:e87aa4c49e95	5508
phungductung	0:e87aa4c49e95	5509	/**
phungductung	0:e87aa4c49e95	5510	* @}
phungductung	0:e87aa4c49e95	5511	*/
phungductung	0:e87aa4c49e95	5512
phungductung	0:e87aa4c49e95	5513	#endif /* HAL_TIM_MODULE_ENABLED */
phungductung	0:e87aa4c49e95	5514	/**
phungductung	0:e87aa4c49e95	5515	* @}
phungductung	0:e87aa4c49e95	5516	*/
phungductung	0:e87aa4c49e95	5517
phungductung	0:e87aa4c49e95	5518	/**
phungductung	0:e87aa4c49e95	5519	* @}
phungductung	0:e87aa4c49e95	5520	*/
phungductung	0:e87aa4c49e95	5521	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Jun 2019
Imports:	8
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@0:e87aa4c49e95, 2019-06-04 (annotated)

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