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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

libray

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User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/**
phungductung	0:e87aa4c49e95	2	******************************************************************************
phungductung	0:e87aa4c49e95	3	* @file stm32f7xx_hal_eth.h
phungductung	0:e87aa4c49e95	4	* @author MCD Application Team
phungductung	0:e87aa4c49e95	5	* @version V1.0.4
phungductung	0:e87aa4c49e95	6	* @date 09-December-2015
phungductung	0:e87aa4c49e95	7	* @brief Header file of ETH HAL module.
phungductung	0:e87aa4c49e95	8	******************************************************************************
phungductung	0:e87aa4c49e95	9	* @attention
phungductung	0:e87aa4c49e95	10	*
phungductung	0:e87aa4c49e95	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung	0:e87aa4c49e95	12	*
phungductung	0:e87aa4c49e95	13	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:e87aa4c49e95	14	* are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	15	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:e87aa4c49e95	16	* this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:e87aa4c49e95	18	* this list of conditions and the following disclaimer in the documentation
phungductung	0:e87aa4c49e95	19	* and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:e87aa4c49e95	21	* may be used to endorse or promote products derived from this software
phungductung	0:e87aa4c49e95	22	* without specific prior written permission.
phungductung	0:e87aa4c49e95	23	*
phungductung	0:e87aa4c49e95	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:e87aa4c49e95	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:e87aa4c49e95	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:e87aa4c49e95	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:e87aa4c49e95	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:e87aa4c49e95	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:e87aa4c49e95	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:e87aa4c49e95	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	34	*
phungductung	0:e87aa4c49e95	35	******************************************************************************
phungductung	0:e87aa4c49e95	36	*/
phungductung	0:e87aa4c49e95	37
phungductung	0:e87aa4c49e95	38	/* Define to prevent recursive inclusion -------------------------------------*/
phungductung	0:e87aa4c49e95	39	#ifndef __STM32F7xx_HAL_ETH_H
phungductung	0:e87aa4c49e95	40	#define __STM32F7xx_HAL_ETH_H
phungductung	0:e87aa4c49e95	41
phungductung	0:e87aa4c49e95	42	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	43	extern "C" {
phungductung	0:e87aa4c49e95	44	#endif
phungductung	0:e87aa4c49e95	45
phungductung	0:e87aa4c49e95	46	/* Includes ------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	47	#include "stm32f7xx_hal_def.h"
phungductung	0:e87aa4c49e95	48
phungductung	0:e87aa4c49e95	49	/** @addtogroup STM32F7xx_HAL_Driver
phungductung	0:e87aa4c49e95	50	* @{
phungductung	0:e87aa4c49e95	51	*/
phungductung	0:e87aa4c49e95	52
phungductung	0:e87aa4c49e95	53	/** @addtogroup ETH
phungductung	0:e87aa4c49e95	54	* @{
phungductung	0:e87aa4c49e95	55	*/
phungductung	0:e87aa4c49e95	56
phungductung	0:e87aa4c49e95	57	/** @addtogroup ETH_Private_Macros
phungductung	0:e87aa4c49e95	58	* @{
phungductung	0:e87aa4c49e95	59	*/
phungductung	0:e87aa4c49e95	60	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
phungductung	0:e87aa4c49e95	61	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	62	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
phungductung	0:e87aa4c49e95	63	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
phungductung	0:e87aa4c49e95	64	((SPEED) == ETH_SPEED_100M))
phungductung	0:e87aa4c49e95	65	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
phungductung	0:e87aa4c49e95	66	((MODE) == ETH_MODE_HALFDUPLEX))
phungductung	0:e87aa4c49e95	67	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
phungductung	0:e87aa4c49e95	68	((MODE) == ETH_RXINTERRUPT_MODE))
phungductung	0:e87aa4c49e95	69	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
phungductung	0:e87aa4c49e95	70	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
phungductung	0:e87aa4c49e95	71	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
phungductung	0:e87aa4c49e95	72	((MODE) == ETH_MEDIA_INTERFACE_RMII))
phungductung	0:e87aa4c49e95	73	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	74	((CMD) == ETH_WATCHDOG_DISABLE))
phungductung	0:e87aa4c49e95	75	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	76	((CMD) == ETH_JABBER_DISABLE))
phungductung	0:e87aa4c49e95	77	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
phungductung	0:e87aa4c49e95	78	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
phungductung	0:e87aa4c49e95	79	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
phungductung	0:e87aa4c49e95	80	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
phungductung	0:e87aa4c49e95	81	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
phungductung	0:e87aa4c49e95	82	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
phungductung	0:e87aa4c49e95	83	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
phungductung	0:e87aa4c49e95	84	((GAP) == ETH_INTERFRAMEGAP_40BIT))
phungductung	0:e87aa4c49e95	85	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	86	((CMD) == ETH_CARRIERSENCE_DISABLE))
phungductung	0:e87aa4c49e95	87	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	88	((CMD) == ETH_RECEIVEOWN_DISABLE))
phungductung	0:e87aa4c49e95	89	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	90	((CMD) == ETH_LOOPBACKMODE_DISABLE))
phungductung	0:e87aa4c49e95	91	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	92	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
phungductung	0:e87aa4c49e95	93	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	94	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
phungductung	0:e87aa4c49e95	95	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	96	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
phungductung	0:e87aa4c49e95	97	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
phungductung	0:e87aa4c49e95	98	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
phungductung	0:e87aa4c49e95	99	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
phungductung	0:e87aa4c49e95	100	((LIMIT) == ETH_BACKOFFLIMIT_1))
phungductung	0:e87aa4c49e95	101	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	102	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
phungductung	0:e87aa4c49e95	103	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	104	((CMD) == ETH_RECEIVEAll_DISABLE))
phungductung	0:e87aa4c49e95	105	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	106	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	107	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
phungductung	0:e87aa4c49e95	108	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
phungductung	0:e87aa4c49e95	109	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
phungductung	0:e87aa4c49e95	110	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
phungductung	0:e87aa4c49e95	111	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	112	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
phungductung	0:e87aa4c49e95	113	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
phungductung	0:e87aa4c49e95	114	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
phungductung	0:e87aa4c49e95	115	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	116	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
phungductung	0:e87aa4c49e95	117	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
phungductung	0:e87aa4c49e95	118	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
phungductung	0:e87aa4c49e95	119	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
phungductung	0:e87aa4c49e95	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
phungductung	0:e87aa4c49e95	121	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
phungductung	0:e87aa4c49e95	122	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
phungductung	0:e87aa4c49e95	123	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
phungductung	0:e87aa4c49e95	124	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
phungductung	0:e87aa4c49e95	125	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	126	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
phungductung	0:e87aa4c49e95	127	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
phungductung	0:e87aa4c49e95	128	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
phungductung	0:e87aa4c49e95	129	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
phungductung	0:e87aa4c49e95	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
phungductung	0:e87aa4c49e95	131	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	132	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
phungductung	0:e87aa4c49e95	133	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	134	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
phungductung	0:e87aa4c49e95	135	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	136	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
phungductung	0:e87aa4c49e95	137	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
phungductung	0:e87aa4c49e95	138	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
phungductung	0:e87aa4c49e95	139	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
phungductung	0:e87aa4c49e95	140	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
phungductung	0:e87aa4c49e95	141	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
phungductung	0:e87aa4c49e95	142	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
phungductung	0:e87aa4c49e95	143	((ADDRESS) == ETH_MAC_ADDRESS3))
phungductung	0:e87aa4c49e95	144	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
phungductung	0:e87aa4c49e95	145	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
phungductung	0:e87aa4c49e95	146	((ADDRESS) == ETH_MAC_ADDRESS3))
phungductung	0:e87aa4c49e95	147	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
phungductung	0:e87aa4c49e95	148	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
phungductung	0:e87aa4c49e95	149	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
phungductung	0:e87aa4c49e95	150	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
phungductung	0:e87aa4c49e95	151	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
phungductung	0:e87aa4c49e95	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
phungductung	0:e87aa4c49e95	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
phungductung	0:e87aa4c49e95	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
phungductung	0:e87aa4c49e95	155	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	156	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
phungductung	0:e87aa4c49e95	157	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	158	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
phungductung	0:e87aa4c49e95	159	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	160	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
phungductung	0:e87aa4c49e95	161	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	162	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
phungductung	0:e87aa4c49e95	163	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
phungductung	0:e87aa4c49e95	164	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
phungductung	0:e87aa4c49e95	165	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
phungductung	0:e87aa4c49e95	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
phungductung	0:e87aa4c49e95	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
phungductung	0:e87aa4c49e95	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
phungductung	0:e87aa4c49e95	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
phungductung	0:e87aa4c49e95	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
phungductung	0:e87aa4c49e95	171	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	172	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
phungductung	0:e87aa4c49e95	173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
phungductung	0:e87aa4c49e95	175	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
phungductung	0:e87aa4c49e95	176	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
phungductung	0:e87aa4c49e95	177	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
phungductung	0:e87aa4c49e95	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
phungductung	0:e87aa4c49e95	179	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	180	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
phungductung	0:e87aa4c49e95	181	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	182	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
phungductung	0:e87aa4c49e95	183	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	184	((CMD) == ETH_FIXEDBURST_DISABLE))
phungductung	0:e87aa4c49e95	185	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
phungductung	0:e87aa4c49e95	186	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
phungductung	0:e87aa4c49e95	187	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
phungductung	0:e87aa4c49e95	188	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
phungductung	0:e87aa4c49e95	189	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
phungductung	0:e87aa4c49e95	190	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
phungductung	0:e87aa4c49e95	191	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
phungductung	0:e87aa4c49e95	192	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
phungductung	0:e87aa4c49e95	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
phungductung	0:e87aa4c49e95	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
phungductung	0:e87aa4c49e95	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
phungductung	0:e87aa4c49e95	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
phungductung	0:e87aa4c49e95	197	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
phungductung	0:e87aa4c49e95	198	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
phungductung	0:e87aa4c49e95	199	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
phungductung	0:e87aa4c49e95	200	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
phungductung	0:e87aa4c49e95	201	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
phungductung	0:e87aa4c49e95	202	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
phungductung	0:e87aa4c49e95	203	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
phungductung	0:e87aa4c49e95	204	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
phungductung	0:e87aa4c49e95	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
phungductung	0:e87aa4c49e95	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
phungductung	0:e87aa4c49e95	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
phungductung	0:e87aa4c49e95	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
phungductung	0:e87aa4c49e95	209	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
phungductung	0:e87aa4c49e95	210	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
phungductung	0:e87aa4c49e95	211	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
phungductung	0:e87aa4c49e95	212	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
phungductung	0:e87aa4c49e95	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
phungductung	0:e87aa4c49e95	214	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
phungductung	0:e87aa4c49e95	215	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
phungductung	0:e87aa4c49e95	216	((FLAG) == ETH_DMATXDESC_IC) \|\| \
phungductung	0:e87aa4c49e95	217	((FLAG) == ETH_DMATXDESC_LS) \|\| \
phungductung	0:e87aa4c49e95	218	((FLAG) == ETH_DMATXDESC_FS) \|\| \
phungductung	0:e87aa4c49e95	219	((FLAG) == ETH_DMATXDESC_DC) \|\| \
phungductung	0:e87aa4c49e95	220	((FLAG) == ETH_DMATXDESC_DP) \|\| \
phungductung	0:e87aa4c49e95	221	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
phungductung	0:e87aa4c49e95	222	((FLAG) == ETH_DMATXDESC_TER) \|\| \
phungductung	0:e87aa4c49e95	223	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
phungductung	0:e87aa4c49e95	224	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
phungductung	0:e87aa4c49e95	225	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
phungductung	0:e87aa4c49e95	226	((FLAG) == ETH_DMATXDESC_ES) \|\| \
phungductung	0:e87aa4c49e95	227	((FLAG) == ETH_DMATXDESC_JT) \|\| \
phungductung	0:e87aa4c49e95	228	((FLAG) == ETH_DMATXDESC_FF) \|\| \
phungductung	0:e87aa4c49e95	229	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
phungductung	0:e87aa4c49e95	230	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
phungductung	0:e87aa4c49e95	231	((FLAG) == ETH_DMATXDESC_NC) \|\| \
phungductung	0:e87aa4c49e95	232	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
phungductung	0:e87aa4c49e95	233	((FLAG) == ETH_DMATXDESC_EC) \|\| \
phungductung	0:e87aa4c49e95	234	((FLAG) == ETH_DMATXDESC_VF) \|\| \
phungductung	0:e87aa4c49e95	235	((FLAG) == ETH_DMATXDESC_CC) \|\| \
phungductung	0:e87aa4c49e95	236	((FLAG) == ETH_DMATXDESC_ED) \|\| \
phungductung	0:e87aa4c49e95	237	((FLAG) == ETH_DMATXDESC_UF) \|\| \
phungductung	0:e87aa4c49e95	238	((FLAG) == ETH_DMATXDESC_DB))
phungductung	0:e87aa4c49e95	239	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
phungductung	0:e87aa4c49e95	240	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
phungductung	0:e87aa4c49e95	241	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
phungductung	0:e87aa4c49e95	242	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
phungductung	0:e87aa4c49e95	243	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
phungductung	0:e87aa4c49e95	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
phungductung	0:e87aa4c49e95	245	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
phungductung	0:e87aa4c49e95	246	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
phungductung	0:e87aa4c49e95	247	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
phungductung	0:e87aa4c49e95	248	((FLAG) == ETH_DMARXDESC_ES) \|\| \
phungductung	0:e87aa4c49e95	249	((FLAG) == ETH_DMARXDESC_DE) \|\| \
phungductung	0:e87aa4c49e95	250	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
phungductung	0:e87aa4c49e95	251	((FLAG) == ETH_DMARXDESC_LE) \|\| \
phungductung	0:e87aa4c49e95	252	((FLAG) == ETH_DMARXDESC_OE) \|\| \
phungductung	0:e87aa4c49e95	253	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
phungductung	0:e87aa4c49e95	254	((FLAG) == ETH_DMARXDESC_FS) \|\| \
phungductung	0:e87aa4c49e95	255	((FLAG) == ETH_DMARXDESC_LS) \|\| \
phungductung	0:e87aa4c49e95	256	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
phungductung	0:e87aa4c49e95	257	((FLAG) == ETH_DMARXDESC_LC) \|\| \
phungductung	0:e87aa4c49e95	258	((FLAG) == ETH_DMARXDESC_FT) \|\| \
phungductung	0:e87aa4c49e95	259	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
phungductung	0:e87aa4c49e95	260	((FLAG) == ETH_DMARXDESC_RE) \|\| \
phungductung	0:e87aa4c49e95	261	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
phungductung	0:e87aa4c49e95	262	((FLAG) == ETH_DMARXDESC_CE) \|\| \
phungductung	0:e87aa4c49e95	263	((FLAG) == ETH_DMARXDESC_MAMPCE))
phungductung	0:e87aa4c49e95	264	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
phungductung	0:e87aa4c49e95	265	((BUFFER) == ETH_DMARXDESC_BUFFER2))
phungductung	0:e87aa4c49e95	266	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
phungductung	0:e87aa4c49e95	267	((FLAG) == ETH_PMT_FLAG_MPR))
phungductung	0:e87aa4c49e95	268	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
phungductung	0:e87aa4c49e95	269	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
phungductung	0:e87aa4c49e95	270	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
phungductung	0:e87aa4c49e95	271	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
phungductung	0:e87aa4c49e95	272	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
phungductung	0:e87aa4c49e95	273	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
phungductung	0:e87aa4c49e95	274	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
phungductung	0:e87aa4c49e95	275	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
phungductung	0:e87aa4c49e95	276	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
phungductung	0:e87aa4c49e95	277	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
phungductung	0:e87aa4c49e95	278	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
phungductung	0:e87aa4c49e95	279	((FLAG) == ETH_DMA_FLAG_T))
phungductung	0:e87aa4c49e95	280	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
phungductung	0:e87aa4c49e95	281	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
phungductung	0:e87aa4c49e95	282	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
phungductung	0:e87aa4c49e95	283	((IT) == ETH_MAC_IT_PMT))
phungductung	0:e87aa4c49e95	284	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
phungductung	0:e87aa4c49e95	285	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
phungductung	0:e87aa4c49e95	286	((FLAG) == ETH_MAC_FLAG_PMT))
phungductung	0:e87aa4c49e95	287	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
phungductung	0:e87aa4c49e95	288	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
phungductung	0:e87aa4c49e95	289	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
phungductung	0:e87aa4c49e95	290	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
phungductung	0:e87aa4c49e95	291	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
phungductung	0:e87aa4c49e95	292	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
phungductung	0:e87aa4c49e95	293	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
phungductung	0:e87aa4c49e95	294	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
phungductung	0:e87aa4c49e95	295	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
phungductung	0:e87aa4c49e95	296	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
phungductung	0:e87aa4c49e95	297	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
phungductung	0:e87aa4c49e95	298	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
phungductung	0:e87aa4c49e95	299	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
phungductung	0:e87aa4c49e95	300	((IT) != 0x00))
phungductung	0:e87aa4c49e95	301	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
phungductung	0:e87aa4c49e95	302	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
phungductung	0:e87aa4c49e95	303	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
phungductung	0:e87aa4c49e95	304	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
phungductung	0:e87aa4c49e95	305	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
phungductung	0:e87aa4c49e95	306
phungductung	0:e87aa4c49e95	307
phungductung	0:e87aa4c49e95	308	/**
phungductung	0:e87aa4c49e95	309	* @}
phungductung	0:e87aa4c49e95	310	*/
phungductung	0:e87aa4c49e95	311
phungductung	0:e87aa4c49e95	312	/** @addtogroup ETH_Private_Defines
phungductung	0:e87aa4c49e95	313	* @{
phungductung	0:e87aa4c49e95	314	*/
phungductung	0:e87aa4c49e95	315	/* Delay to wait when writing to some Ethernet registers */
phungductung	0:e87aa4c49e95	316	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	317
phungductung	0:e87aa4c49e95	318	/* ETHERNET Errors */
phungductung	0:e87aa4c49e95	319	#define ETH_SUCCESS ((uint32_t)0)
phungductung	0:e87aa4c49e95	320	#define ETH_ERROR ((uint32_t)1)
phungductung	0:e87aa4c49e95	321
phungductung	0:e87aa4c49e95	322	/* ETHERNET DMA Tx descriptors Collision Count Shift */
phungductung	0:e87aa4c49e95	323	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
phungductung	0:e87aa4c49e95	324
phungductung	0:e87aa4c49e95	325	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
phungductung	0:e87aa4c49e95	326	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
phungductung	0:e87aa4c49e95	327
phungductung	0:e87aa4c49e95	328	/* ETHERNET DMA Rx descriptors Frame Length Shift */
phungductung	0:e87aa4c49e95	329	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
phungductung	0:e87aa4c49e95	330
phungductung	0:e87aa4c49e95	331	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
phungductung	0:e87aa4c49e95	332	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
phungductung	0:e87aa4c49e95	333
phungductung	0:e87aa4c49e95	334	/* ETHERNET DMA Rx descriptors Frame length Shift */
phungductung	0:e87aa4c49e95	335	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
phungductung	0:e87aa4c49e95	336
phungductung	0:e87aa4c49e95	337	/* ETHERNET MAC address offsets */
phungductung	0:e87aa4c49e95	338	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
phungductung	0:e87aa4c49e95	339	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
phungductung	0:e87aa4c49e95	340
phungductung	0:e87aa4c49e95	341	/* ETHERNET MACMIIAR register Mask */
phungductung	0:e87aa4c49e95	342	#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
phungductung	0:e87aa4c49e95	343
phungductung	0:e87aa4c49e95	344	/* ETHERNET MACCR register Mask */
phungductung	0:e87aa4c49e95	345	#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
phungductung	0:e87aa4c49e95	346
phungductung	0:e87aa4c49e95	347	/* ETHERNET MACFCR register Mask */
phungductung	0:e87aa4c49e95	348	#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
phungductung	0:e87aa4c49e95	349
phungductung	0:e87aa4c49e95	350	/* ETHERNET DMAOMR register Mask */
phungductung	0:e87aa4c49e95	351	#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
phungductung	0:e87aa4c49e95	352
phungductung	0:e87aa4c49e95	353	/* ETHERNET Remote Wake-up frame register length */
phungductung	0:e87aa4c49e95	354	#define ETH_WAKEUP_REGISTER_LENGTH 8
phungductung	0:e87aa4c49e95	355
phungductung	0:e87aa4c49e95	356	/* ETHERNET Missed frames counter Shift */
phungductung	0:e87aa4c49e95	357	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
phungductung	0:e87aa4c49e95	358	/**
phungductung	0:e87aa4c49e95	359	* @}
phungductung	0:e87aa4c49e95	360	*/
phungductung	0:e87aa4c49e95	361
phungductung	0:e87aa4c49e95	362	/* Exported types ------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	363	/** @defgroup ETH_Exported_Types ETH Exported Types
phungductung	0:e87aa4c49e95	364	* @{
phungductung	0:e87aa4c49e95	365	*/
phungductung	0:e87aa4c49e95	366
phungductung	0:e87aa4c49e95	367	/**
phungductung	0:e87aa4c49e95	368	* @brief HAL State structures definition
phungductung	0:e87aa4c49e95	369	*/
phungductung	0:e87aa4c49e95	370	typedef enum
phungductung	0:e87aa4c49e95	371	{
phungductung	0:e87aa4c49e95	372	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
phungductung	0:e87aa4c49e95	373	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
phungductung	0:e87aa4c49e95	374	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
phungductung	0:e87aa4c49e95	375	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
phungductung	0:e87aa4c49e95	376	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
phungductung	0:e87aa4c49e95	377	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
phungductung	0:e87aa4c49e95	378	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
phungductung	0:e87aa4c49e95	379	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
phungductung	0:e87aa4c49e95	380	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
phungductung	0:e87aa4c49e95	381	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
phungductung	0:e87aa4c49e95	382	}HAL_ETH_StateTypeDef;
phungductung	0:e87aa4c49e95	383
phungductung	0:e87aa4c49e95	384	/**
phungductung	0:e87aa4c49e95	385	* @brief ETH Init Structure definition
phungductung	0:e87aa4c49e95	386	*/
phungductung	0:e87aa4c49e95	387
phungductung	0:e87aa4c49e95	388	typedef struct
phungductung	0:e87aa4c49e95	389	{
phungductung	0:e87aa4c49e95	390	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
phungductung	0:e87aa4c49e95	391	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
phungductung	0:e87aa4c49e95	392	and the mode (half/full-duplex).
phungductung	0:e87aa4c49e95	393	This parameter can be a value of @ref ETH_AutoNegotiation */
phungductung	0:e87aa4c49e95	394
phungductung	0:e87aa4c49e95	395	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
phungductung	0:e87aa4c49e95	396	This parameter can be a value of @ref ETH_Speed */
phungductung	0:e87aa4c49e95	397
phungductung	0:e87aa4c49e95	398	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
phungductung	0:e87aa4c49e95	399	This parameter can be a value of @ref ETH_Duplex_Mode */
phungductung	0:e87aa4c49e95	400
phungductung	0:e87aa4c49e95	401	uint16_t PhyAddress; /*!< Ethernet PHY address.
phungductung	0:e87aa4c49e95	402	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
phungductung	0:e87aa4c49e95	403
phungductung	0:e87aa4c49e95	404	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
phungductung	0:e87aa4c49e95	405
phungductung	0:e87aa4c49e95	406	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
phungductung	0:e87aa4c49e95	407	This parameter can be a value of @ref ETH_Rx_Mode */
phungductung	0:e87aa4c49e95	408
phungductung	0:e87aa4c49e95	409	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
phungductung	0:e87aa4c49e95	410	This parameter can be a value of @ref ETH_Checksum_Mode */
phungductung	0:e87aa4c49e95	411
phungductung	0:e87aa4c49e95	412	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
phungductung	0:e87aa4c49e95	413	This parameter can be a value of @ref ETH_Media_Interface */
phungductung	0:e87aa4c49e95	414
phungductung	0:e87aa4c49e95	415	} ETH_InitTypeDef;
phungductung	0:e87aa4c49e95	416
phungductung	0:e87aa4c49e95	417
phungductung	0:e87aa4c49e95	418	/**
phungductung	0:e87aa4c49e95	419	* @brief ETH MAC Configuration Structure definition
phungductung	0:e87aa4c49e95	420	*/
phungductung	0:e87aa4c49e95	421
phungductung	0:e87aa4c49e95	422	typedef struct
phungductung	0:e87aa4c49e95	423	{
phungductung	0:e87aa4c49e95	424	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
phungductung	0:e87aa4c49e95	425	When enabled, the MAC allows no more then 2048 bytes to be received.
phungductung	0:e87aa4c49e95	426	When disabled, the MAC can receive up to 16384 bytes.
phungductung	0:e87aa4c49e95	427	This parameter can be a value of @ref ETH_Watchdog */
phungductung	0:e87aa4c49e95	428
phungductung	0:e87aa4c49e95	429	uint32_t Jabber; /*!< Selects or not Jabber timer
phungductung	0:e87aa4c49e95	430	When enabled, the MAC allows no more then 2048 bytes to be sent.
phungductung	0:e87aa4c49e95	431	When disabled, the MAC can send up to 16384 bytes.
phungductung	0:e87aa4c49e95	432	This parameter can be a value of @ref ETH_Jabber */
phungductung	0:e87aa4c49e95	433
phungductung	0:e87aa4c49e95	434	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
phungductung	0:e87aa4c49e95	435	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
phungductung	0:e87aa4c49e95	436
phungductung	0:e87aa4c49e95	437	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
phungductung	0:e87aa4c49e95	438	This parameter can be a value of @ref ETH_Carrier_Sense */
phungductung	0:e87aa4c49e95	439
phungductung	0:e87aa4c49e95	440	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
phungductung	0:e87aa4c49e95	441	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
phungductung	0:e87aa4c49e95	442	in Half-Duplex mode.
phungductung	0:e87aa4c49e95	443	This parameter can be a value of @ref ETH_Receive_Own */
phungductung	0:e87aa4c49e95	444
phungductung	0:e87aa4c49e95	445	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
phungductung	0:e87aa4c49e95	446	This parameter can be a value of @ref ETH_Loop_Back_Mode */
phungductung	0:e87aa4c49e95	447
phungductung	0:e87aa4c49e95	448	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
phungductung	0:e87aa4c49e95	449	This parameter can be a value of @ref ETH_Checksum_Offload */
phungductung	0:e87aa4c49e95	450
phungductung	0:e87aa4c49e95	451	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
phungductung	0:e87aa4c49e95	452	when a collision occurs (Half-Duplex mode).
phungductung	0:e87aa4c49e95	453	This parameter can be a value of @ref ETH_Retry_Transmission */
phungductung	0:e87aa4c49e95	454
phungductung	0:e87aa4c49e95	455	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
phungductung	0:e87aa4c49e95	456	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
phungductung	0:e87aa4c49e95	457
phungductung	0:e87aa4c49e95	458	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
phungductung	0:e87aa4c49e95	459	This parameter can be a value of @ref ETH_Back_Off_Limit */
phungductung	0:e87aa4c49e95	460
phungductung	0:e87aa4c49e95	461	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
phungductung	0:e87aa4c49e95	462	This parameter can be a value of @ref ETH_Deferral_Check */
phungductung	0:e87aa4c49e95	463
phungductung	0:e87aa4c49e95	464	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
phungductung	0:e87aa4c49e95	465	This parameter can be a value of @ref ETH_Receive_All */
phungductung	0:e87aa4c49e95	466
phungductung	0:e87aa4c49e95	467	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
phungductung	0:e87aa4c49e95	468	This parameter can be a value of @ref ETH_Source_Addr_Filter */
phungductung	0:e87aa4c49e95	469
phungductung	0:e87aa4c49e95	470	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
phungductung	0:e87aa4c49e95	471	This parameter can be a value of @ref ETH_Pass_Control_Frames */
phungductung	0:e87aa4c49e95	472
phungductung	0:e87aa4c49e95	473	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
phungductung	0:e87aa4c49e95	474	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
phungductung	0:e87aa4c49e95	475
phungductung	0:e87aa4c49e95	476	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
phungductung	0:e87aa4c49e95	477	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
phungductung	0:e87aa4c49e95	478
phungductung	0:e87aa4c49e95	479	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
phungductung	0:e87aa4c49e95	480	This parameter can be a value of @ref ETH_Promiscuous_Mode */
phungductung	0:e87aa4c49e95	481
phungductung	0:e87aa4c49e95	482	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
phungductung	0:e87aa4c49e95	483	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
phungductung	0:e87aa4c49e95	484
phungductung	0:e87aa4c49e95	485	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
phungductung	0:e87aa4c49e95	486	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
phungductung	0:e87aa4c49e95	487
phungductung	0:e87aa4c49e95	488	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
phungductung	0:e87aa4c49e95	489	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
phungductung	0:e87aa4c49e95	490
phungductung	0:e87aa4c49e95	491	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
phungductung	0:e87aa4c49e95	492	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
phungductung	0:e87aa4c49e95	493
phungductung	0:e87aa4c49e95	494	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
phungductung	0:e87aa4c49e95	495	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
phungductung	0:e87aa4c49e95	496
phungductung	0:e87aa4c49e95	497	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
phungductung	0:e87aa4c49e95	498	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
phungductung	0:e87aa4c49e95	499
phungductung	0:e87aa4c49e95	500	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
phungductung	0:e87aa4c49e95	501	automatic retransmission of PAUSE Frame.
phungductung	0:e87aa4c49e95	502	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
phungductung	0:e87aa4c49e95	503
phungductung	0:e87aa4c49e95	504	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
phungductung	0:e87aa4c49e95	505	unicast address and unique multicast address).
phungductung	0:e87aa4c49e95	506	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
phungductung	0:e87aa4c49e95	507
phungductung	0:e87aa4c49e95	508	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
phungductung	0:e87aa4c49e95	509	disable its transmitter for a specified time (Pause Time)
phungductung	0:e87aa4c49e95	510	This parameter can be a value of @ref ETH_Receive_Flow_Control */
phungductung	0:e87aa4c49e95	511
phungductung	0:e87aa4c49e95	512	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
phungductung	0:e87aa4c49e95	513	or the MAC back-pressure operation (Half-Duplex mode)
phungductung	0:e87aa4c49e95	514	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
phungductung	0:e87aa4c49e95	515
phungductung	0:e87aa4c49e95	516	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
phungductung	0:e87aa4c49e95	517	comparison and filtering.
phungductung	0:e87aa4c49e95	518	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
phungductung	0:e87aa4c49e95	519
phungductung	0:e87aa4c49e95	520	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
phungductung	0:e87aa4c49e95	521
phungductung	0:e87aa4c49e95	522	} ETH_MACInitTypeDef;
phungductung	0:e87aa4c49e95	523
phungductung	0:e87aa4c49e95	524
phungductung	0:e87aa4c49e95	525	/**
phungductung	0:e87aa4c49e95	526	* @brief ETH DMA Configuration Structure definition
phungductung	0:e87aa4c49e95	527	*/
phungductung	0:e87aa4c49e95	528
phungductung	0:e87aa4c49e95	529	typedef struct
phungductung	0:e87aa4c49e95	530	{
phungductung	0:e87aa4c49e95	531	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
phungductung	0:e87aa4c49e95	532	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
phungductung	0:e87aa4c49e95	533
phungductung	0:e87aa4c49e95	534	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
phungductung	0:e87aa4c49e95	535	This parameter can be a value of @ref ETH_Receive_Store_Forward */
phungductung	0:e87aa4c49e95	536
phungductung	0:e87aa4c49e95	537	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
phungductung	0:e87aa4c49e95	538	This parameter can be a value of @ref ETH_Flush_Received_Frame */
phungductung	0:e87aa4c49e95	539
phungductung	0:e87aa4c49e95	540	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
phungductung	0:e87aa4c49e95	541	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
phungductung	0:e87aa4c49e95	542
phungductung	0:e87aa4c49e95	543	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
phungductung	0:e87aa4c49e95	544	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
phungductung	0:e87aa4c49e95	545
phungductung	0:e87aa4c49e95	546	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
phungductung	0:e87aa4c49e95	547	This parameter can be a value of @ref ETH_Forward_Error_Frames */
phungductung	0:e87aa4c49e95	548
phungductung	0:e87aa4c49e95	549	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
phungductung	0:e87aa4c49e95	550	and length less than 64 bytes) including pad-bytes and CRC)
phungductung	0:e87aa4c49e95	551	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
phungductung	0:e87aa4c49e95	552
phungductung	0:e87aa4c49e95	553	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
phungductung	0:e87aa4c49e95	554	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
phungductung	0:e87aa4c49e95	555
phungductung	0:e87aa4c49e95	556	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
phungductung	0:e87aa4c49e95	557	frame of Transmit data even before obtaining the status for the first frame.
phungductung	0:e87aa4c49e95	558	This parameter can be a value of @ref ETH_Second_Frame_Operate */
phungductung	0:e87aa4c49e95	559
phungductung	0:e87aa4c49e95	560	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
phungductung	0:e87aa4c49e95	561	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
phungductung	0:e87aa4c49e95	562
phungductung	0:e87aa4c49e95	563	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
phungductung	0:e87aa4c49e95	564	This parameter can be a value of @ref ETH_Fixed_Burst */
phungductung	0:e87aa4c49e95	565
phungductung	0:e87aa4c49e95	566	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
phungductung	0:e87aa4c49e95	567	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
phungductung	0:e87aa4c49e95	568
phungductung	0:e87aa4c49e95	569	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
phungductung	0:e87aa4c49e95	570	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
phungductung	0:e87aa4c49e95	571
phungductung	0:e87aa4c49e95	572	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
phungductung	0:e87aa4c49e95	573	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
phungductung	0:e87aa4c49e95	574
phungductung	0:e87aa4c49e95	575	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
phungductung	0:e87aa4c49e95	576	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
phungductung	0:e87aa4c49e95	577
phungductung	0:e87aa4c49e95	578	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
phungductung	0:e87aa4c49e95	579	This parameter can be a value of @ref ETH_DMA_Arbitration */
phungductung	0:e87aa4c49e95	580	} ETH_DMAInitTypeDef;
phungductung	0:e87aa4c49e95	581
phungductung	0:e87aa4c49e95	582
phungductung	0:e87aa4c49e95	583	/**
phungductung	0:e87aa4c49e95	584	* @brief ETH DMA Descriptors data structure definition
phungductung	0:e87aa4c49e95	585	*/
phungductung	0:e87aa4c49e95	586
phungductung	0:e87aa4c49e95	587	typedef struct
phungductung	0:e87aa4c49e95	588	{
phungductung	0:e87aa4c49e95	589	__IO uint32_t Status; /!< Status /
phungductung	0:e87aa4c49e95	590
phungductung	0:e87aa4c49e95	591	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
phungductung	0:e87aa4c49e95	592
phungductung	0:e87aa4c49e95	593	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
phungductung	0:e87aa4c49e95	594
phungductung	0:e87aa4c49e95	595	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
phungductung	0:e87aa4c49e95	596
phungductung	0:e87aa4c49e95	597	/!< Enhanced ETHERNET DMA PTP Descriptors /
phungductung	0:e87aa4c49e95	598	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
phungductung	0:e87aa4c49e95	599
phungductung	0:e87aa4c49e95	600	uint32_t Reserved1; /!< Reserved /
phungductung	0:e87aa4c49e95	601
phungductung	0:e87aa4c49e95	602	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
phungductung	0:e87aa4c49e95	603
phungductung	0:e87aa4c49e95	604	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
phungductung	0:e87aa4c49e95	605
phungductung	0:e87aa4c49e95	606	} ETH_DMADescTypeDef;
phungductung	0:e87aa4c49e95	607
phungductung	0:e87aa4c49e95	608
phungductung	0:e87aa4c49e95	609	/**
phungductung	0:e87aa4c49e95	610	* @brief Received Frame Informations structure definition
phungductung	0:e87aa4c49e95	611	*/
phungductung	0:e87aa4c49e95	612	typedef struct
phungductung	0:e87aa4c49e95	613	{
phungductung	0:e87aa4c49e95	614	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
phungductung	0:e87aa4c49e95	615
phungductung	0:e87aa4c49e95	616	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
phungductung	0:e87aa4c49e95	617
phungductung	0:e87aa4c49e95	618	uint32_t SegCount; /!< Segment count /
phungductung	0:e87aa4c49e95	619
phungductung	0:e87aa4c49e95	620	uint32_t length; /!< Frame length /
phungductung	0:e87aa4c49e95	621
phungductung	0:e87aa4c49e95	622	uint32_t buffer; /!< Frame buffer /
phungductung	0:e87aa4c49e95	623
phungductung	0:e87aa4c49e95	624	} ETH_DMARxFrameInfos;
phungductung	0:e87aa4c49e95	625
phungductung	0:e87aa4c49e95	626
phungductung	0:e87aa4c49e95	627	/**
phungductung	0:e87aa4c49e95	628	* @brief ETH Handle Structure definition
phungductung	0:e87aa4c49e95	629	*/
phungductung	0:e87aa4c49e95	630
phungductung	0:e87aa4c49e95	631	typedef struct
phungductung	0:e87aa4c49e95	632	{
phungductung	0:e87aa4c49e95	633	ETH_TypeDef Instance; /!< Register base address */
phungductung	0:e87aa4c49e95	634
phungductung	0:e87aa4c49e95	635	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
phungductung	0:e87aa4c49e95	636
phungductung	0:e87aa4c49e95	637	uint32_t LinkStatus; /!< Ethernet link status /
phungductung	0:e87aa4c49e95	638
phungductung	0:e87aa4c49e95	639	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
phungductung	0:e87aa4c49e95	640
phungductung	0:e87aa4c49e95	641	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
phungductung	0:e87aa4c49e95	642
phungductung	0:e87aa4c49e95	643	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
phungductung	0:e87aa4c49e95	644
phungductung	0:e87aa4c49e95	645	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
phungductung	0:e87aa4c49e95	646
phungductung	0:e87aa4c49e95	647	HAL_LockTypeDef Lock; /!< ETH Lock /
phungductung	0:e87aa4c49e95	648
phungductung	0:e87aa4c49e95	649	} ETH_HandleTypeDef;
phungductung	0:e87aa4c49e95	650
phungductung	0:e87aa4c49e95	651	/**
phungductung	0:e87aa4c49e95	652	* @}
phungductung	0:e87aa4c49e95	653	*/
phungductung	0:e87aa4c49e95	654
phungductung	0:e87aa4c49e95	655	/* Exported constants --------------------------------------------------------*/
phungductung	0:e87aa4c49e95	656	/** @defgroup ETH_Exported_Constants ETH Exported Constants
phungductung	0:e87aa4c49e95	657	* @{
phungductung	0:e87aa4c49e95	658	*/
phungductung	0:e87aa4c49e95	659
phungductung	0:e87aa4c49e95	660	/** @defgroup ETH_Buffers_setting ETH Buffers setting
phungductung	0:e87aa4c49e95	661	* @{
phungductung	0:e87aa4c49e95	662	*/
phungductung	0:e87aa4c49e95	663	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
phungductung	0:e87aa4c49e95	664	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
phungductung	0:e87aa4c49e95	665	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
phungductung	0:e87aa4c49e95	666	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
phungductung	0:e87aa4c49e95	667	#define ETH_VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
phungductung	0:e87aa4c49e95	668	#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
phungductung	0:e87aa4c49e95	669	#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
phungductung	0:e87aa4c49e95	670	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
phungductung	0:e87aa4c49e95	671
phungductung	0:e87aa4c49e95	672	/* Ethernet driver receive buffers are organized in a chained linked-list, when
phungductung	0:e87aa4c49e95	673	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
phungductung	0:e87aa4c49e95	674	to the driver receive buffers memory.
phungductung	0:e87aa4c49e95	675
phungductung	0:e87aa4c49e95	676	Depending on the size of the received ethernet packet and the size of
phungductung	0:e87aa4c49e95	677	each ethernet driver receive buffer, the received packet can take one or more
phungductung	0:e87aa4c49e95	678	ethernet driver receive buffer.
phungductung	0:e87aa4c49e95	679
phungductung	0:e87aa4c49e95	680	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
phungductung	0:e87aa4c49e95	681	and the total count of the driver receive buffers ETH_RXBUFNB.
phungductung	0:e87aa4c49e95	682
phungductung	0:e87aa4c49e95	683	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
phungductung	0:e87aa4c49e95	684	example, they can be reconfigured in the application layer to fit the application
phungductung	0:e87aa4c49e95	685	needs */
phungductung	0:e87aa4c49e95	686
phungductung	0:e87aa4c49e95	687	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
phungductung	0:e87aa4c49e95	688	packet */
phungductung	0:e87aa4c49e95	689	#ifndef ETH_RX_BUF_SIZE
phungductung	0:e87aa4c49e95	690	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
phungductung	0:e87aa4c49e95	691	#endif
phungductung	0:e87aa4c49e95	692
phungductung	0:e87aa4c49e95	693	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
phungductung	0:e87aa4c49e95	694	#ifndef ETH_RXBUFNB
phungductung	0:e87aa4c49e95	695	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
phungductung	0:e87aa4c49e95	696	#endif
phungductung	0:e87aa4c49e95	697
phungductung	0:e87aa4c49e95	698
phungductung	0:e87aa4c49e95	699	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
phungductung	0:e87aa4c49e95	700	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
phungductung	0:e87aa4c49e95	701	driver transmit buffers memory to the TxFIFO.
phungductung	0:e87aa4c49e95	702
phungductung	0:e87aa4c49e95	703	Depending on the size of the Ethernet packet to be transmitted and the size of
phungductung	0:e87aa4c49e95	704	each ethernet driver transmit buffer, the packet to be transmitted can take
phungductung	0:e87aa4c49e95	705	one or more ethernet driver transmit buffer.
phungductung	0:e87aa4c49e95	706
phungductung	0:e87aa4c49e95	707	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
phungductung	0:e87aa4c49e95	708	and the total count of the driver transmit buffers ETH_TXBUFNB.
phungductung	0:e87aa4c49e95	709
phungductung	0:e87aa4c49e95	710	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
phungductung	0:e87aa4c49e95	711	example, they can be reconfigured in the application layer to fit the application
phungductung	0:e87aa4c49e95	712	needs */
phungductung	0:e87aa4c49e95	713
phungductung	0:e87aa4c49e95	714	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
phungductung	0:e87aa4c49e95	715	packet */
phungductung	0:e87aa4c49e95	716	#ifndef ETH_TX_BUF_SIZE
phungductung	0:e87aa4c49e95	717	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
phungductung	0:e87aa4c49e95	718	#endif
phungductung	0:e87aa4c49e95	719
phungductung	0:e87aa4c49e95	720	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
phungductung	0:e87aa4c49e95	721	#ifndef ETH_TXBUFNB
phungductung	0:e87aa4c49e95	722	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
phungductung	0:e87aa4c49e95	723	#endif
phungductung	0:e87aa4c49e95	724
phungductung	0:e87aa4c49e95	725	/**
phungductung	0:e87aa4c49e95	726	* @}
phungductung	0:e87aa4c49e95	727	*/
phungductung	0:e87aa4c49e95	728
phungductung	0:e87aa4c49e95	729	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
phungductung	0:e87aa4c49e95	730	* @{
phungductung	0:e87aa4c49e95	731	*/
phungductung	0:e87aa4c49e95	732
phungductung	0:e87aa4c49e95	733	/*
phungductung	0:e87aa4c49e95	734	DMA Tx Descriptor
phungductung	0:e87aa4c49e95	735	-----------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	736	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
phungductung	0:e87aa4c49e95	737	-----------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	738	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
phungductung	0:e87aa4c49e95	739	-----------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	740	TDES2 \| Buffer1 Address [31:0] \|
phungductung	0:e87aa4c49e95	741	-----------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	742	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
phungductung	0:e87aa4c49e95	743	-----------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	744	*/
phungductung	0:e87aa4c49e95	745
phungductung	0:e87aa4c49e95	746	/**
phungductung	0:e87aa4c49e95	747	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
phungductung	0:e87aa4c49e95	748	*/
phungductung	0:e87aa4c49e95	749	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
phungductung	0:e87aa4c49e95	750	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
phungductung	0:e87aa4c49e95	751	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
phungductung	0:e87aa4c49e95	752	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
phungductung	0:e87aa4c49e95	753	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
phungductung	0:e87aa4c49e95	754	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
phungductung	0:e87aa4c49e95	755	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
phungductung	0:e87aa4c49e95	756	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
phungductung	0:e87aa4c49e95	757	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
phungductung	0:e87aa4c49e95	758	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
phungductung	0:e87aa4c49e95	759	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
phungductung	0:e87aa4c49e95	760	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
phungductung	0:e87aa4c49e95	761	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
phungductung	0:e87aa4c49e95	762	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
phungductung	0:e87aa4c49e95	763	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
phungductung	0:e87aa4c49e95	764	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
phungductung	0:e87aa4c49e95	765	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
phungductung	0:e87aa4c49e95	766	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
phungductung	0:e87aa4c49e95	767	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
phungductung	0:e87aa4c49e95	768	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
phungductung	0:e87aa4c49e95	769	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
phungductung	0:e87aa4c49e95	770	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
phungductung	0:e87aa4c49e95	771	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
phungductung	0:e87aa4c49e95	772	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
phungductung	0:e87aa4c49e95	773	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
phungductung	0:e87aa4c49e95	774	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
phungductung	0:e87aa4c49e95	775	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
phungductung	0:e87aa4c49e95	776	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
phungductung	0:e87aa4c49e95	777	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
phungductung	0:e87aa4c49e95	778
phungductung	0:e87aa4c49e95	779	/**
phungductung	0:e87aa4c49e95	780	* @brief Bit definition of TDES1 register
phungductung	0:e87aa4c49e95	781	*/
phungductung	0:e87aa4c49e95	782	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
phungductung	0:e87aa4c49e95	783	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
phungductung	0:e87aa4c49e95	784
phungductung	0:e87aa4c49e95	785	/**
phungductung	0:e87aa4c49e95	786	* @brief Bit definition of TDES2 register
phungductung	0:e87aa4c49e95	787	*/
phungductung	0:e87aa4c49e95	788	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
phungductung	0:e87aa4c49e95	789
phungductung	0:e87aa4c49e95	790	/**
phungductung	0:e87aa4c49e95	791	* @brief Bit definition of TDES3 register
phungductung	0:e87aa4c49e95	792	*/
phungductung	0:e87aa4c49e95	793	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
phungductung	0:e87aa4c49e95	794
phungductung	0:e87aa4c49e95	795	/*---------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	796	TDES6 \| Transmit Time Stamp Low [31:0] \|
phungductung	0:e87aa4c49e95	797	-----------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	798	TDES7 \| Transmit Time Stamp High [31:0] \|
phungductung	0:e87aa4c49e95	799	----------------------------------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	800
phungductung	0:e87aa4c49e95	801	/* Bit definition of TDES6 register */
phungductung	0:e87aa4c49e95	802	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
phungductung	0:e87aa4c49e95	803
phungductung	0:e87aa4c49e95	804	/* Bit definition of TDES7 register */
phungductung	0:e87aa4c49e95	805	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
phungductung	0:e87aa4c49e95	806
phungductung	0:e87aa4c49e95	807	/**
phungductung	0:e87aa4c49e95	808	* @}
phungductung	0:e87aa4c49e95	809	*/
phungductung	0:e87aa4c49e95	810	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
phungductung	0:e87aa4c49e95	811	* @{
phungductung	0:e87aa4c49e95	812	*/
phungductung	0:e87aa4c49e95	813
phungductung	0:e87aa4c49e95	814	/*
phungductung	0:e87aa4c49e95	815	DMA Rx Descriptor
phungductung	0:e87aa4c49e95	816	--------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	817	RDES0 \| OWN(31) \| Status [30:0] \|
phungductung	0:e87aa4c49e95	818	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	819	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
phungductung	0:e87aa4c49e95	820	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	821	RDES2 \| Buffer1 Address [31:0] \|
phungductung	0:e87aa4c49e95	822	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	823	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
phungductung	0:e87aa4c49e95	824	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	825	*/
phungductung	0:e87aa4c49e95	826
phungductung	0:e87aa4c49e95	827	/**
phungductung	0:e87aa4c49e95	828	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
phungductung	0:e87aa4c49e95	829	*/
phungductung	0:e87aa4c49e95	830	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
phungductung	0:e87aa4c49e95	831	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
phungductung	0:e87aa4c49e95	832	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
phungductung	0:e87aa4c49e95	833	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
phungductung	0:e87aa4c49e95	834	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
phungductung	0:e87aa4c49e95	835	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
phungductung	0:e87aa4c49e95	836	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
phungductung	0:e87aa4c49e95	837	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
phungductung	0:e87aa4c49e95	838	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
phungductung	0:e87aa4c49e95	839	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
phungductung	0:e87aa4c49e95	840	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
phungductung	0:e87aa4c49e95	841	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
phungductung	0:e87aa4c49e95	842	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
phungductung	0:e87aa4c49e95	843	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
phungductung	0:e87aa4c49e95	844	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
phungductung	0:e87aa4c49e95	845	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
phungductung	0:e87aa4c49e95	846	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
phungductung	0:e87aa4c49e95	847	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
phungductung	0:e87aa4c49e95	848	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
phungductung	0:e87aa4c49e95	849
phungductung	0:e87aa4c49e95	850	/**
phungductung	0:e87aa4c49e95	851	* @brief Bit definition of RDES1 register
phungductung	0:e87aa4c49e95	852	*/
phungductung	0:e87aa4c49e95	853	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
phungductung	0:e87aa4c49e95	854	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
phungductung	0:e87aa4c49e95	855	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
phungductung	0:e87aa4c49e95	856	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
phungductung	0:e87aa4c49e95	857	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
phungductung	0:e87aa4c49e95	858
phungductung	0:e87aa4c49e95	859	/**
phungductung	0:e87aa4c49e95	860	* @brief Bit definition of RDES2 register
phungductung	0:e87aa4c49e95	861	*/
phungductung	0:e87aa4c49e95	862	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
phungductung	0:e87aa4c49e95	863
phungductung	0:e87aa4c49e95	864	/**
phungductung	0:e87aa4c49e95	865	* @brief Bit definition of RDES3 register
phungductung	0:e87aa4c49e95	866	*/
phungductung	0:e87aa4c49e95	867	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
phungductung	0:e87aa4c49e95	868
phungductung	0:e87aa4c49e95	869	/*---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	870	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
phungductung	0:e87aa4c49e95	871	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	872	RDES5 \| Reserved[31:0] \|
phungductung	0:e87aa4c49e95	873	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	874	RDES6 \| Receive Time Stamp Low [31:0] \|
phungductung	0:e87aa4c49e95	875	---------------------------------------------------------------------------------------------------------------------
phungductung	0:e87aa4c49e95	876	RDES7 \| Receive Time Stamp High [31:0] \|
phungductung	0:e87aa4c49e95	877	--------------------------------------------------------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	878
phungductung	0:e87aa4c49e95	879	/* Bit definition of RDES4 register */
phungductung	0:e87aa4c49e95	880	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
phungductung	0:e87aa4c49e95	881	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
phungductung	0:e87aa4c49e95	882	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
phungductung	0:e87aa4c49e95	883	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
phungductung	0:e87aa4c49e95	884	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
phungductung	0:e87aa4c49e95	885	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
phungductung	0:e87aa4c49e95	886	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
phungductung	0:e87aa4c49e95	887	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
phungductung	0:e87aa4c49e95	888	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
phungductung	0:e87aa4c49e95	889	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
phungductung	0:e87aa4c49e95	890	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
phungductung	0:e87aa4c49e95	891	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
phungductung	0:e87aa4c49e95	892	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
phungductung	0:e87aa4c49e95	893	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
phungductung	0:e87aa4c49e95	894	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
phungductung	0:e87aa4c49e95	895	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
phungductung	0:e87aa4c49e95	896	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
phungductung	0:e87aa4c49e95	897	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
phungductung	0:e87aa4c49e95	898	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
phungductung	0:e87aa4c49e95	899
phungductung	0:e87aa4c49e95	900	/* Bit definition of RDES6 register */
phungductung	0:e87aa4c49e95	901	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
phungductung	0:e87aa4c49e95	902
phungductung	0:e87aa4c49e95	903	/* Bit definition of RDES7 register */
phungductung	0:e87aa4c49e95	904	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
phungductung	0:e87aa4c49e95	905	/**
phungductung	0:e87aa4c49e95	906	* @}
phungductung	0:e87aa4c49e95	907	*/
phungductung	0:e87aa4c49e95	908	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
phungductung	0:e87aa4c49e95	909	* @{
phungductung	0:e87aa4c49e95	910	*/
phungductung	0:e87aa4c49e95	911	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	912	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	913
phungductung	0:e87aa4c49e95	914	/**
phungductung	0:e87aa4c49e95	915	* @}
phungductung	0:e87aa4c49e95	916	*/
phungductung	0:e87aa4c49e95	917	/** @defgroup ETH_Speed ETH Speed
phungductung	0:e87aa4c49e95	918	* @{
phungductung	0:e87aa4c49e95	919	*/
phungductung	0:e87aa4c49e95	920	#define ETH_SPEED_10M ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	921	#define ETH_SPEED_100M ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	922
phungductung	0:e87aa4c49e95	923	/**
phungductung	0:e87aa4c49e95	924	* @}
phungductung	0:e87aa4c49e95	925	*/
phungductung	0:e87aa4c49e95	926	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
phungductung	0:e87aa4c49e95	927	* @{
phungductung	0:e87aa4c49e95	928	*/
phungductung	0:e87aa4c49e95	929	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	930	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	931	/**
phungductung	0:e87aa4c49e95	932	* @}
phungductung	0:e87aa4c49e95	933	*/
phungductung	0:e87aa4c49e95	934	/** @defgroup ETH_Rx_Mode ETH Rx Mode
phungductung	0:e87aa4c49e95	935	* @{
phungductung	0:e87aa4c49e95	936	*/
phungductung	0:e87aa4c49e95	937	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	938	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	939	/**
phungductung	0:e87aa4c49e95	940	* @}
phungductung	0:e87aa4c49e95	941	*/
phungductung	0:e87aa4c49e95	942
phungductung	0:e87aa4c49e95	943	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
phungductung	0:e87aa4c49e95	944	* @{
phungductung	0:e87aa4c49e95	945	*/
phungductung	0:e87aa4c49e95	946	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	947	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	948	/**
phungductung	0:e87aa4c49e95	949	* @}
phungductung	0:e87aa4c49e95	950	*/
phungductung	0:e87aa4c49e95	951
phungductung	0:e87aa4c49e95	952	/** @defgroup ETH_Media_Interface ETH Media Interface
phungductung	0:e87aa4c49e95	953	* @{
phungductung	0:e87aa4c49e95	954	*/
phungductung	0:e87aa4c49e95	955	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	956	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
phungductung	0:e87aa4c49e95	957	/**
phungductung	0:e87aa4c49e95	958	* @}
phungductung	0:e87aa4c49e95	959	*/
phungductung	0:e87aa4c49e95	960
phungductung	0:e87aa4c49e95	961	/** @defgroup ETH_Watchdog ETH Watchdog
phungductung	0:e87aa4c49e95	962	* @{
phungductung	0:e87aa4c49e95	963	*/
phungductung	0:e87aa4c49e95	964	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	965	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	966	/**
phungductung	0:e87aa4c49e95	967	* @}
phungductung	0:e87aa4c49e95	968	*/
phungductung	0:e87aa4c49e95	969
phungductung	0:e87aa4c49e95	970	/** @defgroup ETH_Jabber ETH Jabber
phungductung	0:e87aa4c49e95	971	* @{
phungductung	0:e87aa4c49e95	972	*/
phungductung	0:e87aa4c49e95	973	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	974	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	975	/**
phungductung	0:e87aa4c49e95	976	* @}
phungductung	0:e87aa4c49e95	977	*/
phungductung	0:e87aa4c49e95	978
phungductung	0:e87aa4c49e95	979	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
phungductung	0:e87aa4c49e95	980	* @{
phungductung	0:e87aa4c49e95	981	*/
phungductung	0:e87aa4c49e95	982	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
phungductung	0:e87aa4c49e95	983	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
phungductung	0:e87aa4c49e95	984	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
phungductung	0:e87aa4c49e95	985	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
phungductung	0:e87aa4c49e95	986	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
phungductung	0:e87aa4c49e95	987	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
phungductung	0:e87aa4c49e95	988	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
phungductung	0:e87aa4c49e95	989	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
phungductung	0:e87aa4c49e95	990	/**
phungductung	0:e87aa4c49e95	991	* @}
phungductung	0:e87aa4c49e95	992	*/
phungductung	0:e87aa4c49e95	993
phungductung	0:e87aa4c49e95	994	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
phungductung	0:e87aa4c49e95	995	* @{
phungductung	0:e87aa4c49e95	996	*/
phungductung	0:e87aa4c49e95	997	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	998	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	999	/**
phungductung	0:e87aa4c49e95	1000	* @}
phungductung	0:e87aa4c49e95	1001	*/
phungductung	0:e87aa4c49e95	1002
phungductung	0:e87aa4c49e95	1003	/** @defgroup ETH_Receive_Own ETH Receive Own
phungductung	0:e87aa4c49e95	1004	* @{
phungductung	0:e87aa4c49e95	1005	*/
phungductung	0:e87aa4c49e95	1006	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1007	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	1008	/**
phungductung	0:e87aa4c49e95	1009	* @}
phungductung	0:e87aa4c49e95	1010	*/
phungductung	0:e87aa4c49e95	1011
phungductung	0:e87aa4c49e95	1012	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
phungductung	0:e87aa4c49e95	1013	* @{
phungductung	0:e87aa4c49e95	1014	*/
phungductung	0:e87aa4c49e95	1015	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	1016	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1017	/**
phungductung	0:e87aa4c49e95	1018	* @}
phungductung	0:e87aa4c49e95	1019	*/
phungductung	0:e87aa4c49e95	1020
phungductung	0:e87aa4c49e95	1021	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
phungductung	0:e87aa4c49e95	1022	* @{
phungductung	0:e87aa4c49e95	1023	*/
phungductung	0:e87aa4c49e95	1024	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	1025	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1026	/**
phungductung	0:e87aa4c49e95	1027	* @}
phungductung	0:e87aa4c49e95	1028	*/
phungductung	0:e87aa4c49e95	1029
phungductung	0:e87aa4c49e95	1030	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
phungductung	0:e87aa4c49e95	1031	* @{
phungductung	0:e87aa4c49e95	1032	*/
phungductung	0:e87aa4c49e95	1033	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1034	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	1035	/**
phungductung	0:e87aa4c49e95	1036	* @}
phungductung	0:e87aa4c49e95	1037	*/
phungductung	0:e87aa4c49e95	1038
phungductung	0:e87aa4c49e95	1039	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
phungductung	0:e87aa4c49e95	1040	* @{
phungductung	0:e87aa4c49e95	1041	*/
phungductung	0:e87aa4c49e95	1042	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	1043	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1044	/**
phungductung	0:e87aa4c49e95	1045	* @}
phungductung	0:e87aa4c49e95	1046	*/
phungductung	0:e87aa4c49e95	1047
phungductung	0:e87aa4c49e95	1048	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
phungductung	0:e87aa4c49e95	1049	* @{
phungductung	0:e87aa4c49e95	1050	*/
phungductung	0:e87aa4c49e95	1051	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1052	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	1053	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	1054	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
phungductung	0:e87aa4c49e95	1055	/**
phungductung	0:e87aa4c49e95	1056	* @}
phungductung	0:e87aa4c49e95	1057	*/
phungductung	0:e87aa4c49e95	1058
phungductung	0:e87aa4c49e95	1059	/** @defgroup ETH_Deferral_Check ETH Deferral Check
phungductung	0:e87aa4c49e95	1060	* @{
phungductung	0:e87aa4c49e95	1061	*/
phungductung	0:e87aa4c49e95	1062	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	1063	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1064	/**
phungductung	0:e87aa4c49e95	1065	* @}
phungductung	0:e87aa4c49e95	1066	*/
phungductung	0:e87aa4c49e95	1067
phungductung	0:e87aa4c49e95	1068	/** @defgroup ETH_Receive_All ETH Receive All
phungductung	0:e87aa4c49e95	1069	* @{
phungductung	0:e87aa4c49e95	1070	*/
phungductung	0:e87aa4c49e95	1071	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	1072	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1073	/**
phungductung	0:e87aa4c49e95	1074	* @}
phungductung	0:e87aa4c49e95	1075	*/
phungductung	0:e87aa4c49e95	1076
phungductung	0:e87aa4c49e95	1077	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
phungductung	0:e87aa4c49e95	1078	* @{
phungductung	0:e87aa4c49e95	1079	*/
phungductung	0:e87aa4c49e95	1080	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	1081	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	1082	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1083	/**
phungductung	0:e87aa4c49e95	1084	* @}
phungductung	0:e87aa4c49e95	1085	*/
phungductung	0:e87aa4c49e95	1086
phungductung	0:e87aa4c49e95	1087	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
phungductung	0:e87aa4c49e95	1088	* @{
phungductung	0:e87aa4c49e95	1089	*/
phungductung	0:e87aa4c49e95	1090	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
phungductung	0:e87aa4c49e95	1091	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
phungductung	0:e87aa4c49e95	1092	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
phungductung	0:e87aa4c49e95	1093	/**
phungductung	0:e87aa4c49e95	1094	* @}
phungductung	0:e87aa4c49e95	1095	*/
phungductung	0:e87aa4c49e95	1096
phungductung	0:e87aa4c49e95	1097	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
phungductung	0:e87aa4c49e95	1098	* @{
phungductung	0:e87aa4c49e95	1099	*/
phungductung	0:e87aa4c49e95	1100	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1101	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	1102	/**
phungductung	0:e87aa4c49e95	1103	* @}
phungductung	0:e87aa4c49e95	1104	*/
phungductung	0:e87aa4c49e95	1105
phungductung	0:e87aa4c49e95	1106	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
phungductung	0:e87aa4c49e95	1107	* @{
phungductung	0:e87aa4c49e95	1108	*/
phungductung	0:e87aa4c49e95	1109	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1110	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	1111	/**
phungductung	0:e87aa4c49e95	1112	* @}
phungductung	0:e87aa4c49e95	1113	*/
phungductung	0:e87aa4c49e95	1114
phungductung	0:e87aa4c49e95	1115	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
phungductung	0:e87aa4c49e95	1116	* @{
phungductung	0:e87aa4c49e95	1117	*/
phungductung	0:e87aa4c49e95	1118	#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	1119	#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1120	/**
phungductung	0:e87aa4c49e95	1121	* @}
phungductung	0:e87aa4c49e95	1122	*/
phungductung	0:e87aa4c49e95	1123
phungductung	0:e87aa4c49e95	1124	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
phungductung	0:e87aa4c49e95	1125	* @{
phungductung	0:e87aa4c49e95	1126	*/
phungductung	0:e87aa4c49e95	1127	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
phungductung	0:e87aa4c49e95	1128	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	1129	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1130	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	1131	/**
phungductung	0:e87aa4c49e95	1132	* @}
phungductung	0:e87aa4c49e95	1133	*/
phungductung	0:e87aa4c49e95	1134
phungductung	0:e87aa4c49e95	1135	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
phungductung	0:e87aa4c49e95	1136	* @{
phungductung	0:e87aa4c49e95	1137	*/
phungductung	0:e87aa4c49e95	1138	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
phungductung	0:e87aa4c49e95	1139	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	1140	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1141	/**
phungductung	0:e87aa4c49e95	1142	* @}
phungductung	0:e87aa4c49e95	1143	*/
phungductung	0:e87aa4c49e95	1144
phungductung	0:e87aa4c49e95	1145	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
phungductung	0:e87aa4c49e95	1146	* @{
phungductung	0:e87aa4c49e95	1147	*/
phungductung	0:e87aa4c49e95	1148	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1149	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	1150	/**
phungductung	0:e87aa4c49e95	1151	* @}
phungductung	0:e87aa4c49e95	1152	*/
phungductung	0:e87aa4c49e95	1153
phungductung	0:e87aa4c49e95	1154	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
phungductung	0:e87aa4c49e95	1155	* @{
phungductung	0:e87aa4c49e95	1156	*/
phungductung	0:e87aa4c49e95	1157	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
phungductung	0:e87aa4c49e95	1158	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
phungductung	0:e87aa4c49e95	1159	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
phungductung	0:e87aa4c49e95	1160	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
phungductung	0:e87aa4c49e95	1161	/**
phungductung	0:e87aa4c49e95	1162	* @}
phungductung	0:e87aa4c49e95	1163	*/
phungductung	0:e87aa4c49e95	1164
phungductung	0:e87aa4c49e95	1165	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
phungductung	0:e87aa4c49e95	1166	* @{
phungductung	0:e87aa4c49e95	1167	*/
phungductung	0:e87aa4c49e95	1168	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	1169	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1170	/**
phungductung	0:e87aa4c49e95	1171	* @}
phungductung	0:e87aa4c49e95	1172	*/
phungductung	0:e87aa4c49e95	1173
phungductung	0:e87aa4c49e95	1174	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
phungductung	0:e87aa4c49e95	1175	* @{
phungductung	0:e87aa4c49e95	1176	*/
phungductung	0:e87aa4c49e95	1177	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	1178	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1179	/**
phungductung	0:e87aa4c49e95	1180	* @}
phungductung	0:e87aa4c49e95	1181	*/
phungductung	0:e87aa4c49e95	1182
phungductung	0:e87aa4c49e95	1183	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
phungductung	0:e87aa4c49e95	1184	* @{
phungductung	0:e87aa4c49e95	1185	*/
phungductung	0:e87aa4c49e95	1186	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	1187	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1188	/**
phungductung	0:e87aa4c49e95	1189	* @}
phungductung	0:e87aa4c49e95	1190	*/
phungductung	0:e87aa4c49e95	1191
phungductung	0:e87aa4c49e95	1192	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
phungductung	0:e87aa4c49e95	1193	* @{
phungductung	0:e87aa4c49e95	1194	*/
phungductung	0:e87aa4c49e95	1195	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	1196	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1197	/**
phungductung	0:e87aa4c49e95	1198	* @}
phungductung	0:e87aa4c49e95	1199	*/
phungductung	0:e87aa4c49e95	1200
phungductung	0:e87aa4c49e95	1201	/** @defgroup ETH_MAC_addresses ETH MAC addresses
phungductung	0:e87aa4c49e95	1202	* @{
phungductung	0:e87aa4c49e95	1203	*/
phungductung	0:e87aa4c49e95	1204	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1205	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	1206	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	1207	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
phungductung	0:e87aa4c49e95	1208	/**
phungductung	0:e87aa4c49e95	1209	* @}
phungductung	0:e87aa4c49e95	1210	*/
phungductung	0:e87aa4c49e95	1211
phungductung	0:e87aa4c49e95	1212	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
phungductung	0:e87aa4c49e95	1213	* @{
phungductung	0:e87aa4c49e95	1214	*/
phungductung	0:e87aa4c49e95	1215	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1216	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	1217	/**
phungductung	0:e87aa4c49e95	1218	* @}
phungductung	0:e87aa4c49e95	1219	*/
phungductung	0:e87aa4c49e95	1220
phungductung	0:e87aa4c49e95	1221	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
phungductung	0:e87aa4c49e95	1222	* @{
phungductung	0:e87aa4c49e95	1223	*/
phungductung	0:e87aa4c49e95	1224	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
phungductung	0:e87aa4c49e95	1225	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
phungductung	0:e87aa4c49e95	1226	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
phungductung	0:e87aa4c49e95	1227	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
phungductung	0:e87aa4c49e95	1228	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
phungductung	0:e87aa4c49e95	1229	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
phungductung	0:e87aa4c49e95	1230	/**
phungductung	0:e87aa4c49e95	1231	* @}
phungductung	0:e87aa4c49e95	1232	*/
phungductung	0:e87aa4c49e95	1233
phungductung	0:e87aa4c49e95	1234	/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
phungductung	0:e87aa4c49e95	1235	* @{
phungductung	0:e87aa4c49e95	1236	*/
phungductung	0:e87aa4c49e95	1237	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
phungductung	0:e87aa4c49e95	1238	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
phungductung	0:e87aa4c49e95	1239	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
phungductung	0:e87aa4c49e95	1240	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
phungductung	0:e87aa4c49e95	1241	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
phungductung	0:e87aa4c49e95	1242	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
phungductung	0:e87aa4c49e95	1243	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
phungductung	0:e87aa4c49e95	1244	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
phungductung	0:e87aa4c49e95	1245	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
phungductung	0:e87aa4c49e95	1246	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
phungductung	0:e87aa4c49e95	1247	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
phungductung	0:e87aa4c49e95	1248	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
phungductung	0:e87aa4c49e95	1249	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
phungductung	0:e87aa4c49e95	1250	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
phungductung	0:e87aa4c49e95	1251	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
phungductung	0:e87aa4c49e95	1252	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
phungductung	0:e87aa4c49e95	1253	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
phungductung	0:e87aa4c49e95	1254	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
phungductung	0:e87aa4c49e95	1255	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
phungductung	0:e87aa4c49e95	1256	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
phungductung	0:e87aa4c49e95	1257	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
phungductung	0:e87aa4c49e95	1258	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
phungductung	0:e87aa4c49e95	1259	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
phungductung	0:e87aa4c49e95	1260	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
phungductung	0:e87aa4c49e95	1261	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
phungductung	0:e87aa4c49e95	1262	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
phungductung	0:e87aa4c49e95	1263	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
phungductung	0:e87aa4c49e95	1264	/**
phungductung	0:e87aa4c49e95	1265	* @}
phungductung	0:e87aa4c49e95	1266	*/
phungductung	0:e87aa4c49e95	1267
phungductung	0:e87aa4c49e95	1268	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
phungductung	0:e87aa4c49e95	1269	* @{
phungductung	0:e87aa4c49e95	1270	*/
phungductung	0:e87aa4c49e95	1271	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1272	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	1273	/**
phungductung	0:e87aa4c49e95	1274	* @}
phungductung	0:e87aa4c49e95	1275	*/
phungductung	0:e87aa4c49e95	1276
phungductung	0:e87aa4c49e95	1277	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
phungductung	0:e87aa4c49e95	1278	* @{
phungductung	0:e87aa4c49e95	1279	*/
phungductung	0:e87aa4c49e95	1280	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	1281	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1282	/**
phungductung	0:e87aa4c49e95	1283	* @}
phungductung	0:e87aa4c49e95	1284	*/
phungductung	0:e87aa4c49e95	1285
phungductung	0:e87aa4c49e95	1286	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
phungductung	0:e87aa4c49e95	1287	* @{
phungductung	0:e87aa4c49e95	1288	*/
phungductung	0:e87aa4c49e95	1289	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1290	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	1291	/**
phungductung	0:e87aa4c49e95	1292	* @}
phungductung	0:e87aa4c49e95	1293	*/
phungductung	0:e87aa4c49e95	1294
phungductung	0:e87aa4c49e95	1295	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
phungductung	0:e87aa4c49e95	1296	* @{
phungductung	0:e87aa4c49e95	1297	*/
phungductung	0:e87aa4c49e95	1298	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	1299	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1300	/**
phungductung	0:e87aa4c49e95	1301	* @}
phungductung	0:e87aa4c49e95	1302	*/
phungductung	0:e87aa4c49e95	1303
phungductung	0:e87aa4c49e95	1304	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
phungductung	0:e87aa4c49e95	1305	* @{
phungductung	0:e87aa4c49e95	1306	*/
phungductung	0:e87aa4c49e95	1307	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
phungductung	0:e87aa4c49e95	1308	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
phungductung	0:e87aa4c49e95	1309	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
phungductung	0:e87aa4c49e95	1310	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
phungductung	0:e87aa4c49e95	1311	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
phungductung	0:e87aa4c49e95	1312	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
phungductung	0:e87aa4c49e95	1313	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
phungductung	0:e87aa4c49e95	1314	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
phungductung	0:e87aa4c49e95	1315	/**
phungductung	0:e87aa4c49e95	1316	* @}
phungductung	0:e87aa4c49e95	1317	*/
phungductung	0:e87aa4c49e95	1318
phungductung	0:e87aa4c49e95	1319	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
phungductung	0:e87aa4c49e95	1320	* @{
phungductung	0:e87aa4c49e95	1321	*/
phungductung	0:e87aa4c49e95	1322	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	1323	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1324	/**
phungductung	0:e87aa4c49e95	1325	* @}
phungductung	0:e87aa4c49e95	1326	*/
phungductung	0:e87aa4c49e95	1327
phungductung	0:e87aa4c49e95	1328	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
phungductung	0:e87aa4c49e95	1329	* @{
phungductung	0:e87aa4c49e95	1330	*/
phungductung	0:e87aa4c49e95	1331	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	1332	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1333	/**
phungductung	0:e87aa4c49e95	1334	* @}
phungductung	0:e87aa4c49e95	1335	*/
phungductung	0:e87aa4c49e95	1336
phungductung	0:e87aa4c49e95	1337	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
phungductung	0:e87aa4c49e95	1338	* @{
phungductung	0:e87aa4c49e95	1339	*/
phungductung	0:e87aa4c49e95	1340	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
phungductung	0:e87aa4c49e95	1341	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
phungductung	0:e87aa4c49e95	1342	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
phungductung	0:e87aa4c49e95	1343	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
phungductung	0:e87aa4c49e95	1344	/**
phungductung	0:e87aa4c49e95	1345	* @}
phungductung	0:e87aa4c49e95	1346	*/
phungductung	0:e87aa4c49e95	1347
phungductung	0:e87aa4c49e95	1348	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
phungductung	0:e87aa4c49e95	1349	* @{
phungductung	0:e87aa4c49e95	1350	*/
phungductung	0:e87aa4c49e95	1351	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	1352	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1353	/**
phungductung	0:e87aa4c49e95	1354	* @}
phungductung	0:e87aa4c49e95	1355	*/
phungductung	0:e87aa4c49e95	1356
phungductung	0:e87aa4c49e95	1357	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
phungductung	0:e87aa4c49e95	1358	* @{
phungductung	0:e87aa4c49e95	1359	*/
phungductung	0:e87aa4c49e95	1360	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	1361	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1362	/**
phungductung	0:e87aa4c49e95	1363	* @}
phungductung	0:e87aa4c49e95	1364	*/
phungductung	0:e87aa4c49e95	1365
phungductung	0:e87aa4c49e95	1366	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
phungductung	0:e87aa4c49e95	1367	* @{
phungductung	0:e87aa4c49e95	1368	*/
phungductung	0:e87aa4c49e95	1369	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	1370	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1371	/**
phungductung	0:e87aa4c49e95	1372	* @}
phungductung	0:e87aa4c49e95	1373	*/
phungductung	0:e87aa4c49e95	1374
phungductung	0:e87aa4c49e95	1375	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
phungductung	0:e87aa4c49e95	1376	* @{
phungductung	0:e87aa4c49e95	1377	*/
phungductung	0:e87aa4c49e95	1378	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
phungductung	0:e87aa4c49e95	1379	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
phungductung	0:e87aa4c49e95	1380	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
phungductung	0:e87aa4c49e95	1381	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
phungductung	0:e87aa4c49e95	1382	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
phungductung	0:e87aa4c49e95	1383	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
phungductung	0:e87aa4c49e95	1384	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
phungductung	0:e87aa4c49e95	1385	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
phungductung	0:e87aa4c49e95	1386	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
phungductung	0:e87aa4c49e95	1387	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
phungductung	0:e87aa4c49e95	1388	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
phungductung	0:e87aa4c49e95	1389	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
phungductung	0:e87aa4c49e95	1390	/**
phungductung	0:e87aa4c49e95	1391	* @}
phungductung	0:e87aa4c49e95	1392	*/
phungductung	0:e87aa4c49e95	1393
phungductung	0:e87aa4c49e95	1394	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
phungductung	0:e87aa4c49e95	1395	* @{
phungductung	0:e87aa4c49e95	1396	*/
phungductung	0:e87aa4c49e95	1397	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
phungductung	0:e87aa4c49e95	1398	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
phungductung	0:e87aa4c49e95	1399	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
phungductung	0:e87aa4c49e95	1400	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
phungductung	0:e87aa4c49e95	1401	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
phungductung	0:e87aa4c49e95	1402	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
phungductung	0:e87aa4c49e95	1403	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
phungductung	0:e87aa4c49e95	1404	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
phungductung	0:e87aa4c49e95	1405	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
phungductung	0:e87aa4c49e95	1406	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
phungductung	0:e87aa4c49e95	1407	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
phungductung	0:e87aa4c49e95	1408	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
phungductung	0:e87aa4c49e95	1409	/**
phungductung	0:e87aa4c49e95	1410	* @}
phungductung	0:e87aa4c49e95	1411	*/
phungductung	0:e87aa4c49e95	1412
phungductung	0:e87aa4c49e95	1413	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
phungductung	0:e87aa4c49e95	1414	* @{
phungductung	0:e87aa4c49e95	1415	*/
phungductung	0:e87aa4c49e95	1416	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	1417	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1418	/**
phungductung	0:e87aa4c49e95	1419	* @}
phungductung	0:e87aa4c49e95	1420	*/
phungductung	0:e87aa4c49e95	1421
phungductung	0:e87aa4c49e95	1422	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
phungductung	0:e87aa4c49e95	1423	* @{
phungductung	0:e87aa4c49e95	1424	*/
phungductung	0:e87aa4c49e95	1425	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	1426	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	1427	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	1428	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
phungductung	0:e87aa4c49e95	1429	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	1430	/**
phungductung	0:e87aa4c49e95	1431	* @}
phungductung	0:e87aa4c49e95	1432	*/
phungductung	0:e87aa4c49e95	1433
phungductung	0:e87aa4c49e95	1434	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
phungductung	0:e87aa4c49e95	1435	* @{
phungductung	0:e87aa4c49e95	1436	*/
phungductung	0:e87aa4c49e95	1437	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
phungductung	0:e87aa4c49e95	1438	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
phungductung	0:e87aa4c49e95	1439	/**
phungductung	0:e87aa4c49e95	1440	* @}
phungductung	0:e87aa4c49e95	1441	*/
phungductung	0:e87aa4c49e95	1442
phungductung	0:e87aa4c49e95	1443	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
phungductung	0:e87aa4c49e95	1444	* @{
phungductung	0:e87aa4c49e95	1445	*/
phungductung	0:e87aa4c49e95	1446	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
phungductung	0:e87aa4c49e95	1447	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
phungductung	0:e87aa4c49e95	1448	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
phungductung	0:e87aa4c49e95	1449	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
phungductung	0:e87aa4c49e95	1450	/**
phungductung	0:e87aa4c49e95	1451	* @}
phungductung	0:e87aa4c49e95	1452	*/
phungductung	0:e87aa4c49e95	1453
phungductung	0:e87aa4c49e95	1454	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
phungductung	0:e87aa4c49e95	1455	* @{
phungductung	0:e87aa4c49e95	1456	*/
phungductung	0:e87aa4c49e95	1457	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
phungductung	0:e87aa4c49e95	1458	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
phungductung	0:e87aa4c49e95	1459	/**
phungductung	0:e87aa4c49e95	1460	* @}
phungductung	0:e87aa4c49e95	1461	*/
phungductung	0:e87aa4c49e95	1462
phungductung	0:e87aa4c49e95	1463	/** @defgroup ETH_PMT_Flags ETH PMT Flags
phungductung	0:e87aa4c49e95	1464	* @{
phungductung	0:e87aa4c49e95	1465	*/
phungductung	0:e87aa4c49e95	1466	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
phungductung	0:e87aa4c49e95	1467	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
phungductung	0:e87aa4c49e95	1468	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
phungductung	0:e87aa4c49e95	1469	/**
phungductung	0:e87aa4c49e95	1470	* @}
phungductung	0:e87aa4c49e95	1471	*/
phungductung	0:e87aa4c49e95	1472
phungductung	0:e87aa4c49e95	1473	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
phungductung	0:e87aa4c49e95	1474	* @{
phungductung	0:e87aa4c49e95	1475	*/
phungductung	0:e87aa4c49e95	1476	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
phungductung	0:e87aa4c49e95	1477	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
phungductung	0:e87aa4c49e95	1478	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
phungductung	0:e87aa4c49e95	1479	/**
phungductung	0:e87aa4c49e95	1480	* @}
phungductung	0:e87aa4c49e95	1481	*/
phungductung	0:e87aa4c49e95	1482
phungductung	0:e87aa4c49e95	1483	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
phungductung	0:e87aa4c49e95	1484	* @{
phungductung	0:e87aa4c49e95	1485	*/
phungductung	0:e87aa4c49e95	1486	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
phungductung	0:e87aa4c49e95	1487	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
phungductung	0:e87aa4c49e95	1488	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
phungductung	0:e87aa4c49e95	1489	/**
phungductung	0:e87aa4c49e95	1490	* @}
phungductung	0:e87aa4c49e95	1491	*/
phungductung	0:e87aa4c49e95	1492
phungductung	0:e87aa4c49e95	1493	/** @defgroup ETH_MAC_Flags ETH MAC Flags
phungductung	0:e87aa4c49e95	1494	* @{
phungductung	0:e87aa4c49e95	1495	*/
phungductung	0:e87aa4c49e95	1496	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
phungductung	0:e87aa4c49e95	1497	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
phungductung	0:e87aa4c49e95	1498	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
phungductung	0:e87aa4c49e95	1499	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
phungductung	0:e87aa4c49e95	1500	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
phungductung	0:e87aa4c49e95	1501	/**
phungductung	0:e87aa4c49e95	1502	* @}
phungductung	0:e87aa4c49e95	1503	*/
phungductung	0:e87aa4c49e95	1504
phungductung	0:e87aa4c49e95	1505	/** @defgroup ETH_DMA_Flags ETH DMA Flags
phungductung	0:e87aa4c49e95	1506	* @{
phungductung	0:e87aa4c49e95	1507	*/
phungductung	0:e87aa4c49e95	1508	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
phungductung	0:e87aa4c49e95	1509	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
phungductung	0:e87aa4c49e95	1510	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
phungductung	0:e87aa4c49e95	1511	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
phungductung	0:e87aa4c49e95	1512	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write transfer, 1-read transfer /
phungductung	0:e87aa4c49e95	1513	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
phungductung	0:e87aa4c49e95	1514	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
phungductung	0:e87aa4c49e95	1515	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
phungductung	0:e87aa4c49e95	1516	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
phungductung	0:e87aa4c49e95	1517	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
phungductung	0:e87aa4c49e95	1518	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
phungductung	0:e87aa4c49e95	1519	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
phungductung	0:e87aa4c49e95	1520	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
phungductung	0:e87aa4c49e95	1521	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
phungductung	0:e87aa4c49e95	1522	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
phungductung	0:e87aa4c49e95	1523	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
phungductung	0:e87aa4c49e95	1524	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
phungductung	0:e87aa4c49e95	1525	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
phungductung	0:e87aa4c49e95	1526	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
phungductung	0:e87aa4c49e95	1527	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
phungductung	0:e87aa4c49e95	1528	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
phungductung	0:e87aa4c49e95	1529	/**
phungductung	0:e87aa4c49e95	1530	* @}
phungductung	0:e87aa4c49e95	1531	*/
phungductung	0:e87aa4c49e95	1532
phungductung	0:e87aa4c49e95	1533	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
phungductung	0:e87aa4c49e95	1534	* @{
phungductung	0:e87aa4c49e95	1535	*/
phungductung	0:e87aa4c49e95	1536	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
phungductung	0:e87aa4c49e95	1537	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
phungductung	0:e87aa4c49e95	1538	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
phungductung	0:e87aa4c49e95	1539	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
phungductung	0:e87aa4c49e95	1540	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
phungductung	0:e87aa4c49e95	1541	/**
phungductung	0:e87aa4c49e95	1542	* @}
phungductung	0:e87aa4c49e95	1543	*/
phungductung	0:e87aa4c49e95	1544
phungductung	0:e87aa4c49e95	1545	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
phungductung	0:e87aa4c49e95	1546	* @{
phungductung	0:e87aa4c49e95	1547	*/
phungductung	0:e87aa4c49e95	1548	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
phungductung	0:e87aa4c49e95	1549	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
phungductung	0:e87aa4c49e95	1550	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
phungductung	0:e87aa4c49e95	1551	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
phungductung	0:e87aa4c49e95	1552	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
phungductung	0:e87aa4c49e95	1553	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
phungductung	0:e87aa4c49e95	1554	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
phungductung	0:e87aa4c49e95	1555	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
phungductung	0:e87aa4c49e95	1556	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
phungductung	0:e87aa4c49e95	1557	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
phungductung	0:e87aa4c49e95	1558	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
phungductung	0:e87aa4c49e95	1559	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
phungductung	0:e87aa4c49e95	1560	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
phungductung	0:e87aa4c49e95	1561	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
phungductung	0:e87aa4c49e95	1562	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
phungductung	0:e87aa4c49e95	1563	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
phungductung	0:e87aa4c49e95	1564	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
phungductung	0:e87aa4c49e95	1565	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
phungductung	0:e87aa4c49e95	1566	/**
phungductung	0:e87aa4c49e95	1567	* @}
phungductung	0:e87aa4c49e95	1568	*/
phungductung	0:e87aa4c49e95	1569
phungductung	0:e87aa4c49e95	1570	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
phungductung	0:e87aa4c49e95	1571	* @{
phungductung	0:e87aa4c49e95	1572	*/
phungductung	0:e87aa4c49e95	1573	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
phungductung	0:e87aa4c49e95	1574	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
phungductung	0:e87aa4c49e95	1575	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
phungductung	0:e87aa4c49e95	1576	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
phungductung	0:e87aa4c49e95	1577	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
phungductung	0:e87aa4c49e95	1578	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
phungductung	0:e87aa4c49e95	1579
phungductung	0:e87aa4c49e95	1580	/**
phungductung	0:e87aa4c49e95	1581	* @}
phungductung	0:e87aa4c49e95	1582	*/
phungductung	0:e87aa4c49e95	1583
phungductung	0:e87aa4c49e95	1584
phungductung	0:e87aa4c49e95	1585	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
phungductung	0:e87aa4c49e95	1586	* @{
phungductung	0:e87aa4c49e95	1587	*/
phungductung	0:e87aa4c49e95	1588	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
phungductung	0:e87aa4c49e95	1589	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
phungductung	0:e87aa4c49e95	1590	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
phungductung	0:e87aa4c49e95	1591	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
phungductung	0:e87aa4c49e95	1592	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
phungductung	0:e87aa4c49e95	1593	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
phungductung	0:e87aa4c49e95	1594
phungductung	0:e87aa4c49e95	1595	/**
phungductung	0:e87aa4c49e95	1596	* @}
phungductung	0:e87aa4c49e95	1597	*/
phungductung	0:e87aa4c49e95	1598
phungductung	0:e87aa4c49e95	1599	/** @defgroup ETH_DMA_overflow ETH DMA overflow
phungductung	0:e87aa4c49e95	1600	* @{
phungductung	0:e87aa4c49e95	1601	*/
phungductung	0:e87aa4c49e95	1602	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
phungductung	0:e87aa4c49e95	1603	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
phungductung	0:e87aa4c49e95	1604	/**
phungductung	0:e87aa4c49e95	1605	* @}
phungductung	0:e87aa4c49e95	1606	*/
phungductung	0:e87aa4c49e95	1607
phungductung	0:e87aa4c49e95	1608	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
phungductung	0:e87aa4c49e95	1609	* @{
phungductung	0:e87aa4c49e95	1610	*/
phungductung	0:e87aa4c49e95	1611	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
phungductung	0:e87aa4c49e95	1612
phungductung	0:e87aa4c49e95	1613	/**
phungductung	0:e87aa4c49e95	1614	* @}
phungductung	0:e87aa4c49e95	1615	*/
phungductung	0:e87aa4c49e95	1616
phungductung	0:e87aa4c49e95	1617	/**
phungductung	0:e87aa4c49e95	1618	* @}
phungductung	0:e87aa4c49e95	1619	*/
phungductung	0:e87aa4c49e95	1620
phungductung	0:e87aa4c49e95	1621	/* Exported macro ------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	1622	/** @defgroup ETH_Exported_Macros ETH Exported Macros
phungductung	0:e87aa4c49e95	1623	* @brief macros to handle interrupts and specific clock configurations
phungductung	0:e87aa4c49e95	1624	* @{
phungductung	0:e87aa4c49e95	1625	*/
phungductung	0:e87aa4c49e95	1626
phungductung	0:e87aa4c49e95	1627	/** @brief Reset ETH handle state
phungductung	0:e87aa4c49e95	1628	* @param __HANDLE__: specifies the ETH handle.
phungductung	0:e87aa4c49e95	1629	* @retval None
phungductung	0:e87aa4c49e95	1630	*/
phungductung	0:e87aa4c49e95	1631	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
phungductung	0:e87aa4c49e95	1632
phungductung	0:e87aa4c49e95	1633	/**
phungductung	0:e87aa4c49e95	1634	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
phungductung	0:e87aa4c49e95	1635	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1636	* @param __FLAG__: specifies the flag of TDES0 to check.
phungductung	0:e87aa4c49e95	1637	* @retval the ETH_DMATxDescFlag (SET or RESET).
phungductung	0:e87aa4c49e95	1638	*/
phungductung	0:e87aa4c49e95	1639	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
phungductung	0:e87aa4c49e95	1640
phungductung	0:e87aa4c49e95	1641	/**
phungductung	0:e87aa4c49e95	1642	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
phungductung	0:e87aa4c49e95	1643	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1644	* @param __FLAG__: specifies the flag of RDES0 to check.
phungductung	0:e87aa4c49e95	1645	* @retval the ETH_DMATxDescFlag (SET or RESET).
phungductung	0:e87aa4c49e95	1646	*/
phungductung	0:e87aa4c49e95	1647	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
phungductung	0:e87aa4c49e95	1648
phungductung	0:e87aa4c49e95	1649	/**
phungductung	0:e87aa4c49e95	1650	* @brief Enables the specified DMA Rx Desc receive interrupt.
phungductung	0:e87aa4c49e95	1651	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1652	* @retval None
phungductung	0:e87aa4c49e95	1653	*/
phungductung	0:e87aa4c49e95	1654	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
phungductung	0:e87aa4c49e95	1655
phungductung	0:e87aa4c49e95	1656	/**
phungductung	0:e87aa4c49e95	1657	* @brief Disables the specified DMA Rx Desc receive interrupt.
phungductung	0:e87aa4c49e95	1658	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1659	* @retval None
phungductung	0:e87aa4c49e95	1660	*/
phungductung	0:e87aa4c49e95	1661	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
phungductung	0:e87aa4c49e95	1662
phungductung	0:e87aa4c49e95	1663	/**
phungductung	0:e87aa4c49e95	1664	* @brief Set the specified DMA Rx Desc Own bit.
phungductung	0:e87aa4c49e95	1665	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1666	* @retval None
phungductung	0:e87aa4c49e95	1667	*/
phungductung	0:e87aa4c49e95	1668	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
phungductung	0:e87aa4c49e95	1669
phungductung	0:e87aa4c49e95	1670	/**
phungductung	0:e87aa4c49e95	1671	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
phungductung	0:e87aa4c49e95	1672	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1673	* @retval The Transmit descriptor collision counter value.
phungductung	0:e87aa4c49e95	1674	*/
phungductung	0:e87aa4c49e95	1675	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
phungductung	0:e87aa4c49e95	1676
phungductung	0:e87aa4c49e95	1677	/**
phungductung	0:e87aa4c49e95	1678	* @brief Set the specified DMA Tx Desc Own bit.
phungductung	0:e87aa4c49e95	1679	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1680	* @retval None
phungductung	0:e87aa4c49e95	1681	*/
phungductung	0:e87aa4c49e95	1682	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
phungductung	0:e87aa4c49e95	1683
phungductung	0:e87aa4c49e95	1684	/**
phungductung	0:e87aa4c49e95	1685	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
phungductung	0:e87aa4c49e95	1686	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1687	* @retval None
phungductung	0:e87aa4c49e95	1688	*/
phungductung	0:e87aa4c49e95	1689	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
phungductung	0:e87aa4c49e95	1690
phungductung	0:e87aa4c49e95	1691	/**
phungductung	0:e87aa4c49e95	1692	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
phungductung	0:e87aa4c49e95	1693	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1694	* @retval None
phungductung	0:e87aa4c49e95	1695	*/
phungductung	0:e87aa4c49e95	1696	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
phungductung	0:e87aa4c49e95	1697
phungductung	0:e87aa4c49e95	1698	/**
phungductung	0:e87aa4c49e95	1699	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
phungductung	0:e87aa4c49e95	1700	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1701	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
phungductung	0:e87aa4c49e95	1702	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1703	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
phungductung	0:e87aa4c49e95	1704	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
phungductung	0:e87aa4c49e95	1705	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
phungductung	0:e87aa4c49e95	1706	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
phungductung	0:e87aa4c49e95	1707	* @retval None
phungductung	0:e87aa4c49e95	1708	*/
phungductung	0:e87aa4c49e95	1709	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
phungductung	0:e87aa4c49e95	1710
phungductung	0:e87aa4c49e95	1711	/**
phungductung	0:e87aa4c49e95	1712	* @brief Enables the DMA Tx Desc CRC.
phungductung	0:e87aa4c49e95	1713	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1714	* @retval None
phungductung	0:e87aa4c49e95	1715	*/
phungductung	0:e87aa4c49e95	1716	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
phungductung	0:e87aa4c49e95	1717
phungductung	0:e87aa4c49e95	1718	/**
phungductung	0:e87aa4c49e95	1719	* @brief Disables the DMA Tx Desc CRC.
phungductung	0:e87aa4c49e95	1720	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1721	* @retval None
phungductung	0:e87aa4c49e95	1722	*/
phungductung	0:e87aa4c49e95	1723	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
phungductung	0:e87aa4c49e95	1724
phungductung	0:e87aa4c49e95	1725	/**
phungductung	0:e87aa4c49e95	1726	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
phungductung	0:e87aa4c49e95	1727	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1728	* @retval None
phungductung	0:e87aa4c49e95	1729	*/
phungductung	0:e87aa4c49e95	1730	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
phungductung	0:e87aa4c49e95	1731
phungductung	0:e87aa4c49e95	1732	/**
phungductung	0:e87aa4c49e95	1733	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
phungductung	0:e87aa4c49e95	1734	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1735	* @retval None
phungductung	0:e87aa4c49e95	1736	*/
phungductung	0:e87aa4c49e95	1737	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
phungductung	0:e87aa4c49e95	1738
phungductung	0:e87aa4c49e95	1739	/**
phungductung	0:e87aa4c49e95	1740	* @brief Enables the specified ETHERNET MAC interrupts.
phungductung	0:e87aa4c49e95	1741	* @param __HANDLE__ : ETH Handle
phungductung	0:e87aa4c49e95	1742	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
phungductung	0:e87aa4c49e95	1743	* enabled or disabled.
phungductung	0:e87aa4c49e95	1744	* This parameter can be any combination of the following values:
phungductung	0:e87aa4c49e95	1745	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
phungductung	0:e87aa4c49e95	1746	* @arg ETH_MAC_IT_PMT : PMT interrupt
phungductung	0:e87aa4c49e95	1747	* @retval None
phungductung	0:e87aa4c49e95	1748	*/
phungductung	0:e87aa4c49e95	1749	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
phungductung	0:e87aa4c49e95	1750
phungductung	0:e87aa4c49e95	1751	/**
phungductung	0:e87aa4c49e95	1752	* @brief Disables the specified ETHERNET MAC interrupts.
phungductung	0:e87aa4c49e95	1753	* @param __HANDLE__ : ETH Handle
phungductung	0:e87aa4c49e95	1754	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
phungductung	0:e87aa4c49e95	1755	* enabled or disabled.
phungductung	0:e87aa4c49e95	1756	* This parameter can be any combination of the following values:
phungductung	0:e87aa4c49e95	1757	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
phungductung	0:e87aa4c49e95	1758	* @arg ETH_MAC_IT_PMT : PMT interrupt
phungductung	0:e87aa4c49e95	1759	* @retval None
phungductung	0:e87aa4c49e95	1760	*/
phungductung	0:e87aa4c49e95	1761	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
phungductung	0:e87aa4c49e95	1762
phungductung	0:e87aa4c49e95	1763	/**
phungductung	0:e87aa4c49e95	1764	* @brief Initiate a Pause Control Frame (Full-duplex only).
phungductung	0:e87aa4c49e95	1765	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1766	* @retval None
phungductung	0:e87aa4c49e95	1767	*/
phungductung	0:e87aa4c49e95	1768	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
phungductung	0:e87aa4c49e95	1769
phungductung	0:e87aa4c49e95	1770	/**
phungductung	0:e87aa4c49e95	1771	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
phungductung	0:e87aa4c49e95	1772	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1773	* @retval The new state of flow control busy status bit (SET or RESET).
phungductung	0:e87aa4c49e95	1774	*/
phungductung	0:e87aa4c49e95	1775	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
phungductung	0:e87aa4c49e95	1776
phungductung	0:e87aa4c49e95	1777	/**
phungductung	0:e87aa4c49e95	1778	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
phungductung	0:e87aa4c49e95	1779	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1780	* @retval None
phungductung	0:e87aa4c49e95	1781	*/
phungductung	0:e87aa4c49e95	1782	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
phungductung	0:e87aa4c49e95	1783
phungductung	0:e87aa4c49e95	1784	/**
phungductung	0:e87aa4c49e95	1785	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
phungductung	0:e87aa4c49e95	1786	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1787	* @retval None
phungductung	0:e87aa4c49e95	1788	*/
phungductung	0:e87aa4c49e95	1789	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
phungductung	0:e87aa4c49e95	1790
phungductung	0:e87aa4c49e95	1791	/**
phungductung	0:e87aa4c49e95	1792	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
phungductung	0:e87aa4c49e95	1793	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1794	* @param __FLAG__: specifies the flag to check.
phungductung	0:e87aa4c49e95	1795	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1796	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
phungductung	0:e87aa4c49e95	1797	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
phungductung	0:e87aa4c49e95	1798	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
phungductung	0:e87aa4c49e95	1799	* @arg ETH_MAC_FLAG_MMC : MMC flag
phungductung	0:e87aa4c49e95	1800	* @arg ETH_MAC_FLAG_PMT : PMT flag
phungductung	0:e87aa4c49e95	1801	* @retval The state of ETHERNET MAC flag.
phungductung	0:e87aa4c49e95	1802	*/
phungductung	0:e87aa4c49e95	1803	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
phungductung	0:e87aa4c49e95	1804
phungductung	0:e87aa4c49e95	1805	/**
phungductung	0:e87aa4c49e95	1806	* @brief Enables the specified ETHERNET DMA interrupts.
phungductung	0:e87aa4c49e95	1807	* @param __HANDLE__ : ETH Handle
phungductung	0:e87aa4c49e95	1808	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
phungductung	0:e87aa4c49e95	1809	* enabled @ref ETH_DMA_Interrupts
phungductung	0:e87aa4c49e95	1810	* @retval None
phungductung	0:e87aa4c49e95	1811	*/
phungductung	0:e87aa4c49e95	1812	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
phungductung	0:e87aa4c49e95	1813
phungductung	0:e87aa4c49e95	1814	/**
phungductung	0:e87aa4c49e95	1815	* @brief Disables the specified ETHERNET DMA interrupts.
phungductung	0:e87aa4c49e95	1816	* @param __HANDLE__ : ETH Handle
phungductung	0:e87aa4c49e95	1817	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
phungductung	0:e87aa4c49e95	1818	* disabled. @ref ETH_DMA_Interrupts
phungductung	0:e87aa4c49e95	1819	* @retval None
phungductung	0:e87aa4c49e95	1820	*/
phungductung	0:e87aa4c49e95	1821	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
phungductung	0:e87aa4c49e95	1822
phungductung	0:e87aa4c49e95	1823	/**
phungductung	0:e87aa4c49e95	1824	* @brief Clears the ETHERNET DMA IT pending bit.
phungductung	0:e87aa4c49e95	1825	* @param __HANDLE__ : ETH Handle
phungductung	0:e87aa4c49e95	1826	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
phungductung	0:e87aa4c49e95	1827	* @retval None
phungductung	0:e87aa4c49e95	1828	*/
phungductung	0:e87aa4c49e95	1829	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
phungductung	0:e87aa4c49e95	1830
phungductung	0:e87aa4c49e95	1831	/**
phungductung	0:e87aa4c49e95	1832	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
phungductung	0:e87aa4c49e95	1833	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1834	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
phungductung	0:e87aa4c49e95	1835	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
phungductung	0:e87aa4c49e95	1836	*/
phungductung	0:e87aa4c49e95	1837	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
phungductung	0:e87aa4c49e95	1838
phungductung	0:e87aa4c49e95	1839	/**
phungductung	0:e87aa4c49e95	1840	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
phungductung	0:e87aa4c49e95	1841	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1842	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
phungductung	0:e87aa4c49e95	1843	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
phungductung	0:e87aa4c49e95	1844	*/
phungductung	0:e87aa4c49e95	1845	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
phungductung	0:e87aa4c49e95	1846
phungductung	0:e87aa4c49e95	1847	/**
phungductung	0:e87aa4c49e95	1848	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
phungductung	0:e87aa4c49e95	1849	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1850	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
phungductung	0:e87aa4c49e95	1851	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1852	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
phungductung	0:e87aa4c49e95	1853	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
phungductung	0:e87aa4c49e95	1854	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
phungductung	0:e87aa4c49e95	1855	*/
phungductung	0:e87aa4c49e95	1856	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
phungductung	0:e87aa4c49e95	1857
phungductung	0:e87aa4c49e95	1858	/**
phungductung	0:e87aa4c49e95	1859	* @brief Set the DMA Receive status watchdog timer register value
phungductung	0:e87aa4c49e95	1860	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1861	* @param __VALUE__: DMA Receive status watchdog timer register value
phungductung	0:e87aa4c49e95	1862	* @retval None
phungductung	0:e87aa4c49e95	1863	*/
phungductung	0:e87aa4c49e95	1864	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
phungductung	0:e87aa4c49e95	1865
phungductung	0:e87aa4c49e95	1866	/**
phungductung	0:e87aa4c49e95	1867	* @brief Enables any unicast packet filtered by the MAC address
phungductung	0:e87aa4c49e95	1868	* recognition to be a wake-up frame.
phungductung	0:e87aa4c49e95	1869	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1870	* @retval None
phungductung	0:e87aa4c49e95	1871	*/
phungductung	0:e87aa4c49e95	1872	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
phungductung	0:e87aa4c49e95	1873
phungductung	0:e87aa4c49e95	1874	/**
phungductung	0:e87aa4c49e95	1875	* @brief Disables any unicast packet filtered by the MAC address
phungductung	0:e87aa4c49e95	1876	* recognition to be a wake-up frame.
phungductung	0:e87aa4c49e95	1877	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1878	* @retval None
phungductung	0:e87aa4c49e95	1879	*/
phungductung	0:e87aa4c49e95	1880	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
phungductung	0:e87aa4c49e95	1881
phungductung	0:e87aa4c49e95	1882	/**
phungductung	0:e87aa4c49e95	1883	* @brief Enables the MAC Wake-Up Frame Detection.
phungductung	0:e87aa4c49e95	1884	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1885	* @retval None
phungductung	0:e87aa4c49e95	1886	*/
phungductung	0:e87aa4c49e95	1887	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
phungductung	0:e87aa4c49e95	1888
phungductung	0:e87aa4c49e95	1889	/**
phungductung	0:e87aa4c49e95	1890	* @brief Disables the MAC Wake-Up Frame Detection.
phungductung	0:e87aa4c49e95	1891	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1892	* @retval None
phungductung	0:e87aa4c49e95	1893	*/
phungductung	0:e87aa4c49e95	1894	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
phungductung	0:e87aa4c49e95	1895
phungductung	0:e87aa4c49e95	1896	/**
phungductung	0:e87aa4c49e95	1897	* @brief Enables the MAC Magic Packet Detection.
phungductung	0:e87aa4c49e95	1898	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1899	* @retval None
phungductung	0:e87aa4c49e95	1900	*/
phungductung	0:e87aa4c49e95	1901	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
phungductung	0:e87aa4c49e95	1902
phungductung	0:e87aa4c49e95	1903	/**
phungductung	0:e87aa4c49e95	1904	* @brief Disables the MAC Magic Packet Detection.
phungductung	0:e87aa4c49e95	1905	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1906	* @retval None
phungductung	0:e87aa4c49e95	1907	*/
phungductung	0:e87aa4c49e95	1908	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
phungductung	0:e87aa4c49e95	1909
phungductung	0:e87aa4c49e95	1910	/**
phungductung	0:e87aa4c49e95	1911	* @brief Enables the MAC Power Down.
phungductung	0:e87aa4c49e95	1912	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1913	* @retval None
phungductung	0:e87aa4c49e95	1914	*/
phungductung	0:e87aa4c49e95	1915	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
phungductung	0:e87aa4c49e95	1916
phungductung	0:e87aa4c49e95	1917	/**
phungductung	0:e87aa4c49e95	1918	* @brief Disables the MAC Power Down.
phungductung	0:e87aa4c49e95	1919	* @param __HANDLE__: ETH Handle
phungductung	0:e87aa4c49e95	1920	* @retval None
phungductung	0:e87aa4c49e95	1921	*/
phungductung	0:e87aa4c49e95	1922	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
phungductung	0:e87aa4c49e95	1923
phungductung	0:e87aa4c49e95	1924	/**
phungductung	0:e87aa4c49e95	1925	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
phungductung	0:e87aa4c49e95	1926	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1927	* @param __FLAG__: specifies the flag to check.
phungductung	0:e87aa4c49e95	1928	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1929	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
phungductung	0:e87aa4c49e95	1930	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
phungductung	0:e87aa4c49e95	1931	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
phungductung	0:e87aa4c49e95	1932	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
phungductung	0:e87aa4c49e95	1933	*/
phungductung	0:e87aa4c49e95	1934	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
phungductung	0:e87aa4c49e95	1935
phungductung	0:e87aa4c49e95	1936	/**
phungductung	0:e87aa4c49e95	1937	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
phungductung	0:e87aa4c49e95	1938	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1939	* @retval None
phungductung	0:e87aa4c49e95	1940	*/
phungductung	0:e87aa4c49e95	1941	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
phungductung	0:e87aa4c49e95	1942
phungductung	0:e87aa4c49e95	1943	/**
phungductung	0:e87aa4c49e95	1944	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
phungductung	0:e87aa4c49e95	1945	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1946	* @retval None
phungductung	0:e87aa4c49e95	1947	*/
phungductung	0:e87aa4c49e95	1948	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
phungductung	0:e87aa4c49e95	1949	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
phungductung	0:e87aa4c49e95	1950
phungductung	0:e87aa4c49e95	1951	/**
phungductung	0:e87aa4c49e95	1952	* @brief Enables the MMC Counter Freeze.
phungductung	0:e87aa4c49e95	1953	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1954	* @retval None
phungductung	0:e87aa4c49e95	1955	*/
phungductung	0:e87aa4c49e95	1956	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
phungductung	0:e87aa4c49e95	1957
phungductung	0:e87aa4c49e95	1958	/**
phungductung	0:e87aa4c49e95	1959	* @brief Disables the MMC Counter Freeze.
phungductung	0:e87aa4c49e95	1960	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1961	* @retval None
phungductung	0:e87aa4c49e95	1962	*/
phungductung	0:e87aa4c49e95	1963	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
phungductung	0:e87aa4c49e95	1964
phungductung	0:e87aa4c49e95	1965	/**
phungductung	0:e87aa4c49e95	1966	* @brief Enables the MMC Reset On Read.
phungductung	0:e87aa4c49e95	1967	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1968	* @retval None
phungductung	0:e87aa4c49e95	1969	*/
phungductung	0:e87aa4c49e95	1970	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
phungductung	0:e87aa4c49e95	1971
phungductung	0:e87aa4c49e95	1972	/**
phungductung	0:e87aa4c49e95	1973	* @brief Disables the MMC Reset On Read.
phungductung	0:e87aa4c49e95	1974	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1975	* @retval None
phungductung	0:e87aa4c49e95	1976	*/
phungductung	0:e87aa4c49e95	1977	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
phungductung	0:e87aa4c49e95	1978
phungductung	0:e87aa4c49e95	1979	/**
phungductung	0:e87aa4c49e95	1980	* @brief Enables the MMC Counter Stop Rollover.
phungductung	0:e87aa4c49e95	1981	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1982	* @retval None
phungductung	0:e87aa4c49e95	1983	*/
phungductung	0:e87aa4c49e95	1984	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
phungductung	0:e87aa4c49e95	1985
phungductung	0:e87aa4c49e95	1986	/**
phungductung	0:e87aa4c49e95	1987	* @brief Disables the MMC Counter Stop Rollover.
phungductung	0:e87aa4c49e95	1988	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1989	* @retval None
phungductung	0:e87aa4c49e95	1990	*/
phungductung	0:e87aa4c49e95	1991	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
phungductung	0:e87aa4c49e95	1992
phungductung	0:e87aa4c49e95	1993	/**
phungductung	0:e87aa4c49e95	1994	* @brief Resets the MMC Counters.
phungductung	0:e87aa4c49e95	1995	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	1996	* @retval None
phungductung	0:e87aa4c49e95	1997	*/
phungductung	0:e87aa4c49e95	1998	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
phungductung	0:e87aa4c49e95	1999
phungductung	0:e87aa4c49e95	2000	/**
phungductung	0:e87aa4c49e95	2001	* @brief Enables the specified ETHERNET MMC Rx interrupts.
phungductung	0:e87aa4c49e95	2002	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	2003	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
phungductung	0:e87aa4c49e95	2004	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2005	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2006	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2007	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2008	* @retval None
phungductung	0:e87aa4c49e95	2009	*/
phungductung	0:e87aa4c49e95	2010	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
phungductung	0:e87aa4c49e95	2011	/**
phungductung	0:e87aa4c49e95	2012	* @brief Disables the specified ETHERNET MMC Rx interrupts.
phungductung	0:e87aa4c49e95	2013	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	2014	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
phungductung	0:e87aa4c49e95	2015	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2016	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2017	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2018	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2019	* @retval None
phungductung	0:e87aa4c49e95	2020	*/
phungductung	0:e87aa4c49e95	2021	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
phungductung	0:e87aa4c49e95	2022	/**
phungductung	0:e87aa4c49e95	2023	* @brief Enables the specified ETHERNET MMC Tx interrupts.
phungductung	0:e87aa4c49e95	2024	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	2025	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
phungductung	0:e87aa4c49e95	2026	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2027	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2028	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2029	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2030	* @retval None
phungductung	0:e87aa4c49e95	2031	*/
phungductung	0:e87aa4c49e95	2032	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
phungductung	0:e87aa4c49e95	2033
phungductung	0:e87aa4c49e95	2034	/**
phungductung	0:e87aa4c49e95	2035	* @brief Disables the specified ETHERNET MMC Tx interrupts.
phungductung	0:e87aa4c49e95	2036	* @param __HANDLE__: ETH Handle.
phungductung	0:e87aa4c49e95	2037	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
phungductung	0:e87aa4c49e95	2038	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	2039	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2040	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2041	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
phungductung	0:e87aa4c49e95	2042	* @retval None
phungductung	0:e87aa4c49e95	2043	*/
phungductung	0:e87aa4c49e95	2044	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
phungductung	0:e87aa4c49e95	2045
phungductung	0:e87aa4c49e95	2046	/**
phungductung	0:e87aa4c49e95	2047	* @brief Enables the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2048	* @retval None
phungductung	0:e87aa4c49e95	2049	*/
phungductung	0:e87aa4c49e95	2050	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2051
phungductung	0:e87aa4c49e95	2052	/**
phungductung	0:e87aa4c49e95	2053	* @brief Disables the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2054	* @retval None
phungductung	0:e87aa4c49e95	2055	*/
phungductung	0:e87aa4c49e95	2056	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2057
phungductung	0:e87aa4c49e95	2058	/**
phungductung	0:e87aa4c49e95	2059	* @brief Enable event on ETH External event line.
phungductung	0:e87aa4c49e95	2060	* @retval None.
phungductung	0:e87aa4c49e95	2061	*/
phungductung	0:e87aa4c49e95	2062	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2063
phungductung	0:e87aa4c49e95	2064	/**
phungductung	0:e87aa4c49e95	2065	* @brief Disable event on ETH External event line
phungductung	0:e87aa4c49e95	2066	* @retval None.
phungductung	0:e87aa4c49e95	2067	*/
phungductung	0:e87aa4c49e95	2068	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2069
phungductung	0:e87aa4c49e95	2070	/**
phungductung	0:e87aa4c49e95	2071	* @brief Get flag of the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2072	* @retval None
phungductung	0:e87aa4c49e95	2073	*/
phungductung	0:e87aa4c49e95	2074	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2075
phungductung	0:e87aa4c49e95	2076	/**
phungductung	0:e87aa4c49e95	2077	* @brief Clear flag of the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2078	* @retval None
phungductung	0:e87aa4c49e95	2079	*/
phungductung	0:e87aa4c49e95	2080	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2081
phungductung	0:e87aa4c49e95	2082	/**
phungductung	0:e87aa4c49e95	2083	* @brief Enables rising edge trigger to the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2084	* @retval None
phungductung	0:e87aa4c49e95	2085	*/
phungductung	0:e87aa4c49e95	2086	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
phungductung	0:e87aa4c49e95	2087
phungductung	0:e87aa4c49e95	2088	/**
phungductung	0:e87aa4c49e95	2089	* @brief Disables the rising edge trigger to the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2090	* @retval None
phungductung	0:e87aa4c49e95	2091	*/
phungductung	0:e87aa4c49e95	2092	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2093
phungductung	0:e87aa4c49e95	2094	/**
phungductung	0:e87aa4c49e95	2095	* @brief Enables falling edge trigger to the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2096	* @retval None
phungductung	0:e87aa4c49e95	2097	*/
phungductung	0:e87aa4c49e95	2098	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2099
phungductung	0:e87aa4c49e95	2100	/**
phungductung	0:e87aa4c49e95	2101	* @brief Disables falling edge trigger to the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2102	* @retval None
phungductung	0:e87aa4c49e95	2103	*/
phungductung	0:e87aa4c49e95	2104	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2105
phungductung	0:e87aa4c49e95	2106	/**
phungductung	0:e87aa4c49e95	2107	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2108	* @retval None
phungductung	0:e87aa4c49e95	2109	*/
phungductung	0:e87aa4c49e95	2110	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
phungductung	0:e87aa4c49e95	2111	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
phungductung	0:e87aa4c49e95	2112
phungductung	0:e87aa4c49e95	2113	/**
phungductung	0:e87aa4c49e95	2114	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
phungductung	0:e87aa4c49e95	2115	* @retval None
phungductung	0:e87aa4c49e95	2116	*/
phungductung	0:e87aa4c49e95	2117	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
phungductung	0:e87aa4c49e95	2118	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
phungductung	0:e87aa4c49e95	2119
phungductung	0:e87aa4c49e95	2120	/**
phungductung	0:e87aa4c49e95	2121	* @brief Generate a Software interrupt on selected EXTI line.
phungductung	0:e87aa4c49e95	2122	* @retval None.
phungductung	0:e87aa4c49e95	2123	*/
phungductung	0:e87aa4c49e95	2124	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
phungductung	0:e87aa4c49e95	2125
phungductung	0:e87aa4c49e95	2126	/**
phungductung	0:e87aa4c49e95	2127	* @}
phungductung	0:e87aa4c49e95	2128	*/
phungductung	0:e87aa4c49e95	2129	/* Exported functions --------------------------------------------------------*/
phungductung	0:e87aa4c49e95	2130
phungductung	0:e87aa4c49e95	2131	/** @addtogroup ETH_Exported_Functions
phungductung	0:e87aa4c49e95	2132	* @{
phungductung	0:e87aa4c49e95	2133	*/
phungductung	0:e87aa4c49e95	2134
phungductung	0:e87aa4c49e95	2135	/* Initialization and de-initialization functions ****************************/
phungductung	0:e87aa4c49e95	2136
phungductung	0:e87aa4c49e95	2137	/** @addtogroup ETH_Exported_Functions_Group1
phungductung	0:e87aa4c49e95	2138	* @{
phungductung	0:e87aa4c49e95	2139	*/
phungductung	0:e87aa4c49e95	2140	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2141	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2142	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2143	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2144	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
phungductung	0:e87aa4c49e95	2145	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
phungductung	0:e87aa4c49e95	2146
phungductung	0:e87aa4c49e95	2147	/**
phungductung	0:e87aa4c49e95	2148	* @}
phungductung	0:e87aa4c49e95	2149	*/
phungductung	0:e87aa4c49e95	2150	/* IO operation functions ****************************************************/
phungductung	0:e87aa4c49e95	2151
phungductung	0:e87aa4c49e95	2152	/** @addtogroup ETH_Exported_Functions_Group2
phungductung	0:e87aa4c49e95	2153	* @{
phungductung	0:e87aa4c49e95	2154	*/
phungductung	0:e87aa4c49e95	2155	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
phungductung	0:e87aa4c49e95	2156	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2157	/* Communication with PHY functions*/
phungductung	0:e87aa4c49e95	2158	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
phungductung	0:e87aa4c49e95	2159	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
phungductung	0:e87aa4c49e95	2160	/* Non-Blocking mode: Interrupt */
phungductung	0:e87aa4c49e95	2161	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2162	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2163	/* Callback in non blocking modes (Interrupt) */
phungductung	0:e87aa4c49e95	2164	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2165	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2166	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2167	/**
phungductung	0:e87aa4c49e95	2168	* @}
phungductung	0:e87aa4c49e95	2169	*/
phungductung	0:e87aa4c49e95	2170
phungductung	0:e87aa4c49e95	2171	/* Peripheral Control functions **********************************************/
phungductung	0:e87aa4c49e95	2172
phungductung	0:e87aa4c49e95	2173	/** @addtogroup ETH_Exported_Functions_Group3
phungductung	0:e87aa4c49e95	2174	* @{
phungductung	0:e87aa4c49e95	2175	*/
phungductung	0:e87aa4c49e95	2176
phungductung	0:e87aa4c49e95	2177	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2178	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2179	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
phungductung	0:e87aa4c49e95	2180	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
phungductung	0:e87aa4c49e95	2181	/**
phungductung	0:e87aa4c49e95	2182	* @}
phungductung	0:e87aa4c49e95	2183	*/
phungductung	0:e87aa4c49e95	2184
phungductung	0:e87aa4c49e95	2185	/* Peripheral State functions ************************************************/
phungductung	0:e87aa4c49e95	2186
phungductung	0:e87aa4c49e95	2187	/** @addtogroup ETH_Exported_Functions_Group4
phungductung	0:e87aa4c49e95	2188	* @{
phungductung	0:e87aa4c49e95	2189	*/
phungductung	0:e87aa4c49e95	2190	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
phungductung	0:e87aa4c49e95	2191	/**
phungductung	0:e87aa4c49e95	2192	* @}
phungductung	0:e87aa4c49e95	2193	*/
phungductung	0:e87aa4c49e95	2194
phungductung	0:e87aa4c49e95	2195	/**
phungductung	0:e87aa4c49e95	2196	* @}
phungductung	0:e87aa4c49e95	2197	*/
phungductung	0:e87aa4c49e95	2198
phungductung	0:e87aa4c49e95	2199	/**
phungductung	0:e87aa4c49e95	2200	* @}
phungductung	0:e87aa4c49e95	2201	*/
phungductung	0:e87aa4c49e95	2202
phungductung	0:e87aa4c49e95	2203	/**
phungductung	0:e87aa4c49e95	2204	* @}
phungductung	0:e87aa4c49e95	2205	*/
phungductung	0:e87aa4c49e95	2206	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	2207	}
phungductung	0:e87aa4c49e95	2208	#endif
phungductung	0:e87aa4c49e95	2209
phungductung	0:e87aa4c49e95	2210	#endif /* __STM32F7xx_HAL_ETH_H */
phungductung	0:e87aa4c49e95	2211
phungductung	0:e87aa4c49e95	2212
phungductung	0:e87aa4c49e95	2213
phungductung	0:e87aa4c49e95	2214	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Jun 2019
Imports:	8
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h@0:e87aa4c49e95, 2019-06-04 (annotated)

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