PHung Tung
SPKT
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h@0:e87aa4c49e95, 2019-06-04 (annotated)
- Committer:
- phungductung
- Date:
- Tue Jun 04 21:51:46 2019 +0000
- Revision:
- 0:e87aa4c49e95
libray
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| phungductung | 0:e87aa4c49e95 | 1 | /** |
| phungductung | 0:e87aa4c49e95 | 2 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 3 | * @file stm32f7xx_hal_dma.h |
| phungductung | 0:e87aa4c49e95 | 4 | * @author MCD Application Team |
| phungductung | 0:e87aa4c49e95 | 5 | * @version V1.0.4 |
| phungductung | 0:e87aa4c49e95 | 6 | * @date 09-December-2015 |
| phungductung | 0:e87aa4c49e95 | 7 | * @brief Header file of DMA HAL module. |
| phungductung | 0:e87aa4c49e95 | 8 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 9 | * @attention |
| phungductung | 0:e87aa4c49e95 | 10 | * |
| phungductung | 0:e87aa4c49e95 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| phungductung | 0:e87aa4c49e95 | 12 | * |
| phungductung | 0:e87aa4c49e95 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| phungductung | 0:e87aa4c49e95 | 14 | * are permitted provided that the following conditions are met: |
| phungductung | 0:e87aa4c49e95 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| phungductung | 0:e87aa4c49e95 | 16 | * this list of conditions and the following disclaimer. |
| phungductung | 0:e87aa4c49e95 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| phungductung | 0:e87aa4c49e95 | 18 | * this list of conditions and the following disclaimer in the documentation |
| phungductung | 0:e87aa4c49e95 | 19 | * and/or other materials provided with the distribution. |
| phungductung | 0:e87aa4c49e95 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| phungductung | 0:e87aa4c49e95 | 21 | * may be used to endorse or promote products derived from this software |
| phungductung | 0:e87aa4c49e95 | 22 | * without specific prior written permission. |
| phungductung | 0:e87aa4c49e95 | 23 | * |
| phungductung | 0:e87aa4c49e95 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| phungductung | 0:e87aa4c49e95 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| phungductung | 0:e87aa4c49e95 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| phungductung | 0:e87aa4c49e95 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| phungductung | 0:e87aa4c49e95 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| phungductung | 0:e87aa4c49e95 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| phungductung | 0:e87aa4c49e95 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| phungductung | 0:e87aa4c49e95 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| phungductung | 0:e87aa4c49e95 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| phungductung | 0:e87aa4c49e95 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| phungductung | 0:e87aa4c49e95 | 34 | * |
| phungductung | 0:e87aa4c49e95 | 35 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 36 | */ |
| phungductung | 0:e87aa4c49e95 | 37 | |
| phungductung | 0:e87aa4c49e95 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 39 | #ifndef __STM32F7xx_HAL_DMA_H |
| phungductung | 0:e87aa4c49e95 | 40 | #define __STM32F7xx_HAL_DMA_H |
| phungductung | 0:e87aa4c49e95 | 41 | |
| phungductung | 0:e87aa4c49e95 | 42 | #ifdef __cplusplus |
| phungductung | 0:e87aa4c49e95 | 43 | extern "C" { |
| phungductung | 0:e87aa4c49e95 | 44 | #endif |
| phungductung | 0:e87aa4c49e95 | 45 | |
| phungductung | 0:e87aa4c49e95 | 46 | /* Includes ------------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 47 | #include "stm32f7xx_hal_def.h" |
| phungductung | 0:e87aa4c49e95 | 48 | |
| phungductung | 0:e87aa4c49e95 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| phungductung | 0:e87aa4c49e95 | 50 | * @{ |
| phungductung | 0:e87aa4c49e95 | 51 | */ |
| phungductung | 0:e87aa4c49e95 | 52 | |
| phungductung | 0:e87aa4c49e95 | 53 | /** @addtogroup DMA |
| phungductung | 0:e87aa4c49e95 | 54 | * @{ |
| phungductung | 0:e87aa4c49e95 | 55 | */ |
| phungductung | 0:e87aa4c49e95 | 56 | |
| phungductung | 0:e87aa4c49e95 | 57 | /* Exported types ------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 58 | |
| phungductung | 0:e87aa4c49e95 | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| phungductung | 0:e87aa4c49e95 | 60 | * @brief DMA Exported Types |
| phungductung | 0:e87aa4c49e95 | 61 | * @{ |
| phungductung | 0:e87aa4c49e95 | 62 | */ |
| phungductung | 0:e87aa4c49e95 | 63 | |
| phungductung | 0:e87aa4c49e95 | 64 | /** |
| phungductung | 0:e87aa4c49e95 | 65 | * @brief DMA Configuration Structure definition |
| phungductung | 0:e87aa4c49e95 | 66 | */ |
| phungductung | 0:e87aa4c49e95 | 67 | typedef struct |
| phungductung | 0:e87aa4c49e95 | 68 | { |
| phungductung | 0:e87aa4c49e95 | 69 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
| phungductung | 0:e87aa4c49e95 | 70 | This parameter can be a value of @ref DMA_Channel_selection */ |
| phungductung | 0:e87aa4c49e95 | 71 | |
| phungductung | 0:e87aa4c49e95 | 72 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| phungductung | 0:e87aa4c49e95 | 73 | from memory to memory or from peripheral to memory. |
| phungductung | 0:e87aa4c49e95 | 74 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| phungductung | 0:e87aa4c49e95 | 75 | |
| phungductung | 0:e87aa4c49e95 | 76 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| phungductung | 0:e87aa4c49e95 | 77 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| phungductung | 0:e87aa4c49e95 | 78 | |
| phungductung | 0:e87aa4c49e95 | 79 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| phungductung | 0:e87aa4c49e95 | 80 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| phungductung | 0:e87aa4c49e95 | 81 | |
| phungductung | 0:e87aa4c49e95 | 82 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| phungductung | 0:e87aa4c49e95 | 83 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| phungductung | 0:e87aa4c49e95 | 84 | |
| phungductung | 0:e87aa4c49e95 | 85 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| phungductung | 0:e87aa4c49e95 | 86 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| phungductung | 0:e87aa4c49e95 | 87 | |
| phungductung | 0:e87aa4c49e95 | 88 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| phungductung | 0:e87aa4c49e95 | 89 | This parameter can be a value of @ref DMA_mode |
| phungductung | 0:e87aa4c49e95 | 90 | @note The circular buffer mode cannot be used if the memory-to-memory |
| phungductung | 0:e87aa4c49e95 | 91 | data transfer is configured on the selected Stream */ |
| phungductung | 0:e87aa4c49e95 | 92 | |
| phungductung | 0:e87aa4c49e95 | 93 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| phungductung | 0:e87aa4c49e95 | 94 | This parameter can be a value of @ref DMA_Priority_level */ |
| phungductung | 0:e87aa4c49e95 | 95 | |
| phungductung | 0:e87aa4c49e95 | 96 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
| phungductung | 0:e87aa4c49e95 | 97 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
| phungductung | 0:e87aa4c49e95 | 98 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| phungductung | 0:e87aa4c49e95 | 99 | memory-to-memory data transfer is configured on the selected stream */ |
| phungductung | 0:e87aa4c49e95 | 100 | |
| phungductung | 0:e87aa4c49e95 | 101 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| phungductung | 0:e87aa4c49e95 | 102 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
| phungductung | 0:e87aa4c49e95 | 103 | |
| phungductung | 0:e87aa4c49e95 | 104 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| phungductung | 0:e87aa4c49e95 | 105 | It specifies the amount of data to be transferred in a single non interruptible |
| phungductung | 0:e87aa4c49e95 | 106 | transaction. |
| phungductung | 0:e87aa4c49e95 | 107 | This parameter can be a value of @ref DMA_Memory_burst |
| phungductung | 0:e87aa4c49e95 | 108 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| phungductung | 0:e87aa4c49e95 | 109 | |
| phungductung | 0:e87aa4c49e95 | 110 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| phungductung | 0:e87aa4c49e95 | 111 | It specifies the amount of data to be transferred in a single non interruptible |
| phungductung | 0:e87aa4c49e95 | 112 | transaction. |
| phungductung | 0:e87aa4c49e95 | 113 | This parameter can be a value of @ref DMA_Peripheral_burst |
| phungductung | 0:e87aa4c49e95 | 114 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| phungductung | 0:e87aa4c49e95 | 115 | }DMA_InitTypeDef; |
| phungductung | 0:e87aa4c49e95 | 116 | |
| phungductung | 0:e87aa4c49e95 | 117 | /** |
| phungductung | 0:e87aa4c49e95 | 118 | * @brief HAL DMA State structures definition |
| phungductung | 0:e87aa4c49e95 | 119 | */ |
| phungductung | 0:e87aa4c49e95 | 120 | typedef enum |
| phungductung | 0:e87aa4c49e95 | 121 | { |
| phungductung | 0:e87aa4c49e95 | 122 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| phungductung | 0:e87aa4c49e95 | 123 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
| phungductung | 0:e87aa4c49e95 | 124 | HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ |
| phungductung | 0:e87aa4c49e95 | 125 | HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ |
| phungductung | 0:e87aa4c49e95 | 126 | HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ |
| phungductung | 0:e87aa4c49e95 | 127 | HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ |
| phungductung | 0:e87aa4c49e95 | 128 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| phungductung | 0:e87aa4c49e95 | 129 | HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ |
| phungductung | 0:e87aa4c49e95 | 130 | HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ |
| phungductung | 0:e87aa4c49e95 | 131 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| phungductung | 0:e87aa4c49e95 | 132 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| phungductung | 0:e87aa4c49e95 | 133 | }HAL_DMA_StateTypeDef; |
| phungductung | 0:e87aa4c49e95 | 134 | |
| phungductung | 0:e87aa4c49e95 | 135 | /** |
| phungductung | 0:e87aa4c49e95 | 136 | * @brief HAL DMA Error Code structure definition |
| phungductung | 0:e87aa4c49e95 | 137 | */ |
| phungductung | 0:e87aa4c49e95 | 138 | typedef enum |
| phungductung | 0:e87aa4c49e95 | 139 | { |
| phungductung | 0:e87aa4c49e95 | 140 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| phungductung | 0:e87aa4c49e95 | 141 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| phungductung | 0:e87aa4c49e95 | 142 | }HAL_DMA_LevelCompleteTypeDef; |
| phungductung | 0:e87aa4c49e95 | 143 | |
| phungductung | 0:e87aa4c49e95 | 144 | /** |
| phungductung | 0:e87aa4c49e95 | 145 | * @brief DMA handle Structure definition |
| phungductung | 0:e87aa4c49e95 | 146 | */ |
| phungductung | 0:e87aa4c49e95 | 147 | typedef struct __DMA_HandleTypeDef |
| phungductung | 0:e87aa4c49e95 | 148 | { |
| phungductung | 0:e87aa4c49e95 | 149 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
| phungductung | 0:e87aa4c49e95 | 150 | |
| phungductung | 0:e87aa4c49e95 | 151 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| phungductung | 0:e87aa4c49e95 | 152 | |
| phungductung | 0:e87aa4c49e95 | 153 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| phungductung | 0:e87aa4c49e95 | 154 | |
| phungductung | 0:e87aa4c49e95 | 155 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| phungductung | 0:e87aa4c49e95 | 156 | |
| phungductung | 0:e87aa4c49e95 | 157 | void *Parent; /*!< Parent object state */ |
| phungductung | 0:e87aa4c49e95 | 158 | |
| phungductung | 0:e87aa4c49e95 | 159 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| phungductung | 0:e87aa4c49e95 | 160 | |
| phungductung | 0:e87aa4c49e95 | 161 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| phungductung | 0:e87aa4c49e95 | 162 | |
| phungductung | 0:e87aa4c49e95 | 163 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
| phungductung | 0:e87aa4c49e95 | 164 | |
| phungductung | 0:e87aa4c49e95 | 165 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| phungductung | 0:e87aa4c49e95 | 166 | |
| phungductung | 0:e87aa4c49e95 | 167 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| phungductung | 0:e87aa4c49e95 | 168 | |
| phungductung | 0:e87aa4c49e95 | 169 | uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ |
| phungductung | 0:e87aa4c49e95 | 170 | |
| phungductung | 0:e87aa4c49e95 | 171 | uint32_t StreamIndex; /*!< DMA Stream Index */ |
| phungductung | 0:e87aa4c49e95 | 172 | |
| phungductung | 0:e87aa4c49e95 | 173 | }DMA_HandleTypeDef; |
| phungductung | 0:e87aa4c49e95 | 174 | |
| phungductung | 0:e87aa4c49e95 | 175 | /** |
| phungductung | 0:e87aa4c49e95 | 176 | * @} |
| phungductung | 0:e87aa4c49e95 | 177 | */ |
| phungductung | 0:e87aa4c49e95 | 178 | |
| phungductung | 0:e87aa4c49e95 | 179 | |
| phungductung | 0:e87aa4c49e95 | 180 | /* Exported constants --------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 181 | |
| phungductung | 0:e87aa4c49e95 | 182 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| phungductung | 0:e87aa4c49e95 | 183 | * @brief DMA Exported constants |
| phungductung | 0:e87aa4c49e95 | 184 | * @{ |
| phungductung | 0:e87aa4c49e95 | 185 | */ |
| phungductung | 0:e87aa4c49e95 | 186 | |
| phungductung | 0:e87aa4c49e95 | 187 | /** @defgroup DMA_Error_Code DMA Error Code |
| phungductung | 0:e87aa4c49e95 | 188 | * @brief DMA Error Code |
| phungductung | 0:e87aa4c49e95 | 189 | * @{ |
| phungductung | 0:e87aa4c49e95 | 190 | */ |
| phungductung | 0:e87aa4c49e95 | 191 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| phungductung | 0:e87aa4c49e95 | 192 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| phungductung | 0:e87aa4c49e95 | 193 | #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ |
| phungductung | 0:e87aa4c49e95 | 194 | #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ |
| phungductung | 0:e87aa4c49e95 | 195 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| phungductung | 0:e87aa4c49e95 | 196 | /** |
| phungductung | 0:e87aa4c49e95 | 197 | * @} |
| phungductung | 0:e87aa4c49e95 | 198 | */ |
| phungductung | 0:e87aa4c49e95 | 199 | |
| phungductung | 0:e87aa4c49e95 | 200 | /** @defgroup DMA_Channel_selection DMA Channel selection |
| phungductung | 0:e87aa4c49e95 | 201 | * @brief DMA channel selection |
| phungductung | 0:e87aa4c49e95 | 202 | * @{ |
| phungductung | 0:e87aa4c49e95 | 203 | */ |
| phungductung | 0:e87aa4c49e95 | 204 | #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ |
| phungductung | 0:e87aa4c49e95 | 205 | #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ |
| phungductung | 0:e87aa4c49e95 | 206 | #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ |
| phungductung | 0:e87aa4c49e95 | 207 | #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ |
| phungductung | 0:e87aa4c49e95 | 208 | #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ |
| phungductung | 0:e87aa4c49e95 | 209 | #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ |
| phungductung | 0:e87aa4c49e95 | 210 | #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ |
| phungductung | 0:e87aa4c49e95 | 211 | #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ |
| phungductung | 0:e87aa4c49e95 | 212 | /** |
| phungductung | 0:e87aa4c49e95 | 213 | * @} |
| phungductung | 0:e87aa4c49e95 | 214 | */ |
| phungductung | 0:e87aa4c49e95 | 215 | |
| phungductung | 0:e87aa4c49e95 | 216 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| phungductung | 0:e87aa4c49e95 | 217 | * @brief DMA data transfer direction |
| phungductung | 0:e87aa4c49e95 | 218 | * @{ |
| phungductung | 0:e87aa4c49e95 | 219 | */ |
| phungductung | 0:e87aa4c49e95 | 220 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| phungductung | 0:e87aa4c49e95 | 221 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
| phungductung | 0:e87aa4c49e95 | 222 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
| phungductung | 0:e87aa4c49e95 | 223 | /** |
| phungductung | 0:e87aa4c49e95 | 224 | * @} |
| phungductung | 0:e87aa4c49e95 | 225 | */ |
| phungductung | 0:e87aa4c49e95 | 226 | |
| phungductung | 0:e87aa4c49e95 | 227 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| phungductung | 0:e87aa4c49e95 | 228 | * @brief DMA peripheral incremented mode |
| phungductung | 0:e87aa4c49e95 | 229 | * @{ |
| phungductung | 0:e87aa4c49e95 | 230 | */ |
| phungductung | 0:e87aa4c49e95 | 231 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
| phungductung | 0:e87aa4c49e95 | 232 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ |
| phungductung | 0:e87aa4c49e95 | 233 | /** |
| phungductung | 0:e87aa4c49e95 | 234 | * @} |
| phungductung | 0:e87aa4c49e95 | 235 | */ |
| phungductung | 0:e87aa4c49e95 | 236 | |
| phungductung | 0:e87aa4c49e95 | 237 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| phungductung | 0:e87aa4c49e95 | 238 | * @brief DMA memory incremented mode |
| phungductung | 0:e87aa4c49e95 | 239 | * @{ |
| phungductung | 0:e87aa4c49e95 | 240 | */ |
| phungductung | 0:e87aa4c49e95 | 241 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
| phungductung | 0:e87aa4c49e95 | 242 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ |
| phungductung | 0:e87aa4c49e95 | 243 | /** |
| phungductung | 0:e87aa4c49e95 | 244 | * @} |
| phungductung | 0:e87aa4c49e95 | 245 | */ |
| phungductung | 0:e87aa4c49e95 | 246 | |
| phungductung | 0:e87aa4c49e95 | 247 | |
| phungductung | 0:e87aa4c49e95 | 248 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| phungductung | 0:e87aa4c49e95 | 249 | * @brief DMA peripheral data size |
| phungductung | 0:e87aa4c49e95 | 250 | * @{ |
| phungductung | 0:e87aa4c49e95 | 251 | */ |
| phungductung | 0:e87aa4c49e95 | 252 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ |
| phungductung | 0:e87aa4c49e95 | 253 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| phungductung | 0:e87aa4c49e95 | 254 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| phungductung | 0:e87aa4c49e95 | 255 | /** |
| phungductung | 0:e87aa4c49e95 | 256 | * @} |
| phungductung | 0:e87aa4c49e95 | 257 | */ |
| phungductung | 0:e87aa4c49e95 | 258 | |
| phungductung | 0:e87aa4c49e95 | 259 | |
| phungductung | 0:e87aa4c49e95 | 260 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| phungductung | 0:e87aa4c49e95 | 261 | * @brief DMA memory data size |
| phungductung | 0:e87aa4c49e95 | 262 | * @{ |
| phungductung | 0:e87aa4c49e95 | 263 | */ |
| phungductung | 0:e87aa4c49e95 | 264 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ |
| phungductung | 0:e87aa4c49e95 | 265 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| phungductung | 0:e87aa4c49e95 | 266 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| phungductung | 0:e87aa4c49e95 | 267 | /** |
| phungductung | 0:e87aa4c49e95 | 268 | * @} |
| phungductung | 0:e87aa4c49e95 | 269 | */ |
| phungductung | 0:e87aa4c49e95 | 270 | |
| phungductung | 0:e87aa4c49e95 | 271 | /** @defgroup DMA_mode DMA mode |
| phungductung | 0:e87aa4c49e95 | 272 | * @brief DMA mode |
| phungductung | 0:e87aa4c49e95 | 273 | * @{ |
| phungductung | 0:e87aa4c49e95 | 274 | */ |
| phungductung | 0:e87aa4c49e95 | 275 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
| phungductung | 0:e87aa4c49e95 | 276 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
| phungductung | 0:e87aa4c49e95 | 277 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
| phungductung | 0:e87aa4c49e95 | 278 | /** |
| phungductung | 0:e87aa4c49e95 | 279 | * @} |
| phungductung | 0:e87aa4c49e95 | 280 | */ |
| phungductung | 0:e87aa4c49e95 | 281 | |
| phungductung | 0:e87aa4c49e95 | 282 | |
| phungductung | 0:e87aa4c49e95 | 283 | /** @defgroup DMA_Priority_level DMA Priority level |
| phungductung | 0:e87aa4c49e95 | 284 | * @brief DMA priority levels |
| phungductung | 0:e87aa4c49e95 | 285 | * @{ |
| phungductung | 0:e87aa4c49e95 | 286 | */ |
| phungductung | 0:e87aa4c49e95 | 287 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ |
| phungductung | 0:e87aa4c49e95 | 288 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
| phungductung | 0:e87aa4c49e95 | 289 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
| phungductung | 0:e87aa4c49e95 | 290 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
| phungductung | 0:e87aa4c49e95 | 291 | /** |
| phungductung | 0:e87aa4c49e95 | 292 | * @} |
| phungductung | 0:e87aa4c49e95 | 293 | */ |
| phungductung | 0:e87aa4c49e95 | 294 | |
| phungductung | 0:e87aa4c49e95 | 295 | |
| phungductung | 0:e87aa4c49e95 | 296 | /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode |
| phungductung | 0:e87aa4c49e95 | 297 | * @brief DMA FIFO direct mode |
| phungductung | 0:e87aa4c49e95 | 298 | * @{ |
| phungductung | 0:e87aa4c49e95 | 299 | */ |
| phungductung | 0:e87aa4c49e95 | 300 | #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ |
| phungductung | 0:e87aa4c49e95 | 301 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
| phungductung | 0:e87aa4c49e95 | 302 | /** |
| phungductung | 0:e87aa4c49e95 | 303 | * @} |
| phungductung | 0:e87aa4c49e95 | 304 | */ |
| phungductung | 0:e87aa4c49e95 | 305 | |
| phungductung | 0:e87aa4c49e95 | 306 | /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level |
| phungductung | 0:e87aa4c49e95 | 307 | * @brief DMA FIFO level |
| phungductung | 0:e87aa4c49e95 | 308 | * @{ |
| phungductung | 0:e87aa4c49e95 | 309 | */ |
| phungductung | 0:e87aa4c49e95 | 310 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ |
| phungductung | 0:e87aa4c49e95 | 311 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
| phungductung | 0:e87aa4c49e95 | 312 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
| phungductung | 0:e87aa4c49e95 | 313 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
| phungductung | 0:e87aa4c49e95 | 314 | /** |
| phungductung | 0:e87aa4c49e95 | 315 | * @} |
| phungductung | 0:e87aa4c49e95 | 316 | */ |
| phungductung | 0:e87aa4c49e95 | 317 | |
| phungductung | 0:e87aa4c49e95 | 318 | /** @defgroup DMA_Memory_burst DMA Memory burst |
| phungductung | 0:e87aa4c49e95 | 319 | * @brief DMA memory burst |
| phungductung | 0:e87aa4c49e95 | 320 | * @{ |
| phungductung | 0:e87aa4c49e95 | 321 | */ |
| phungductung | 0:e87aa4c49e95 | 322 | #define DMA_MBURST_SINGLE ((uint32_t)0x00000000) |
| phungductung | 0:e87aa4c49e95 | 323 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
| phungductung | 0:e87aa4c49e95 | 324 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
| phungductung | 0:e87aa4c49e95 | 325 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
| phungductung | 0:e87aa4c49e95 | 326 | /** |
| phungductung | 0:e87aa4c49e95 | 327 | * @} |
| phungductung | 0:e87aa4c49e95 | 328 | */ |
| phungductung | 0:e87aa4c49e95 | 329 | |
| phungductung | 0:e87aa4c49e95 | 330 | |
| phungductung | 0:e87aa4c49e95 | 331 | /** @defgroup DMA_Peripheral_burst DMA Peripheral burst |
| phungductung | 0:e87aa4c49e95 | 332 | * @brief DMA peripheral burst |
| phungductung | 0:e87aa4c49e95 | 333 | * @{ |
| phungductung | 0:e87aa4c49e95 | 334 | */ |
| phungductung | 0:e87aa4c49e95 | 335 | #define DMA_PBURST_SINGLE ((uint32_t)0x00000000) |
| phungductung | 0:e87aa4c49e95 | 336 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
| phungductung | 0:e87aa4c49e95 | 337 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
| phungductung | 0:e87aa4c49e95 | 338 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
| phungductung | 0:e87aa4c49e95 | 339 | /** |
| phungductung | 0:e87aa4c49e95 | 340 | * @} |
| phungductung | 0:e87aa4c49e95 | 341 | */ |
| phungductung | 0:e87aa4c49e95 | 342 | |
| phungductung | 0:e87aa4c49e95 | 343 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| phungductung | 0:e87aa4c49e95 | 344 | * @brief DMA interrupts definition |
| phungductung | 0:e87aa4c49e95 | 345 | * @{ |
| phungductung | 0:e87aa4c49e95 | 346 | */ |
| phungductung | 0:e87aa4c49e95 | 347 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
| phungductung | 0:e87aa4c49e95 | 348 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
| phungductung | 0:e87aa4c49e95 | 349 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
| phungductung | 0:e87aa4c49e95 | 350 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
| phungductung | 0:e87aa4c49e95 | 351 | #define DMA_IT_FE ((uint32_t)0x00000080) |
| phungductung | 0:e87aa4c49e95 | 352 | /** |
| phungductung | 0:e87aa4c49e95 | 353 | * @} |
| phungductung | 0:e87aa4c49e95 | 354 | */ |
| phungductung | 0:e87aa4c49e95 | 355 | |
| phungductung | 0:e87aa4c49e95 | 356 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| phungductung | 0:e87aa4c49e95 | 357 | * @brief DMA flag definitions |
| phungductung | 0:e87aa4c49e95 | 358 | * @{ |
| phungductung | 0:e87aa4c49e95 | 359 | */ |
| phungductung | 0:e87aa4c49e95 | 360 | #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) |
| phungductung | 0:e87aa4c49e95 | 361 | #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) |
| phungductung | 0:e87aa4c49e95 | 362 | #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) |
| phungductung | 0:e87aa4c49e95 | 363 | #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) |
| phungductung | 0:e87aa4c49e95 | 364 | #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) |
| phungductung | 0:e87aa4c49e95 | 365 | #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) |
| phungductung | 0:e87aa4c49e95 | 366 | #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) |
| phungductung | 0:e87aa4c49e95 | 367 | #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) |
| phungductung | 0:e87aa4c49e95 | 368 | #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) |
| phungductung | 0:e87aa4c49e95 | 369 | #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) |
| phungductung | 0:e87aa4c49e95 | 370 | #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) |
| phungductung | 0:e87aa4c49e95 | 371 | #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) |
| phungductung | 0:e87aa4c49e95 | 372 | #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) |
| phungductung | 0:e87aa4c49e95 | 373 | #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) |
| phungductung | 0:e87aa4c49e95 | 374 | #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) |
| phungductung | 0:e87aa4c49e95 | 375 | #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) |
| phungductung | 0:e87aa4c49e95 | 376 | #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) |
| phungductung | 0:e87aa4c49e95 | 377 | #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) |
| phungductung | 0:e87aa4c49e95 | 378 | #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) |
| phungductung | 0:e87aa4c49e95 | 379 | #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) |
| phungductung | 0:e87aa4c49e95 | 380 | /** |
| phungductung | 0:e87aa4c49e95 | 381 | * @} |
| phungductung | 0:e87aa4c49e95 | 382 | */ |
| phungductung | 0:e87aa4c49e95 | 383 | |
| phungductung | 0:e87aa4c49e95 | 384 | /** |
| phungductung | 0:e87aa4c49e95 | 385 | * @} |
| phungductung | 0:e87aa4c49e95 | 386 | */ |
| phungductung | 0:e87aa4c49e95 | 387 | |
| phungductung | 0:e87aa4c49e95 | 388 | /* Exported macro ------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 389 | |
| phungductung | 0:e87aa4c49e95 | 390 | /** @brief Reset DMA handle state |
| phungductung | 0:e87aa4c49e95 | 391 | * @param __HANDLE__: specifies the DMA handle. |
| phungductung | 0:e87aa4c49e95 | 392 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 393 | */ |
| phungductung | 0:e87aa4c49e95 | 394 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| phungductung | 0:e87aa4c49e95 | 395 | |
| phungductung | 0:e87aa4c49e95 | 396 | /** |
| phungductung | 0:e87aa4c49e95 | 397 | * @brief Return the current DMA Stream FIFO filled level. |
| phungductung | 0:e87aa4c49e95 | 398 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 399 | * @retval The FIFO filling state. |
| phungductung | 0:e87aa4c49e95 | 400 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
| phungductung | 0:e87aa4c49e95 | 401 | * and not empty. |
| phungductung | 0:e87aa4c49e95 | 402 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
| phungductung | 0:e87aa4c49e95 | 403 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
| phungductung | 0:e87aa4c49e95 | 404 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
| phungductung | 0:e87aa4c49e95 | 405 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
| phungductung | 0:e87aa4c49e95 | 406 | * - DMA_FIFOStatus_Full: when FIFO is full |
| phungductung | 0:e87aa4c49e95 | 407 | */ |
| phungductung | 0:e87aa4c49e95 | 408 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
| phungductung | 0:e87aa4c49e95 | 409 | |
| phungductung | 0:e87aa4c49e95 | 410 | /** |
| phungductung | 0:e87aa4c49e95 | 411 | * @brief Enable the specified DMA Stream. |
| phungductung | 0:e87aa4c49e95 | 412 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 413 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 414 | */ |
| phungductung | 0:e87aa4c49e95 | 415 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
| phungductung | 0:e87aa4c49e95 | 416 | |
| phungductung | 0:e87aa4c49e95 | 417 | /** |
| phungductung | 0:e87aa4c49e95 | 418 | * @brief Disable the specified DMA Stream. |
| phungductung | 0:e87aa4c49e95 | 419 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 420 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 421 | */ |
| phungductung | 0:e87aa4c49e95 | 422 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
| phungductung | 0:e87aa4c49e95 | 423 | |
| phungductung | 0:e87aa4c49e95 | 424 | /* Interrupt & Flag management */ |
| phungductung | 0:e87aa4c49e95 | 425 | |
| phungductung | 0:e87aa4c49e95 | 426 | /** |
| phungductung | 0:e87aa4c49e95 | 427 | * @brief Return the current DMA Stream transfer complete flag. |
| phungductung | 0:e87aa4c49e95 | 428 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 429 | * @retval The specified transfer complete flag index. |
| phungductung | 0:e87aa4c49e95 | 430 | */ |
| phungductung | 0:e87aa4c49e95 | 431 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| phungductung | 0:e87aa4c49e95 | 432 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 433 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 434 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 435 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 436 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 437 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 438 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 439 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 440 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 441 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 442 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 443 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 444 | DMA_FLAG_TCIF3_7) |
| phungductung | 0:e87aa4c49e95 | 445 | |
| phungductung | 0:e87aa4c49e95 | 446 | /** |
| phungductung | 0:e87aa4c49e95 | 447 | * @brief Return the current DMA Stream half transfer complete flag. |
| phungductung | 0:e87aa4c49e95 | 448 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 449 | * @retval The specified half transfer complete flag index. |
| phungductung | 0:e87aa4c49e95 | 450 | */ |
| phungductung | 0:e87aa4c49e95 | 451 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| phungductung | 0:e87aa4c49e95 | 452 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 453 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 454 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 455 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 456 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 457 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 458 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 459 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 460 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 461 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 462 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 463 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 464 | DMA_FLAG_HTIF3_7) |
| phungductung | 0:e87aa4c49e95 | 465 | |
| phungductung | 0:e87aa4c49e95 | 466 | /** |
| phungductung | 0:e87aa4c49e95 | 467 | * @brief Return the current DMA Stream transfer error flag. |
| phungductung | 0:e87aa4c49e95 | 468 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 469 | * @retval The specified transfer error flag index. |
| phungductung | 0:e87aa4c49e95 | 470 | */ |
| phungductung | 0:e87aa4c49e95 | 471 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| phungductung | 0:e87aa4c49e95 | 472 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 473 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 476 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 477 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 479 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 480 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 481 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 482 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 483 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 484 | DMA_FLAG_TEIF3_7) |
| phungductung | 0:e87aa4c49e95 | 485 | |
| phungductung | 0:e87aa4c49e95 | 486 | /** |
| phungductung | 0:e87aa4c49e95 | 487 | * @brief Return the current DMA Stream FIFO error flag. |
| phungductung | 0:e87aa4c49e95 | 488 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 489 | * @retval The specified FIFO error flag index. |
| phungductung | 0:e87aa4c49e95 | 490 | */ |
| phungductung | 0:e87aa4c49e95 | 491 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
| phungductung | 0:e87aa4c49e95 | 492 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 493 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 494 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 495 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 499 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 501 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 502 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 503 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 504 | DMA_FLAG_FEIF3_7) |
| phungductung | 0:e87aa4c49e95 | 505 | |
| phungductung | 0:e87aa4c49e95 | 506 | /** |
| phungductung | 0:e87aa4c49e95 | 507 | * @brief Return the current DMA Stream direct mode error flag. |
| phungductung | 0:e87aa4c49e95 | 508 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 509 | * @retval The specified direct mode error flag index. |
| phungductung | 0:e87aa4c49e95 | 510 | */ |
| phungductung | 0:e87aa4c49e95 | 511 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
| phungductung | 0:e87aa4c49e95 | 512 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 514 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| phungductung | 0:e87aa4c49e95 | 516 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 517 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| phungductung | 0:e87aa4c49e95 | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 523 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| phungductung | 0:e87aa4c49e95 | 524 | DMA_FLAG_DMEIF3_7) |
| phungductung | 0:e87aa4c49e95 | 525 | |
| phungductung | 0:e87aa4c49e95 | 526 | /** |
| phungductung | 0:e87aa4c49e95 | 527 | * @brief Get the DMA Stream pending flags. |
| phungductung | 0:e87aa4c49e95 | 528 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 529 | * @param __FLAG__: Get the specified flag. |
| phungductung | 0:e87aa4c49e95 | 530 | * This parameter can be any combination of the following values: |
| phungductung | 0:e87aa4c49e95 | 531 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| phungductung | 0:e87aa4c49e95 | 532 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| phungductung | 0:e87aa4c49e95 | 533 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| phungductung | 0:e87aa4c49e95 | 534 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| phungductung | 0:e87aa4c49e95 | 535 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| phungductung | 0:e87aa4c49e95 | 536 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| phungductung | 0:e87aa4c49e95 | 537 | * @retval The state of FLAG (SET or RESET). |
| phungductung | 0:e87aa4c49e95 | 538 | */ |
| phungductung | 0:e87aa4c49e95 | 539 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| phungductung | 0:e87aa4c49e95 | 540 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
| phungductung | 0:e87aa4c49e95 | 541 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
| phungductung | 0:e87aa4c49e95 | 542 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
| phungductung | 0:e87aa4c49e95 | 543 | |
| phungductung | 0:e87aa4c49e95 | 544 | /** |
| phungductung | 0:e87aa4c49e95 | 545 | * @brief Clear the DMA Stream pending flags. |
| phungductung | 0:e87aa4c49e95 | 546 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 547 | * @param __FLAG__: specifies the flag to clear. |
| phungductung | 0:e87aa4c49e95 | 548 | * This parameter can be any combination of the following values: |
| phungductung | 0:e87aa4c49e95 | 549 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| phungductung | 0:e87aa4c49e95 | 550 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| phungductung | 0:e87aa4c49e95 | 551 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| phungductung | 0:e87aa4c49e95 | 552 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| phungductung | 0:e87aa4c49e95 | 553 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| phungductung | 0:e87aa4c49e95 | 554 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| phungductung | 0:e87aa4c49e95 | 555 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 556 | */ |
| phungductung | 0:e87aa4c49e95 | 557 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| phungductung | 0:e87aa4c49e95 | 558 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ |
| phungductung | 0:e87aa4c49e95 | 559 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ |
| phungductung | 0:e87aa4c49e95 | 560 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) |
| phungductung | 0:e87aa4c49e95 | 561 | |
| phungductung | 0:e87aa4c49e95 | 562 | /** |
| phungductung | 0:e87aa4c49e95 | 563 | * @brief Enable the specified DMA Stream interrupts. |
| phungductung | 0:e87aa4c49e95 | 564 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 565 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| phungductung | 0:e87aa4c49e95 | 566 | * This parameter can be any combination of the following values: |
| phungductung | 0:e87aa4c49e95 | 567 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 568 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 569 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 570 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 571 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| phungductung | 0:e87aa4c49e95 | 572 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 573 | */ |
| phungductung | 0:e87aa4c49e95 | 574 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| phungductung | 0:e87aa4c49e95 | 575 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
| phungductung | 0:e87aa4c49e95 | 576 | |
| phungductung | 0:e87aa4c49e95 | 577 | /** |
| phungductung | 0:e87aa4c49e95 | 578 | * @brief Disable the specified DMA Stream interrupts. |
| phungductung | 0:e87aa4c49e95 | 579 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 580 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| phungductung | 0:e87aa4c49e95 | 581 | * This parameter can be any combination of the following values: |
| phungductung | 0:e87aa4c49e95 | 582 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 583 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 584 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 585 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 586 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| phungductung | 0:e87aa4c49e95 | 587 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 588 | */ |
| phungductung | 0:e87aa4c49e95 | 589 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| phungductung | 0:e87aa4c49e95 | 590 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
| phungductung | 0:e87aa4c49e95 | 591 | |
| phungductung | 0:e87aa4c49e95 | 592 | /** |
| phungductung | 0:e87aa4c49e95 | 593 | * @brief Check whether the specified DMA Stream interrupt is enabled or not. |
| phungductung | 0:e87aa4c49e95 | 594 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 595 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| phungductung | 0:e87aa4c49e95 | 596 | * This parameter can be one of the following values: |
| phungductung | 0:e87aa4c49e95 | 597 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 598 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 599 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 600 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| phungductung | 0:e87aa4c49e95 | 601 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| phungductung | 0:e87aa4c49e95 | 602 | * @retval The state of DMA_IT. |
| phungductung | 0:e87aa4c49e95 | 603 | */ |
| phungductung | 0:e87aa4c49e95 | 604 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| phungductung | 0:e87aa4c49e95 | 605 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
| phungductung | 0:e87aa4c49e95 | 606 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
| phungductung | 0:e87aa4c49e95 | 607 | |
| phungductung | 0:e87aa4c49e95 | 608 | /** |
| phungductung | 0:e87aa4c49e95 | 609 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
| phungductung | 0:e87aa4c49e95 | 610 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 611 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
| phungductung | 0:e87aa4c49e95 | 612 | * Number of data items depends only on the Peripheral data format. |
| phungductung | 0:e87aa4c49e95 | 613 | * |
| phungductung | 0:e87aa4c49e95 | 614 | * @note If Peripheral data format is Bytes: number of data units is equal |
| phungductung | 0:e87aa4c49e95 | 615 | * to total number of bytes to be transferred. |
| phungductung | 0:e87aa4c49e95 | 616 | * |
| phungductung | 0:e87aa4c49e95 | 617 | * @note If Peripheral data format is Half-Word: number of data units is |
| phungductung | 0:e87aa4c49e95 | 618 | * equal to total number of bytes to be transferred / 2. |
| phungductung | 0:e87aa4c49e95 | 619 | * |
| phungductung | 0:e87aa4c49e95 | 620 | * @note If Peripheral data format is Word: number of data units is equal |
| phungductung | 0:e87aa4c49e95 | 621 | * to total number of bytes to be transferred / 4. |
| phungductung | 0:e87aa4c49e95 | 622 | * |
| phungductung | 0:e87aa4c49e95 | 623 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
| phungductung | 0:e87aa4c49e95 | 624 | */ |
| phungductung | 0:e87aa4c49e95 | 625 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
| phungductung | 0:e87aa4c49e95 | 626 | |
| phungductung | 0:e87aa4c49e95 | 627 | /** |
| phungductung | 0:e87aa4c49e95 | 628 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
| phungductung | 0:e87aa4c49e95 | 629 | * @param __HANDLE__: DMA handle |
| phungductung | 0:e87aa4c49e95 | 630 | * |
| phungductung | 0:e87aa4c49e95 | 631 | * @retval The number of remaining data units in the current DMA Stream transfer. |
| phungductung | 0:e87aa4c49e95 | 632 | */ |
| phungductung | 0:e87aa4c49e95 | 633 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
| phungductung | 0:e87aa4c49e95 | 634 | |
| phungductung | 0:e87aa4c49e95 | 635 | |
| phungductung | 0:e87aa4c49e95 | 636 | /* Include DMA HAL Extension module */ |
| phungductung | 0:e87aa4c49e95 | 637 | #include "stm32f7xx_hal_dma_ex.h" |
| phungductung | 0:e87aa4c49e95 | 638 | |
| phungductung | 0:e87aa4c49e95 | 639 | /* Exported functions --------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 640 | |
| phungductung | 0:e87aa4c49e95 | 641 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| phungductung | 0:e87aa4c49e95 | 642 | * @brief DMA Exported functions |
| phungductung | 0:e87aa4c49e95 | 643 | * @{ |
| phungductung | 0:e87aa4c49e95 | 644 | */ |
| phungductung | 0:e87aa4c49e95 | 645 | |
| phungductung | 0:e87aa4c49e95 | 646 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| phungductung | 0:e87aa4c49e95 | 647 | * @brief Initialization and de-initialization functions |
| phungductung | 0:e87aa4c49e95 | 648 | * @{ |
| phungductung | 0:e87aa4c49e95 | 649 | */ |
| phungductung | 0:e87aa4c49e95 | 650 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| phungductung | 0:e87aa4c49e95 | 651 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
| phungductung | 0:e87aa4c49e95 | 652 | /** |
| phungductung | 0:e87aa4c49e95 | 653 | * @} |
| phungductung | 0:e87aa4c49e95 | 654 | */ |
| phungductung | 0:e87aa4c49e95 | 655 | |
| phungductung | 0:e87aa4c49e95 | 656 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| phungductung | 0:e87aa4c49e95 | 657 | * @brief I/O operation functions |
| phungductung | 0:e87aa4c49e95 | 658 | * @{ |
| phungductung | 0:e87aa4c49e95 | 659 | */ |
| phungductung | 0:e87aa4c49e95 | 660 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| phungductung | 0:e87aa4c49e95 | 661 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| phungductung | 0:e87aa4c49e95 | 662 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| phungductung | 0:e87aa4c49e95 | 663 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| phungductung | 0:e87aa4c49e95 | 664 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| phungductung | 0:e87aa4c49e95 | 665 | /** |
| phungductung | 0:e87aa4c49e95 | 666 | * @} |
| phungductung | 0:e87aa4c49e95 | 667 | */ |
| phungductung | 0:e87aa4c49e95 | 668 | |
| phungductung | 0:e87aa4c49e95 | 669 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| phungductung | 0:e87aa4c49e95 | 670 | * @brief Peripheral State functions |
| phungductung | 0:e87aa4c49e95 | 671 | * @{ |
| phungductung | 0:e87aa4c49e95 | 672 | */ |
| phungductung | 0:e87aa4c49e95 | 673 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| phungductung | 0:e87aa4c49e95 | 674 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| phungductung | 0:e87aa4c49e95 | 675 | /** |
| phungductung | 0:e87aa4c49e95 | 676 | * @} |
| phungductung | 0:e87aa4c49e95 | 677 | */ |
| phungductung | 0:e87aa4c49e95 | 678 | /** |
| phungductung | 0:e87aa4c49e95 | 679 | * @} |
| phungductung | 0:e87aa4c49e95 | 680 | */ |
| phungductung | 0:e87aa4c49e95 | 681 | /* Private Constants -------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 682 | /** @defgroup DMA_Private_Constants DMA Private Constants |
| phungductung | 0:e87aa4c49e95 | 683 | * @brief DMA private defines and constants |
| phungductung | 0:e87aa4c49e95 | 684 | * @{ |
| phungductung | 0:e87aa4c49e95 | 685 | */ |
| phungductung | 0:e87aa4c49e95 | 686 | /** |
| phungductung | 0:e87aa4c49e95 | 687 | * @} |
| phungductung | 0:e87aa4c49e95 | 688 | */ |
| phungductung | 0:e87aa4c49e95 | 689 | |
| phungductung | 0:e87aa4c49e95 | 690 | /* Private macros ------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 691 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| phungductung | 0:e87aa4c49e95 | 692 | * @brief DMA private macros |
| phungductung | 0:e87aa4c49e95 | 693 | * @{ |
| phungductung | 0:e87aa4c49e95 | 694 | */ |
| phungductung | 0:e87aa4c49e95 | 695 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
| phungductung | 0:e87aa4c49e95 | 696 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
| phungductung | 0:e87aa4c49e95 | 697 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
| phungductung | 0:e87aa4c49e95 | 698 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
| phungductung | 0:e87aa4c49e95 | 699 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
| phungductung | 0:e87aa4c49e95 | 700 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
| phungductung | 0:e87aa4c49e95 | 701 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
| phungductung | 0:e87aa4c49e95 | 702 | ((CHANNEL) == DMA_CHANNEL_7)) |
| phungductung | 0:e87aa4c49e95 | 703 | |
| phungductung | 0:e87aa4c49e95 | 704 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| phungductung | 0:e87aa4c49e95 | 705 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| phungductung | 0:e87aa4c49e95 | 706 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| phungductung | 0:e87aa4c49e95 | 707 | |
| phungductung | 0:e87aa4c49e95 | 708 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| phungductung | 0:e87aa4c49e95 | 709 | |
| phungductung | 0:e87aa4c49e95 | 710 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 711 | ((STATE) == DMA_PINC_DISABLE)) |
| phungductung | 0:e87aa4c49e95 | 712 | |
| phungductung | 0:e87aa4c49e95 | 713 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 714 | ((STATE) == DMA_MINC_DISABLE)) |
| phungductung | 0:e87aa4c49e95 | 715 | |
| phungductung | 0:e87aa4c49e95 | 716 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| phungductung | 0:e87aa4c49e95 | 717 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| phungductung | 0:e87aa4c49e95 | 718 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| phungductung | 0:e87aa4c49e95 | 719 | |
| phungductung | 0:e87aa4c49e95 | 720 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| phungductung | 0:e87aa4c49e95 | 721 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| phungductung | 0:e87aa4c49e95 | 722 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| phungductung | 0:e87aa4c49e95 | 723 | |
| phungductung | 0:e87aa4c49e95 | 724 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| phungductung | 0:e87aa4c49e95 | 725 | ((MODE) == DMA_CIRCULAR) || \ |
| phungductung | 0:e87aa4c49e95 | 726 | ((MODE) == DMA_PFCTRL)) |
| phungductung | 0:e87aa4c49e95 | 727 | |
| phungductung | 0:e87aa4c49e95 | 728 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| phungductung | 0:e87aa4c49e95 | 729 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| phungductung | 0:e87aa4c49e95 | 730 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| phungductung | 0:e87aa4c49e95 | 731 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| phungductung | 0:e87aa4c49e95 | 732 | |
| phungductung | 0:e87aa4c49e95 | 733 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
| phungductung | 0:e87aa4c49e95 | 734 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
| phungductung | 0:e87aa4c49e95 | 735 | |
| phungductung | 0:e87aa4c49e95 | 736 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
| phungductung | 0:e87aa4c49e95 | 737 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
| phungductung | 0:e87aa4c49e95 | 738 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
| phungductung | 0:e87aa4c49e95 | 739 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
| phungductung | 0:e87aa4c49e95 | 740 | |
| phungductung | 0:e87aa4c49e95 | 741 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
| phungductung | 0:e87aa4c49e95 | 742 | ((BURST) == DMA_MBURST_INC4) || \ |
| phungductung | 0:e87aa4c49e95 | 743 | ((BURST) == DMA_MBURST_INC8) || \ |
| phungductung | 0:e87aa4c49e95 | 744 | ((BURST) == DMA_MBURST_INC16)) |
| phungductung | 0:e87aa4c49e95 | 745 | |
| phungductung | 0:e87aa4c49e95 | 746 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
| phungductung | 0:e87aa4c49e95 | 747 | ((BURST) == DMA_PBURST_INC4) || \ |
| phungductung | 0:e87aa4c49e95 | 748 | ((BURST) == DMA_PBURST_INC8) || \ |
| phungductung | 0:e87aa4c49e95 | 749 | ((BURST) == DMA_PBURST_INC16)) |
| phungductung | 0:e87aa4c49e95 | 750 | /** |
| phungductung | 0:e87aa4c49e95 | 751 | * @} |
| phungductung | 0:e87aa4c49e95 | 752 | */ |
| phungductung | 0:e87aa4c49e95 | 753 | |
| phungductung | 0:e87aa4c49e95 | 754 | /* Private functions ---------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 755 | /** @defgroup DMA_Private_Functions DMA Private Functions |
| phungductung | 0:e87aa4c49e95 | 756 | * @brief DMA private functions |
| phungductung | 0:e87aa4c49e95 | 757 | * @{ |
| phungductung | 0:e87aa4c49e95 | 758 | */ |
| phungductung | 0:e87aa4c49e95 | 759 | /** |
| phungductung | 0:e87aa4c49e95 | 760 | * @} |
| phungductung | 0:e87aa4c49e95 | 761 | */ |
| phungductung | 0:e87aa4c49e95 | 762 | |
| phungductung | 0:e87aa4c49e95 | 763 | /** |
| phungductung | 0:e87aa4c49e95 | 764 | * @} |
| phungductung | 0:e87aa4c49e95 | 765 | */ |
| phungductung | 0:e87aa4c49e95 | 766 | |
| phungductung | 0:e87aa4c49e95 | 767 | /** |
| phungductung | 0:e87aa4c49e95 | 768 | * @} |
| phungductung | 0:e87aa4c49e95 | 769 | */ |
| phungductung | 0:e87aa4c49e95 | 770 | |
| phungductung | 0:e87aa4c49e95 | 771 | #ifdef __cplusplus |
| phungductung | 0:e87aa4c49e95 | 772 | } |
| phungductung | 0:e87aa4c49e95 | 773 | #endif |
| phungductung | 0:e87aa4c49e95 | 774 | |
| phungductung | 0:e87aa4c49e95 | 775 | #endif /* __STM32F7xx_HAL_DMA_H */ |
| phungductung | 0:e87aa4c49e95 | 776 | |
| phungductung | 0:e87aa4c49e95 | 777 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |