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targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

libray

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User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/**
phungductung	0:e87aa4c49e95	2	******************************************************************************
phungductung	0:e87aa4c49e95	3	* @file stm32f746xx.h
phungductung	0:e87aa4c49e95	4	* @author MCD Application Team
phungductung	0:e87aa4c49e95	5	* @version V1.0.2
phungductung	0:e87aa4c49e95	6	* @date 21-September-2015
phungductung	0:e87aa4c49e95	7	* @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
phungductung	0:e87aa4c49e95	8	*
phungductung	0:e87aa4c49e95	9	* This file contains:
phungductung	0:e87aa4c49e95	10	* - Data structures and the address mapping for all peripherals
phungductung	0:e87aa4c49e95	11	* - Peripheral's registers declarations and bits definition
phungductung	0:e87aa4c49e95	12	* - Macros to access peripherals registers hardware
phungductung	0:e87aa4c49e95	13	*
phungductung	0:e87aa4c49e95	14	******************************************************************************
phungductung	0:e87aa4c49e95	15	* @attention
phungductung	0:e87aa4c49e95	16	*
phungductung	0:e87aa4c49e95	17	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
phungductung	0:e87aa4c49e95	18	*
phungductung	0:e87aa4c49e95	19	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:e87aa4c49e95	20	* are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	21	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:e87aa4c49e95	22	* this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:e87aa4c49e95	24	* this list of conditions and the following disclaimer in the documentation
phungductung	0:e87aa4c49e95	25	* and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:e87aa4c49e95	27	* may be used to endorse or promote products derived from this software
phungductung	0:e87aa4c49e95	28	* without specific prior written permission.
phungductung	0:e87aa4c49e95	29	*
phungductung	0:e87aa4c49e95	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:e87aa4c49e95	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:e87aa4c49e95	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:e87aa4c49e95	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:e87aa4c49e95	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:e87aa4c49e95	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:e87aa4c49e95	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:e87aa4c49e95	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	40	*
phungductung	0:e87aa4c49e95	41	******************************************************************************
phungductung	0:e87aa4c49e95	42	*/
phungductung	0:e87aa4c49e95	43
phungductung	0:e87aa4c49e95	44	/** @addtogroup CMSIS_Device
phungductung	0:e87aa4c49e95	45	* @{
phungductung	0:e87aa4c49e95	46	*/
phungductung	0:e87aa4c49e95	47
phungductung	0:e87aa4c49e95	48	/** @addtogroup stm32f746xx
phungductung	0:e87aa4c49e95	49	* @{
phungductung	0:e87aa4c49e95	50	*/
phungductung	0:e87aa4c49e95	51
phungductung	0:e87aa4c49e95	52	#ifndef __STM32F746xx_H
phungductung	0:e87aa4c49e95	53	#define __STM32F746xx_H
phungductung	0:e87aa4c49e95	54
phungductung	0:e87aa4c49e95	55	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	56	extern "C" {
phungductung	0:e87aa4c49e95	57	#endif /* __cplusplus */
phungductung	0:e87aa4c49e95	58
phungductung	0:e87aa4c49e95	59	/** @addtogroup Configuration_section_for_CMSIS
phungductung	0:e87aa4c49e95	60	* @{
phungductung	0:e87aa4c49e95	61	*/
phungductung	0:e87aa4c49e95	62
phungductung	0:e87aa4c49e95	63	/**
phungductung	0:e87aa4c49e95	64	* @brief STM32F7xx Interrupt Number Definition, according to the selected device
phungductung	0:e87aa4c49e95	65	* in @ref Library_configuration_section
phungductung	0:e87aa4c49e95	66	*/
phungductung	0:e87aa4c49e95	67	typedef enum
phungductung	0:e87aa4c49e95	68	{
phungductung	0:e87aa4c49e95	69	/**** Cortex-M7 Processor Exceptions Numbers **************************************************************/
phungductung	0:e87aa4c49e95	70	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
phungductung	0:e87aa4c49e95	71	MemoryManagement_IRQn = -12, /!< 4 Cortex-M7 Memory Management Interrupt /
phungductung	0:e87aa4c49e95	72	BusFault_IRQn = -11, /!< 5 Cortex-M7 Bus Fault Interrupt /
phungductung	0:e87aa4c49e95	73	UsageFault_IRQn = -10, /!< 6 Cortex-M7 Usage Fault Interrupt /
phungductung	0:e87aa4c49e95	74	SVCall_IRQn = -5, /!< 11 Cortex-M7 SV Call Interrupt /
phungductung	0:e87aa4c49e95	75	DebugMonitor_IRQn = -4, /!< 12 Cortex-M7 Debug Monitor Interrupt /
phungductung	0:e87aa4c49e95	76	PendSV_IRQn = -2, /!< 14 Cortex-M7 Pend SV Interrupt /
phungductung	0:e87aa4c49e95	77	SysTick_IRQn = -1, /!< 15 Cortex-M7 System Tick Interrupt /
phungductung	0:e87aa4c49e95	78	/**** STM32 specific Interrupt Numbers ********************************************************************/
phungductung	0:e87aa4c49e95	79	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
phungductung	0:e87aa4c49e95	80	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
phungductung	0:e87aa4c49e95	81	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
phungductung	0:e87aa4c49e95	82	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
phungductung	0:e87aa4c49e95	83	FLASH_IRQn = 4, /!< FLASH global Interrupt /
phungductung	0:e87aa4c49e95	84	RCC_IRQn = 5, /!< RCC global Interrupt /
phungductung	0:e87aa4c49e95	85	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
phungductung	0:e87aa4c49e95	86	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
phungductung	0:e87aa4c49e95	87	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
phungductung	0:e87aa4c49e95	88	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
phungductung	0:e87aa4c49e95	89	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
phungductung	0:e87aa4c49e95	90	DMA1_Stream0_IRQn = 11, /!< DMA1 Stream 0 global Interrupt /
phungductung	0:e87aa4c49e95	91	DMA1_Stream1_IRQn = 12, /!< DMA1 Stream 1 global Interrupt /
phungductung	0:e87aa4c49e95	92	DMA1_Stream2_IRQn = 13, /!< DMA1 Stream 2 global Interrupt /
phungductung	0:e87aa4c49e95	93	DMA1_Stream3_IRQn = 14, /!< DMA1 Stream 3 global Interrupt /
phungductung	0:e87aa4c49e95	94	DMA1_Stream4_IRQn = 15, /!< DMA1 Stream 4 global Interrupt /
phungductung	0:e87aa4c49e95	95	DMA1_Stream5_IRQn = 16, /!< DMA1 Stream 5 global Interrupt /
phungductung	0:e87aa4c49e95	96	DMA1_Stream6_IRQn = 17, /!< DMA1 Stream 6 global Interrupt /
phungductung	0:e87aa4c49e95	97	ADC_IRQn = 18, /!< ADC1, ADC2 and ADC3 global Interrupts /
phungductung	0:e87aa4c49e95	98	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
phungductung	0:e87aa4c49e95	99	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
phungductung	0:e87aa4c49e95	100	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
phungductung	0:e87aa4c49e95	101	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
phungductung	0:e87aa4c49e95	102	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
phungductung	0:e87aa4c49e95	103	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break interrupt and TIM9 global interrupt /
phungductung	0:e87aa4c49e95	104	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global interrupt /
phungductung	0:e87aa4c49e95	105	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
phungductung	0:e87aa4c49e95	106	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
phungductung	0:e87aa4c49e95	107	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
phungductung	0:e87aa4c49e95	108	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
phungductung	0:e87aa4c49e95	109	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
phungductung	0:e87aa4c49e95	110	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
phungductung	0:e87aa4c49e95	111	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
phungductung	0:e87aa4c49e95	112	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
phungductung	0:e87aa4c49e95	113	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
phungductung	0:e87aa4c49e95	114	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
phungductung	0:e87aa4c49e95	115	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
phungductung	0:e87aa4c49e95	116	USART1_IRQn = 37, /!< USART1 global Interrupt /
phungductung	0:e87aa4c49e95	117	USART2_IRQn = 38, /!< USART2 global Interrupt /
phungductung	0:e87aa4c49e95	118	USART3_IRQn = 39, /!< USART3 global Interrupt /
phungductung	0:e87aa4c49e95	119	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
phungductung	0:e87aa4c49e95	120	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
phungductung	0:e87aa4c49e95	121	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS Wakeup through EXTI line interrupt /
phungductung	0:e87aa4c49e95	122	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global interrupt /
phungductung	0:e87aa4c49e95	123	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global interrupt /
phungductung	0:e87aa4c49e95	124	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
phungductung	0:e87aa4c49e95	125	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
phungductung	0:e87aa4c49e95	126	DMA1_Stream7_IRQn = 47, /!< DMA1 Stream7 Interrupt /
phungductung	0:e87aa4c49e95	127	FMC_IRQn = 48, /!< FMC global Interrupt /
phungductung	0:e87aa4c49e95	128	SDMMC1_IRQn = 49, /!< SDMMC1 global Interrupt /
phungductung	0:e87aa4c49e95	129	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
phungductung	0:e87aa4c49e95	130	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
phungductung	0:e87aa4c49e95	131	UART4_IRQn = 52, /!< UART4 global Interrupt /
phungductung	0:e87aa4c49e95	132	UART5_IRQn = 53, /!< UART5 global Interrupt /
phungductung	0:e87aa4c49e95	133	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
phungductung	0:e87aa4c49e95	134	TIM7_IRQn = 55, /!< TIM7 global interrupt /
phungductung	0:e87aa4c49e95	135	DMA2_Stream0_IRQn = 56, /!< DMA2 Stream 0 global Interrupt /
phungductung	0:e87aa4c49e95	136	DMA2_Stream1_IRQn = 57, /!< DMA2 Stream 1 global Interrupt /
phungductung	0:e87aa4c49e95	137	DMA2_Stream2_IRQn = 58, /!< DMA2 Stream 2 global Interrupt /
phungductung	0:e87aa4c49e95	138	DMA2_Stream3_IRQn = 59, /!< DMA2 Stream 3 global Interrupt /
phungductung	0:e87aa4c49e95	139	DMA2_Stream4_IRQn = 60, /!< DMA2 Stream 4 global Interrupt /
phungductung	0:e87aa4c49e95	140	ETH_IRQn = 61, /!< Ethernet global Interrupt /
phungductung	0:e87aa4c49e95	141	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
phungductung	0:e87aa4c49e95	142	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
phungductung	0:e87aa4c49e95	143	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
phungductung	0:e87aa4c49e95	144	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
phungductung	0:e87aa4c49e95	145	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
phungductung	0:e87aa4c49e95	146	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
phungductung	0:e87aa4c49e95	147	DMA2_Stream5_IRQn = 68, /!< DMA2 Stream 5 global interrupt /
phungductung	0:e87aa4c49e95	148	DMA2_Stream6_IRQn = 69, /!< DMA2 Stream 6 global interrupt /
phungductung	0:e87aa4c49e95	149	DMA2_Stream7_IRQn = 70, /!< DMA2 Stream 7 global interrupt /
phungductung	0:e87aa4c49e95	150	USART6_IRQn = 71, /!< USART6 global interrupt /
phungductung	0:e87aa4c49e95	151	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
phungductung	0:e87aa4c49e95	152	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
phungductung	0:e87aa4c49e95	153	OTG_HS_EP1_OUT_IRQn = 74, /!< USB OTG HS End Point 1 Out global interrupt /
phungductung	0:e87aa4c49e95	154	OTG_HS_EP1_IN_IRQn = 75, /!< USB OTG HS End Point 1 In global interrupt /
phungductung	0:e87aa4c49e95	155	OTG_HS_WKUP_IRQn = 76, /!< USB OTG HS Wakeup through EXTI interrupt /
phungductung	0:e87aa4c49e95	156	OTG_HS_IRQn = 77, /!< USB OTG HS global interrupt /
phungductung	0:e87aa4c49e95	157	DCMI_IRQn = 78, /!< DCMI global interrupt /
phungductung	0:e87aa4c49e95	158	RNG_IRQn = 80, /!< RNG global interrupt /
phungductung	0:e87aa4c49e95	159	FPU_IRQn = 81, /!< FPU global interrupt /
phungductung	0:e87aa4c49e95	160	UART7_IRQn = 82, /!< UART7 global interrupt /
phungductung	0:e87aa4c49e95	161	UART8_IRQn = 83, /!< UART8 global interrupt /
phungductung	0:e87aa4c49e95	162	SPI4_IRQn = 84, /!< SPI4 global Interrupt /
phungductung	0:e87aa4c49e95	163	SPI5_IRQn = 85, /!< SPI5 global Interrupt /
phungductung	0:e87aa4c49e95	164	SPI6_IRQn = 86, /!< SPI6 global Interrupt /
phungductung	0:e87aa4c49e95	165	SAI1_IRQn = 87, /!< SAI1 global Interrupt /
phungductung	0:e87aa4c49e95	166	LTDC_IRQn = 88, /!< LTDC global Interrupt /
phungductung	0:e87aa4c49e95	167	LTDC_ER_IRQn = 89, /!< LTDC Error global Interrupt /
phungductung	0:e87aa4c49e95	168	DMA2D_IRQn = 90, /!< DMA2D global Interrupt /
phungductung	0:e87aa4c49e95	169	SAI2_IRQn = 91, /!< SAI2 global Interrupt /
phungductung	0:e87aa4c49e95	170	QUADSPI_IRQn = 92, /!< Quad SPI global interrupt /
phungductung	0:e87aa4c49e95	171	LPTIM1_IRQn = 93, /!< LP TIM1 interrupt /
phungductung	0:e87aa4c49e95	172	CEC_IRQn = 94, /!< HDMI-CEC global Interrupt /
phungductung	0:e87aa4c49e95	173	I2C4_EV_IRQn = 95, /!< I2C4 Event Interrupt /
phungductung	0:e87aa4c49e95	174	I2C4_ER_IRQn = 96, /!< I2C4 Error Interrupt /
phungductung	0:e87aa4c49e95	175	SPDIF_RX_IRQn = 97 /!< SPDIF-RX global Interrupt /
phungductung	0:e87aa4c49e95	176	} IRQn_Type;
phungductung	0:e87aa4c49e95	177
phungductung	0:e87aa4c49e95	178	/**
phungductung	0:e87aa4c49e95	179	* @}
phungductung	0:e87aa4c49e95	180	*/
phungductung	0:e87aa4c49e95	181
phungductung	0:e87aa4c49e95	182	/**
phungductung	0:e87aa4c49e95	183	* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
phungductung	0:e87aa4c49e95	184	*/
phungductung	0:e87aa4c49e95	185	#define __CM7_REV 0x0001 /!< Cortex-M7 revision r0p1 /
phungductung	0:e87aa4c49e95	186	#define __MPU_PRESENT 1 /!< CM7 provides an MPU /
phungductung	0:e87aa4c49e95	187	#define __NVIC_PRIO_BITS 4 /!< CM7 uses 4 Bits for the Priority Levels /
phungductung	0:e87aa4c49e95	188	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
phungductung	0:e87aa4c49e95	189	#define __FPU_PRESENT 1 /!< FPU present /
phungductung	0:e87aa4c49e95	190	#define __ICACHE_PRESENT 1 /!< CM7 instruction cache present /
phungductung	0:e87aa4c49e95	191	#define __DCACHE_PRESENT 1 /!< CM7 data cache present /
phungductung	0:e87aa4c49e95	192	#include "core_cm7.h" /!< Cortex-M7 processor and core peripherals /
phungductung	0:e87aa4c49e95	193
phungductung	0:e87aa4c49e95	194
phungductung	0:e87aa4c49e95	195	#include "system_stm32f7xx.h"
phungductung	0:e87aa4c49e95	196	#include <stdint.h>
phungductung	0:e87aa4c49e95	197
phungductung	0:e87aa4c49e95	198	/** @addtogroup Peripheral_registers_structures
phungductung	0:e87aa4c49e95	199	* @{
phungductung	0:e87aa4c49e95	200	*/
phungductung	0:e87aa4c49e95	201
phungductung	0:e87aa4c49e95	202	/**
phungductung	0:e87aa4c49e95	203	* @brief Analog to Digital Converter
phungductung	0:e87aa4c49e95	204	*/
phungductung	0:e87aa4c49e95	205
phungductung	0:e87aa4c49e95	206	typedef struct
phungductung	0:e87aa4c49e95	207	{
phungductung	0:e87aa4c49e95	208	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	209	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	210	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	211	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	212	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	213	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	214	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	215	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	216	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	217	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	218	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	219	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	220	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	221	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	222	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
phungductung	0:e87aa4c49e95	223	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
phungductung	0:e87aa4c49e95	224	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
phungductung	0:e87aa4c49e95	225	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
phungductung	0:e87aa4c49e95	226	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
phungductung	0:e87aa4c49e95	227	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
phungductung	0:e87aa4c49e95	228	} ADC_TypeDef;
phungductung	0:e87aa4c49e95	229
phungductung	0:e87aa4c49e95	230	typedef struct
phungductung	0:e87aa4c49e95	231	{
phungductung	0:e87aa4c49e95	232	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
phungductung	0:e87aa4c49e95	233	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
phungductung	0:e87aa4c49e95	234	__IO uint32_t CDR; /*!< ADC common regular data register for dual
phungductung	0:e87aa4c49e95	235	AND triple modes, Address offset: ADC1 base address + 0x308 */
phungductung	0:e87aa4c49e95	236	} ADC_Common_TypeDef;
phungductung	0:e87aa4c49e95	237
phungductung	0:e87aa4c49e95	238
phungductung	0:e87aa4c49e95	239	/**
phungductung	0:e87aa4c49e95	240	* @brief Controller Area Network TxMailBox
phungductung	0:e87aa4c49e95	241	*/
phungductung	0:e87aa4c49e95	242
phungductung	0:e87aa4c49e95	243	typedef struct
phungductung	0:e87aa4c49e95	244	{
phungductung	0:e87aa4c49e95	245	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
phungductung	0:e87aa4c49e95	246	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
phungductung	0:e87aa4c49e95	247	__IO uint32_t TDLR; /!< CAN mailbox data low register /
phungductung	0:e87aa4c49e95	248	__IO uint32_t TDHR; /!< CAN mailbox data high register /
phungductung	0:e87aa4c49e95	249	} CAN_TxMailBox_TypeDef;
phungductung	0:e87aa4c49e95	250
phungductung	0:e87aa4c49e95	251	/**
phungductung	0:e87aa4c49e95	252	* @brief Controller Area Network FIFOMailBox
phungductung	0:e87aa4c49e95	253	*/
phungductung	0:e87aa4c49e95	254
phungductung	0:e87aa4c49e95	255	typedef struct
phungductung	0:e87aa4c49e95	256	{
phungductung	0:e87aa4c49e95	257	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
phungductung	0:e87aa4c49e95	258	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
phungductung	0:e87aa4c49e95	259	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
phungductung	0:e87aa4c49e95	260	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
phungductung	0:e87aa4c49e95	261	} CAN_FIFOMailBox_TypeDef;
phungductung	0:e87aa4c49e95	262
phungductung	0:e87aa4c49e95	263	/**
phungductung	0:e87aa4c49e95	264	* @brief Controller Area Network FilterRegister
phungductung	0:e87aa4c49e95	265	*/
phungductung	0:e87aa4c49e95	266
phungductung	0:e87aa4c49e95	267	typedef struct
phungductung	0:e87aa4c49e95	268	{
phungductung	0:e87aa4c49e95	269	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
phungductung	0:e87aa4c49e95	270	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
phungductung	0:e87aa4c49e95	271	} CAN_FilterRegister_TypeDef;
phungductung	0:e87aa4c49e95	272
phungductung	0:e87aa4c49e95	273	/**
phungductung	0:e87aa4c49e95	274	* @brief Controller Area Network
phungductung	0:e87aa4c49e95	275	*/
phungductung	0:e87aa4c49e95	276
phungductung	0:e87aa4c49e95	277	typedef struct
phungductung	0:e87aa4c49e95	278	{
phungductung	0:e87aa4c49e95	279	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	280	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	281	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	282	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	283	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	284	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	285	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	286	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	287	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
phungductung	0:e87aa4c49e95	288	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
phungductung	0:e87aa4c49e95	289	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
phungductung	0:e87aa4c49e95	290	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
phungductung	0:e87aa4c49e95	291	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
phungductung	0:e87aa4c49e95	292	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
phungductung	0:e87aa4c49e95	293	uint32_t RESERVED2; /!< Reserved, 0x208 /
phungductung	0:e87aa4c49e95	294	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
phungductung	0:e87aa4c49e95	295	uint32_t RESERVED3; /!< Reserved, 0x210 /
phungductung	0:e87aa4c49e95	296	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
phungductung	0:e87aa4c49e95	297	uint32_t RESERVED4; /!< Reserved, 0x218 /
phungductung	0:e87aa4c49e95	298	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
phungductung	0:e87aa4c49e95	299	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
phungductung	0:e87aa4c49e95	300	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
phungductung	0:e87aa4c49e95	301	} CAN_TypeDef;
phungductung	0:e87aa4c49e95	302
phungductung	0:e87aa4c49e95	303	/**
phungductung	0:e87aa4c49e95	304	* @brief HDMI-CEC
phungductung	0:e87aa4c49e95	305	*/
phungductung	0:e87aa4c49e95	306
phungductung	0:e87aa4c49e95	307	typedef struct
phungductung	0:e87aa4c49e95	308	{
phungductung	0:e87aa4c49e95	309	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
phungductung	0:e87aa4c49e95	310	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
phungductung	0:e87aa4c49e95	311	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
phungductung	0:e87aa4c49e95	312	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
phungductung	0:e87aa4c49e95	313	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
phungductung	0:e87aa4c49e95	314	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
phungductung	0:e87aa4c49e95	315	}CEC_TypeDef;
phungductung	0:e87aa4c49e95	316
phungductung	0:e87aa4c49e95	317
phungductung	0:e87aa4c49e95	318	/**
phungductung	0:e87aa4c49e95	319	* @brief CRC calculation unit
phungductung	0:e87aa4c49e95	320	*/
phungductung	0:e87aa4c49e95	321
phungductung	0:e87aa4c49e95	322	typedef struct
phungductung	0:e87aa4c49e95	323	{
phungductung	0:e87aa4c49e95	324	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	325	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	326	uint8_t RESERVED0; /!< Reserved, 0x05 /
phungductung	0:e87aa4c49e95	327	uint16_t RESERVED1; /!< Reserved, 0x06 /
phungductung	0:e87aa4c49e95	328	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	329	uint32_t RESERVED2; /!< Reserved, 0x0C /
phungductung	0:e87aa4c49e95	330	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	331	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	332	} CRC_TypeDef;
phungductung	0:e87aa4c49e95	333
phungductung	0:e87aa4c49e95	334	/**
phungductung	0:e87aa4c49e95	335	* @brief Digital to Analog Converter
phungductung	0:e87aa4c49e95	336	*/
phungductung	0:e87aa4c49e95	337
phungductung	0:e87aa4c49e95	338	typedef struct
phungductung	0:e87aa4c49e95	339	{
phungductung	0:e87aa4c49e95	340	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	341	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	342	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	343	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	344	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	345	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	346	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	347	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	348	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	349	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	350	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	351	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	352	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	353	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	354	} DAC_TypeDef;
phungductung	0:e87aa4c49e95	355
phungductung	0:e87aa4c49e95	356
phungductung	0:e87aa4c49e95	357	/**
phungductung	0:e87aa4c49e95	358	* @brief Debug MCU
phungductung	0:e87aa4c49e95	359	*/
phungductung	0:e87aa4c49e95	360
phungductung	0:e87aa4c49e95	361	typedef struct
phungductung	0:e87aa4c49e95	362	{
phungductung	0:e87aa4c49e95	363	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	364	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	365	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	366	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	367	}DBGMCU_TypeDef;
phungductung	0:e87aa4c49e95	368
phungductung	0:e87aa4c49e95	369	/**
phungductung	0:e87aa4c49e95	370	* @brief DCMI
phungductung	0:e87aa4c49e95	371	*/
phungductung	0:e87aa4c49e95	372
phungductung	0:e87aa4c49e95	373	typedef struct
phungductung	0:e87aa4c49e95	374	{
phungductung	0:e87aa4c49e95	375	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	376	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	377	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	378	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	379	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	380	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	381	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	382	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	383	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	384	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	385	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	386	} DCMI_TypeDef;
phungductung	0:e87aa4c49e95	387
phungductung	0:e87aa4c49e95	388	/**
phungductung	0:e87aa4c49e95	389	* @brief DMA Controller
phungductung	0:e87aa4c49e95	390	*/
phungductung	0:e87aa4c49e95	391
phungductung	0:e87aa4c49e95	392	typedef struct
phungductung	0:e87aa4c49e95	393	{
phungductung	0:e87aa4c49e95	394	__IO uint32_t CR; /!< DMA stream x configuration register /
phungductung	0:e87aa4c49e95	395	__IO uint32_t NDTR; /!< DMA stream x number of data register /
phungductung	0:e87aa4c49e95	396	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
phungductung	0:e87aa4c49e95	397	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
phungductung	0:e87aa4c49e95	398	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
phungductung	0:e87aa4c49e95	399	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
phungductung	0:e87aa4c49e95	400	} DMA_Stream_TypeDef;
phungductung	0:e87aa4c49e95	401
phungductung	0:e87aa4c49e95	402	typedef struct
phungductung	0:e87aa4c49e95	403	{
phungductung	0:e87aa4c49e95	404	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	405	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	406	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	407	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	408	} DMA_TypeDef;
phungductung	0:e87aa4c49e95	409
phungductung	0:e87aa4c49e95	410
phungductung	0:e87aa4c49e95	411	/**
phungductung	0:e87aa4c49e95	412	* @brief DMA2D Controller
phungductung	0:e87aa4c49e95	413	*/
phungductung	0:e87aa4c49e95	414
phungductung	0:e87aa4c49e95	415	typedef struct
phungductung	0:e87aa4c49e95	416	{
phungductung	0:e87aa4c49e95	417	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	418	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	419	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	420	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	421	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	422	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	423	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	424	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	425	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	426	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	427	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	428	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	429	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	430	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	431	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
phungductung	0:e87aa4c49e95	432	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
phungductung	0:e87aa4c49e95	433	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
phungductung	0:e87aa4c49e95	434	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
phungductung	0:e87aa4c49e95	435	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
phungductung	0:e87aa4c49e95	436	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
phungductung	0:e87aa4c49e95	437	uint32_t RESERVED[236]; /!< Reserved, 0x50-0x3FF /
phungductung	0:e87aa4c49e95	438	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
phungductung	0:e87aa4c49e95	439	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
phungductung	0:e87aa4c49e95	440	} DMA2D_TypeDef;
phungductung	0:e87aa4c49e95	441
phungductung	0:e87aa4c49e95	442
phungductung	0:e87aa4c49e95	443	/**
phungductung	0:e87aa4c49e95	444	* @brief Ethernet MAC
phungductung	0:e87aa4c49e95	445	*/
phungductung	0:e87aa4c49e95	446
phungductung	0:e87aa4c49e95	447	typedef struct
phungductung	0:e87aa4c49e95	448	{
phungductung	0:e87aa4c49e95	449	__IO uint32_t MACCR;
phungductung	0:e87aa4c49e95	450	__IO uint32_t MACFFR;
phungductung	0:e87aa4c49e95	451	__IO uint32_t MACHTHR;
phungductung	0:e87aa4c49e95	452	__IO uint32_t MACHTLR;
phungductung	0:e87aa4c49e95	453	__IO uint32_t MACMIIAR;
phungductung	0:e87aa4c49e95	454	__IO uint32_t MACMIIDR;
phungductung	0:e87aa4c49e95	455	__IO uint32_t MACFCR;
phungductung	0:e87aa4c49e95	456	__IO uint32_t MACVLANTR; /* 8 */
phungductung	0:e87aa4c49e95	457	uint32_t RESERVED0[2];
phungductung	0:e87aa4c49e95	458	__IO uint32_t MACRWUFFR; /* 11 */
phungductung	0:e87aa4c49e95	459	__IO uint32_t MACPMTCSR;
phungductung	0:e87aa4c49e95	460	uint32_t RESERVED1[2];
phungductung	0:e87aa4c49e95	461	__IO uint32_t MACSR; /* 15 */
phungductung	0:e87aa4c49e95	462	__IO uint32_t MACIMR;
phungductung	0:e87aa4c49e95	463	__IO uint32_t MACA0HR;
phungductung	0:e87aa4c49e95	464	__IO uint32_t MACA0LR;
phungductung	0:e87aa4c49e95	465	__IO uint32_t MACA1HR;
phungductung	0:e87aa4c49e95	466	__IO uint32_t MACA1LR;
phungductung	0:e87aa4c49e95	467	__IO uint32_t MACA2HR;
phungductung	0:e87aa4c49e95	468	__IO uint32_t MACA2LR;
phungductung	0:e87aa4c49e95	469	__IO uint32_t MACA3HR;
phungductung	0:e87aa4c49e95	470	__IO uint32_t MACA3LR; /* 24 */
phungductung	0:e87aa4c49e95	471	uint32_t RESERVED2[40];
phungductung	0:e87aa4c49e95	472	__IO uint32_t MMCCR; /* 65 */
phungductung	0:e87aa4c49e95	473	__IO uint32_t MMCRIR;
phungductung	0:e87aa4c49e95	474	__IO uint32_t MMCTIR;
phungductung	0:e87aa4c49e95	475	__IO uint32_t MMCRIMR;
phungductung	0:e87aa4c49e95	476	__IO uint32_t MMCTIMR; /* 69 */
phungductung	0:e87aa4c49e95	477	uint32_t RESERVED3[14];
phungductung	0:e87aa4c49e95	478	__IO uint32_t MMCTGFSCCR; /* 84 */
phungductung	0:e87aa4c49e95	479	__IO uint32_t MMCTGFMSCCR;
phungductung	0:e87aa4c49e95	480	uint32_t RESERVED4[5];
phungductung	0:e87aa4c49e95	481	__IO uint32_t MMCTGFCR;
phungductung	0:e87aa4c49e95	482	uint32_t RESERVED5[10];
phungductung	0:e87aa4c49e95	483	__IO uint32_t MMCRFCECR;
phungductung	0:e87aa4c49e95	484	__IO uint32_t MMCRFAECR;
phungductung	0:e87aa4c49e95	485	uint32_t RESERVED6[10];
phungductung	0:e87aa4c49e95	486	__IO uint32_t MMCRGUFCR;
phungductung	0:e87aa4c49e95	487	uint32_t RESERVED7[334];
phungductung	0:e87aa4c49e95	488	__IO uint32_t PTPTSCR;
phungductung	0:e87aa4c49e95	489	__IO uint32_t PTPSSIR;
phungductung	0:e87aa4c49e95	490	__IO uint32_t PTPTSHR;
phungductung	0:e87aa4c49e95	491	__IO uint32_t PTPTSLR;
phungductung	0:e87aa4c49e95	492	__IO uint32_t PTPTSHUR;
phungductung	0:e87aa4c49e95	493	__IO uint32_t PTPTSLUR;
phungductung	0:e87aa4c49e95	494	__IO uint32_t PTPTSAR;
phungductung	0:e87aa4c49e95	495	__IO uint32_t PTPTTHR;
phungductung	0:e87aa4c49e95	496	__IO uint32_t PTPTTLR;
phungductung	0:e87aa4c49e95	497	__IO uint32_t RESERVED8;
phungductung	0:e87aa4c49e95	498	__IO uint32_t PTPTSSR;
phungductung	0:e87aa4c49e95	499	uint32_t RESERVED9[565];
phungductung	0:e87aa4c49e95	500	__IO uint32_t DMABMR;
phungductung	0:e87aa4c49e95	501	__IO uint32_t DMATPDR;
phungductung	0:e87aa4c49e95	502	__IO uint32_t DMARPDR;
phungductung	0:e87aa4c49e95	503	__IO uint32_t DMARDLAR;
phungductung	0:e87aa4c49e95	504	__IO uint32_t DMATDLAR;
phungductung	0:e87aa4c49e95	505	__IO uint32_t DMASR;
phungductung	0:e87aa4c49e95	506	__IO uint32_t DMAOMR;
phungductung	0:e87aa4c49e95	507	__IO uint32_t DMAIER;
phungductung	0:e87aa4c49e95	508	__IO uint32_t DMAMFBOCR;
phungductung	0:e87aa4c49e95	509	__IO uint32_t DMARSWTR;
phungductung	0:e87aa4c49e95	510	uint32_t RESERVED10[8];
phungductung	0:e87aa4c49e95	511	__IO uint32_t DMACHTDR;
phungductung	0:e87aa4c49e95	512	__IO uint32_t DMACHRDR;
phungductung	0:e87aa4c49e95	513	__IO uint32_t DMACHTBAR;
phungductung	0:e87aa4c49e95	514	__IO uint32_t DMACHRBAR;
phungductung	0:e87aa4c49e95	515	} ETH_TypeDef;
phungductung	0:e87aa4c49e95	516
phungductung	0:e87aa4c49e95	517	/**
phungductung	0:e87aa4c49e95	518	* @brief External Interrupt/Event Controller
phungductung	0:e87aa4c49e95	519	*/
phungductung	0:e87aa4c49e95	520
phungductung	0:e87aa4c49e95	521	typedef struct
phungductung	0:e87aa4c49e95	522	{
phungductung	0:e87aa4c49e95	523	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	524	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	525	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	526	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	527	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	528	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	529	} EXTI_TypeDef;
phungductung	0:e87aa4c49e95	530
phungductung	0:e87aa4c49e95	531	/**
phungductung	0:e87aa4c49e95	532	* @brief FLASH Registers
phungductung	0:e87aa4c49e95	533	*/
phungductung	0:e87aa4c49e95	534
phungductung	0:e87aa4c49e95	535	typedef struct
phungductung	0:e87aa4c49e95	536	{
phungductung	0:e87aa4c49e95	537	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	538	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	539	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	540	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	541	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	542	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
phungductung	0:e87aa4c49e95	543	__IO uint32_t OPTCR1; /!< FLASH option control register 1 , Address offset: 0x18 /
phungductung	0:e87aa4c49e95	544	} FLASH_TypeDef;
phungductung	0:e87aa4c49e95	545
phungductung	0:e87aa4c49e95	546
phungductung	0:e87aa4c49e95	547
phungductung	0:e87aa4c49e95	548	/**
phungductung	0:e87aa4c49e95	549	* @brief Flexible Memory Controller
phungductung	0:e87aa4c49e95	550	*/
phungductung	0:e87aa4c49e95	551
phungductung	0:e87aa4c49e95	552	typedef struct
phungductung	0:e87aa4c49e95	553	{
phungductung	0:e87aa4c49e95	554	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
phungductung	0:e87aa4c49e95	555	} FMC_Bank1_TypeDef;
phungductung	0:e87aa4c49e95	556
phungductung	0:e87aa4c49e95	557	/**
phungductung	0:e87aa4c49e95	558	* @brief Flexible Memory Controller Bank1E
phungductung	0:e87aa4c49e95	559	*/
phungductung	0:e87aa4c49e95	560
phungductung	0:e87aa4c49e95	561	typedef struct
phungductung	0:e87aa4c49e95	562	{
phungductung	0:e87aa4c49e95	563	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
phungductung	0:e87aa4c49e95	564	} FMC_Bank1E_TypeDef;
phungductung	0:e87aa4c49e95	565
phungductung	0:e87aa4c49e95	566	/**
phungductung	0:e87aa4c49e95	567	* @brief Flexible Memory Controller Bank3
phungductung	0:e87aa4c49e95	568	*/
phungductung	0:e87aa4c49e95	569
phungductung	0:e87aa4c49e95	570	typedef struct
phungductung	0:e87aa4c49e95	571	{
phungductung	0:e87aa4c49e95	572	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
phungductung	0:e87aa4c49e95	573	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
phungductung	0:e87aa4c49e95	574	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
phungductung	0:e87aa4c49e95	575	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
phungductung	0:e87aa4c49e95	576	uint32_t RESERVED0; /!< Reserved, 0x90 /
phungductung	0:e87aa4c49e95	577	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
phungductung	0:e87aa4c49e95	578	} FMC_Bank3_TypeDef;
phungductung	0:e87aa4c49e95	579
phungductung	0:e87aa4c49e95	580	/**
phungductung	0:e87aa4c49e95	581	* @brief Flexible Memory Controller Bank5_6
phungductung	0:e87aa4c49e95	582	*/
phungductung	0:e87aa4c49e95	583
phungductung	0:e87aa4c49e95	584	typedef struct
phungductung	0:e87aa4c49e95	585	{
phungductung	0:e87aa4c49e95	586	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
phungductung	0:e87aa4c49e95	587	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
phungductung	0:e87aa4c49e95	588	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
phungductung	0:e87aa4c49e95	589	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
phungductung	0:e87aa4c49e95	590	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
phungductung	0:e87aa4c49e95	591	} FMC_Bank5_6_TypeDef;
phungductung	0:e87aa4c49e95	592
phungductung	0:e87aa4c49e95	593
phungductung	0:e87aa4c49e95	594	/**
phungductung	0:e87aa4c49e95	595	* @brief General Purpose I/O
phungductung	0:e87aa4c49e95	596	*/
phungductung	0:e87aa4c49e95	597
phungductung	0:e87aa4c49e95	598	typedef struct
phungductung	0:e87aa4c49e95	599	{
phungductung	0:e87aa4c49e95	600	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	601	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	602	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	603	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	604	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	605	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	606	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	607	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	608	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
phungductung	0:e87aa4c49e95	609	} GPIO_TypeDef;
phungductung	0:e87aa4c49e95	610
phungductung	0:e87aa4c49e95	611	/**
phungductung	0:e87aa4c49e95	612	* @brief System configuration controller
phungductung	0:e87aa4c49e95	613	*/
phungductung	0:e87aa4c49e95	614
phungductung	0:e87aa4c49e95	615	typedef struct
phungductung	0:e87aa4c49e95	616	{
phungductung	0:e87aa4c49e95	617	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	618	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	619	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
phungductung	0:e87aa4c49e95	620	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
phungductung	0:e87aa4c49e95	621	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	622	} SYSCFG_TypeDef;
phungductung	0:e87aa4c49e95	623
phungductung	0:e87aa4c49e95	624	/**
phungductung	0:e87aa4c49e95	625	* @brief Inter-integrated Circuit Interface
phungductung	0:e87aa4c49e95	626	*/
phungductung	0:e87aa4c49e95	627
phungductung	0:e87aa4c49e95	628	typedef struct
phungductung	0:e87aa4c49e95	629	{
phungductung	0:e87aa4c49e95	630	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	631	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	632	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	633	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	634	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	635	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	636	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	637	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	638	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	639	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	640	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	641	} I2C_TypeDef;
phungductung	0:e87aa4c49e95	642
phungductung	0:e87aa4c49e95	643	/**
phungductung	0:e87aa4c49e95	644	* @brief Independent WATCHDOG
phungductung	0:e87aa4c49e95	645	*/
phungductung	0:e87aa4c49e95	646
phungductung	0:e87aa4c49e95	647	typedef struct
phungductung	0:e87aa4c49e95	648	{
phungductung	0:e87aa4c49e95	649	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	650	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	651	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	652	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	653	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	654	} IWDG_TypeDef;
phungductung	0:e87aa4c49e95	655
phungductung	0:e87aa4c49e95	656
phungductung	0:e87aa4c49e95	657	/**
phungductung	0:e87aa4c49e95	658	* @brief LCD-TFT Display Controller
phungductung	0:e87aa4c49e95	659	*/
phungductung	0:e87aa4c49e95	660
phungductung	0:e87aa4c49e95	661	typedef struct
phungductung	0:e87aa4c49e95	662	{
phungductung	0:e87aa4c49e95	663	uint32_t RESERVED0[2]; /!< Reserved, 0x00-0x04 /
phungductung	0:e87aa4c49e95	664	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	665	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	666	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	667	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	668	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	669	uint32_t RESERVED1[2]; /!< Reserved, 0x1C-0x20 /
phungductung	0:e87aa4c49e95	670	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	671	uint32_t RESERVED2[1]; /!< Reserved, 0x28 /
phungductung	0:e87aa4c49e95	672	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	673	uint32_t RESERVED3[1]; /!< Reserved, 0x30 /
phungductung	0:e87aa4c49e95	674	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	675	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
phungductung	0:e87aa4c49e95	676	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
phungductung	0:e87aa4c49e95	677	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
phungductung	0:e87aa4c49e95	678	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
phungductung	0:e87aa4c49e95	679	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
phungductung	0:e87aa4c49e95	680	} LTDC_TypeDef;
phungductung	0:e87aa4c49e95	681
phungductung	0:e87aa4c49e95	682	/**
phungductung	0:e87aa4c49e95	683	* @brief LCD-TFT Display layer x Controller
phungductung	0:e87aa4c49e95	684	*/
phungductung	0:e87aa4c49e95	685
phungductung	0:e87aa4c49e95	686	typedef struct
phungductung	0:e87aa4c49e95	687	{
phungductung	0:e87aa4c49e95	688	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
phungductung	0:e87aa4c49e95	689	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
phungductung	0:e87aa4c49e95	690	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
phungductung	0:e87aa4c49e95	691	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
phungductung	0:e87aa4c49e95	692	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
phungductung	0:e87aa4c49e95	693	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
phungductung	0:e87aa4c49e95	694	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
phungductung	0:e87aa4c49e95	695	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
phungductung	0:e87aa4c49e95	696	uint32_t RESERVED0[2]; /!< Reserved /
phungductung	0:e87aa4c49e95	697	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
phungductung	0:e87aa4c49e95	698	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
phungductung	0:e87aa4c49e95	699	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
phungductung	0:e87aa4c49e95	700	uint32_t RESERVED1[3]; /!< Reserved /
phungductung	0:e87aa4c49e95	701	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144 /
phungductung	0:e87aa4c49e95	702
phungductung	0:e87aa4c49e95	703	} LTDC_Layer_TypeDef;
phungductung	0:e87aa4c49e95	704
phungductung	0:e87aa4c49e95	705	/**
phungductung	0:e87aa4c49e95	706	* @brief Power Control
phungductung	0:e87aa4c49e95	707	*/
phungductung	0:e87aa4c49e95	708
phungductung	0:e87aa4c49e95	709	typedef struct
phungductung	0:e87aa4c49e95	710	{
phungductung	0:e87aa4c49e95	711	__IO uint32_t CR1; /!< PWR power control register 1, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	712	__IO uint32_t CSR1; /!< PWR power control/status register 2, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	713	__IO uint32_t CR2; /!< PWR power control register 2, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	714	__IO uint32_t CSR2; /!< PWR power control/status register 2, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	715	} PWR_TypeDef;
phungductung	0:e87aa4c49e95	716
phungductung	0:e87aa4c49e95	717
phungductung	0:e87aa4c49e95	718	/**
phungductung	0:e87aa4c49e95	719	* @brief Reset and Clock Control
phungductung	0:e87aa4c49e95	720	*/
phungductung	0:e87aa4c49e95	721
phungductung	0:e87aa4c49e95	722	typedef struct
phungductung	0:e87aa4c49e95	723	{
phungductung	0:e87aa4c49e95	724	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	725	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	726	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	727	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	728	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	729	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	730	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	731	uint32_t RESERVED0; /!< Reserved, 0x1C /
phungductung	0:e87aa4c49e95	732	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	733	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	734	uint32_t RESERVED1[2]; /!< Reserved, 0x28-0x2C /
phungductung	0:e87aa4c49e95	735	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	736	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	737	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
phungductung	0:e87aa4c49e95	738	uint32_t RESERVED2; /!< Reserved, 0x3C /
phungductung	0:e87aa4c49e95	739	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
phungductung	0:e87aa4c49e95	740	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
phungductung	0:e87aa4c49e95	741	uint32_t RESERVED3[2]; /!< Reserved, 0x48-0x4C /
phungductung	0:e87aa4c49e95	742	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
phungductung	0:e87aa4c49e95	743	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
phungductung	0:e87aa4c49e95	744	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
phungductung	0:e87aa4c49e95	745	uint32_t RESERVED4; /!< Reserved, 0x5C /
phungductung	0:e87aa4c49e95	746	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
phungductung	0:e87aa4c49e95	747	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
phungductung	0:e87aa4c49e95	748	uint32_t RESERVED5[2]; /!< Reserved, 0x68-0x6C /
phungductung	0:e87aa4c49e95	749	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
phungductung	0:e87aa4c49e95	750	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
phungductung	0:e87aa4c49e95	751	uint32_t RESERVED6[2]; /!< Reserved, 0x78-0x7C /
phungductung	0:e87aa4c49e95	752	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
phungductung	0:e87aa4c49e95	753	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
phungductung	0:e87aa4c49e95	754	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
phungductung	0:e87aa4c49e95	755	__IO uint32_t DCKCFGR1; /!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C /
phungductung	0:e87aa4c49e95	756	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 /
phungductung	0:e87aa4c49e95	757
phungductung	0:e87aa4c49e95	758	} RCC_TypeDef;
phungductung	0:e87aa4c49e95	759
phungductung	0:e87aa4c49e95	760	/**
phungductung	0:e87aa4c49e95	761	* @brief Real-Time Clock
phungductung	0:e87aa4c49e95	762	*/
phungductung	0:e87aa4c49e95	763
phungductung	0:e87aa4c49e95	764	typedef struct
phungductung	0:e87aa4c49e95	765	{
phungductung	0:e87aa4c49e95	766	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	767	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	768	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	769	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	770	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	771	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	772	uint32_t reserved; /!< Reserved /
phungductung	0:e87aa4c49e95	773	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	774	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	775	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	776	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	777	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	778	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	779	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	780	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
phungductung	0:e87aa4c49e95	781	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
phungductung	0:e87aa4c49e95	782	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
phungductung	0:e87aa4c49e95	783	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
phungductung	0:e87aa4c49e95	784	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
phungductung	0:e87aa4c49e95	785	__IO uint32_t OR; /!< RTC option register, Address offset: 0x4C /
phungductung	0:e87aa4c49e95	786	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
phungductung	0:e87aa4c49e95	787	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
phungductung	0:e87aa4c49e95	788	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
phungductung	0:e87aa4c49e95	789	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
phungductung	0:e87aa4c49e95	790	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
phungductung	0:e87aa4c49e95	791	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
phungductung	0:e87aa4c49e95	792	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
phungductung	0:e87aa4c49e95	793	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
phungductung	0:e87aa4c49e95	794	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
phungductung	0:e87aa4c49e95	795	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
phungductung	0:e87aa4c49e95	796	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
phungductung	0:e87aa4c49e95	797	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
phungductung	0:e87aa4c49e95	798	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
phungductung	0:e87aa4c49e95	799	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
phungductung	0:e87aa4c49e95	800	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
phungductung	0:e87aa4c49e95	801	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
phungductung	0:e87aa4c49e95	802	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
phungductung	0:e87aa4c49e95	803	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
phungductung	0:e87aa4c49e95	804	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
phungductung	0:e87aa4c49e95	805	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
phungductung	0:e87aa4c49e95	806	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
phungductung	0:e87aa4c49e95	807	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
phungductung	0:e87aa4c49e95	808	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
phungductung	0:e87aa4c49e95	809	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
phungductung	0:e87aa4c49e95	810	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
phungductung	0:e87aa4c49e95	811	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
phungductung	0:e87aa4c49e95	812	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
phungductung	0:e87aa4c49e95	813	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
phungductung	0:e87aa4c49e95	814	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
phungductung	0:e87aa4c49e95	815	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
phungductung	0:e87aa4c49e95	816	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
phungductung	0:e87aa4c49e95	817	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
phungductung	0:e87aa4c49e95	818	} RTC_TypeDef;
phungductung	0:e87aa4c49e95	819
phungductung	0:e87aa4c49e95	820
phungductung	0:e87aa4c49e95	821	/**
phungductung	0:e87aa4c49e95	822	* @brief Serial Audio Interface
phungductung	0:e87aa4c49e95	823	*/
phungductung	0:e87aa4c49e95	824
phungductung	0:e87aa4c49e95	825	typedef struct
phungductung	0:e87aa4c49e95	826	{
phungductung	0:e87aa4c49e95	827	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	828	} SAI_TypeDef;
phungductung	0:e87aa4c49e95	829
phungductung	0:e87aa4c49e95	830	typedef struct
phungductung	0:e87aa4c49e95	831	{
phungductung	0:e87aa4c49e95	832	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	833	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	834	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	835	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	836	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	837	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	838	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	839	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	840	} SAI_Block_TypeDef;
phungductung	0:e87aa4c49e95	841
phungductung	0:e87aa4c49e95	842	/**
phungductung	0:e87aa4c49e95	843	* @brief SPDIF-RX Interface
phungductung	0:e87aa4c49e95	844	*/
phungductung	0:e87aa4c49e95	845
phungductung	0:e87aa4c49e95	846	typedef struct
phungductung	0:e87aa4c49e95	847	{
phungductung	0:e87aa4c49e95	848	__IO uint32_t CR; /!< Control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	849	__IO uint32_t IMR; /!< Interrupt mask register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	850	__IO uint32_t SR; /!< Status register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	851	__IO uint32_t IFCR; /!< Interrupt Flag Clear register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	852	__IO uint32_t DR; /!< Data input register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	853	__IO uint32_t CSR; /!< Channel Status register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	854	__IO uint32_t DIR; /!< Debug Information register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	855	} SPDIFRX_TypeDef;
phungductung	0:e87aa4c49e95	856
phungductung	0:e87aa4c49e95	857
phungductung	0:e87aa4c49e95	858	/**
phungductung	0:e87aa4c49e95	859	* @brief SD host Interface
phungductung	0:e87aa4c49e95	860	*/
phungductung	0:e87aa4c49e95	861
phungductung	0:e87aa4c49e95	862	typedef struct
phungductung	0:e87aa4c49e95	863	{
phungductung	0:e87aa4c49e95	864	__IO uint32_t POWER; /!< SDMMC power control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	865	__IO uint32_t CLKCR; /!< SDMMClock control register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	866	__IO uint32_t ARG; /!< SDMMC argument register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	867	__IO uint32_t CMD; /!< SDMMC command register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	868	__I uint32_t RESPCMD; /!< SDMMC command response register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	869	__I uint32_t RESP1; /!< SDMMC response 1 register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	870	__I uint32_t RESP2; /!< SDMMC response 2 register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	871	__I uint32_t RESP3; /!< SDMMC response 3 register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	872	__I uint32_t RESP4; /!< SDMMC response 4 register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	873	__IO uint32_t DTIMER; /!< SDMMC data timer register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	874	__IO uint32_t DLEN; /!< SDMMC data length register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	875	__IO uint32_t DCTRL; /!< SDMMC data control register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	876	__I uint32_t DCOUNT; /!< SDMMC data counter register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	877	__I uint32_t STA; /!< SDMMC status register, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	878	__IO uint32_t ICR; /!< SDMMC interrupt clear register, Address offset: 0x38 /
phungductung	0:e87aa4c49e95	879	__IO uint32_t MASK; /!< SDMMC mask register, Address offset: 0x3C /
phungductung	0:e87aa4c49e95	880	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
phungductung	0:e87aa4c49e95	881	__I uint32_t FIFOCNT; /!< SDMMC FIFO counter register, Address offset: 0x48 /
phungductung	0:e87aa4c49e95	882	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
phungductung	0:e87aa4c49e95	883	__IO uint32_t FIFO; /!< SDMMC data FIFO register, Address offset: 0x80 /
phungductung	0:e87aa4c49e95	884	} SDMMC_TypeDef;
phungductung	0:e87aa4c49e95	885
phungductung	0:e87aa4c49e95	886	/**
phungductung	0:e87aa4c49e95	887	* @brief Serial Peripheral Interface
phungductung	0:e87aa4c49e95	888	*/
phungductung	0:e87aa4c49e95	889
phungductung	0:e87aa4c49e95	890	typedef struct
phungductung	0:e87aa4c49e95	891	{
phungductung	0:e87aa4c49e95	892	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
phungductung	0:e87aa4c49e95	893	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	894	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	895	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	896	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
phungductung	0:e87aa4c49e95	897	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
phungductung	0:e87aa4c49e95	898	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
phungductung	0:e87aa4c49e95	899	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	900	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	901	} SPI_TypeDef;
phungductung	0:e87aa4c49e95	902
phungductung	0:e87aa4c49e95	903	/**
phungductung	0:e87aa4c49e95	904	* @brief QUAD Serial Peripheral Interface
phungductung	0:e87aa4c49e95	905	*/
phungductung	0:e87aa4c49e95	906
phungductung	0:e87aa4c49e95	907	typedef struct
phungductung	0:e87aa4c49e95	908	{
phungductung	0:e87aa4c49e95	909	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	910	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	911	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	912	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	913	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	914	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	915	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	916	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	917	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	918	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	919	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	920	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	921	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	922	} QUADSPI_TypeDef;
phungductung	0:e87aa4c49e95	923
phungductung	0:e87aa4c49e95	924	/**
phungductung	0:e87aa4c49e95	925	* @brief TIM
phungductung	0:e87aa4c49e95	926	*/
phungductung	0:e87aa4c49e95	927
phungductung	0:e87aa4c49e95	928	typedef struct
phungductung	0:e87aa4c49e95	929	{
phungductung	0:e87aa4c49e95	930	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	931	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	932	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	933	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	934	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	935	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	936	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	937	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	938	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	939	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	940	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	941	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
phungductung	0:e87aa4c49e95	942	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
phungductung	0:e87aa4c49e95	943	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
phungductung	0:e87aa4c49e95	944	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
phungductung	0:e87aa4c49e95	945	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
phungductung	0:e87aa4c49e95	946	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
phungductung	0:e87aa4c49e95	947	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
phungductung	0:e87aa4c49e95	948	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
phungductung	0:e87aa4c49e95	949	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
phungductung	0:e87aa4c49e95	950	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
phungductung	0:e87aa4c49e95	951	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
phungductung	0:e87aa4c49e95	952	__IO uint32_t CCR5; /!< TIM capture/compare mode register5, Address offset: 0x58 /
phungductung	0:e87aa4c49e95	953	__IO uint32_t CCR6; /!< TIM capture/compare mode register6, Address offset: 0x5C /
phungductung	0:e87aa4c49e95	954
phungductung	0:e87aa4c49e95	955	} TIM_TypeDef;
phungductung	0:e87aa4c49e95	956
phungductung	0:e87aa4c49e95	957	/**
phungductung	0:e87aa4c49e95	958	* @brief LPTIMIMER
phungductung	0:e87aa4c49e95	959	*/
phungductung	0:e87aa4c49e95	960	typedef struct
phungductung	0:e87aa4c49e95	961	{
phungductung	0:e87aa4c49e95	962	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	963	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	964	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	965	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	966	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	967	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	968	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	969	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	970	} LPTIM_TypeDef;
phungductung	0:e87aa4c49e95	971
phungductung	0:e87aa4c49e95	972
phungductung	0:e87aa4c49e95	973	/**
phungductung	0:e87aa4c49e95	974	* @brief Universal Synchronous Asynchronous Receiver Transmitter
phungductung	0:e87aa4c49e95	975	*/
phungductung	0:e87aa4c49e95	976
phungductung	0:e87aa4c49e95	977	typedef struct
phungductung	0:e87aa4c49e95	978	{
phungductung	0:e87aa4c49e95	979	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	980	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	981	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	982	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
phungductung	0:e87aa4c49e95	983	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
phungductung	0:e87aa4c49e95	984	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
phungductung	0:e87aa4c49e95	985	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
phungductung	0:e87aa4c49e95	986	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
phungductung	0:e87aa4c49e95	987	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
phungductung	0:e87aa4c49e95	988	__IO uint32_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
phungductung	0:e87aa4c49e95	989	__IO uint32_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
phungductung	0:e87aa4c49e95	990	} USART_TypeDef;
phungductung	0:e87aa4c49e95	991
phungductung	0:e87aa4c49e95	992
phungductung	0:e87aa4c49e95	993	/**
phungductung	0:e87aa4c49e95	994	* @brief Window WATCHDOG
phungductung	0:e87aa4c49e95	995	*/
phungductung	0:e87aa4c49e95	996
phungductung	0:e87aa4c49e95	997	typedef struct
phungductung	0:e87aa4c49e95	998	{
phungductung	0:e87aa4c49e95	999	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	1000	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	1001	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	1002	} WWDG_TypeDef;
phungductung	0:e87aa4c49e95	1003
phungductung	0:e87aa4c49e95	1004
phungductung	0:e87aa4c49e95	1005	/**
phungductung	0:e87aa4c49e95	1006	* @brief RNG
phungductung	0:e87aa4c49e95	1007	*/
phungductung	0:e87aa4c49e95	1008
phungductung	0:e87aa4c49e95	1009	typedef struct
phungductung	0:e87aa4c49e95	1010	{
phungductung	0:e87aa4c49e95	1011	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
phungductung	0:e87aa4c49e95	1012	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
phungductung	0:e87aa4c49e95	1013	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
phungductung	0:e87aa4c49e95	1014	} RNG_TypeDef;
phungductung	0:e87aa4c49e95	1015
phungductung	0:e87aa4c49e95	1016	/**
phungductung	0:e87aa4c49e95	1017	* @}
phungductung	0:e87aa4c49e95	1018	*/
phungductung	0:e87aa4c49e95	1019
phungductung	0:e87aa4c49e95	1020	/**
phungductung	0:e87aa4c49e95	1021	* @brief USB_OTG_Core_Registers
phungductung	0:e87aa4c49e95	1022	*/
phungductung	0:e87aa4c49e95	1023	typedef struct
phungductung	0:e87aa4c49e95	1024	{
phungductung	0:e87aa4c49e95	1025	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
phungductung	0:e87aa4c49e95	1026	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
phungductung	0:e87aa4c49e95	1027	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
phungductung	0:e87aa4c49e95	1028	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
phungductung	0:e87aa4c49e95	1029	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
phungductung	0:e87aa4c49e95	1030	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
phungductung	0:e87aa4c49e95	1031	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
phungductung	0:e87aa4c49e95	1032	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
phungductung	0:e87aa4c49e95	1033	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
phungductung	0:e87aa4c49e95	1034	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
phungductung	0:e87aa4c49e95	1035	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
phungductung	0:e87aa4c49e95	1036	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
phungductung	0:e87aa4c49e95	1037	uint32_t Reserved30[2]; /!< Reserved 030h /
phungductung	0:e87aa4c49e95	1038	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
phungductung	0:e87aa4c49e95	1039	__IO uint32_t CID; /!< User ID Register 03Ch /
phungductung	0:e87aa4c49e95	1040	uint32_t Reserved5[3]; /!< Reserved 040h-048h /
phungductung	0:e87aa4c49e95	1041	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
phungductung	0:e87aa4c49e95	1042	uint32_t Reserved6; /!< Reserved 050h /
phungductung	0:e87aa4c49e95	1043	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
phungductung	0:e87aa4c49e95	1044	__IO uint32_t GPWRDN; /!< Power Down Register 058h /
phungductung	0:e87aa4c49e95	1045	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
phungductung	0:e87aa4c49e95	1046	__IO uint32_t GADPCTL; /!< ADP Timer, Control and Status Register 60Ch /
phungductung	0:e87aa4c49e95	1047	uint32_t Reserved43[39]; /!< Reserved 058h-0FFh /
phungductung	0:e87aa4c49e95	1048	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
phungductung	0:e87aa4c49e95	1049	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
phungductung	0:e87aa4c49e95	1050	} USB_OTG_GlobalTypeDef;
phungductung	0:e87aa4c49e95	1051
phungductung	0:e87aa4c49e95	1052
phungductung	0:e87aa4c49e95	1053	/**
phungductung	0:e87aa4c49e95	1054	* @brief USB_OTG_device_Registers
phungductung	0:e87aa4c49e95	1055	*/
phungductung	0:e87aa4c49e95	1056	typedef struct
phungductung	0:e87aa4c49e95	1057	{
phungductung	0:e87aa4c49e95	1058	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
phungductung	0:e87aa4c49e95	1059	__IO uint32_t DCTL; /!< dev Control Register 804h /
phungductung	0:e87aa4c49e95	1060	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
phungductung	0:e87aa4c49e95	1061	uint32_t Reserved0C; /!< Reserved 80Ch /
phungductung	0:e87aa4c49e95	1062	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
phungductung	0:e87aa4c49e95	1063	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
phungductung	0:e87aa4c49e95	1064	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
phungductung	0:e87aa4c49e95	1065	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
phungductung	0:e87aa4c49e95	1066	uint32_t Reserved20; /!< Reserved 820h /
phungductung	0:e87aa4c49e95	1067	uint32_t Reserved9; /!< Reserved 824h /
phungductung	0:e87aa4c49e95	1068	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
phungductung	0:e87aa4c49e95	1069	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
phungductung	0:e87aa4c49e95	1070	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
phungductung	0:e87aa4c49e95	1071	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
phungductung	0:e87aa4c49e95	1072	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
phungductung	0:e87aa4c49e95	1073	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
phungductung	0:e87aa4c49e95	1074	uint32_t Reserved40; /!< dedicated EP mask 840h /
phungductung	0:e87aa4c49e95	1075	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
phungductung	0:e87aa4c49e95	1076	uint32_t Reserved44[15]; /!< Reserved 844-87Ch /
phungductung	0:e87aa4c49e95	1077	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
phungductung	0:e87aa4c49e95	1078	} USB_OTG_DeviceTypeDef;
phungductung	0:e87aa4c49e95	1079
phungductung	0:e87aa4c49e95	1080
phungductung	0:e87aa4c49e95	1081	/**
phungductung	0:e87aa4c49e95	1082	* @brief USB_OTG_IN_Endpoint-Specific_Register
phungductung	0:e87aa4c49e95	1083	*/
phungductung	0:e87aa4c49e95	1084	typedef struct
phungductung	0:e87aa4c49e95	1085	{
phungductung	0:e87aa4c49e95	1086	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
phungductung	0:e87aa4c49e95	1087	uint32_t Reserved04; /!< Reserved 900h + (ep_num 20h) + 04h */
phungductung	0:e87aa4c49e95	1088	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
phungductung	0:e87aa4c49e95	1089	uint32_t Reserved0C; /!< Reserved 900h + (ep_num 20h) + 0Ch */
phungductung	0:e87aa4c49e95	1090	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
phungductung	0:e87aa4c49e95	1091	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
phungductung	0:e87aa4c49e95	1092	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
phungductung	0:e87aa4c49e95	1093	uint32_t Reserved18; /!< Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
phungductung	0:e87aa4c49e95	1094	} USB_OTG_INEndpointTypeDef;
phungductung	0:e87aa4c49e95	1095
phungductung	0:e87aa4c49e95	1096
phungductung	0:e87aa4c49e95	1097	/**
phungductung	0:e87aa4c49e95	1098	* @brief USB_OTG_OUT_Endpoint-Specific_Registers
phungductung	0:e87aa4c49e95	1099	*/
phungductung	0:e87aa4c49e95	1100	typedef struct
phungductung	0:e87aa4c49e95	1101	{
phungductung	0:e87aa4c49e95	1102	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
phungductung	0:e87aa4c49e95	1103	uint32_t Reserved04; /!< Reserved B00h + (ep_num 20h) + 04h */
phungductung	0:e87aa4c49e95	1104	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
phungductung	0:e87aa4c49e95	1105	uint32_t Reserved0C; /!< Reserved B00h + (ep_num 20h) + 0Ch */
phungductung	0:e87aa4c49e95	1106	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
phungductung	0:e87aa4c49e95	1107	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
phungductung	0:e87aa4c49e95	1108	uint32_t Reserved18[2]; /!< Reserved B00h + (ep_num 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
phungductung	0:e87aa4c49e95	1109	} USB_OTG_OUTEndpointTypeDef;
phungductung	0:e87aa4c49e95	1110
phungductung	0:e87aa4c49e95	1111
phungductung	0:e87aa4c49e95	1112	/**
phungductung	0:e87aa4c49e95	1113	* @brief USB_OTG_Host_Mode_Register_Structures
phungductung	0:e87aa4c49e95	1114	*/
phungductung	0:e87aa4c49e95	1115	typedef struct
phungductung	0:e87aa4c49e95	1116	{
phungductung	0:e87aa4c49e95	1117	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
phungductung	0:e87aa4c49e95	1118	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
phungductung	0:e87aa4c49e95	1119	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
phungductung	0:e87aa4c49e95	1120	uint32_t Reserved40C; /!< Reserved 40Ch /
phungductung	0:e87aa4c49e95	1121	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
phungductung	0:e87aa4c49e95	1122	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
phungductung	0:e87aa4c49e95	1123	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
phungductung	0:e87aa4c49e95	1124	} USB_OTG_HostTypeDef;
phungductung	0:e87aa4c49e95	1125
phungductung	0:e87aa4c49e95	1126	/**
phungductung	0:e87aa4c49e95	1127	* @brief USB_OTG_Host_Channel_Specific_Registers
phungductung	0:e87aa4c49e95	1128	*/
phungductung	0:e87aa4c49e95	1129	typedef struct
phungductung	0:e87aa4c49e95	1130	{
phungductung	0:e87aa4c49e95	1131	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
phungductung	0:e87aa4c49e95	1132	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
phungductung	0:e87aa4c49e95	1133	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
phungductung	0:e87aa4c49e95	1134	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
phungductung	0:e87aa4c49e95	1135	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
phungductung	0:e87aa4c49e95	1136	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
phungductung	0:e87aa4c49e95	1137	uint32_t Reserved[2]; /!< Reserved /
phungductung	0:e87aa4c49e95	1138	} USB_OTG_HostChannelTypeDef;
phungductung	0:e87aa4c49e95	1139	/**
phungductung	0:e87aa4c49e95	1140	* @}
phungductung	0:e87aa4c49e95	1141	*/
phungductung	0:e87aa4c49e95	1142
phungductung	0:e87aa4c49e95	1143
phungductung	0:e87aa4c49e95	1144
phungductung	0:e87aa4c49e95	1145	/** @addtogroup Peripheral_memory_map
phungductung	0:e87aa4c49e95	1146	* @{
phungductung	0:e87aa4c49e95	1147	*/
phungductung	0:e87aa4c49e95	1148	#define RAMITCM_BASE ((uint32_t)0x00000000) /!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM /
phungductung	0:e87aa4c49e95	1149	#define FLASHITCM_BASE ((uint32_t)0x00200000) /!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM /
phungductung	0:e87aa4c49e95	1150	#define FLASHAXI_BASE ((uint32_t)0x08000000) /!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI /
phungductung	0:e87aa4c49e95	1151	#define RAMDTCM_BASE ((uint32_t)0x20000000) /!< Base address of : 64KB system data RAM accessible over DTCM /
phungductung	0:e87aa4c49e95	1152	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Base address of : AHB/ABP Peripherals /
phungductung	0:e87aa4c49e95	1153	#define BKPSRAM_BASE ((uint32_t)0x40024000) /!< Base address of : Backup SRAM(4 KB) /
phungductung	0:e87aa4c49e95	1154	#define QSPI_BASE ((uint32_t)0x90000000) /!< Base address of : QSPI memories accessible over AXI /
phungductung	0:e87aa4c49e95	1155	#define FMC_R_BASE ((uint32_t)0xA0000000) /!< Base address of : FMC Control registers /
phungductung	0:e87aa4c49e95	1156	#define QSPI_R_BASE ((uint32_t)0xA0001000) /!< Base address of : QSPI Control registers /
phungductung	0:e87aa4c49e95	1157	#define SRAM1_BASE ((uint32_t)0x20010000) /!< Base address of : 240KB RAM1 accessible over AXI/AHB /
phungductung	0:e87aa4c49e95	1158	#define SRAM2_BASE ((uint32_t)0x2004C000) /!< Base address of : 16KB RAM2 accessible over AXI/AHB /
phungductung	0:e87aa4c49e95	1159	#define FLASH_END ((uint32_t)0x080FFFFF) /!< FLASH end address /
phungductung	0:e87aa4c49e95	1160
phungductung	0:e87aa4c49e95	1161	/* Legacy define */
phungductung	0:e87aa4c49e95	1162	#define FLASH_BASE FLASHAXI_BASE
phungductung	0:e87aa4c49e95	1163
phungductung	0:e87aa4c49e95	1164	/!< Peripheral memory map /
phungductung	0:e87aa4c49e95	1165	#define APB1PERIPH_BASE PERIPH_BASE
phungductung	0:e87aa4c49e95	1166	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
phungductung	0:e87aa4c49e95	1167	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
phungductung	0:e87aa4c49e95	1168	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
phungductung	0:e87aa4c49e95	1169
phungductung	0:e87aa4c49e95	1170	/!< APB1 peripherals /
phungductung	0:e87aa4c49e95	1171	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
phungductung	0:e87aa4c49e95	1172	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
phungductung	0:e87aa4c49e95	1173	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
phungductung	0:e87aa4c49e95	1174	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
phungductung	0:e87aa4c49e95	1175	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
phungductung	0:e87aa4c49e95	1176	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
phungductung	0:e87aa4c49e95	1177	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
phungductung	0:e87aa4c49e95	1178	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
phungductung	0:e87aa4c49e95	1179	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
phungductung	0:e87aa4c49e95	1180	#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
phungductung	0:e87aa4c49e95	1181	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
phungductung	0:e87aa4c49e95	1182	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
phungductung	0:e87aa4c49e95	1183	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
phungductung	0:e87aa4c49e95	1184	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
phungductung	0:e87aa4c49e95	1185	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
phungductung	0:e87aa4c49e95	1186	#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
phungductung	0:e87aa4c49e95	1187	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
phungductung	0:e87aa4c49e95	1188	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
phungductung	0:e87aa4c49e95	1189	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
phungductung	0:e87aa4c49e95	1190	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
phungductung	0:e87aa4c49e95	1191	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
phungductung	0:e87aa4c49e95	1192	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
phungductung	0:e87aa4c49e95	1193	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
phungductung	0:e87aa4c49e95	1194	#define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
phungductung	0:e87aa4c49e95	1195	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
phungductung	0:e87aa4c49e95	1196	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
phungductung	0:e87aa4c49e95	1197	#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
phungductung	0:e87aa4c49e95	1198	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
phungductung	0:e87aa4c49e95	1199	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
phungductung	0:e87aa4c49e95	1200	#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
phungductung	0:e87aa4c49e95	1201	#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
phungductung	0:e87aa4c49e95	1202
phungductung	0:e87aa4c49e95	1203	/!< APB2 peripherals /
phungductung	0:e87aa4c49e95	1204	#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
phungductung	0:e87aa4c49e95	1205	#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
phungductung	0:e87aa4c49e95	1206	#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
phungductung	0:e87aa4c49e95	1207	#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
phungductung	0:e87aa4c49e95	1208	#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
phungductung	0:e87aa4c49e95	1209	#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
phungductung	0:e87aa4c49e95	1210	#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
phungductung	0:e87aa4c49e95	1211	#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
phungductung	0:e87aa4c49e95	1212	#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
phungductung	0:e87aa4c49e95	1213	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
phungductung	0:e87aa4c49e95	1214	#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
phungductung	0:e87aa4c49e95	1215	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
phungductung	0:e87aa4c49e95	1216	#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
phungductung	0:e87aa4c49e95	1217	#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
phungductung	0:e87aa4c49e95	1218	#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
phungductung	0:e87aa4c49e95	1219	#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
phungductung	0:e87aa4c49e95	1220	#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
phungductung	0:e87aa4c49e95	1221	#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
phungductung	0:e87aa4c49e95	1222	#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
phungductung	0:e87aa4c49e95	1223	#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
phungductung	0:e87aa4c49e95	1224	#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
phungductung	0:e87aa4c49e95	1225	#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
phungductung	0:e87aa4c49e95	1226	#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
phungductung	0:e87aa4c49e95	1227	#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
phungductung	0:e87aa4c49e95	1228	#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
phungductung	0:e87aa4c49e95	1229	#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
phungductung	0:e87aa4c49e95	1230	#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
phungductung	0:e87aa4c49e95	1231	/!< AHB1 peripherals /
phungductung	0:e87aa4c49e95	1232	#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
phungductung	0:e87aa4c49e95	1233	#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
phungductung	0:e87aa4c49e95	1234	#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
phungductung	0:e87aa4c49e95	1235	#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
phungductung	0:e87aa4c49e95	1236	#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
phungductung	0:e87aa4c49e95	1237	#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
phungductung	0:e87aa4c49e95	1238	#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
phungductung	0:e87aa4c49e95	1239	#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
phungductung	0:e87aa4c49e95	1240	#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
phungductung	0:e87aa4c49e95	1241	#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
phungductung	0:e87aa4c49e95	1242	#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
phungductung	0:e87aa4c49e95	1243	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
phungductung	0:e87aa4c49e95	1244	#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
phungductung	0:e87aa4c49e95	1245	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
phungductung	0:e87aa4c49e95	1246	#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
phungductung	0:e87aa4c49e95	1247	#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
phungductung	0:e87aa4c49e95	1248	#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
phungductung	0:e87aa4c49e95	1249	#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
phungductung	0:e87aa4c49e95	1250	#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
phungductung	0:e87aa4c49e95	1251	#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
phungductung	0:e87aa4c49e95	1252	#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
phungductung	0:e87aa4c49e95	1253	#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
phungductung	0:e87aa4c49e95	1254	#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
phungductung	0:e87aa4c49e95	1255	#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
phungductung	0:e87aa4c49e95	1256	#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
phungductung	0:e87aa4c49e95	1257	#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
phungductung	0:e87aa4c49e95	1258	#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
phungductung	0:e87aa4c49e95	1259	#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
phungductung	0:e87aa4c49e95	1260	#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
phungductung	0:e87aa4c49e95	1261	#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
phungductung	0:e87aa4c49e95	1262	#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
phungductung	0:e87aa4c49e95	1263	#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
phungductung	0:e87aa4c49e95	1264	#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
phungductung	0:e87aa4c49e95	1265	#define ETH_MAC_BASE (ETH_BASE)
phungductung	0:e87aa4c49e95	1266	#define ETH_MMC_BASE (ETH_BASE + 0x0100)
phungductung	0:e87aa4c49e95	1267	#define ETH_PTP_BASE (ETH_BASE + 0x0700)
phungductung	0:e87aa4c49e95	1268	#define ETH_DMA_BASE (ETH_BASE + 0x1000)
phungductung	0:e87aa4c49e95	1269	#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
phungductung	0:e87aa4c49e95	1270	/!< AHB2 peripherals /
phungductung	0:e87aa4c49e95	1271	#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
phungductung	0:e87aa4c49e95	1272	#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
phungductung	0:e87aa4c49e95	1273	/!< FMC Bankx registers base address /
phungductung	0:e87aa4c49e95	1274	#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
phungductung	0:e87aa4c49e95	1275	#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
phungductung	0:e87aa4c49e95	1276	#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
phungductung	0:e87aa4c49e95	1277	#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
phungductung	0:e87aa4c49e95	1278
phungductung	0:e87aa4c49e95	1279	/* Debug MCU registers base address */
phungductung	0:e87aa4c49e95	1280	#define DBGMCU_BASE ((uint32_t )0xE0042000)
phungductung	0:e87aa4c49e95	1281
phungductung	0:e87aa4c49e95	1282	/!< USB registers base address /
phungductung	0:e87aa4c49e95	1283	#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
phungductung	0:e87aa4c49e95	1284	#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
phungductung	0:e87aa4c49e95	1285
phungductung	0:e87aa4c49e95	1286	#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
phungductung	0:e87aa4c49e95	1287	#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
phungductung	0:e87aa4c49e95	1288	#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
phungductung	0:e87aa4c49e95	1289	#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
phungductung	0:e87aa4c49e95	1290	#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
phungductung	0:e87aa4c49e95	1291	#define USB_OTG_HOST_BASE ((uint32_t )0x400)
phungductung	0:e87aa4c49e95	1292	#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
phungductung	0:e87aa4c49e95	1293	#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
phungductung	0:e87aa4c49e95	1294	#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
phungductung	0:e87aa4c49e95	1295	#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
phungductung	0:e87aa4c49e95	1296	#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
phungductung	0:e87aa4c49e95	1297	#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
phungductung	0:e87aa4c49e95	1298
phungductung	0:e87aa4c49e95	1299	/**
phungductung	0:e87aa4c49e95	1300	* @}
phungductung	0:e87aa4c49e95	1301	*/
phungductung	0:e87aa4c49e95	1302
phungductung	0:e87aa4c49e95	1303	/** @addtogroup Peripheral_declaration
phungductung	0:e87aa4c49e95	1304	* @{
phungductung	0:e87aa4c49e95	1305	*/
phungductung	0:e87aa4c49e95	1306	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
phungductung	0:e87aa4c49e95	1307	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
phungductung	0:e87aa4c49e95	1308	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
phungductung	0:e87aa4c49e95	1309	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
phungductung	0:e87aa4c49e95	1310	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
phungductung	0:e87aa4c49e95	1311	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
phungductung	0:e87aa4c49e95	1312	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
phungductung	0:e87aa4c49e95	1313	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
phungductung	0:e87aa4c49e95	1314	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
phungductung	0:e87aa4c49e95	1315	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
phungductung	0:e87aa4c49e95	1316	#define RTC ((RTC_TypeDef *) RTC_BASE)
phungductung	0:e87aa4c49e95	1317	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
phungductung	0:e87aa4c49e95	1318	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
phungductung	0:e87aa4c49e95	1319	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
phungductung	0:e87aa4c49e95	1320	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
phungductung	0:e87aa4c49e95	1321	#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
phungductung	0:e87aa4c49e95	1322	#define USART2 ((USART_TypeDef *) USART2_BASE)
phungductung	0:e87aa4c49e95	1323	#define USART3 ((USART_TypeDef *) USART3_BASE)
phungductung	0:e87aa4c49e95	1324	#define UART4 ((USART_TypeDef *) UART4_BASE)
phungductung	0:e87aa4c49e95	1325	#define UART5 ((USART_TypeDef *) UART5_BASE)
phungductung	0:e87aa4c49e95	1326	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
phungductung	0:e87aa4c49e95	1327	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
phungductung	0:e87aa4c49e95	1328	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
phungductung	0:e87aa4c49e95	1329	#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
phungductung	0:e87aa4c49e95	1330	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
phungductung	0:e87aa4c49e95	1331	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
phungductung	0:e87aa4c49e95	1332	#define CEC ((CEC_TypeDef *) CEC_BASE)
phungductung	0:e87aa4c49e95	1333	#define PWR ((PWR_TypeDef *) PWR_BASE)
phungductung	0:e87aa4c49e95	1334	#define DAC ((DAC_TypeDef *) DAC_BASE)
phungductung	0:e87aa4c49e95	1335	#define UART7 ((USART_TypeDef *) UART7_BASE)
phungductung	0:e87aa4c49e95	1336	#define UART8 ((USART_TypeDef *) UART8_BASE)
phungductung	0:e87aa4c49e95	1337	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
phungductung	0:e87aa4c49e95	1338	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
phungductung	0:e87aa4c49e95	1339	#define USART1 ((USART_TypeDef *) USART1_BASE)
phungductung	0:e87aa4c49e95	1340	#define USART6 ((USART_TypeDef *) USART6_BASE)
phungductung	0:e87aa4c49e95	1341	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
phungductung	0:e87aa4c49e95	1342	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
phungductung	0:e87aa4c49e95	1343	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
phungductung	0:e87aa4c49e95	1344	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
phungductung	0:e87aa4c49e95	1345	#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
phungductung	0:e87aa4c49e95	1346	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
phungductung	0:e87aa4c49e95	1347	#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
phungductung	0:e87aa4c49e95	1348	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
phungductung	0:e87aa4c49e95	1349	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
phungductung	0:e87aa4c49e95	1350	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
phungductung	0:e87aa4c49e95	1351	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
phungductung	0:e87aa4c49e95	1352	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
phungductung	0:e87aa4c49e95	1353	#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
phungductung	0:e87aa4c49e95	1354	#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
phungductung	0:e87aa4c49e95	1355	#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
phungductung	0:e87aa4c49e95	1356	#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
phungductung	0:e87aa4c49e95	1357	#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
phungductung	0:e87aa4c49e95	1358	#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
phungductung	0:e87aa4c49e95	1359	#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
phungductung	0:e87aa4c49e95	1360	#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
phungductung	0:e87aa4c49e95	1361	#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
phungductung	0:e87aa4c49e95	1362	#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
phungductung	0:e87aa4c49e95	1363	#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
phungductung	0:e87aa4c49e95	1364	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
phungductung	0:e87aa4c49e95	1365	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
phungductung	0:e87aa4c49e95	1366	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
phungductung	0:e87aa4c49e95	1367	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
phungductung	0:e87aa4c49e95	1368	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
phungductung	0:e87aa4c49e95	1369	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
phungductung	0:e87aa4c49e95	1370	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
phungductung	0:e87aa4c49e95	1371	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
phungductung	0:e87aa4c49e95	1372	#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
phungductung	0:e87aa4c49e95	1373	#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
phungductung	0:e87aa4c49e95	1374	#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
phungductung	0:e87aa4c49e95	1375	#define CRC ((CRC_TypeDef *) CRC_BASE)
phungductung	0:e87aa4c49e95	1376	#define RCC ((RCC_TypeDef *) RCC_BASE)
phungductung	0:e87aa4c49e95	1377	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
phungductung	0:e87aa4c49e95	1378	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
phungductung	0:e87aa4c49e95	1379	#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
phungductung	0:e87aa4c49e95	1380	#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
phungductung	0:e87aa4c49e95	1381	#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
phungductung	0:e87aa4c49e95	1382	#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
phungductung	0:e87aa4c49e95	1383	#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
phungductung	0:e87aa4c49e95	1384	#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
phungductung	0:e87aa4c49e95	1385	#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
phungductung	0:e87aa4c49e95	1386	#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
phungductung	0:e87aa4c49e95	1387	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
phungductung	0:e87aa4c49e95	1388	#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
phungductung	0:e87aa4c49e95	1389	#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
phungductung	0:e87aa4c49e95	1390	#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
phungductung	0:e87aa4c49e95	1391	#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
phungductung	0:e87aa4c49e95	1392	#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
phungductung	0:e87aa4c49e95	1393	#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
phungductung	0:e87aa4c49e95	1394	#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
phungductung	0:e87aa4c49e95	1395	#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
phungductung	0:e87aa4c49e95	1396	#define ETH ((ETH_TypeDef *) ETH_BASE)
phungductung	0:e87aa4c49e95	1397	#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
phungductung	0:e87aa4c49e95	1398	#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
phungductung	0:e87aa4c49e95	1399	#define RNG ((RNG_TypeDef *) RNG_BASE)
phungductung	0:e87aa4c49e95	1400	#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
phungductung	0:e87aa4c49e95	1401	#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
phungductung	0:e87aa4c49e95	1402	#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
phungductung	0:e87aa4c49e95	1403	#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
phungductung	0:e87aa4c49e95	1404	#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
phungductung	0:e87aa4c49e95	1405	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
phungductung	0:e87aa4c49e95	1406	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
phungductung	0:e87aa4c49e95	1407	#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
phungductung	0:e87aa4c49e95	1408
phungductung	0:e87aa4c49e95	1409	/**
phungductung	0:e87aa4c49e95	1410	* @}
phungductung	0:e87aa4c49e95	1411	*/
phungductung	0:e87aa4c49e95	1412
phungductung	0:e87aa4c49e95	1413	/** @addtogroup Exported_constants
phungductung	0:e87aa4c49e95	1414	* @{
phungductung	0:e87aa4c49e95	1415	*/
phungductung	0:e87aa4c49e95	1416
phungductung	0:e87aa4c49e95	1417	/** @addtogroup Peripheral_Registers_Bits_Definition
phungductung	0:e87aa4c49e95	1418	* @{
phungductung	0:e87aa4c49e95	1419	*/
phungductung	0:e87aa4c49e95	1420
phungductung	0:e87aa4c49e95	1421	/******************************************************************************/
phungductung	0:e87aa4c49e95	1422	/* Peripheral Registers_Bits_Definition */
phungductung	0:e87aa4c49e95	1423	/******************************************************************************/
phungductung	0:e87aa4c49e95	1424
phungductung	0:e87aa4c49e95	1425	/******************************************************************************/
phungductung	0:e87aa4c49e95	1426	/* */
phungductung	0:e87aa4c49e95	1427	/* Analog to Digital Converter */
phungductung	0:e87aa4c49e95	1428	/* */
phungductung	0:e87aa4c49e95	1429	/******************************************************************************/
phungductung	0:e87aa4c49e95	1430	/****************** Bit definition for ADC_SR register ******************/
phungductung	0:e87aa4c49e95	1431	#define ADC_SR_AWD ((uint32_t)0x00000001) /!<Analog watchdog flag /
phungductung	0:e87aa4c49e95	1432	#define ADC_SR_EOC ((uint32_t)0x00000002) /!<End of conversion /
phungductung	0:e87aa4c49e95	1433	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!<Injected channel end of conversion /
phungductung	0:e87aa4c49e95	1434	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!<Injected channel Start flag /
phungductung	0:e87aa4c49e95	1435	#define ADC_SR_STRT ((uint32_t)0x00000010) /!<Regular channel Start flag /
phungductung	0:e87aa4c49e95	1436	#define ADC_SR_OVR ((uint32_t)0x00000020) /!<Overrun flag /
phungductung	0:e87aa4c49e95	1437
phungductung	0:e87aa4c49e95	1438	/***************** Bit definition for ADC_CR1 register ******************/
phungductung	0:e87aa4c49e95	1439	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!<AWDCH[4:0] bits (Analog watchdog channel select bits) /
phungductung	0:e87aa4c49e95	1440	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1441	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1442	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1443	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1444	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1445	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!<Interrupt enable for EOC /
phungductung	0:e87aa4c49e95	1446	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!<AAnalog Watchdog interrupt enable /
phungductung	0:e87aa4c49e95	1447	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!<Interrupt enable for injected channels /
phungductung	0:e87aa4c49e95	1448	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!<Scan mode /
phungductung	0:e87aa4c49e95	1449	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!<Enable the watchdog on a single channel in scan mode /
phungductung	0:e87aa4c49e95	1450	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!<Automatic injected group conversion /
phungductung	0:e87aa4c49e95	1451	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!<Discontinuous mode on regular channels /
phungductung	0:e87aa4c49e95	1452	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!<Discontinuous mode on injected channels /
phungductung	0:e87aa4c49e95	1453	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!<DISCNUM[2:0] bits (Discontinuous mode channel count) /
phungductung	0:e87aa4c49e95	1454	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1455	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1456	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1457	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!<Analog watchdog enable on injected channels /
phungductung	0:e87aa4c49e95	1458	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!<Analog watchdog enable on regular channels /
phungductung	0:e87aa4c49e95	1459	#define ADC_CR1_RES ((uint32_t)0x03000000) /!<RES[2:0] bits (Resolution) /
phungductung	0:e87aa4c49e95	1460	#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1461	#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1462	#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /!<overrun interrupt enable /
phungductung	0:e87aa4c49e95	1463
phungductung	0:e87aa4c49e95	1464	/***************** Bit definition for ADC_CR2 register ******************/
phungductung	0:e87aa4c49e95	1465	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!<A/D Converter ON / OFF /
phungductung	0:e87aa4c49e95	1466	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!<Continuous Conversion /
phungductung	0:e87aa4c49e95	1467	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!<Direct Memory access mode /
phungductung	0:e87aa4c49e95	1468	#define ADC_CR2_DDS ((uint32_t)0x00000200) /!<DMA disable selection (Single ADC) /
phungductung	0:e87aa4c49e95	1469	#define ADC_CR2_EOCS ((uint32_t)0x00000400) /!<End of conversion selection /
phungductung	0:e87aa4c49e95	1470	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!<Data Alignment /
phungductung	0:e87aa4c49e95	1471	#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /!<JEXTSEL[3:0] bits (External event select for injected group) /
phungductung	0:e87aa4c49e95	1472	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1473	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1474	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1475	#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1476	#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) /
phungductung	0:e87aa4c49e95	1477	#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1478	#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1479	#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /!<Start Conversion of injected channels /
phungductung	0:e87aa4c49e95	1480	#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /!<EXTSEL[3:0] bits (External Event Select for regular group) /
phungductung	0:e87aa4c49e95	1481	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1482	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1483	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1484	#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1485	#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) /
phungductung	0:e87aa4c49e95	1486	#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1487	#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1488	#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /!<Start Conversion of regular channels /
phungductung	0:e87aa4c49e95	1489
phungductung	0:e87aa4c49e95	1490	/**************** Bit definition for ADC_SMPR1 register *****************/
phungductung	0:e87aa4c49e95	1491	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!<SMP10[2:0] bits (Channel 10 Sample time selection) /
phungductung	0:e87aa4c49e95	1492	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1493	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1494	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1495	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!<SMP11[2:0] bits (Channel 11 Sample time selection) /
phungductung	0:e87aa4c49e95	1496	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1497	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1498	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1499	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!<SMP12[2:0] bits (Channel 12 Sample time selection) /
phungductung	0:e87aa4c49e95	1500	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1501	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1502	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1503	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!<SMP13[2:0] bits (Channel 13 Sample time selection) /
phungductung	0:e87aa4c49e95	1504	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1505	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1506	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1507	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!<SMP14[2:0] bits (Channel 14 Sample time selection) /
phungductung	0:e87aa4c49e95	1508	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1509	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1510	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1511	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!<SMP15[2:0] bits (Channel 15 Sample time selection) /
phungductung	0:e87aa4c49e95	1512	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1513	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1514	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1515	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!<SMP16[2:0] bits (Channel 16 Sample time selection) /
phungductung	0:e87aa4c49e95	1516	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1517	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1518	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1519	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!<SMP17[2:0] bits (Channel 17 Sample time selection) /
phungductung	0:e87aa4c49e95	1520	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1521	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1522	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1523	#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /!<SMP18[2:0] bits (Channel 18 Sample time selection) /
phungductung	0:e87aa4c49e95	1524	#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1525	#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1526	#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1527
phungductung	0:e87aa4c49e95	1528	/**************** Bit definition for ADC_SMPR2 register *****************/
phungductung	0:e87aa4c49e95	1529	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!<SMP0[2:0] bits (Channel 0 Sample time selection) /
phungductung	0:e87aa4c49e95	1530	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1531	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1532	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1533	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!<SMP1[2:0] bits (Channel 1 Sample time selection) /
phungductung	0:e87aa4c49e95	1534	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1535	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1536	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1537	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!<SMP2[2:0] bits (Channel 2 Sample time selection) /
phungductung	0:e87aa4c49e95	1538	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1539	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1540	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1541	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!<SMP3[2:0] bits (Channel 3 Sample time selection) /
phungductung	0:e87aa4c49e95	1542	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1543	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1544	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1545	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!<SMP4[2:0] bits (Channel 4 Sample time selection) /
phungductung	0:e87aa4c49e95	1546	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1547	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1548	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1549	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!<SMP5[2:0] bits (Channel 5 Sample time selection) /
phungductung	0:e87aa4c49e95	1550	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1551	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1552	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1553	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!<SMP6[2:0] bits (Channel 6 Sample time selection) /
phungductung	0:e87aa4c49e95	1554	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1555	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1556	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1557	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!<SMP7[2:0] bits (Channel 7 Sample time selection) /
phungductung	0:e87aa4c49e95	1558	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1559	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1560	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1561	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!<SMP8[2:0] bits (Channel 8 Sample time selection) /
phungductung	0:e87aa4c49e95	1562	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1563	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1564	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1565	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!<SMP9[2:0] bits (Channel 9 Sample time selection) /
phungductung	0:e87aa4c49e95	1566	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1567	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1568	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1569
phungductung	0:e87aa4c49e95	1570	/**************** Bit definition for ADC_JOFR1 register *****************/
phungductung	0:e87aa4c49e95	1571	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /!<Data offset for injected channel 1 /
phungductung	0:e87aa4c49e95	1572
phungductung	0:e87aa4c49e95	1573	/**************** Bit definition for ADC_JOFR2 register *****************/
phungductung	0:e87aa4c49e95	1574	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /!<Data offset for injected channel 2 /
phungductung	0:e87aa4c49e95	1575
phungductung	0:e87aa4c49e95	1576	/**************** Bit definition for ADC_JOFR3 register *****************/
phungductung	0:e87aa4c49e95	1577	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /!<Data offset for injected channel 3 /
phungductung	0:e87aa4c49e95	1578
phungductung	0:e87aa4c49e95	1579	/**************** Bit definition for ADC_JOFR4 register *****************/
phungductung	0:e87aa4c49e95	1580	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /!<Data offset for injected channel 4 /
phungductung	0:e87aa4c49e95	1581
phungductung	0:e87aa4c49e95	1582	/***************** Bit definition for ADC_HTR register ******************/
phungductung	0:e87aa4c49e95	1583	#define ADC_HTR_HT ((uint32_t)0x0FFF) /!<Analog watchdog high threshold /
phungductung	0:e87aa4c49e95	1584
phungductung	0:e87aa4c49e95	1585	/***************** Bit definition for ADC_LTR register ******************/
phungductung	0:e87aa4c49e95	1586	#define ADC_LTR_LT ((uint32_t)0x0FFF) /!<Analog watchdog low threshold /
phungductung	0:e87aa4c49e95	1587
phungductung	0:e87aa4c49e95	1588	/***************** Bit definition for ADC_SQR1 register *****************/
phungductung	0:e87aa4c49e95	1589	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!<SQ13[4:0] bits (13th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1590	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1591	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1592	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1593	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1594	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1595	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!<SQ14[4:0] bits (14th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1596	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1597	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1598	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1599	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1600	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1601	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!<SQ15[4:0] bits (15th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1602	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1603	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1604	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1605	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1606	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1607	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!<SQ16[4:0] bits (16th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1608	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1609	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1610	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1611	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1612	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1613	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!<L[3:0] bits (Regular channel sequence length) /
phungductung	0:e87aa4c49e95	1614	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1615	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1616	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1617	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1618
phungductung	0:e87aa4c49e95	1619	/***************** Bit definition for ADC_SQR2 register *****************/
phungductung	0:e87aa4c49e95	1620	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!<SQ7[4:0] bits (7th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1621	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1622	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1623	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1624	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1625	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1626	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!<SQ8[4:0] bits (8th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1627	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1628	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1629	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1630	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1631	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1632	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!<SQ9[4:0] bits (9th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1633	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1634	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1635	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1636	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1637	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1638	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!<SQ10[4:0] bits (10th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1639	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1640	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1641	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1642	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1643	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1644	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!<SQ11[4:0] bits (11th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1645	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1646	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1647	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1648	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1649	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1650	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!<SQ12[4:0] bits (12th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1651	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1652	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1653	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1654	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1655	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1656
phungductung	0:e87aa4c49e95	1657	/***************** Bit definition for ADC_SQR3 register *****************/
phungductung	0:e87aa4c49e95	1658	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!<SQ1[4:0] bits (1st conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1659	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1660	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1661	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1662	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1663	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1664	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!<SQ2[4:0] bits (2nd conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1665	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1666	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1667	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1668	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1669	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1670	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!<SQ3[4:0] bits (3rd conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1671	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1672	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1673	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1674	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1675	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1676	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!<SQ4[4:0] bits (4th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1677	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1678	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1679	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1680	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1681	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1682	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!<SQ5[4:0] bits (5th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1683	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1684	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1685	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1686	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1687	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1688	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!<SQ6[4:0] bits (6th conversion in regular sequence) /
phungductung	0:e87aa4c49e95	1689	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1690	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1691	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1692	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1693	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1694
phungductung	0:e87aa4c49e95	1695	/***************** Bit definition for ADC_JSQR register *****************/
phungductung	0:e87aa4c49e95	1696	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!<JSQ1[4:0] bits (1st conversion in injected sequence) /
phungductung	0:e87aa4c49e95	1697	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1698	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1699	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1700	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1701	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1702	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!<JSQ2[4:0] bits (2nd conversion in injected sequence) /
phungductung	0:e87aa4c49e95	1703	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1704	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1705	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1706	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1707	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1708	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!<JSQ3[4:0] bits (3rd conversion in injected sequence) /
phungductung	0:e87aa4c49e95	1709	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1710	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1711	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1712	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1713	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1714	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!<JSQ4[4:0] bits (4th conversion in injected sequence) /
phungductung	0:e87aa4c49e95	1715	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1716	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1717	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1718	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1719	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1720	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!<JL[1:0] bits (Injected Sequence length) /
phungductung	0:e87aa4c49e95	1721	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1722	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1723
phungductung	0:e87aa4c49e95	1724	/***************** Bit definition for ADC_JDR1 register *****************/
phungductung	0:e87aa4c49e95	1725	#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /!<Injected data /
phungductung	0:e87aa4c49e95	1726
phungductung	0:e87aa4c49e95	1727	/***************** Bit definition for ADC_JDR2 register *****************/
phungductung	0:e87aa4c49e95	1728	#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /!<Injected data /
phungductung	0:e87aa4c49e95	1729
phungductung	0:e87aa4c49e95	1730	/***************** Bit definition for ADC_JDR3 register *****************/
phungductung	0:e87aa4c49e95	1731	#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /!<Injected data /
phungductung	0:e87aa4c49e95	1732
phungductung	0:e87aa4c49e95	1733	/***************** Bit definition for ADC_JDR4 register *****************/
phungductung	0:e87aa4c49e95	1734	#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /!<Injected data /
phungductung	0:e87aa4c49e95	1735
phungductung	0:e87aa4c49e95	1736	/****************** Bit definition for ADC_DR register ******************/
phungductung	0:e87aa4c49e95	1737	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!<Regular data /
phungductung	0:e87aa4c49e95	1738	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!<ADC2 data /
phungductung	0:e87aa4c49e95	1739
phungductung	0:e87aa4c49e95	1740	/***************** Bit definition for ADC_CSR register ******************/
phungductung	0:e87aa4c49e95	1741	#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /!<ADC1 Analog watchdog flag /
phungductung	0:e87aa4c49e95	1742	#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /!<ADC1 End of conversion /
phungductung	0:e87aa4c49e95	1743	#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /!<ADC1 Injected channel end of conversion /
phungductung	0:e87aa4c49e95	1744	#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /!<ADC1 Injected channel Start flag /
phungductung	0:e87aa4c49e95	1745	#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /!<ADC1 Regular channel Start flag /
phungductung	0:e87aa4c49e95	1746	#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /!<ADC1 DMA overrun flag /
phungductung	0:e87aa4c49e95	1747	#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /!<ADC2 Analog watchdog flag /
phungductung	0:e87aa4c49e95	1748	#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /!<ADC2 End of conversion /
phungductung	0:e87aa4c49e95	1749	#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /!<ADC2 Injected channel end of conversion /
phungductung	0:e87aa4c49e95	1750	#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /!<ADC2 Injected channel Start flag /
phungductung	0:e87aa4c49e95	1751	#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /!<ADC2 Regular channel Start flag /
phungductung	0:e87aa4c49e95	1752	#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /!<ADC2 DMA overrun flag /
phungductung	0:e87aa4c49e95	1753	#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /!<ADC3 Analog watchdog flag /
phungductung	0:e87aa4c49e95	1754	#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /!<ADC3 End of conversion /
phungductung	0:e87aa4c49e95	1755	#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /!<ADC3 Injected channel end of conversion /
phungductung	0:e87aa4c49e95	1756	#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /!<ADC3 Injected channel Start flag /
phungductung	0:e87aa4c49e95	1757	#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /!<ADC3 Regular channel Start flag /
phungductung	0:e87aa4c49e95	1758	#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /!<ADC3 DMA overrun flag /
phungductung	0:e87aa4c49e95	1759
phungductung	0:e87aa4c49e95	1760	/***************** Bit definition for ADC_CCR register ******************/
phungductung	0:e87aa4c49e95	1761	#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /!<MULTI[4:0] bits (Multi-ADC mode selection) /
phungductung	0:e87aa4c49e95	1762	#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1763	#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1764	#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1765	#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1766	#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	1767	#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /!<DELAY[3:0] bits (Delay between 2 sampling phases) /
phungductung	0:e87aa4c49e95	1768	#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1769	#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1770	#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1771	#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1772	#define ADC_CCR_DDS ((uint32_t)0x00002000) /!<DMA disable selection (Multi-ADC mode) /
phungductung	0:e87aa4c49e95	1773	#define ADC_CCR_DMA ((uint32_t)0x0000C000) /!<DMA[1:0] bits (Direct Memory Access mode for multimode) /
phungductung	0:e87aa4c49e95	1774	#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1775	#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1776	#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /!<ADCPRE[1:0] bits (ADC prescaler) /
phungductung	0:e87aa4c49e95	1777	#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1778	#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1779	#define ADC_CCR_VBATE ((uint32_t)0x00400000) /!<VBAT Enable /
phungductung	0:e87aa4c49e95	1780	#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /!<Temperature Sensor and VREFINT Enable /
phungductung	0:e87aa4c49e95	1781
phungductung	0:e87aa4c49e95	1782	/***************** Bit definition for ADC_CDR register ******************/
phungductung	0:e87aa4c49e95	1783	#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /!<1st data of a pair of regular conversions /
phungductung	0:e87aa4c49e95	1784	#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /!<2nd data of a pair of regular conversions /
phungductung	0:e87aa4c49e95	1785
phungductung	0:e87aa4c49e95	1786	/******************************************************************************/
phungductung	0:e87aa4c49e95	1787	/* */
phungductung	0:e87aa4c49e95	1788	/* Controller Area Network */
phungductung	0:e87aa4c49e95	1789	/* */
phungductung	0:e87aa4c49e95	1790	/******************************************************************************/
phungductung	0:e87aa4c49e95	1791	/!<CAN control and status registers /
phungductung	0:e87aa4c49e95	1792	/***************** Bit definition for CAN_MCR register ******************/
phungductung	0:e87aa4c49e95	1793	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!<Initialization Request /
phungductung	0:e87aa4c49e95	1794	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!<Sleep Mode Request /
phungductung	0:e87aa4c49e95	1795	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!<Transmit FIFO Priority /
phungductung	0:e87aa4c49e95	1796	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!<Receive FIFO Locked Mode /
phungductung	0:e87aa4c49e95	1797	#define CAN_MCR_NART ((uint32_t)0x00000010) /!<No Automatic Retransmission /
phungductung	0:e87aa4c49e95	1798	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!<Automatic Wakeup Mode /
phungductung	0:e87aa4c49e95	1799	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!<Automatic Bus-Off Management /
phungductung	0:e87aa4c49e95	1800	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!<Time Triggered Communication Mode /
phungductung	0:e87aa4c49e95	1801	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!<bxCAN software master reset /
phungductung	0:e87aa4c49e95	1802
phungductung	0:e87aa4c49e95	1803	/***************** Bit definition for CAN_MSR register ******************/
phungductung	0:e87aa4c49e95	1804	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!<Initialization Acknowledge /
phungductung	0:e87aa4c49e95	1805	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!<Sleep Acknowledge /
phungductung	0:e87aa4c49e95	1806	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!<Error Interrupt /
phungductung	0:e87aa4c49e95	1807	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!<Wakeup Interrupt /
phungductung	0:e87aa4c49e95	1808	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!<Sleep Acknowledge Interrupt /
phungductung	0:e87aa4c49e95	1809	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!<Transmit Mode /
phungductung	0:e87aa4c49e95	1810	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!<Receive Mode /
phungductung	0:e87aa4c49e95	1811	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!<Last Sample Point /
phungductung	0:e87aa4c49e95	1812	#define CAN_MSR_RX ((uint32_t)0x00000800) /!<CAN Rx Signal /
phungductung	0:e87aa4c49e95	1813
phungductung	0:e87aa4c49e95	1814	/***************** Bit definition for CAN_TSR register ******************/
phungductung	0:e87aa4c49e95	1815	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
phungductung	0:e87aa4c49e95	1816	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
phungductung	0:e87aa4c49e95	1817	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
phungductung	0:e87aa4c49e95	1818	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
phungductung	0:e87aa4c49e95	1819	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
phungductung	0:e87aa4c49e95	1820	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
phungductung	0:e87aa4c49e95	1821	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
phungductung	0:e87aa4c49e95	1822	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
phungductung	0:e87aa4c49e95	1823	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
phungductung	0:e87aa4c49e95	1824	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
phungductung	0:e87aa4c49e95	1825	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
phungductung	0:e87aa4c49e95	1826	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
phungductung	0:e87aa4c49e95	1827	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
phungductung	0:e87aa4c49e95	1828	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
phungductung	0:e87aa4c49e95	1829	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
phungductung	0:e87aa4c49e95	1830	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
phungductung	0:e87aa4c49e95	1831
phungductung	0:e87aa4c49e95	1832	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
phungductung	0:e87aa4c49e95	1833	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
phungductung	0:e87aa4c49e95	1834	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
phungductung	0:e87aa4c49e95	1835	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
phungductung	0:e87aa4c49e95	1836
phungductung	0:e87aa4c49e95	1837	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
phungductung	0:e87aa4c49e95	1838	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
phungductung	0:e87aa4c49e95	1839	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
phungductung	0:e87aa4c49e95	1840	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
phungductung	0:e87aa4c49e95	1841
phungductung	0:e87aa4c49e95	1842	/***************** Bit definition for CAN_RF0R register *****************/
phungductung	0:e87aa4c49e95	1843	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!<FIFO 0 Message Pending /
phungductung	0:e87aa4c49e95	1844	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!<FIFO 0 Full /
phungductung	0:e87aa4c49e95	1845	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!<FIFO 0 Overrun /
phungductung	0:e87aa4c49e95	1846	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!<Release FIFO 0 Output Mailbox /
phungductung	0:e87aa4c49e95	1847
phungductung	0:e87aa4c49e95	1848	/***************** Bit definition for CAN_RF1R register *****************/
phungductung	0:e87aa4c49e95	1849	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!<FIFO 1 Message Pending /
phungductung	0:e87aa4c49e95	1850	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!<FIFO 1 Full /
phungductung	0:e87aa4c49e95	1851	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!<FIFO 1 Overrun /
phungductung	0:e87aa4c49e95	1852	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!<Release FIFO 1 Output Mailbox /
phungductung	0:e87aa4c49e95	1853
phungductung	0:e87aa4c49e95	1854	/****************** Bit definition for CAN_IER register *****************/
phungductung	0:e87aa4c49e95	1855	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
phungductung	0:e87aa4c49e95	1856	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
phungductung	0:e87aa4c49e95	1857	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
phungductung	0:e87aa4c49e95	1858	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
phungductung	0:e87aa4c49e95	1859	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
phungductung	0:e87aa4c49e95	1860	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
phungductung	0:e87aa4c49e95	1861	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
phungductung	0:e87aa4c49e95	1862	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
phungductung	0:e87aa4c49e95	1863	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
phungductung	0:e87aa4c49e95	1864	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
phungductung	0:e87aa4c49e95	1865	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
phungductung	0:e87aa4c49e95	1866	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
phungductung	0:e87aa4c49e95	1867	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
phungductung	0:e87aa4c49e95	1868	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
phungductung	0:e87aa4c49e95	1869
phungductung	0:e87aa4c49e95	1870	/****************** Bit definition for CAN_ESR register *****************/
phungductung	0:e87aa4c49e95	1871	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
phungductung	0:e87aa4c49e95	1872	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
phungductung	0:e87aa4c49e95	1873	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
phungductung	0:e87aa4c49e95	1874
phungductung	0:e87aa4c49e95	1875	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
phungductung	0:e87aa4c49e95	1876	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1877	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1878	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1879
phungductung	0:e87aa4c49e95	1880	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
phungductung	0:e87aa4c49e95	1881	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
phungductung	0:e87aa4c49e95	1882
phungductung	0:e87aa4c49e95	1883	/***************** Bit definition for CAN_BTR register ******************/
phungductung	0:e87aa4c49e95	1884	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
phungductung	0:e87aa4c49e95	1885	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
phungductung	0:e87aa4c49e95	1886	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1887	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1888	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1889	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	1890	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
phungductung	0:e87aa4c49e95	1891	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1892	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1893	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	1894	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
phungductung	0:e87aa4c49e95	1895	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	1896	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	1897	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
phungductung	0:e87aa4c49e95	1898	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
phungductung	0:e87aa4c49e95	1899
phungductung	0:e87aa4c49e95	1900	/!<Mailbox registers /
phungductung	0:e87aa4c49e95	1901	/**************** Bit definition for CAN_TI0R register ******************/
phungductung	0:e87aa4c49e95	1902	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
phungductung	0:e87aa4c49e95	1903	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
phungductung	0:e87aa4c49e95	1904	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
phungductung	0:e87aa4c49e95	1905	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
phungductung	0:e87aa4c49e95	1906	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
phungductung	0:e87aa4c49e95	1907
phungductung	0:e87aa4c49e95	1908	/**************** Bit definition for CAN_TDT0R register *****************/
phungductung	0:e87aa4c49e95	1909	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
phungductung	0:e87aa4c49e95	1910	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
phungductung	0:e87aa4c49e95	1911	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
phungductung	0:e87aa4c49e95	1912
phungductung	0:e87aa4c49e95	1913	/**************** Bit definition for CAN_TDL0R register *****************/
phungductung	0:e87aa4c49e95	1914	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
phungductung	0:e87aa4c49e95	1915	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
phungductung	0:e87aa4c49e95	1916	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
phungductung	0:e87aa4c49e95	1917	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
phungductung	0:e87aa4c49e95	1918
phungductung	0:e87aa4c49e95	1919	/**************** Bit definition for CAN_TDH0R register *****************/
phungductung	0:e87aa4c49e95	1920	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
phungductung	0:e87aa4c49e95	1921	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
phungductung	0:e87aa4c49e95	1922	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
phungductung	0:e87aa4c49e95	1923	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
phungductung	0:e87aa4c49e95	1924
phungductung	0:e87aa4c49e95	1925	/***************** Bit definition for CAN_TI1R register *****************/
phungductung	0:e87aa4c49e95	1926	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
phungductung	0:e87aa4c49e95	1927	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
phungductung	0:e87aa4c49e95	1928	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
phungductung	0:e87aa4c49e95	1929	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
phungductung	0:e87aa4c49e95	1930	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
phungductung	0:e87aa4c49e95	1931
phungductung	0:e87aa4c49e95	1932	/***************** Bit definition for CAN_TDT1R register ****************/
phungductung	0:e87aa4c49e95	1933	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
phungductung	0:e87aa4c49e95	1934	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
phungductung	0:e87aa4c49e95	1935	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
phungductung	0:e87aa4c49e95	1936
phungductung	0:e87aa4c49e95	1937	/***************** Bit definition for CAN_TDL1R register ****************/
phungductung	0:e87aa4c49e95	1938	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
phungductung	0:e87aa4c49e95	1939	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
phungductung	0:e87aa4c49e95	1940	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
phungductung	0:e87aa4c49e95	1941	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
phungductung	0:e87aa4c49e95	1942
phungductung	0:e87aa4c49e95	1943	/***************** Bit definition for CAN_TDH1R register ****************/
phungductung	0:e87aa4c49e95	1944	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
phungductung	0:e87aa4c49e95	1945	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
phungductung	0:e87aa4c49e95	1946	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
phungductung	0:e87aa4c49e95	1947	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
phungductung	0:e87aa4c49e95	1948
phungductung	0:e87aa4c49e95	1949	/***************** Bit definition for CAN_TI2R register *****************/
phungductung	0:e87aa4c49e95	1950	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
phungductung	0:e87aa4c49e95	1951	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
phungductung	0:e87aa4c49e95	1952	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
phungductung	0:e87aa4c49e95	1953	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
phungductung	0:e87aa4c49e95	1954	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
phungductung	0:e87aa4c49e95	1955
phungductung	0:e87aa4c49e95	1956	/***************** Bit definition for CAN_TDT2R register ****************/
phungductung	0:e87aa4c49e95	1957	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
phungductung	0:e87aa4c49e95	1958	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
phungductung	0:e87aa4c49e95	1959	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
phungductung	0:e87aa4c49e95	1960
phungductung	0:e87aa4c49e95	1961	/***************** Bit definition for CAN_TDL2R register ****************/
phungductung	0:e87aa4c49e95	1962	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
phungductung	0:e87aa4c49e95	1963	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
phungductung	0:e87aa4c49e95	1964	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
phungductung	0:e87aa4c49e95	1965	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
phungductung	0:e87aa4c49e95	1966
phungductung	0:e87aa4c49e95	1967	/***************** Bit definition for CAN_TDH2R register ****************/
phungductung	0:e87aa4c49e95	1968	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
phungductung	0:e87aa4c49e95	1969	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
phungductung	0:e87aa4c49e95	1970	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
phungductung	0:e87aa4c49e95	1971	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
phungductung	0:e87aa4c49e95	1972
phungductung	0:e87aa4c49e95	1973	/***************** Bit definition for CAN_RI0R register *****************/
phungductung	0:e87aa4c49e95	1974	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
phungductung	0:e87aa4c49e95	1975	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
phungductung	0:e87aa4c49e95	1976	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
phungductung	0:e87aa4c49e95	1977	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
phungductung	0:e87aa4c49e95	1978
phungductung	0:e87aa4c49e95	1979	/***************** Bit definition for CAN_RDT0R register ****************/
phungductung	0:e87aa4c49e95	1980	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
phungductung	0:e87aa4c49e95	1981	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
phungductung	0:e87aa4c49e95	1982	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
phungductung	0:e87aa4c49e95	1983
phungductung	0:e87aa4c49e95	1984	/***************** Bit definition for CAN_RDL0R register ****************/
phungductung	0:e87aa4c49e95	1985	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
phungductung	0:e87aa4c49e95	1986	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
phungductung	0:e87aa4c49e95	1987	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
phungductung	0:e87aa4c49e95	1988	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
phungductung	0:e87aa4c49e95	1989
phungductung	0:e87aa4c49e95	1990	/***************** Bit definition for CAN_RDH0R register ****************/
phungductung	0:e87aa4c49e95	1991	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
phungductung	0:e87aa4c49e95	1992	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
phungductung	0:e87aa4c49e95	1993	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
phungductung	0:e87aa4c49e95	1994	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
phungductung	0:e87aa4c49e95	1995
phungductung	0:e87aa4c49e95	1996	/***************** Bit definition for CAN_RI1R register *****************/
phungductung	0:e87aa4c49e95	1997	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
phungductung	0:e87aa4c49e95	1998	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
phungductung	0:e87aa4c49e95	1999	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
phungductung	0:e87aa4c49e95	2000	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
phungductung	0:e87aa4c49e95	2001
phungductung	0:e87aa4c49e95	2002	/***************** Bit definition for CAN_RDT1R register ****************/
phungductung	0:e87aa4c49e95	2003	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
phungductung	0:e87aa4c49e95	2004	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
phungductung	0:e87aa4c49e95	2005	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
phungductung	0:e87aa4c49e95	2006
phungductung	0:e87aa4c49e95	2007	/***************** Bit definition for CAN_RDL1R register ****************/
phungductung	0:e87aa4c49e95	2008	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
phungductung	0:e87aa4c49e95	2009	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
phungductung	0:e87aa4c49e95	2010	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
phungductung	0:e87aa4c49e95	2011	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
phungductung	0:e87aa4c49e95	2012
phungductung	0:e87aa4c49e95	2013	/***************** Bit definition for CAN_RDH1R register ****************/
phungductung	0:e87aa4c49e95	2014	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
phungductung	0:e87aa4c49e95	2015	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
phungductung	0:e87aa4c49e95	2016	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
phungductung	0:e87aa4c49e95	2017	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
phungductung	0:e87aa4c49e95	2018
phungductung	0:e87aa4c49e95	2019	/!<CAN filter registers /
phungductung	0:e87aa4c49e95	2020	/***************** Bit definition for CAN_FMR register ******************/
phungductung	0:e87aa4c49e95	2021	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
phungductung	0:e87aa4c49e95	2022	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!<CAN2 start bank /
phungductung	0:e87aa4c49e95	2023
phungductung	0:e87aa4c49e95	2024	/***************** Bit definition for CAN_FM1R register *****************/
phungductung	0:e87aa4c49e95	2025	#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /!<Filter Mode /
phungductung	0:e87aa4c49e95	2026	#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /!<Filter Init Mode bit 0 /
phungductung	0:e87aa4c49e95	2027	#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /!<Filter Init Mode bit 1 /
phungductung	0:e87aa4c49e95	2028	#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /!<Filter Init Mode bit 2 /
phungductung	0:e87aa4c49e95	2029	#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /!<Filter Init Mode bit 3 /
phungductung	0:e87aa4c49e95	2030	#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /!<Filter Init Mode bit 4 /
phungductung	0:e87aa4c49e95	2031	#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /!<Filter Init Mode bit 5 /
phungductung	0:e87aa4c49e95	2032	#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /!<Filter Init Mode bit 6 /
phungductung	0:e87aa4c49e95	2033	#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /!<Filter Init Mode bit 7 /
phungductung	0:e87aa4c49e95	2034	#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /!<Filter Init Mode bit 8 /
phungductung	0:e87aa4c49e95	2035	#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /!<Filter Init Mode bit 9 /
phungductung	0:e87aa4c49e95	2036	#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /!<Filter Init Mode bit 10 /
phungductung	0:e87aa4c49e95	2037	#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /!<Filter Init Mode bit 11 /
phungductung	0:e87aa4c49e95	2038	#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /!<Filter Init Mode bit 12 /
phungductung	0:e87aa4c49e95	2039	#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /!<Filter Init Mode bit 13 /
phungductung	0:e87aa4c49e95	2040
phungductung	0:e87aa4c49e95	2041	/***************** Bit definition for CAN_FS1R register *****************/
phungductung	0:e87aa4c49e95	2042	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!<Filter Scale Configuration /
phungductung	0:e87aa4c49e95	2043	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!<Filter Scale Configuration bit 0 /
phungductung	0:e87aa4c49e95	2044	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!<Filter Scale Configuration bit 1 /
phungductung	0:e87aa4c49e95	2045	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!<Filter Scale Configuration bit 2 /
phungductung	0:e87aa4c49e95	2046	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!<Filter Scale Configuration bit 3 /
phungductung	0:e87aa4c49e95	2047	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!<Filter Scale Configuration bit 4 /
phungductung	0:e87aa4c49e95	2048	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!<Filter Scale Configuration bit 5 /
phungductung	0:e87aa4c49e95	2049	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!<Filter Scale Configuration bit 6 /
phungductung	0:e87aa4c49e95	2050	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!<Filter Scale Configuration bit 7 /
phungductung	0:e87aa4c49e95	2051	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!<Filter Scale Configuration bit 8 /
phungductung	0:e87aa4c49e95	2052	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!<Filter Scale Configuration bit 9 /
phungductung	0:e87aa4c49e95	2053	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!<Filter Scale Configuration bit 10 /
phungductung	0:e87aa4c49e95	2054	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!<Filter Scale Configuration bit 11 /
phungductung	0:e87aa4c49e95	2055	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!<Filter Scale Configuration bit 12 /
phungductung	0:e87aa4c49e95	2056	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!<Filter Scale Configuration bit 13 /
phungductung	0:e87aa4c49e95	2057
phungductung	0:e87aa4c49e95	2058	/**************** Bit definition for CAN_FFA1R register *****************/
phungductung	0:e87aa4c49e95	2059	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!<Filter FIFO Assignment /
phungductung	0:e87aa4c49e95	2060	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!<Filter FIFO Assignment for Filter 0 /
phungductung	0:e87aa4c49e95	2061	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!<Filter FIFO Assignment for Filter 1 /
phungductung	0:e87aa4c49e95	2062	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!<Filter FIFO Assignment for Filter 2 /
phungductung	0:e87aa4c49e95	2063	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!<Filter FIFO Assignment for Filter 3 /
phungductung	0:e87aa4c49e95	2064	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!<Filter FIFO Assignment for Filter 4 /
phungductung	0:e87aa4c49e95	2065	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!<Filter FIFO Assignment for Filter 5 /
phungductung	0:e87aa4c49e95	2066	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!<Filter FIFO Assignment for Filter 6 /
phungductung	0:e87aa4c49e95	2067	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!<Filter FIFO Assignment for Filter 7 /
phungductung	0:e87aa4c49e95	2068	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!<Filter FIFO Assignment for Filter 8 /
phungductung	0:e87aa4c49e95	2069	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!<Filter FIFO Assignment for Filter 9 /
phungductung	0:e87aa4c49e95	2070	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!<Filter FIFO Assignment for Filter 10 /
phungductung	0:e87aa4c49e95	2071	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!<Filter FIFO Assignment for Filter 11 /
phungductung	0:e87aa4c49e95	2072	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!<Filter FIFO Assignment for Filter 12 /
phungductung	0:e87aa4c49e95	2073	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!<Filter FIFO Assignment for Filter 13 /
phungductung	0:e87aa4c49e95	2074
phungductung	0:e87aa4c49e95	2075	/***************** Bit definition for CAN_FA1R register *****************/
phungductung	0:e87aa4c49e95	2076	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!<Filter Active /
phungductung	0:e87aa4c49e95	2077	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!<Filter 0 Active /
phungductung	0:e87aa4c49e95	2078	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!<Filter 1 Active /
phungductung	0:e87aa4c49e95	2079	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!<Filter 2 Active /
phungductung	0:e87aa4c49e95	2080	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!<Filter 3 Active /
phungductung	0:e87aa4c49e95	2081	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!<Filter 4 Active /
phungductung	0:e87aa4c49e95	2082	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!<Filter 5 Active /
phungductung	0:e87aa4c49e95	2083	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!<Filter 6 Active /
phungductung	0:e87aa4c49e95	2084	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!<Filter 7 Active /
phungductung	0:e87aa4c49e95	2085	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!<Filter 8 Active /
phungductung	0:e87aa4c49e95	2086	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!<Filter 9 Active /
phungductung	0:e87aa4c49e95	2087	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!<Filter 10 Active /
phungductung	0:e87aa4c49e95	2088	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!<Filter 11 Active /
phungductung	0:e87aa4c49e95	2089	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!<Filter 12 Active /
phungductung	0:e87aa4c49e95	2090	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!<Filter 13 Active /
phungductung	0:e87aa4c49e95	2091
phungductung	0:e87aa4c49e95	2092	/***************** Bit definition for CAN_F0R1 register *****************/
phungductung	0:e87aa4c49e95	2093	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2094	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2095	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2096	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2097	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2098	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2099	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2100	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2101	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2102	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2103	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2104	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2105	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2106	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2107	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2108	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2109	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2110	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2111	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2112	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2113	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2114	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2115	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2116	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2117	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2118	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2119	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2120	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2121	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2122	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2123	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2124	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2125
phungductung	0:e87aa4c49e95	2126	/***************** Bit definition for CAN_F1R1 register *****************/
phungductung	0:e87aa4c49e95	2127	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2128	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2129	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2130	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2131	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2132	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2133	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2134	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2135	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2136	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2137	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2138	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2139	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2140	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2141	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2142	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2143	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2144	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2145	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2146	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2147	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2148	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2149	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2150	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2151	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2152	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2153	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2154	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2155	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2156	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2157	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2158	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2159
phungductung	0:e87aa4c49e95	2160	/***************** Bit definition for CAN_F2R1 register *****************/
phungductung	0:e87aa4c49e95	2161	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2162	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2163	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2164	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2165	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2166	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2167	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2168	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2169	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2170	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2171	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2172	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2173	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2174	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2175	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2176	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2177	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2178	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2179	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2180	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2181	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2182	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2183	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2184	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2185	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2186	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2187	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2188	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2189	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2190	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2191	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2192	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2193
phungductung	0:e87aa4c49e95	2194	/***************** Bit definition for CAN_F3R1 register *****************/
phungductung	0:e87aa4c49e95	2195	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2196	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2197	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2198	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2199	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2200	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2201	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2202	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2203	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2204	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2205	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2206	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2207	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2208	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2209	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2210	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2211	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2212	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2213	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2214	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2215	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2216	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2217	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2218	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2219	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2220	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2221	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2222	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2223	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2224	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2225	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2226	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2227
phungductung	0:e87aa4c49e95	2228	/***************** Bit definition for CAN_F4R1 register *****************/
phungductung	0:e87aa4c49e95	2229	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2230	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2231	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2232	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2233	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2234	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2235	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2236	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2237	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2238	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2239	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2240	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2241	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2242	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2243	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2244	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2245	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2246	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2247	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2248	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2249	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2250	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2251	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2252	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2253	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2254	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2255	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2256	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2257	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2258	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2259	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2260	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2261
phungductung	0:e87aa4c49e95	2262	/***************** Bit definition for CAN_F5R1 register *****************/
phungductung	0:e87aa4c49e95	2263	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2264	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2265	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2266	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2267	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2268	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2269	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2270	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2271	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2272	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2273	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2274	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2275	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2276	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2277	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2278	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2279	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2280	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2281	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2282	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2283	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2284	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2285	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2286	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2287	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2288	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2289	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2290	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2291	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2292	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2293	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2294	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2295
phungductung	0:e87aa4c49e95	2296	/***************** Bit definition for CAN_F6R1 register *****************/
phungductung	0:e87aa4c49e95	2297	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2298	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2299	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2300	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2301	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2302	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2303	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2304	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2305	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2306	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2307	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2308	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2309	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2310	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2311	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2312	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2313	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2314	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2315	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2316	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2317	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2318	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2319	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2320	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2321	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2322	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2323	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2324	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2325	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2326	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2327	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2328	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2329
phungductung	0:e87aa4c49e95	2330	/***************** Bit definition for CAN_F7R1 register *****************/
phungductung	0:e87aa4c49e95	2331	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2332	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2333	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2334	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2335	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2336	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2337	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2338	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2339	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2340	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2341	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2342	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2343	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2344	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2345	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2346	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2347	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2348	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2349	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2350	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2351	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2352	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2353	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2354	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2355	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2356	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2357	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2358	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2359	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2360	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2361	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2362	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2363
phungductung	0:e87aa4c49e95	2364	/***************** Bit definition for CAN_F8R1 register *****************/
phungductung	0:e87aa4c49e95	2365	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2366	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2367	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2368	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2369	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2370	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2371	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2372	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2373	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2374	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2375	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2376	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2377	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2378	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2379	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2380	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2381	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2382	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2383	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2384	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2385	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2386	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2387	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2388	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2389	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2390	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2391	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2392	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2393	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2394	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2395	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2396	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2397
phungductung	0:e87aa4c49e95	2398	/***************** Bit definition for CAN_F9R1 register *****************/
phungductung	0:e87aa4c49e95	2399	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2400	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2401	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2402	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2403	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2404	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2405	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2406	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2407	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2408	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2409	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2410	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2411	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2412	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2413	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2414	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2415	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2416	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2417	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2418	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2419	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2420	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2421	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2422	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2423	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2424	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2425	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2426	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2427	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2428	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2429	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2430	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2431
phungductung	0:e87aa4c49e95	2432	/***************** Bit definition for CAN_F10R1 register ****************/
phungductung	0:e87aa4c49e95	2433	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2434	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2435	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2436	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2437	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2438	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2439	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2440	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2441	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2442	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2443	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2444	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2445	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2446	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2447	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2448	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2449	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2450	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2451	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2452	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2453	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2454	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2455	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2456	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2457	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2458	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2459	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2460	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2461	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2462	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2463	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2464	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2465
phungductung	0:e87aa4c49e95	2466	/***************** Bit definition for CAN_F11R1 register ****************/
phungductung	0:e87aa4c49e95	2467	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2468	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2469	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2470	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2471	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2472	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2473	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2474	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2475	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2476	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2477	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2478	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2479	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2480	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2481	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2482	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2483	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2484	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2485	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2486	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2487	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2488	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2489	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2490	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2491	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2492	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2493	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2494	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2495	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2496	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2497	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2498	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2499
phungductung	0:e87aa4c49e95	2500	/***************** Bit definition for CAN_F12R1 register ****************/
phungductung	0:e87aa4c49e95	2501	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2502	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2503	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2504	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2505	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2506	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2507	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2508	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2509	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2510	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2511	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2512	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2513	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2514	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2515	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2516	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2517	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2518	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2519	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2520	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2521	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2522	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2523	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2524	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2525	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2526	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2527	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2528	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2529	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2530	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2531	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2532	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2533
phungductung	0:e87aa4c49e95	2534	/***************** Bit definition for CAN_F13R1 register ****************/
phungductung	0:e87aa4c49e95	2535	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2536	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2537	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2538	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2539	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2540	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2541	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2542	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2543	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2544	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2545	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2546	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2547	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2548	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2549	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2550	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2551	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2552	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2553	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2554	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2555	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2556	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2557	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2558	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2559	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2560	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2561	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2562	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2563	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2564	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2565	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2566	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2567
phungductung	0:e87aa4c49e95	2568	/***************** Bit definition for CAN_F0R2 register *****************/
phungductung	0:e87aa4c49e95	2569	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2570	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2571	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2572	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2573	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2574	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2575	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2576	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2577	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2578	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2579	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2580	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2581	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2582	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2583	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2584	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2585	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2586	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2587	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2588	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2589	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2590	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2591	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2592	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2593	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2594	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2595	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2596	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2597	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2598	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2599	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2600	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2601
phungductung	0:e87aa4c49e95	2602	/***************** Bit definition for CAN_F1R2 register *****************/
phungductung	0:e87aa4c49e95	2603	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2604	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2605	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2606	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2607	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2608	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2609	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2610	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2611	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2612	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2613	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2614	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2615	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2616	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2617	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2618	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2619	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2620	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2621	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2622	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2623	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2624	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2625	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2626	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2627	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2628	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2629	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2630	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2631	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2632	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2633	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2634	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2635
phungductung	0:e87aa4c49e95	2636	/***************** Bit definition for CAN_F2R2 register *****************/
phungductung	0:e87aa4c49e95	2637	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2638	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2639	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2640	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2641	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2642	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2643	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2644	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2645	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2646	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2647	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2648	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2649	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2650	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2651	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2652	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2653	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2654	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2655	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2656	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2657	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2658	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2659	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2660	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2661	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2662	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2663	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2664	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2665	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2666	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2667	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2668	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2669
phungductung	0:e87aa4c49e95	2670	/***************** Bit definition for CAN_F3R2 register *****************/
phungductung	0:e87aa4c49e95	2671	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2672	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2673	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2674	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2675	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2676	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2677	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2678	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2679	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2680	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2681	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2682	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2683	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2684	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2685	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2686	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2687	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2688	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2689	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2690	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2691	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2692	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2693	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2694	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2695	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2696	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2697	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2698	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2699	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2700	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2701	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2702	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2703
phungductung	0:e87aa4c49e95	2704	/***************** Bit definition for CAN_F4R2 register *****************/
phungductung	0:e87aa4c49e95	2705	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2706	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2707	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2708	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2709	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2710	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2711	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2712	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2713	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2714	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2715	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2716	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2717	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2718	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2719	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2720	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2721	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2722	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2723	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2724	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2725	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2726	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2727	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2728	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2729	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2730	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2731	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2732	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2733	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2734	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2735	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2736	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2737
phungductung	0:e87aa4c49e95	2738	/***************** Bit definition for CAN_F5R2 register *****************/
phungductung	0:e87aa4c49e95	2739	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2740	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2741	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2742	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2743	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2744	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2745	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2746	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2747	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2748	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2749	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2750	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2751	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2752	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2753	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2754	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2755	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2756	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2757	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2758	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2759	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2760	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2761	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2762	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2763	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2764	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2765	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2766	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2767	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2768	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2769	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2770	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2771
phungductung	0:e87aa4c49e95	2772	/***************** Bit definition for CAN_F6R2 register *****************/
phungductung	0:e87aa4c49e95	2773	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2774	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2775	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2776	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2777	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2778	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2779	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2780	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2781	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2782	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2783	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2784	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2785	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2786	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2787	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2788	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2789	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2790	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2791	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2792	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2793	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2794	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2795	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2796	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2797	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2798	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2799	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2800	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2801	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2802	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2803	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2804	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2805
phungductung	0:e87aa4c49e95	2806	/***************** Bit definition for CAN_F7R2 register *****************/
phungductung	0:e87aa4c49e95	2807	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2808	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2809	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2810	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2811	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2812	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2813	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2814	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2815	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2816	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2817	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2818	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2819	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2820	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2821	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2822	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2823	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2824	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2825	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2826	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2827	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2828	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2829	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2830	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2831	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2832	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2833	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2834	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2835	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2836	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2837	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2838	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2839
phungductung	0:e87aa4c49e95	2840	/***************** Bit definition for CAN_F8R2 register *****************/
phungductung	0:e87aa4c49e95	2841	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2842	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2843	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2844	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2845	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2846	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2847	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2848	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2849	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2850	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2851	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2852	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2853	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2854	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2855	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2856	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2857	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2858	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2859	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2860	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2861	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2862	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2863	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2864	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2865	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2866	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2867	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2868	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2869	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2870	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2871	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2872	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2873
phungductung	0:e87aa4c49e95	2874	/***************** Bit definition for CAN_F9R2 register *****************/
phungductung	0:e87aa4c49e95	2875	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2876	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2877	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2878	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2879	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2880	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2881	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2882	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2883	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2884	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2885	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2886	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2887	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2888	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2889	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2890	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2891	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2892	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2893	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2894	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2895	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2896	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2897	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2898	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2899	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2900	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2901	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2902	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2903	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2904	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2905	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2906	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2907
phungductung	0:e87aa4c49e95	2908	/***************** Bit definition for CAN_F10R2 register ****************/
phungductung	0:e87aa4c49e95	2909	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2910	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2911	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2912	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2913	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2914	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2915	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2916	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2917	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2918	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2919	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2920	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2921	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2922	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2923	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2924	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2925	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2926	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2927	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2928	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2929	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2930	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2931	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2932	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2933	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2934	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2935	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2936	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2937	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2938	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2939	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2940	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2941
phungductung	0:e87aa4c49e95	2942	/***************** Bit definition for CAN_F11R2 register ****************/
phungductung	0:e87aa4c49e95	2943	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2944	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2945	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2946	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2947	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2948	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2949	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2950	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2951	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2952	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2953	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2954	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2955	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2956	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2957	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2958	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2959	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2960	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2961	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2962	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2963	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2964	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2965	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	2966	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	2967	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	2968	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	2969	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	2970	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	2971	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	2972	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	2973	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	2974	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	2975
phungductung	0:e87aa4c49e95	2976	/***************** Bit definition for CAN_F12R2 register ****************/
phungductung	0:e87aa4c49e95	2977	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	2978	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	2979	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	2980	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	2981	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	2982	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	2983	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	2984	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	2985	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	2986	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	2987	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	2988	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	2989	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	2990	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	2991	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	2992	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	2993	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	2994	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	2995	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	2996	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	2997	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	2998	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	2999	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	3000	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	3001	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	3002	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	3003	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	3004	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	3005	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	3006	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	3007	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	3008	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	3009
phungductung	0:e87aa4c49e95	3010	/***************** Bit definition for CAN_F13R2 register ****************/
phungductung	0:e87aa4c49e95	3011	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
phungductung	0:e87aa4c49e95	3012	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
phungductung	0:e87aa4c49e95	3013	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
phungductung	0:e87aa4c49e95	3014	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
phungductung	0:e87aa4c49e95	3015	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
phungductung	0:e87aa4c49e95	3016	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
phungductung	0:e87aa4c49e95	3017	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
phungductung	0:e87aa4c49e95	3018	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
phungductung	0:e87aa4c49e95	3019	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
phungductung	0:e87aa4c49e95	3020	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
phungductung	0:e87aa4c49e95	3021	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
phungductung	0:e87aa4c49e95	3022	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
phungductung	0:e87aa4c49e95	3023	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
phungductung	0:e87aa4c49e95	3024	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
phungductung	0:e87aa4c49e95	3025	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
phungductung	0:e87aa4c49e95	3026	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
phungductung	0:e87aa4c49e95	3027	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
phungductung	0:e87aa4c49e95	3028	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
phungductung	0:e87aa4c49e95	3029	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
phungductung	0:e87aa4c49e95	3030	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
phungductung	0:e87aa4c49e95	3031	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
phungductung	0:e87aa4c49e95	3032	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
phungductung	0:e87aa4c49e95	3033	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
phungductung	0:e87aa4c49e95	3034	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
phungductung	0:e87aa4c49e95	3035	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
phungductung	0:e87aa4c49e95	3036	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
phungductung	0:e87aa4c49e95	3037	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
phungductung	0:e87aa4c49e95	3038	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
phungductung	0:e87aa4c49e95	3039	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
phungductung	0:e87aa4c49e95	3040	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
phungductung	0:e87aa4c49e95	3041	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
phungductung	0:e87aa4c49e95	3042	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
phungductung	0:e87aa4c49e95	3043
phungductung	0:e87aa4c49e95	3044	/******************************************************************************/
phungductung	0:e87aa4c49e95	3045	/* */
phungductung	0:e87aa4c49e95	3046	/* HDMI-CEC (CEC) */
phungductung	0:e87aa4c49e95	3047	/* */
phungductung	0:e87aa4c49e95	3048	/******************************************************************************/
phungductung	0:e87aa4c49e95	3049
phungductung	0:e87aa4c49e95	3050	/***************** Bit definition for CEC_CR register *******************/
phungductung	0:e87aa4c49e95	3051	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
phungductung	0:e87aa4c49e95	3052	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
phungductung	0:e87aa4c49e95	3053	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
phungductung	0:e87aa4c49e95	3054
phungductung	0:e87aa4c49e95	3055	/***************** Bit definition for CEC_CFGR register *****************/
phungductung	0:e87aa4c49e95	3056	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
phungductung	0:e87aa4c49e95	3057	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
phungductung	0:e87aa4c49e95	3058	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
phungductung	0:e87aa4c49e95	3059	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
phungductung	0:e87aa4c49e95	3060	#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /!< CEC Long Period Error generation /
phungductung	0:e87aa4c49e95	3061	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast no Error generation /
phungductung	0:e87aa4c49e95	3062	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
phungductung	0:e87aa4c49e95	3063	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
phungductung	0:e87aa4c49e95	3064	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
phungductung	0:e87aa4c49e95	3065
phungductung	0:e87aa4c49e95	3066	/***************** Bit definition for CEC_TXDR register *****************/
phungductung	0:e87aa4c49e95	3067	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
phungductung	0:e87aa4c49e95	3068
phungductung	0:e87aa4c49e95	3069	/***************** Bit definition for CEC_RXDR register *****************/
phungductung	0:e87aa4c49e95	3070	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
phungductung	0:e87aa4c49e95	3071
phungductung	0:e87aa4c49e95	3072	/***************** Bit definition for CEC_ISR register ******************/
phungductung	0:e87aa4c49e95	3073	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
phungductung	0:e87aa4c49e95	3074	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
phungductung	0:e87aa4c49e95	3075	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
phungductung	0:e87aa4c49e95	3076	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
phungductung	0:e87aa4c49e95	3077	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
phungductung	0:e87aa4c49e95	3078	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
phungductung	0:e87aa4c49e95	3079	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
phungductung	0:e87aa4c49e95	3080	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
phungductung	0:e87aa4c49e95	3081	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
phungductung	0:e87aa4c49e95	3082	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
phungductung	0:e87aa4c49e95	3083	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
phungductung	0:e87aa4c49e95	3084	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
phungductung	0:e87aa4c49e95	3085	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
phungductung	0:e87aa4c49e95	3086
phungductung	0:e87aa4c49e95	3087	/***************** Bit definition for CEC_IER register ******************/
phungductung	0:e87aa4c49e95	3088	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
phungductung	0:e87aa4c49e95	3089	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
phungductung	0:e87aa4c49e95	3090	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
phungductung	0:e87aa4c49e95	3091	#define CEC_IER_BREIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
phungductung	0:e87aa4c49e95	3092	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
phungductung	0:e87aa4c49e95	3093	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
phungductung	0:e87aa4c49e95	3094	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
phungductung	0:e87aa4c49e95	3095	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
phungductung	0:e87aa4c49e95	3096	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
phungductung	0:e87aa4c49e95	3097	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
phungductung	0:e87aa4c49e95	3098	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
phungductung	0:e87aa4c49e95	3099	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
phungductung	0:e87aa4c49e95	3100	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
phungductung	0:e87aa4c49e95	3101
phungductung	0:e87aa4c49e95	3102	/******************************************************************************/
phungductung	0:e87aa4c49e95	3103	/* */
phungductung	0:e87aa4c49e95	3104	/* CRC calculation unit */
phungductung	0:e87aa4c49e95	3105	/* */
phungductung	0:e87aa4c49e95	3106	/******************************************************************************/
phungductung	0:e87aa4c49e95	3107	/***************** Bit definition for CRC_DR register *******************/
phungductung	0:e87aa4c49e95	3108	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
phungductung	0:e87aa4c49e95	3109
phungductung	0:e87aa4c49e95	3110	/***************** Bit definition for CRC_IDR register ******************/
phungductung	0:e87aa4c49e95	3111	#define CRC_IDR_IDR ((uint32_t)0x000000FF) /!< General-purpose 8-bit data register bits /
phungductung	0:e87aa4c49e95	3112
phungductung	0:e87aa4c49e95	3113	/****************** Bit definition for CRC_CR register ******************/
phungductung	0:e87aa4c49e95	3114	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
phungductung	0:e87aa4c49e95	3115	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
phungductung	0:e87aa4c49e95	3116	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
phungductung	0:e87aa4c49e95	3117	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
phungductung	0:e87aa4c49e95	3118	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
phungductung	0:e87aa4c49e95	3119	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< Bit 0 /
phungductung	0:e87aa4c49e95	3120	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< Bit 1 /
phungductung	0:e87aa4c49e95	3121	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
phungductung	0:e87aa4c49e95	3122
phungductung	0:e87aa4c49e95	3123	/***************** Bit definition for CRC_INIT register *****************/
phungductung	0:e87aa4c49e95	3124	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
phungductung	0:e87aa4c49e95	3125
phungductung	0:e87aa4c49e95	3126	/***************** Bit definition for CRC_POL register ******************/
phungductung	0:e87aa4c49e95	3127	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
phungductung	0:e87aa4c49e95	3128
phungductung	0:e87aa4c49e95	3129
phungductung	0:e87aa4c49e95	3130	/******************************************************************************/
phungductung	0:e87aa4c49e95	3131	/* */
phungductung	0:e87aa4c49e95	3132	/* Digital to Analog Converter */
phungductung	0:e87aa4c49e95	3133	/* */
phungductung	0:e87aa4c49e95	3134	/******************************************************************************/
phungductung	0:e87aa4c49e95	3135	/****************** Bit definition for DAC_CR register ******************/
phungductung	0:e87aa4c49e95	3136	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
phungductung	0:e87aa4c49e95	3137	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!<DAC channel1 output buffer disable /
phungductung	0:e87aa4c49e95	3138	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
phungductung	0:e87aa4c49e95	3139
phungductung	0:e87aa4c49e95	3140	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
phungductung	0:e87aa4c49e95	3141	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3142	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3143	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3144
phungductung	0:e87aa4c49e95	3145	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
phungductung	0:e87aa4c49e95	3146	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3147	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3148
phungductung	0:e87aa4c49e95	3149	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
phungductung	0:e87aa4c49e95	3150	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3151	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3152	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3153	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3154
phungductung	0:e87aa4c49e95	3155	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
phungductung	0:e87aa4c49e95	3156	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
phungductung	0:e87aa4c49e95	3157	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!<DAC channel2 output buffer disable /
phungductung	0:e87aa4c49e95	3158	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
phungductung	0:e87aa4c49e95	3159
phungductung	0:e87aa4c49e95	3160	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
phungductung	0:e87aa4c49e95	3161	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3162	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3163	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3164
phungductung	0:e87aa4c49e95	3165	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
phungductung	0:e87aa4c49e95	3166	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3167	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3168
phungductung	0:e87aa4c49e95	3169	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
phungductung	0:e87aa4c49e95	3170	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3171	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3172	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3173	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3174
phungductung	0:e87aa4c49e95	3175	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
phungductung	0:e87aa4c49e95	3176
phungductung	0:e87aa4c49e95	3177	/*************** Bit definition for DAC_SWTRIGR register ****************/
phungductung	0:e87aa4c49e95	3178	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /!<DAC channel1 software trigger /
phungductung	0:e87aa4c49e95	3179	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /!<DAC channel2 software trigger /
phungductung	0:e87aa4c49e95	3180
phungductung	0:e87aa4c49e95	3181	/*************** Bit definition for DAC_DHR12R1 register ****************/
phungductung	0:e87aa4c49e95	3182	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /!<DAC channel1 12-bit Right aligned data /
phungductung	0:e87aa4c49e95	3183
phungductung	0:e87aa4c49e95	3184	/*************** Bit definition for DAC_DHR12L1 register ****************/
phungductung	0:e87aa4c49e95	3185	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /!<DAC channel1 12-bit Left aligned data /
phungductung	0:e87aa4c49e95	3186
phungductung	0:e87aa4c49e95	3187	/**************** Bit definition for DAC_DHR8R1 register ****************/
phungductung	0:e87aa4c49e95	3188	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /!<DAC channel1 8-bit Right aligned data /
phungductung	0:e87aa4c49e95	3189
phungductung	0:e87aa4c49e95	3190	/*************** Bit definition for DAC_DHR12R2 register ****************/
phungductung	0:e87aa4c49e95	3191	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /!<DAC channel2 12-bit Right aligned data /
phungductung	0:e87aa4c49e95	3192
phungductung	0:e87aa4c49e95	3193	/*************** Bit definition for DAC_DHR12L2 register ****************/
phungductung	0:e87aa4c49e95	3194	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /!<DAC channel2 12-bit Left aligned data /
phungductung	0:e87aa4c49e95	3195
phungductung	0:e87aa4c49e95	3196	/**************** Bit definition for DAC_DHR8R2 register ****************/
phungductung	0:e87aa4c49e95	3197	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /!<DAC channel2 8-bit Right aligned data /
phungductung	0:e87aa4c49e95	3198
phungductung	0:e87aa4c49e95	3199	/*************** Bit definition for DAC_DHR12RD register ****************/
phungductung	0:e87aa4c49e95	3200	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
phungductung	0:e87aa4c49e95	3201	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
phungductung	0:e87aa4c49e95	3202
phungductung	0:e87aa4c49e95	3203	/*************** Bit definition for DAC_DHR12LD register ****************/
phungductung	0:e87aa4c49e95	3204	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
phungductung	0:e87aa4c49e95	3205	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
phungductung	0:e87aa4c49e95	3206
phungductung	0:e87aa4c49e95	3207	/**************** Bit definition for DAC_DHR8RD register ****************/
phungductung	0:e87aa4c49e95	3208	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /!<DAC channel1 8-bit Right aligned data /
phungductung	0:e87aa4c49e95	3209	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /!<DAC channel2 8-bit Right aligned data /
phungductung	0:e87aa4c49e95	3210
phungductung	0:e87aa4c49e95	3211	/***************** Bit definition for DAC_DOR1 register *****************/
phungductung	0:e87aa4c49e95	3212	#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /!<DAC channel1 data output /
phungductung	0:e87aa4c49e95	3213
phungductung	0:e87aa4c49e95	3214	/***************** Bit definition for DAC_DOR2 register *****************/
phungductung	0:e87aa4c49e95	3215	#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /!<DAC channel2 data output /
phungductung	0:e87aa4c49e95	3216
phungductung	0:e87aa4c49e95	3217	/****************** Bit definition for DAC_SR register ******************/
phungductung	0:e87aa4c49e95	3218	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
phungductung	0:e87aa4c49e95	3219	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
phungductung	0:e87aa4c49e95	3220
phungductung	0:e87aa4c49e95	3221
phungductung	0:e87aa4c49e95	3222	/******************************************************************************/
phungductung	0:e87aa4c49e95	3223	/* */
phungductung	0:e87aa4c49e95	3224	/* Debug MCU */
phungductung	0:e87aa4c49e95	3225	/* */
phungductung	0:e87aa4c49e95	3226	/******************************************************************************/
phungductung	0:e87aa4c49e95	3227
phungductung	0:e87aa4c49e95	3228	/******************************************************************************/
phungductung	0:e87aa4c49e95	3229	/* */
phungductung	0:e87aa4c49e95	3230	/* DCMI */
phungductung	0:e87aa4c49e95	3231	/* */
phungductung	0:e87aa4c49e95	3232	/******************************************************************************/
phungductung	0:e87aa4c49e95	3233	/****************** Bits definition for DCMI_CR register ****************/
phungductung	0:e87aa4c49e95	3234	#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3235	#define DCMI_CR_CM ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3236	#define DCMI_CR_CROP ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3237	#define DCMI_CR_JPEG ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3238	#define DCMI_CR_ESS ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3239	#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3240	#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3241	#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	3242	#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3243	#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3244	#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3245	#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3246	#define DCMI_CR_CRE ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	3247	#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	3248	#define DCMI_CR_BSM ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	3249	#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3250	#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	3251	#define DCMI_CR_OEBS ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3252	#define DCMI_CR_LSM ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3253	#define DCMI_CR_OELS ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3254
phungductung	0:e87aa4c49e95	3255	/****************** Bits definition for DCMI_SR register ****************/
phungductung	0:e87aa4c49e95	3256	#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3257	#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3258	#define DCMI_SR_FNE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3259
phungductung	0:e87aa4c49e95	3260	/****************** Bits definition for DCMI_RISR register **************/
phungductung	0:e87aa4c49e95	3261	#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3262	#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3263	#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3264	#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3265	#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3266
phungductung	0:e87aa4c49e95	3267	/****************** Bits definition for DCMI_IER register ***************/
phungductung	0:e87aa4c49e95	3268	#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3269	#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3270	#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3271	#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3272	#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3273
phungductung	0:e87aa4c49e95	3274	/****************** Bits definition for DCMI_MISR register **************/
phungductung	0:e87aa4c49e95	3275	#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3276	#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3277	#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3278	#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3279	#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3280
phungductung	0:e87aa4c49e95	3281	/****************** Bits definition for DCMI_ICR register ***************/
phungductung	0:e87aa4c49e95	3282	#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3283	#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3284	#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3285	#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3286	#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3287
phungductung	0:e87aa4c49e95	3288	/******************************************************************************/
phungductung	0:e87aa4c49e95	3289	/* */
phungductung	0:e87aa4c49e95	3290	/* DMA Controller */
phungductung	0:e87aa4c49e95	3291	/* */
phungductung	0:e87aa4c49e95	3292	/******************************************************************************/
phungductung	0:e87aa4c49e95	3293	/****************** Bits definition for DMA_SxCR register ***************/
phungductung	0:e87aa4c49e95	3294	#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
phungductung	0:e87aa4c49e95	3295	#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	3296	#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	3297	#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	3298	#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
phungductung	0:e87aa4c49e95	3299	#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	3300	#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	3301	#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
phungductung	0:e87aa4c49e95	3302	#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	3303	#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	3304	#define DMA_SxCR_ACK ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3305	#define DMA_SxCR_CT ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3306	#define DMA_SxCR_DBM ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3307	#define DMA_SxCR_PL ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	3308	#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3309	#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	3310	#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	3311	#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
phungductung	0:e87aa4c49e95	3312	#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	3313	#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	3314	#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
phungductung	0:e87aa4c49e95	3315	#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3316	#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	3317	#define DMA_SxCR_MINC ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3318	#define DMA_SxCR_PINC ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3319	#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3320	#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
phungductung	0:e87aa4c49e95	3321	#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3322	#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	3323	#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3324	#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3325	#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3326	#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3327	#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3328	#define DMA_SxCR_EN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3329
phungductung	0:e87aa4c49e95	3330	/****************** Bits definition for DMA_SxCNDTR register ************/
phungductung	0:e87aa4c49e95	3331	#define DMA_SxNDT ((uint32_t)0x0000FFFF)
phungductung	0:e87aa4c49e95	3332	#define DMA_SxNDT_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3333	#define DMA_SxNDT_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3334	#define DMA_SxNDT_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3335	#define DMA_SxNDT_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3336	#define DMA_SxNDT_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3337	#define DMA_SxNDT_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3338	#define DMA_SxNDT_6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3339	#define DMA_SxNDT_7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	3340	#define DMA_SxNDT_8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3341	#define DMA_SxNDT_9 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3342	#define DMA_SxNDT_10 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3343	#define DMA_SxNDT_11 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3344	#define DMA_SxNDT_12 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	3345	#define DMA_SxNDT_13 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	3346	#define DMA_SxNDT_14 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	3347	#define DMA_SxNDT_15 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	3348
phungductung	0:e87aa4c49e95	3349	/****************** Bits definition for DMA_SxFCR register **************/
phungductung	0:e87aa4c49e95	3350	#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	3351	#define DMA_SxFCR_FS ((uint32_t)0x00000038)
phungductung	0:e87aa4c49e95	3352	#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3353	#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3354	#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3355	#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3356	#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
phungductung	0:e87aa4c49e95	3357	#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3358	#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3359
phungductung	0:e87aa4c49e95	3360	/****************** Bits definition for DMA_LISR register ***************/
phungductung	0:e87aa4c49e95	3361	#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	3362	#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	3363	#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	3364	#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	3365	#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	3366	#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	3367	#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3368	#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3369	#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3370	#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3371	#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3372	#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3373	#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3374	#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3375	#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3376	#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3377	#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3378	#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3379	#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3380	#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3381
phungductung	0:e87aa4c49e95	3382	/****************** Bits definition for DMA_HISR register ***************/
phungductung	0:e87aa4c49e95	3383	#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	3384	#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	3385	#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	3386	#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	3387	#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	3388	#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	3389	#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3390	#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3391	#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3392	#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3393	#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3394	#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3395	#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3396	#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3397	#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3398	#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3399	#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3400	#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3401	#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3402	#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3403
phungductung	0:e87aa4c49e95	3404	/****************** Bits definition for DMA_LIFCR register **************/
phungductung	0:e87aa4c49e95	3405	#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	3406	#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	3407	#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	3408	#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	3409	#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	3410	#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	3411	#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3412	#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3413	#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3414	#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3415	#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3416	#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3417	#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3418	#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3419	#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3420	#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3421	#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3422	#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3423	#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3424	#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3425
phungductung	0:e87aa4c49e95	3426	/****************** Bits definition for DMA_HIFCR register **************/
phungductung	0:e87aa4c49e95	3427	#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	3428	#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	3429	#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	3430	#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	3431	#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	3432	#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	3433	#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3434	#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3435	#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3436	#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3437	#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3438	#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3439	#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3440	#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3441	#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3442	#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3443	#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3444	#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3445	#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3446	#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3447
phungductung	0:e87aa4c49e95	3448	/******************************************************************************/
phungductung	0:e87aa4c49e95	3449	/* */
phungductung	0:e87aa4c49e95	3450	/* AHB Master DMA2D Controller (DMA2D) */
phungductung	0:e87aa4c49e95	3451	/* */
phungductung	0:e87aa4c49e95	3452	/******************************************************************************/
phungductung	0:e87aa4c49e95	3453
phungductung	0:e87aa4c49e95	3454	/****************** Bit definition for DMA2D_CR register ****************/
phungductung	0:e87aa4c49e95	3455
phungductung	0:e87aa4c49e95	3456	#define DMA2D_CR_START ((uint32_t)0x00000001) /!< Start transfer /
phungductung	0:e87aa4c49e95	3457	#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /!< Suspend transfer /
phungductung	0:e87aa4c49e95	3458	#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /!< Abort transfer /
phungductung	0:e87aa4c49e95	3459	#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /!< Transfer Error Interrupt Enable /
phungductung	0:e87aa4c49e95	3460	#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /!< Transfer Complete Interrupt Enable /
phungductung	0:e87aa4c49e95	3461	#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /!< Transfer Watermark Interrupt Enable /
phungductung	0:e87aa4c49e95	3462	#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /!< CLUT Access Error Interrupt Enable /
phungductung	0:e87aa4c49e95	3463	#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /!< CLUT Transfer Complete Interrupt Enable /
phungductung	0:e87aa4c49e95	3464	#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /!< Configuration Error Interrupt Enable /
phungductung	0:e87aa4c49e95	3465	#define DMA2D_CR_MODE ((uint32_t)0x00030000) /!< DMA2D Mode /
phungductung	0:e87aa4c49e95	3466
phungductung	0:e87aa4c49e95	3467	/****************** Bit definition for DMA2D_ISR register ***************/
phungductung	0:e87aa4c49e95	3468
phungductung	0:e87aa4c49e95	3469	#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /!< Transfer Error Interrupt Flag /
phungductung	0:e87aa4c49e95	3470	#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /!< Transfer Complete Interrupt Flag /
phungductung	0:e87aa4c49e95	3471	#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /!< Transfer Watermark Interrupt Flag /
phungductung	0:e87aa4c49e95	3472	#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /!< CLUT Access Error Interrupt Flag /
phungductung	0:e87aa4c49e95	3473	#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /!< CLUT Transfer Complete Interrupt Flag /
phungductung	0:e87aa4c49e95	3474	#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /!< Configuration Error Interrupt Flag /
phungductung	0:e87aa4c49e95	3475
phungductung	0:e87aa4c49e95	3476	/****************** Bit definition for DMA2D_IFSR register **************/
phungductung	0:e87aa4c49e95	3477
phungductung	0:e87aa4c49e95	3478	#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /!< Clears Transfer Error Interrupt Flag /
phungductung	0:e87aa4c49e95	3479	#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /!< Clears Transfer Complete Interrupt Flag /
phungductung	0:e87aa4c49e95	3480	#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /!< Clears Transfer Watermark Interrupt Flag /
phungductung	0:e87aa4c49e95	3481	#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /!< Clears CLUT Access Error Interrupt Flag /
phungductung	0:e87aa4c49e95	3482	#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /!< Clears CLUT Transfer Complete Interrupt Flag /
phungductung	0:e87aa4c49e95	3483	#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /!< Clears Configuration Error Interrupt Flag /
phungductung	0:e87aa4c49e95	3484
phungductung	0:e87aa4c49e95	3485	/****************** Bit definition for DMA2D_FGMAR register *************/
phungductung	0:e87aa4c49e95	3486
phungductung	0:e87aa4c49e95	3487	#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
phungductung	0:e87aa4c49e95	3488
phungductung	0:e87aa4c49e95	3489	/****************** Bit definition for DMA2D_FGOR register **************/
phungductung	0:e87aa4c49e95	3490
phungductung	0:e87aa4c49e95	3491	#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /!< Line Offset /
phungductung	0:e87aa4c49e95	3492
phungductung	0:e87aa4c49e95	3493	/****************** Bit definition for DMA2D_BGMAR register *************/
phungductung	0:e87aa4c49e95	3494
phungductung	0:e87aa4c49e95	3495	#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
phungductung	0:e87aa4c49e95	3496
phungductung	0:e87aa4c49e95	3497	/****************** Bit definition for DMA2D_BGOR register **************/
phungductung	0:e87aa4c49e95	3498
phungductung	0:e87aa4c49e95	3499	#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /!< Line Offset /
phungductung	0:e87aa4c49e95	3500
phungductung	0:e87aa4c49e95	3501	/****************** Bit definition for DMA2D_FGPFCCR register ***********/
phungductung	0:e87aa4c49e95	3502
phungductung	0:e87aa4c49e95	3503	#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /!< Color mode /
phungductung	0:e87aa4c49e95	3504	#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /!< CLUT Color mode /
phungductung	0:e87aa4c49e95	3505	#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /!< Start /
phungductung	0:e87aa4c49e95	3506	#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /!< CLUT size /
phungductung	0:e87aa4c49e95	3507	#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /!< Alpha mode /
phungductung	0:e87aa4c49e95	3508	#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /!< Alpha value /
phungductung	0:e87aa4c49e95	3509
phungductung	0:e87aa4c49e95	3510	/****************** Bit definition for DMA2D_FGCOLR register ************/
phungductung	0:e87aa4c49e95	3511
phungductung	0:e87aa4c49e95	3512	#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /!< Blue Value /
phungductung	0:e87aa4c49e95	3513	#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /!< Green Value /
phungductung	0:e87aa4c49e95	3514	#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /!< Red Value /
phungductung	0:e87aa4c49e95	3515
phungductung	0:e87aa4c49e95	3516	/****************** Bit definition for DMA2D_BGPFCCR register ***********/
phungductung	0:e87aa4c49e95	3517
phungductung	0:e87aa4c49e95	3518	#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /!< Color mode /
phungductung	0:e87aa4c49e95	3519	#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /!< CLUT Color mode /
phungductung	0:e87aa4c49e95	3520	#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /!< Start /
phungductung	0:e87aa4c49e95	3521	#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /!< CLUT size /
phungductung	0:e87aa4c49e95	3522	#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /!< Alpha Mode /
phungductung	0:e87aa4c49e95	3523	#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /!< Alpha value /
phungductung	0:e87aa4c49e95	3524
phungductung	0:e87aa4c49e95	3525	/****************** Bit definition for DMA2D_BGCOLR register ************/
phungductung	0:e87aa4c49e95	3526
phungductung	0:e87aa4c49e95	3527	#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /!< Blue Value /
phungductung	0:e87aa4c49e95	3528	#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /!< Green Value /
phungductung	0:e87aa4c49e95	3529	#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /!< Red Value /
phungductung	0:e87aa4c49e95	3530
phungductung	0:e87aa4c49e95	3531	/****************** Bit definition for DMA2D_FGCMAR register ************/
phungductung	0:e87aa4c49e95	3532
phungductung	0:e87aa4c49e95	3533	#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
phungductung	0:e87aa4c49e95	3534
phungductung	0:e87aa4c49e95	3535	/****************** Bit definition for DMA2D_BGCMAR register ************/
phungductung	0:e87aa4c49e95	3536
phungductung	0:e87aa4c49e95	3537	#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
phungductung	0:e87aa4c49e95	3538
phungductung	0:e87aa4c49e95	3539	/****************** Bit definition for DMA2D_OPFCCR register ************/
phungductung	0:e87aa4c49e95	3540
phungductung	0:e87aa4c49e95	3541	#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /!< Color mode /
phungductung	0:e87aa4c49e95	3542
phungductung	0:e87aa4c49e95	3543	/****************** Bit definition for DMA2D_OCOLR register *************/
phungductung	0:e87aa4c49e95	3544
phungductung	0:e87aa4c49e95	3545	/!<Mode_ARGB8888/RGB888 /
phungductung	0:e87aa4c49e95	3546
phungductung	0:e87aa4c49e95	3547	#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /!< BLUE Value /
phungductung	0:e87aa4c49e95	3548	#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /!< GREEN Value /
phungductung	0:e87aa4c49e95	3549	#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /!< Red Value /
phungductung	0:e87aa4c49e95	3550	#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /!< Alpha Channel Value /
phungductung	0:e87aa4c49e95	3551
phungductung	0:e87aa4c49e95	3552	/!<Mode_RGB565 /
phungductung	0:e87aa4c49e95	3553	#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /!< BLUE Value /
phungductung	0:e87aa4c49e95	3554	#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /!< GREEN Value /
phungductung	0:e87aa4c49e95	3555	#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /!< Red Value /
phungductung	0:e87aa4c49e95	3556
phungductung	0:e87aa4c49e95	3557	/!<Mode_ARGB1555 /
phungductung	0:e87aa4c49e95	3558	#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /!< BLUE Value /
phungductung	0:e87aa4c49e95	3559	#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /!< GREEN Value /
phungductung	0:e87aa4c49e95	3560	#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /!< Red Value /
phungductung	0:e87aa4c49e95	3561	#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /!< Alpha Channel Value /
phungductung	0:e87aa4c49e95	3562
phungductung	0:e87aa4c49e95	3563	/!<Mode_ARGB4444 /
phungductung	0:e87aa4c49e95	3564	#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /!< BLUE Value /
phungductung	0:e87aa4c49e95	3565	#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /!< GREEN Value /
phungductung	0:e87aa4c49e95	3566	#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /!< Red Value /
phungductung	0:e87aa4c49e95	3567	#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /!< Alpha Channel Value /
phungductung	0:e87aa4c49e95	3568
phungductung	0:e87aa4c49e95	3569	/****************** Bit definition for DMA2D_OMAR register **************/
phungductung	0:e87aa4c49e95	3570
phungductung	0:e87aa4c49e95	3571	#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
phungductung	0:e87aa4c49e95	3572
phungductung	0:e87aa4c49e95	3573	/****************** Bit definition for DMA2D_OOR register ***************/
phungductung	0:e87aa4c49e95	3574
phungductung	0:e87aa4c49e95	3575	#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /!< Line Offset /
phungductung	0:e87aa4c49e95	3576
phungductung	0:e87aa4c49e95	3577	/****************** Bit definition for DMA2D_NLR register ***************/
phungductung	0:e87aa4c49e95	3578
phungductung	0:e87aa4c49e95	3579	#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /!< Number of Lines /
phungductung	0:e87aa4c49e95	3580	#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /!< Pixel per Lines /
phungductung	0:e87aa4c49e95	3581
phungductung	0:e87aa4c49e95	3582	/****************** Bit definition for DMA2D_LWR register ***************/
phungductung	0:e87aa4c49e95	3583
phungductung	0:e87aa4c49e95	3584	#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /!< Line Watermark /
phungductung	0:e87aa4c49e95	3585
phungductung	0:e87aa4c49e95	3586	/****************** Bit definition for DMA2D_AMTCR register *************/
phungductung	0:e87aa4c49e95	3587
phungductung	0:e87aa4c49e95	3588	#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /!< Enable /
phungductung	0:e87aa4c49e95	3589	#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /!< Dead Time /
phungductung	0:e87aa4c49e95	3590
phungductung	0:e87aa4c49e95	3591
phungductung	0:e87aa4c49e95	3592
phungductung	0:e87aa4c49e95	3593	/****************** Bit definition for DMA2D_FGCLUT register ************/
phungductung	0:e87aa4c49e95	3594
phungductung	0:e87aa4c49e95	3595	/****************** Bit definition for DMA2D_BGCLUT register ************/
phungductung	0:e87aa4c49e95	3596
phungductung	0:e87aa4c49e95	3597
phungductung	0:e87aa4c49e95	3598	/******************************************************************************/
phungductung	0:e87aa4c49e95	3599	/* */
phungductung	0:e87aa4c49e95	3600	/* External Interrupt/Event Controller */
phungductung	0:e87aa4c49e95	3601	/* */
phungductung	0:e87aa4c49e95	3602	/******************************************************************************/
phungductung	0:e87aa4c49e95	3603	/***************** Bit definition for EXTI_IMR register *****************/
phungductung	0:e87aa4c49e95	3604	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
phungductung	0:e87aa4c49e95	3605	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
phungductung	0:e87aa4c49e95	3606	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
phungductung	0:e87aa4c49e95	3607	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
phungductung	0:e87aa4c49e95	3608	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
phungductung	0:e87aa4c49e95	3609	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
phungductung	0:e87aa4c49e95	3610	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
phungductung	0:e87aa4c49e95	3611	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
phungductung	0:e87aa4c49e95	3612	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
phungductung	0:e87aa4c49e95	3613	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
phungductung	0:e87aa4c49e95	3614	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
phungductung	0:e87aa4c49e95	3615	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
phungductung	0:e87aa4c49e95	3616	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
phungductung	0:e87aa4c49e95	3617	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
phungductung	0:e87aa4c49e95	3618	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
phungductung	0:e87aa4c49e95	3619	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
phungductung	0:e87aa4c49e95	3620	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
phungductung	0:e87aa4c49e95	3621	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
phungductung	0:e87aa4c49e95	3622	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
phungductung	0:e87aa4c49e95	3623	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
phungductung	0:e87aa4c49e95	3624	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
phungductung	0:e87aa4c49e95	3625	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
phungductung	0:e87aa4c49e95	3626	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
phungductung	0:e87aa4c49e95	3627	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
phungductung	0:e87aa4c49e95	3628
phungductung	0:e87aa4c49e95	3629	/***************** Bit definition for EXTI_EMR register *****************/
phungductung	0:e87aa4c49e95	3630	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
phungductung	0:e87aa4c49e95	3631	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
phungductung	0:e87aa4c49e95	3632	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
phungductung	0:e87aa4c49e95	3633	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
phungductung	0:e87aa4c49e95	3634	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
phungductung	0:e87aa4c49e95	3635	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
phungductung	0:e87aa4c49e95	3636	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
phungductung	0:e87aa4c49e95	3637	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
phungductung	0:e87aa4c49e95	3638	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
phungductung	0:e87aa4c49e95	3639	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
phungductung	0:e87aa4c49e95	3640	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
phungductung	0:e87aa4c49e95	3641	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
phungductung	0:e87aa4c49e95	3642	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
phungductung	0:e87aa4c49e95	3643	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
phungductung	0:e87aa4c49e95	3644	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
phungductung	0:e87aa4c49e95	3645	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
phungductung	0:e87aa4c49e95	3646	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
phungductung	0:e87aa4c49e95	3647	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
phungductung	0:e87aa4c49e95	3648	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
phungductung	0:e87aa4c49e95	3649	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
phungductung	0:e87aa4c49e95	3650	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
phungductung	0:e87aa4c49e95	3651	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
phungductung	0:e87aa4c49e95	3652	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
phungductung	0:e87aa4c49e95	3653	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
phungductung	0:e87aa4c49e95	3654
phungductung	0:e87aa4c49e95	3655	/**************** Bit definition for EXTI_RTSR register *****************/
phungductung	0:e87aa4c49e95	3656	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
phungductung	0:e87aa4c49e95	3657	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
phungductung	0:e87aa4c49e95	3658	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
phungductung	0:e87aa4c49e95	3659	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
phungductung	0:e87aa4c49e95	3660	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
phungductung	0:e87aa4c49e95	3661	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
phungductung	0:e87aa4c49e95	3662	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
phungductung	0:e87aa4c49e95	3663	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
phungductung	0:e87aa4c49e95	3664	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
phungductung	0:e87aa4c49e95	3665	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
phungductung	0:e87aa4c49e95	3666	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
phungductung	0:e87aa4c49e95	3667	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
phungductung	0:e87aa4c49e95	3668	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
phungductung	0:e87aa4c49e95	3669	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
phungductung	0:e87aa4c49e95	3670	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
phungductung	0:e87aa4c49e95	3671	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
phungductung	0:e87aa4c49e95	3672	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
phungductung	0:e87aa4c49e95	3673	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
phungductung	0:e87aa4c49e95	3674	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
phungductung	0:e87aa4c49e95	3675	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
phungductung	0:e87aa4c49e95	3676	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
phungductung	0:e87aa4c49e95	3677	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
phungductung	0:e87aa4c49e95	3678	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
phungductung	0:e87aa4c49e95	3679	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
phungductung	0:e87aa4c49e95	3680
phungductung	0:e87aa4c49e95	3681	/**************** Bit definition for EXTI_FTSR register *****************/
phungductung	0:e87aa4c49e95	3682	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
phungductung	0:e87aa4c49e95	3683	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
phungductung	0:e87aa4c49e95	3684	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
phungductung	0:e87aa4c49e95	3685	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
phungductung	0:e87aa4c49e95	3686	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
phungductung	0:e87aa4c49e95	3687	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
phungductung	0:e87aa4c49e95	3688	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
phungductung	0:e87aa4c49e95	3689	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
phungductung	0:e87aa4c49e95	3690	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
phungductung	0:e87aa4c49e95	3691	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
phungductung	0:e87aa4c49e95	3692	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
phungductung	0:e87aa4c49e95	3693	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
phungductung	0:e87aa4c49e95	3694	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
phungductung	0:e87aa4c49e95	3695	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
phungductung	0:e87aa4c49e95	3696	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
phungductung	0:e87aa4c49e95	3697	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
phungductung	0:e87aa4c49e95	3698	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
phungductung	0:e87aa4c49e95	3699	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
phungductung	0:e87aa4c49e95	3700	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
phungductung	0:e87aa4c49e95	3701	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
phungductung	0:e87aa4c49e95	3702	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
phungductung	0:e87aa4c49e95	3703	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
phungductung	0:e87aa4c49e95	3704	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
phungductung	0:e87aa4c49e95	3705	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
phungductung	0:e87aa4c49e95	3706
phungductung	0:e87aa4c49e95	3707	/**************** Bit definition for EXTI_SWIER register ****************/
phungductung	0:e87aa4c49e95	3708	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
phungductung	0:e87aa4c49e95	3709	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
phungductung	0:e87aa4c49e95	3710	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
phungductung	0:e87aa4c49e95	3711	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
phungductung	0:e87aa4c49e95	3712	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
phungductung	0:e87aa4c49e95	3713	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
phungductung	0:e87aa4c49e95	3714	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
phungductung	0:e87aa4c49e95	3715	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
phungductung	0:e87aa4c49e95	3716	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
phungductung	0:e87aa4c49e95	3717	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
phungductung	0:e87aa4c49e95	3718	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
phungductung	0:e87aa4c49e95	3719	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
phungductung	0:e87aa4c49e95	3720	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
phungductung	0:e87aa4c49e95	3721	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
phungductung	0:e87aa4c49e95	3722	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
phungductung	0:e87aa4c49e95	3723	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
phungductung	0:e87aa4c49e95	3724	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
phungductung	0:e87aa4c49e95	3725	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
phungductung	0:e87aa4c49e95	3726	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
phungductung	0:e87aa4c49e95	3727	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
phungductung	0:e87aa4c49e95	3728	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
phungductung	0:e87aa4c49e95	3729	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
phungductung	0:e87aa4c49e95	3730	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
phungductung	0:e87aa4c49e95	3731	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
phungductung	0:e87aa4c49e95	3732
phungductung	0:e87aa4c49e95	3733	/***************** Bit definition for EXTI_PR register ******************/
phungductung	0:e87aa4c49e95	3734	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
phungductung	0:e87aa4c49e95	3735	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
phungductung	0:e87aa4c49e95	3736	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
phungductung	0:e87aa4c49e95	3737	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
phungductung	0:e87aa4c49e95	3738	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
phungductung	0:e87aa4c49e95	3739	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
phungductung	0:e87aa4c49e95	3740	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
phungductung	0:e87aa4c49e95	3741	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
phungductung	0:e87aa4c49e95	3742	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
phungductung	0:e87aa4c49e95	3743	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
phungductung	0:e87aa4c49e95	3744	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
phungductung	0:e87aa4c49e95	3745	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
phungductung	0:e87aa4c49e95	3746	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
phungductung	0:e87aa4c49e95	3747	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
phungductung	0:e87aa4c49e95	3748	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
phungductung	0:e87aa4c49e95	3749	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
phungductung	0:e87aa4c49e95	3750	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
phungductung	0:e87aa4c49e95	3751	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
phungductung	0:e87aa4c49e95	3752	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
phungductung	0:e87aa4c49e95	3753	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
phungductung	0:e87aa4c49e95	3754	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit for line 20 /
phungductung	0:e87aa4c49e95	3755	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit for line 21 /
phungductung	0:e87aa4c49e95	3756	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit for line 22 /
phungductung	0:e87aa4c49e95	3757	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit for line 23 /
phungductung	0:e87aa4c49e95	3758
phungductung	0:e87aa4c49e95	3759	/******************************************************************************/
phungductung	0:e87aa4c49e95	3760	/* */
phungductung	0:e87aa4c49e95	3761	/* FLASH */
phungductung	0:e87aa4c49e95	3762	/* */
phungductung	0:e87aa4c49e95	3763	/******************************************************************************/
phungductung	0:e87aa4c49e95	3764	/***************** Bits definition for FLASH_ACR register ***************/
phungductung	0:e87aa4c49e95	3765	#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	3766	#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	3767	#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3768	#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3769	#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
phungductung	0:e87aa4c49e95	3770	#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3771	#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
phungductung	0:e87aa4c49e95	3772	#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
phungductung	0:e87aa4c49e95	3773	#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
phungductung	0:e87aa4c49e95	3774	#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3775	#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
phungductung	0:e87aa4c49e95	3776	#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
phungductung	0:e87aa4c49e95	3777	#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
phungductung	0:e87aa4c49e95	3778	#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
phungductung	0:e87aa4c49e95	3779	#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
phungductung	0:e87aa4c49e95	3780	#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
phungductung	0:e87aa4c49e95	3781	#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	3782	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3783	#define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3784	#define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3785
phungductung	0:e87aa4c49e95	3786	/***************** Bits definition for FLASH_SR register ****************/
phungductung	0:e87aa4c49e95	3787	#define FLASH_SR_EOP ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3788	#define FLASH_SR_OPERR ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3789	#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3790	#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3791	#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3792	#define FLASH_SR_ERSERR ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	3793	#define FLASH_SR_BSY ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3794
phungductung	0:e87aa4c49e95	3795	/***************** Bits definition for FLASH_CR register ****************/
phungductung	0:e87aa4c49e95	3796	#define FLASH_CR_PG ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3797	#define FLASH_CR_SER ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3798	#define FLASH_CR_MER ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3799	#define FLASH_CR_SNB ((uint32_t)0x00000078)
phungductung	0:e87aa4c49e95	3800	#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3801	#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3802	#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3803	#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3804	#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	3805	#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3806	#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3807	#define FLASH_CR_STRT ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3808	#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	3809	#define FLASH_CR_ERRIE ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	3810	#define FLASH_CR_LOCK ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	3811
phungductung	0:e87aa4c49e95	3812	/***************** Bits definition for FLASH_OPTCR register *************/
phungductung	0:e87aa4c49e95	3813	#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	3814	#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	3815	#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
phungductung	0:e87aa4c49e95	3816	#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	3817	#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	3818	#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	3819	#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	3820	#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	3821	#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	3822	#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
phungductung	0:e87aa4c49e95	3823	#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	3824	#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	3825	#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	3826	#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	3827	#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	3828	#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	3829	#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	3830	#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	3831	#define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
phungductung	0:e87aa4c49e95	3832	#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	3833	#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	3834	#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	3835	#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	3836	#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	3837	#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	3838	#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	3839	#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	3840	#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	3841	#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	3842
phungductung	0:e87aa4c49e95	3843	/***************** Bits definition for FLASH_OPTCR1 register *************/
phungductung	0:e87aa4c49e95	3844	#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
phungductung	0:e87aa4c49e95	3845	#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
phungductung	0:e87aa4c49e95	3846
phungductung	0:e87aa4c49e95	3847	/******************************************************************************/
phungductung	0:e87aa4c49e95	3848	/* */
phungductung	0:e87aa4c49e95	3849	/* Flexible Memory Controller */
phungductung	0:e87aa4c49e95	3850	/* */
phungductung	0:e87aa4c49e95	3851	/******************************************************************************/
phungductung	0:e87aa4c49e95	3852	/**************** Bit definition for FMC_BCR1 register *****************/
phungductung	0:e87aa4c49e95	3853	#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
phungductung	0:e87aa4c49e95	3854	#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
phungductung	0:e87aa4c49e95	3855
phungductung	0:e87aa4c49e95	3856	#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
phungductung	0:e87aa4c49e95	3857	#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3858	#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3859
phungductung	0:e87aa4c49e95	3860	#define FMC_BCR1_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
phungductung	0:e87aa4c49e95	3861	#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3862	#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3863
phungductung	0:e87aa4c49e95	3864	#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
phungductung	0:e87aa4c49e95	3865	#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
phungductung	0:e87aa4c49e95	3866	#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
phungductung	0:e87aa4c49e95	3867	#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
phungductung	0:e87aa4c49e95	3868	#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
phungductung	0:e87aa4c49e95	3869	#define FMC_BCR1_WREN ((uint32_t)0x00001000) /!<Write enable bit /
phungductung	0:e87aa4c49e95	3870	#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
phungductung	0:e87aa4c49e95	3871	#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
phungductung	0:e87aa4c49e95	3872	#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
phungductung	0:e87aa4c49e95	3873	#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
phungductung	0:e87aa4c49e95	3874	#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3875	#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3876	#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3877	#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
phungductung	0:e87aa4c49e95	3878	#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /!<Continous clock enable /
phungductung	0:e87aa4c49e95	3879	#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /!<Write FIFO Disable /
phungductung	0:e87aa4c49e95	3880
phungductung	0:e87aa4c49e95	3881	/**************** Bit definition for FMC_BCR2 register *****************/
phungductung	0:e87aa4c49e95	3882	#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
phungductung	0:e87aa4c49e95	3883	#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
phungductung	0:e87aa4c49e95	3884
phungductung	0:e87aa4c49e95	3885	#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
phungductung	0:e87aa4c49e95	3886	#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3887	#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3888
phungductung	0:e87aa4c49e95	3889	#define FMC_BCR2_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
phungductung	0:e87aa4c49e95	3890	#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3891	#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3892
phungductung	0:e87aa4c49e95	3893	#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
phungductung	0:e87aa4c49e95	3894	#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
phungductung	0:e87aa4c49e95	3895	#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
phungductung	0:e87aa4c49e95	3896	#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
phungductung	0:e87aa4c49e95	3897	#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
phungductung	0:e87aa4c49e95	3898	#define FMC_BCR2_WREN ((uint32_t)0x00001000) /!<Write enable bit /
phungductung	0:e87aa4c49e95	3899	#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
phungductung	0:e87aa4c49e95	3900	#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
phungductung	0:e87aa4c49e95	3901	#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
phungductung	0:e87aa4c49e95	3902	#define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
phungductung	0:e87aa4c49e95	3903	#define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3904	#define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3905	#define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3906	#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
phungductung	0:e87aa4c49e95	3907
phungductung	0:e87aa4c49e95	3908	/**************** Bit definition for FMC_BCR3 register *****************/
phungductung	0:e87aa4c49e95	3909	#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
phungductung	0:e87aa4c49e95	3910	#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
phungductung	0:e87aa4c49e95	3911
phungductung	0:e87aa4c49e95	3912	#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
phungductung	0:e87aa4c49e95	3913	#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3914	#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3915
phungductung	0:e87aa4c49e95	3916	#define FMC_BCR3_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
phungductung	0:e87aa4c49e95	3917	#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3918	#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3919
phungductung	0:e87aa4c49e95	3920	#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
phungductung	0:e87aa4c49e95	3921	#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
phungductung	0:e87aa4c49e95	3922	#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
phungductung	0:e87aa4c49e95	3923	#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
phungductung	0:e87aa4c49e95	3924	#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
phungductung	0:e87aa4c49e95	3925	#define FMC_BCR3_WREN ((uint32_t)0x00001000) /!<Write enable bit /
phungductung	0:e87aa4c49e95	3926	#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
phungductung	0:e87aa4c49e95	3927	#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
phungductung	0:e87aa4c49e95	3928	#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
phungductung	0:e87aa4c49e95	3929	#define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
phungductung	0:e87aa4c49e95	3930	#define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3931	#define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3932	#define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3933	#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
phungductung	0:e87aa4c49e95	3934
phungductung	0:e87aa4c49e95	3935	/**************** Bit definition for FMC_BCR4 register *****************/
phungductung	0:e87aa4c49e95	3936	#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
phungductung	0:e87aa4c49e95	3937	#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
phungductung	0:e87aa4c49e95	3938
phungductung	0:e87aa4c49e95	3939	#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
phungductung	0:e87aa4c49e95	3940	#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3941	#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3942
phungductung	0:e87aa4c49e95	3943	#define FMC_BCR4_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
phungductung	0:e87aa4c49e95	3944	#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3945	#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3946
phungductung	0:e87aa4c49e95	3947	#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
phungductung	0:e87aa4c49e95	3948	#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
phungductung	0:e87aa4c49e95	3949	#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
phungductung	0:e87aa4c49e95	3950	#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /!<Wrapped burst mode support /
phungductung	0:e87aa4c49e95	3951	#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
phungductung	0:e87aa4c49e95	3952	#define FMC_BCR4_WREN ((uint32_t)0x00001000) /!<Write enable bit /
phungductung	0:e87aa4c49e95	3953	#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
phungductung	0:e87aa4c49e95	3954	#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
phungductung	0:e87aa4c49e95	3955	#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
phungductung	0:e87aa4c49e95	3956	#define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
phungductung	0:e87aa4c49e95	3957	#define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3958	#define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3959	#define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3960	#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
phungductung	0:e87aa4c49e95	3961
phungductung	0:e87aa4c49e95	3962	/**************** Bit definition for FMC_BTR1 register ****************/
phungductung	0:e87aa4c49e95	3963	#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	3964	#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3965	#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3966	#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3967	#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3968
phungductung	0:e87aa4c49e95	3969	#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	3970	#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3971	#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3972	#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3973	#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3974
phungductung	0:e87aa4c49e95	3975	#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	3976	#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3977	#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3978	#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3979	#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3980	#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	3981	#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	3982	#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	3983	#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	3984
phungductung	0:e87aa4c49e95	3985	#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	3986	#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3987	#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3988	#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3989	#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3990
phungductung	0:e87aa4c49e95	3991	#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
phungductung	0:e87aa4c49e95	3992	#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3993	#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	3994	#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	3995	#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	3996
phungductung	0:e87aa4c49e95	3997	#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
phungductung	0:e87aa4c49e95	3998	#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	3999	#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4000	#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4001	#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4002
phungductung	0:e87aa4c49e95	4003	#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4004	#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4005	#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4006
phungductung	0:e87aa4c49e95	4007	/**************** Bit definition for FMC_BTR2 register *****************/
phungductung	0:e87aa4c49e95	4008	#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4009	#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4010	#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4011	#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4012	#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4013
phungductung	0:e87aa4c49e95	4014	#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4015	#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4016	#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4017	#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4018	#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4019
phungductung	0:e87aa4c49e95	4020	#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4021	#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4022	#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4023	#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4024	#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4025	#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4026	#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4027	#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4028	#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4029
phungductung	0:e87aa4c49e95	4030	#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4031	#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4032	#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4033	#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4034	#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4035
phungductung	0:e87aa4c49e95	4036	#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
phungductung	0:e87aa4c49e95	4037	#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4038	#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4039	#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4040	#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4041
phungductung	0:e87aa4c49e95	4042	#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
phungductung	0:e87aa4c49e95	4043	#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4044	#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4045	#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4046	#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4047
phungductung	0:e87aa4c49e95	4048	#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4049	#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4050	#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4051
phungductung	0:e87aa4c49e95	4052	/***************** Bit definition for FMC_BTR3 register *****************/
phungductung	0:e87aa4c49e95	4053	#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4054	#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4055	#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4056	#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4057	#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4058
phungductung	0:e87aa4c49e95	4059	#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4060	#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4061	#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4062	#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4063	#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4064
phungductung	0:e87aa4c49e95	4065	#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4066	#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4067	#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4068	#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4069	#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4070	#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4071	#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4072	#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4073	#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4074
phungductung	0:e87aa4c49e95	4075	#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4076	#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4077	#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4078	#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4079	#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4080
phungductung	0:e87aa4c49e95	4081	#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
phungductung	0:e87aa4c49e95	4082	#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4083	#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4084	#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4085	#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4086
phungductung	0:e87aa4c49e95	4087	#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
phungductung	0:e87aa4c49e95	4088	#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4089	#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4090	#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4091	#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4092
phungductung	0:e87aa4c49e95	4093	#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4094	#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4095	#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4096
phungductung	0:e87aa4c49e95	4097	/**************** Bit definition for FMC_BTR4 register *****************/
phungductung	0:e87aa4c49e95	4098	#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4099	#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4100	#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4101	#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4102	#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4103
phungductung	0:e87aa4c49e95	4104	#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4105	#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4106	#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4107	#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4108	#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4109
phungductung	0:e87aa4c49e95	4110	#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4111	#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4112	#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4113	#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4114	#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4115	#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4116	#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4117	#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4118	#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4119
phungductung	0:e87aa4c49e95	4120	#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4121	#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4122	#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4123	#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4124	#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4125
phungductung	0:e87aa4c49e95	4126	#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
phungductung	0:e87aa4c49e95	4127	#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4128	#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4129	#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4130	#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4131
phungductung	0:e87aa4c49e95	4132	#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
phungductung	0:e87aa4c49e95	4133	#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4134	#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4135	#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4136	#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4137
phungductung	0:e87aa4c49e95	4138	#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4139	#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4140	#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4141
phungductung	0:e87aa4c49e95	4142	/**************** Bit definition for FMC_BWTR1 register ****************/
phungductung	0:e87aa4c49e95	4143	#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4144	#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4145	#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4146	#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4147	#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4148
phungductung	0:e87aa4c49e95	4149	#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4150	#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4151	#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4152	#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4153	#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4154
phungductung	0:e87aa4c49e95	4155	#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4156	#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4157	#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4158	#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4159	#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4160	#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4161	#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4162	#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4163	#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4164
phungductung	0:e87aa4c49e95	4165	#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4166	#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4167	#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4168	#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4169	#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4170
phungductung	0:e87aa4c49e95	4171	#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4172	#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4173	#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4174
phungductung	0:e87aa4c49e95	4175	/**************** Bit definition for FMC_BWTR2 register ****************/
phungductung	0:e87aa4c49e95	4176	#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4177	#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4178	#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4179	#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4180	#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4181
phungductung	0:e87aa4c49e95	4182	#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4183	#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4184	#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4185	#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4186	#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4187
phungductung	0:e87aa4c49e95	4188	#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4189	#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4190	#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4191	#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4192	#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4193	#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4194	#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4195	#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4196	#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4197
phungductung	0:e87aa4c49e95	4198	#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4199	#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4200	#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4201	#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4202	#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4203
phungductung	0:e87aa4c49e95	4204	#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4205	#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4206	#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4207
phungductung	0:e87aa4c49e95	4208	/**************** Bit definition for FMC_BWTR3 register ****************/
phungductung	0:e87aa4c49e95	4209	#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4210	#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4211	#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4212	#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4213	#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4214
phungductung	0:e87aa4c49e95	4215	#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4216	#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4217	#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4218	#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4219	#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4220
phungductung	0:e87aa4c49e95	4221	#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4222	#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4223	#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4224	#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4225	#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4226	#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4227	#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4228	#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4229	#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4230
phungductung	0:e87aa4c49e95	4231	#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4232	#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4233	#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4234	#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4235	#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4236
phungductung	0:e87aa4c49e95	4237	#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4238	#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4239	#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4240
phungductung	0:e87aa4c49e95	4241	/**************** Bit definition for FMC_BWTR4 register ****************/
phungductung	0:e87aa4c49e95	4242	#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
phungductung	0:e87aa4c49e95	4243	#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4244	#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4245	#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4246	#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4247
phungductung	0:e87aa4c49e95	4248	#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
phungductung	0:e87aa4c49e95	4249	#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4250	#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4251	#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4252	#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4253
phungductung	0:e87aa4c49e95	4254	#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
phungductung	0:e87aa4c49e95	4255	#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4256	#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4257	#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4258	#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4259	#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4260	#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4261	#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4262	#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4263
phungductung	0:e87aa4c49e95	4264	#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
phungductung	0:e87aa4c49e95	4265	#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4266	#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4267	#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4268	#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4269
phungductung	0:e87aa4c49e95	4270	#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
phungductung	0:e87aa4c49e95	4271	#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4272	#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4273
phungductung	0:e87aa4c49e95	4274	/**************** Bit definition for FMC_PCR register *****************/
phungductung	0:e87aa4c49e95	4275	#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
phungductung	0:e87aa4c49e95	4276	#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /!<PC Card/NAND Flash memory bank enable bit /
phungductung	0:e87aa4c49e95	4277	#define FMC_PCR_PTYP ((uint32_t)0x00000008) /!<Memory type /
phungductung	0:e87aa4c49e95	4278
phungductung	0:e87aa4c49e95	4279	#define FMC_PCR_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
phungductung	0:e87aa4c49e95	4280	#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4281	#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4282
phungductung	0:e87aa4c49e95	4283	#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
phungductung	0:e87aa4c49e95	4284
phungductung	0:e87aa4c49e95	4285	#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
phungductung	0:e87aa4c49e95	4286	#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4287	#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4288	#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4289	#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4290
phungductung	0:e87aa4c49e95	4291	#define FMC_PCR_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
phungductung	0:e87aa4c49e95	4292	#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4293	#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4294	#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4295	#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4296
phungductung	0:e87aa4c49e95	4297	#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[2:0] bits (ECC page size) /
phungductung	0:e87aa4c49e95	4298	#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4299	#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4300	#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4301
phungductung	0:e87aa4c49e95	4302	/***************** Bit definition for FMC_SR register *****************/
phungductung	0:e87aa4c49e95	4303	#define FMC_SR_IRS ((uint32_t)0x01) /!<Interrupt Rising Edge status /
phungductung	0:e87aa4c49e95	4304	#define FMC_SR_ILS ((uint32_t)0x02) /!<Interrupt Level status /
phungductung	0:e87aa4c49e95	4305	#define FMC_SR_IFS ((uint32_t)0x04) /!<Interrupt Falling Edge status /
phungductung	0:e87aa4c49e95	4306	#define FMC_SR_IREN ((uint32_t)0x08) /!<Interrupt Rising Edge detection Enable bit /
phungductung	0:e87aa4c49e95	4307	#define FMC_SR_ILEN ((uint32_t)0x10) /!<Interrupt Level detection Enable bit /
phungductung	0:e87aa4c49e95	4308	#define FMC_SR_IFEN ((uint32_t)0x20) /!<Interrupt Falling Edge detection Enable bit /
phungductung	0:e87aa4c49e95	4309	#define FMC_SR_FEMPT ((uint32_t)0x40) /!<FIFO empty /
phungductung	0:e87aa4c49e95	4310
phungductung	0:e87aa4c49e95	4311	/**************** Bit definition for FMC_PMEM register ****************/
phungductung	0:e87aa4c49e95	4312	#define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /!<MEMSET3[7:0] bits (Common memory 3 setup time) /
phungductung	0:e87aa4c49e95	4313	#define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4314	#define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4315	#define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4316	#define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4317	#define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4318	#define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4319	#define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4320	#define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4321
phungductung	0:e87aa4c49e95	4322	#define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /!<MEMWAIT3[7:0] bits (Common memory 3 wait time) /
phungductung	0:e87aa4c49e95	4323	#define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4324	#define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4325	#define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4326	#define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4327	#define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4328	#define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4329	#define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4330	#define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4331
phungductung	0:e87aa4c49e95	4332	#define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /!<MEMHOLD3[7:0] bits (Common memory 3 hold time) /
phungductung	0:e87aa4c49e95	4333	#define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4334	#define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4335	#define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4336	#define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4337	#define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4338	#define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4339	#define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4340	#define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4341
phungductung	0:e87aa4c49e95	4342	#define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) /
phungductung	0:e87aa4c49e95	4343	#define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4344	#define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4345	#define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4346	#define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4347	#define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4348	#define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4349	#define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4350	#define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4351
phungductung	0:e87aa4c49e95	4352	/**************** Bit definition for FMC_PATT register ****************/
phungductung	0:e87aa4c49e95	4353	#define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /!<ATTSET3[7:0] bits (Attribute memory 3 setup time) /
phungductung	0:e87aa4c49e95	4354	#define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4355	#define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4356	#define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4357	#define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4358	#define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4359	#define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4360	#define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4361	#define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4362
phungductung	0:e87aa4c49e95	4363	#define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) /
phungductung	0:e87aa4c49e95	4364	#define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4365	#define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4366	#define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4367	#define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4368	#define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4369	#define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4370	#define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4371	#define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4372
phungductung	0:e87aa4c49e95	4373	#define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) /
phungductung	0:e87aa4c49e95	4374	#define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4375	#define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4376	#define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4377	#define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4378	#define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4379	#define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4380	#define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4381	#define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4382
phungductung	0:e87aa4c49e95	4383	#define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) /
phungductung	0:e87aa4c49e95	4384	#define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4385	#define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4386	#define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4387	#define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4388	#define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	4389	#define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	4390	#define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	4391	#define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	4392
phungductung	0:e87aa4c49e95	4393	/**************** Bit definition for FMC_ECCR register ****************/
phungductung	0:e87aa4c49e95	4394	#define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /!<ECC result /
phungductung	0:e87aa4c49e95	4395
phungductung	0:e87aa4c49e95	4396	/**************** Bit definition for FMC_SDCR1 register ****************/
phungductung	0:e87aa4c49e95	4397	#define FMC_SDCR1_NC ((uint32_t)0x00000003) /!<NC[1:0] bits (Number of column bits) /
phungductung	0:e87aa4c49e95	4398	#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4399	#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4400
phungductung	0:e87aa4c49e95	4401	#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /!<NR[1:0] bits (Number of row bits) /
phungductung	0:e87aa4c49e95	4402	#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4403	#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4404
phungductung	0:e87aa4c49e95	4405	#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /!<NR[1:0] bits (Number of row bits) /
phungductung	0:e87aa4c49e95	4406	#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4407	#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4408
phungductung	0:e87aa4c49e95	4409	#define FMC_SDCR1_NB ((uint32_t)0x00000040) /!<Number of internal bank /
phungductung	0:e87aa4c49e95	4410
phungductung	0:e87aa4c49e95	4411	#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /!<CAS[1:0] bits (CAS latency) /
phungductung	0:e87aa4c49e95	4412	#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4413	#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4414
phungductung	0:e87aa4c49e95	4415	#define FMC_SDCR1_WP ((uint32_t)0x00000200) /!<Write protection /
phungductung	0:e87aa4c49e95	4416
phungductung	0:e87aa4c49e95	4417	#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /!<SDRAM clock configuration /
phungductung	0:e87aa4c49e95	4418	#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4419	#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4420
phungductung	0:e87aa4c49e95	4421	#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /!<Read burst /
phungductung	0:e87aa4c49e95	4422
phungductung	0:e87aa4c49e95	4423	#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /!<Write protection /
phungductung	0:e87aa4c49e95	4424	#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4425	#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4426
phungductung	0:e87aa4c49e95	4427	/**************** Bit definition for FMC_SDCR2 register ****************/
phungductung	0:e87aa4c49e95	4428	#define FMC_SDCR2_NC ((uint32_t)0x00000003) /!<NC[1:0] bits (Number of column bits) /
phungductung	0:e87aa4c49e95	4429	#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4430	#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4431
phungductung	0:e87aa4c49e95	4432	#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /!<NR[1:0] bits (Number of row bits) /
phungductung	0:e87aa4c49e95	4433	#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4434	#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4435
phungductung	0:e87aa4c49e95	4436	#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /!<NR[1:0] bits (Number of row bits) /
phungductung	0:e87aa4c49e95	4437	#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4438	#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4439
phungductung	0:e87aa4c49e95	4440	#define FMC_SDCR2_NB ((uint32_t)0x00000040) /!<Number of internal bank /
phungductung	0:e87aa4c49e95	4441
phungductung	0:e87aa4c49e95	4442	#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /!<CAS[1:0] bits (CAS latency) /
phungductung	0:e87aa4c49e95	4443	#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4444	#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4445
phungductung	0:e87aa4c49e95	4446	#define FMC_SDCR2_WP ((uint32_t)0x00000200) /!<Write protection /
phungductung	0:e87aa4c49e95	4447
phungductung	0:e87aa4c49e95	4448	#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /!<SDCLK[1:0] (SDRAM clock configuration) /
phungductung	0:e87aa4c49e95	4449	#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4450	#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4451
phungductung	0:e87aa4c49e95	4452	#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /!<Read burst /
phungductung	0:e87aa4c49e95	4453
phungductung	0:e87aa4c49e95	4454	#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /!<RPIPE[1:0](Read pipe) /
phungductung	0:e87aa4c49e95	4455	#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4456	#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4457
phungductung	0:e87aa4c49e95	4458	/**************** Bit definition for FMC_SDTR1 register ****************/
phungductung	0:e87aa4c49e95	4459	#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /!<TMRD[3:0] bits (Load mode register to active) /
phungductung	0:e87aa4c49e95	4460	#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4461	#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4462	#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4463	#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4464
phungductung	0:e87aa4c49e95	4465	#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /!<TXSR[3:0] bits (Exit self refresh) /
phungductung	0:e87aa4c49e95	4466	#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4467	#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4468	#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4469	#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4470
phungductung	0:e87aa4c49e95	4471	#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /!<TRAS[3:0] bits (Self refresh time) /
phungductung	0:e87aa4c49e95	4472	#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4473	#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4474	#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4475	#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4476
phungductung	0:e87aa4c49e95	4477	#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /!<TRC[2:0] bits (Row cycle delay) /
phungductung	0:e87aa4c49e95	4478	#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4479	#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4480	#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4481
phungductung	0:e87aa4c49e95	4482	#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /!<TRC[2:0] bits (Write recovery delay) /
phungductung	0:e87aa4c49e95	4483	#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4484	#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4485	#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4486
phungductung	0:e87aa4c49e95	4487	#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /!<TRP[2:0] bits (Row precharge delay) /
phungductung	0:e87aa4c49e95	4488	#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4489	#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4490	#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4491
phungductung	0:e87aa4c49e95	4492	#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /!<TRP[2:0] bits (Row to column delay) /
phungductung	0:e87aa4c49e95	4493	#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4494	#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4495	#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4496
phungductung	0:e87aa4c49e95	4497	/**************** Bit definition for FMC_SDTR2 register ****************/
phungductung	0:e87aa4c49e95	4498	#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /!<TMRD[3:0] bits (Load mode register to active) /
phungductung	0:e87aa4c49e95	4499	#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4500	#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4501	#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4502	#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4503
phungductung	0:e87aa4c49e95	4504	#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /!<TXSR[3:0] bits (Exit self refresh) /
phungductung	0:e87aa4c49e95	4505	#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4506	#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4507	#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4508	#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4509
phungductung	0:e87aa4c49e95	4510	#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /!<TRAS[3:0] bits (Self refresh time) /
phungductung	0:e87aa4c49e95	4511	#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4512	#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4513	#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4514	#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4515
phungductung	0:e87aa4c49e95	4516	#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /!<TRC[2:0] bits (Row cycle delay) /
phungductung	0:e87aa4c49e95	4517	#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4518	#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4519	#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4520
phungductung	0:e87aa4c49e95	4521	#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /!<TRC[2:0] bits (Write recovery delay) /
phungductung	0:e87aa4c49e95	4522	#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4523	#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4524	#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4525
phungductung	0:e87aa4c49e95	4526	#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /!<TRP[2:0] bits (Row precharge delay) /
phungductung	0:e87aa4c49e95	4527	#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4528	#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4529	#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4530
phungductung	0:e87aa4c49e95	4531	#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /!<TRP[2:0] bits (Row to column delay) /
phungductung	0:e87aa4c49e95	4532	#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4533	#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4534	#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4535
phungductung	0:e87aa4c49e95	4536	/**************** Bit definition for FMC_SDCMR register ****************/
phungductung	0:e87aa4c49e95	4537	#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /!<MODE[2:0] bits (Command mode) /
phungductung	0:e87aa4c49e95	4538	#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4539	#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4540	#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4541
phungductung	0:e87aa4c49e95	4542	#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /!<Command target 2 /
phungductung	0:e87aa4c49e95	4543
phungductung	0:e87aa4c49e95	4544	#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /!<Command target 1 /
phungductung	0:e87aa4c49e95	4545
phungductung	0:e87aa4c49e95	4546	#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /!<NRFS[3:0] bits (Number of auto-refresh) /
phungductung	0:e87aa4c49e95	4547	#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4548	#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4549	#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /!<Bit 2 /
phungductung	0:e87aa4c49e95	4550	#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /!<Bit 3 /
phungductung	0:e87aa4c49e95	4551
phungductung	0:e87aa4c49e95	4552	#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /!<MRD[12:0] bits (Mode register definition) /
phungductung	0:e87aa4c49e95	4553
phungductung	0:e87aa4c49e95	4554	/**************** Bit definition for FMC_SDRTR register ****************/
phungductung	0:e87aa4c49e95	4555	#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /!<Clear refresh error flag /
phungductung	0:e87aa4c49e95	4556
phungductung	0:e87aa4c49e95	4557	#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /!<COUNT[12:0] bits (Refresh timer count) /
phungductung	0:e87aa4c49e95	4558
phungductung	0:e87aa4c49e95	4559	#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /!<RES interupt enable /
phungductung	0:e87aa4c49e95	4560
phungductung	0:e87aa4c49e95	4561	/**************** Bit definition for FMC_SDSR register ****************/
phungductung	0:e87aa4c49e95	4562	#define FMC_SDSR_RE ((uint32_t)0x00000001) /!<Refresh error flag /
phungductung	0:e87aa4c49e95	4563
phungductung	0:e87aa4c49e95	4564	#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /!<MODES1[1:0]bits (Status mode for bank 1) /
phungductung	0:e87aa4c49e95	4565	#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4566	#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4567
phungductung	0:e87aa4c49e95	4568	#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /!<MODES2[1:0]bits (Status mode for bank 2) /
phungductung	0:e87aa4c49e95	4569	#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /!<Bit 0 /
phungductung	0:e87aa4c49e95	4570	#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /!<Bit 1 /
phungductung	0:e87aa4c49e95	4571
phungductung	0:e87aa4c49e95	4572	#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /!<Busy status /
phungductung	0:e87aa4c49e95	4573
phungductung	0:e87aa4c49e95	4574	/******************************************************************************/
phungductung	0:e87aa4c49e95	4575	/* */
phungductung	0:e87aa4c49e95	4576	/* General Purpose I/O */
phungductung	0:e87aa4c49e95	4577	/* */
phungductung	0:e87aa4c49e95	4578	/******************************************************************************/
phungductung	0:e87aa4c49e95	4579	/**************** Bits definition for GPIO_MODER register ***************/
phungductung	0:e87aa4c49e95	4580	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
phungductung	0:e87aa4c49e95	4581	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4582	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4583
phungductung	0:e87aa4c49e95	4584	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
phungductung	0:e87aa4c49e95	4585	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4586	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4587
phungductung	0:e87aa4c49e95	4588	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
phungductung	0:e87aa4c49e95	4589	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4590	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4591
phungductung	0:e87aa4c49e95	4592	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
phungductung	0:e87aa4c49e95	4593	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4594	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4595
phungductung	0:e87aa4c49e95	4596	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	4597	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4598	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4599
phungductung	0:e87aa4c49e95	4600	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
phungductung	0:e87aa4c49e95	4601	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4602	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4603
phungductung	0:e87aa4c49e95	4604	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
phungductung	0:e87aa4c49e95	4605	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4606	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4607
phungductung	0:e87aa4c49e95	4608	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
phungductung	0:e87aa4c49e95	4609	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4610	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4611
phungductung	0:e87aa4c49e95	4612	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	4613	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	4614	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	4615
phungductung	0:e87aa4c49e95	4616	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
phungductung	0:e87aa4c49e95	4617	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	4618	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	4619
phungductung	0:e87aa4c49e95	4620	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	4621	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	4622	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	4623
phungductung	0:e87aa4c49e95	4624	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
phungductung	0:e87aa4c49e95	4625	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	4626	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	4627
phungductung	0:e87aa4c49e95	4628	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
phungductung	0:e87aa4c49e95	4629	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	4630	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	4631
phungductung	0:e87aa4c49e95	4632	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
phungductung	0:e87aa4c49e95	4633	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	4634	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	4635
phungductung	0:e87aa4c49e95	4636	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
phungductung	0:e87aa4c49e95	4637	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	4638	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	4639
phungductung	0:e87aa4c49e95	4640	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
phungductung	0:e87aa4c49e95	4641	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	4642	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	4643
phungductung	0:e87aa4c49e95	4644	/**************** Bits definition for GPIO_OTYPER register **************/
phungductung	0:e87aa4c49e95	4645	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4646	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4647	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4648	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4649	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4650	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4651	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4652	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4653	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4654	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4655	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4656	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4657	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4658	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4659	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4660	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4661
phungductung	0:e87aa4c49e95	4662	/**************** Bits definition for GPIO_OSPEEDR register *************/
phungductung	0:e87aa4c49e95	4663	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
phungductung	0:e87aa4c49e95	4664	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4665	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4666
phungductung	0:e87aa4c49e95	4667	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
phungductung	0:e87aa4c49e95	4668	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4669	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4670
phungductung	0:e87aa4c49e95	4671	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
phungductung	0:e87aa4c49e95	4672	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4673	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4674
phungductung	0:e87aa4c49e95	4675	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
phungductung	0:e87aa4c49e95	4676	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4677	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4678
phungductung	0:e87aa4c49e95	4679	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	4680	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4681	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4682
phungductung	0:e87aa4c49e95	4683	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
phungductung	0:e87aa4c49e95	4684	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4685	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4686
phungductung	0:e87aa4c49e95	4687	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
phungductung	0:e87aa4c49e95	4688	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4689	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4690
phungductung	0:e87aa4c49e95	4691	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
phungductung	0:e87aa4c49e95	4692	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4693	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4694
phungductung	0:e87aa4c49e95	4695	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	4696	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	4697	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	4698
phungductung	0:e87aa4c49e95	4699	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
phungductung	0:e87aa4c49e95	4700	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	4701	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	4702
phungductung	0:e87aa4c49e95	4703	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	4704	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	4705	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	4706
phungductung	0:e87aa4c49e95	4707	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
phungductung	0:e87aa4c49e95	4708	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	4709	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	4710
phungductung	0:e87aa4c49e95	4711	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
phungductung	0:e87aa4c49e95	4712	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	4713	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	4714
phungductung	0:e87aa4c49e95	4715	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
phungductung	0:e87aa4c49e95	4716	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	4717	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	4718
phungductung	0:e87aa4c49e95	4719	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
phungductung	0:e87aa4c49e95	4720	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	4721	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	4722
phungductung	0:e87aa4c49e95	4723	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
phungductung	0:e87aa4c49e95	4724	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	4725	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	4726
phungductung	0:e87aa4c49e95	4727	/**************** Bits definition for GPIO_PUPDR register ***************/
phungductung	0:e87aa4c49e95	4728	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
phungductung	0:e87aa4c49e95	4729	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4730	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4731
phungductung	0:e87aa4c49e95	4732	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
phungductung	0:e87aa4c49e95	4733	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4734	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4735
phungductung	0:e87aa4c49e95	4736	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
phungductung	0:e87aa4c49e95	4737	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4738	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4739
phungductung	0:e87aa4c49e95	4740	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
phungductung	0:e87aa4c49e95	4741	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4742	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4743
phungductung	0:e87aa4c49e95	4744	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	4745	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4746	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4747
phungductung	0:e87aa4c49e95	4748	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
phungductung	0:e87aa4c49e95	4749	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4750	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4751
phungductung	0:e87aa4c49e95	4752	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
phungductung	0:e87aa4c49e95	4753	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4754	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4755
phungductung	0:e87aa4c49e95	4756	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
phungductung	0:e87aa4c49e95	4757	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4758	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4759
phungductung	0:e87aa4c49e95	4760	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	4761	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	4762	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	4763
phungductung	0:e87aa4c49e95	4764	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
phungductung	0:e87aa4c49e95	4765	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	4766	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	4767
phungductung	0:e87aa4c49e95	4768	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	4769	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	4770	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	4771
phungductung	0:e87aa4c49e95	4772	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
phungductung	0:e87aa4c49e95	4773	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	4774	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	4775
phungductung	0:e87aa4c49e95	4776	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
phungductung	0:e87aa4c49e95	4777	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	4778	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	4779
phungductung	0:e87aa4c49e95	4780	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
phungductung	0:e87aa4c49e95	4781	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	4782	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	4783
phungductung	0:e87aa4c49e95	4784	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
phungductung	0:e87aa4c49e95	4785	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	4786	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	4787
phungductung	0:e87aa4c49e95	4788	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
phungductung	0:e87aa4c49e95	4789	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	4790	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	4791
phungductung	0:e87aa4c49e95	4792	/**************** Bits definition for GPIO_IDR register *****************/
phungductung	0:e87aa4c49e95	4793	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4794	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4795	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4796	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4797	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4798	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4799	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4800	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4801	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4802	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4803	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4804	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4805	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4806	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4807	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4808	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4809
phungductung	0:e87aa4c49e95	4810	/**************** Bits definition for GPIO_ODR register *****************/
phungductung	0:e87aa4c49e95	4811	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4812	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4813	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4814	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4815	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4816	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4817	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4818	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4819	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4820	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4821	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4822	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4823	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4824	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4825	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4826	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4827
phungductung	0:e87aa4c49e95	4828	/**************** Bits definition for GPIO_BSRR register ****************/
phungductung	0:e87aa4c49e95	4829	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4830	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4831	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4832	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4833	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4834	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4835	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4836	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4837	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4838	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4839	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4840	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4841	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4842	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4843	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4844	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4845	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	4846	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	4847	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	4848	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	4849	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	4850	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	4851	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	4852	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	4853	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	4854	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	4855	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	4856	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	4857	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	4858	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	4859	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	4860	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	4861
phungductung	0:e87aa4c49e95	4862	/**************** Bit definition for GPIO_LCKR register *******************/
phungductung	0:e87aa4c49e95	4863	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	4864	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	4865	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	4866	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	4867	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	4868	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	4869	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	4870	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	4871	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	4872	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	4873	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	4874	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	4875	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	4876	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	4877	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	4878	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	4879	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	4880
phungductung	0:e87aa4c49e95	4881
phungductung	0:e87aa4c49e95	4882	/******************************************************************************/
phungductung	0:e87aa4c49e95	4883	/* */
phungductung	0:e87aa4c49e95	4884	/* Inter-integrated Circuit Interface (I2C) */
phungductung	0:e87aa4c49e95	4885	/* */
phungductung	0:e87aa4c49e95	4886	/******************************************************************************/
phungductung	0:e87aa4c49e95	4887	/***************** Bit definition for I2C_CR1 register *****************/
phungductung	0:e87aa4c49e95	4888	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
phungductung	0:e87aa4c49e95	4889	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
phungductung	0:e87aa4c49e95	4890	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
phungductung	0:e87aa4c49e95	4891	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
phungductung	0:e87aa4c49e95	4892	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
phungductung	0:e87aa4c49e95	4893	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
phungductung	0:e87aa4c49e95	4894	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
phungductung	0:e87aa4c49e95	4895	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
phungductung	0:e87aa4c49e95	4896	#define I2C_CR1_DNF ((uint32_t)0x00000F00) /!< Digital noise filter /
phungductung	0:e87aa4c49e95	4897	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
phungductung	0:e87aa4c49e95	4898	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
phungductung	0:e87aa4c49e95	4899	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
phungductung	0:e87aa4c49e95	4900	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
phungductung	0:e87aa4c49e95	4901	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
phungductung	0:e87aa4c49e95	4902	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
phungductung	0:e87aa4c49e95	4903	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
phungductung	0:e87aa4c49e95	4904	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
phungductung	0:e87aa4c49e95	4905	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
phungductung	0:e87aa4c49e95	4906	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
phungductung	0:e87aa4c49e95	4907	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
phungductung	0:e87aa4c49e95	4908	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
phungductung	0:e87aa4c49e95	4909
phungductung	0:e87aa4c49e95	4910	/* Legacy define */
phungductung	0:e87aa4c49e95	4911	#define I2C_CR1_DFN I2C_CR1_DNF /!< Digital noise filter /
phungductung	0:e87aa4c49e95	4912
phungductung	0:e87aa4c49e95	4913	/**************** Bit definition for I2C_CR2 register ******************/
phungductung	0:e87aa4c49e95	4914	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
phungductung	0:e87aa4c49e95	4915	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
phungductung	0:e87aa4c49e95	4916	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
phungductung	0:e87aa4c49e95	4917	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
phungductung	0:e87aa4c49e95	4918	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
phungductung	0:e87aa4c49e95	4919	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
phungductung	0:e87aa4c49e95	4920	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
phungductung	0:e87aa4c49e95	4921	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
phungductung	0:e87aa4c49e95	4922	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
phungductung	0:e87aa4c49e95	4923	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
phungductung	0:e87aa4c49e95	4924	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
phungductung	0:e87aa4c49e95	4925
phungductung	0:e87aa4c49e95	4926	/***************** Bit definition for I2C_OAR1 register ****************/
phungductung	0:e87aa4c49e95	4927	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
phungductung	0:e87aa4c49e95	4928	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
phungductung	0:e87aa4c49e95	4929	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
phungductung	0:e87aa4c49e95	4930
phungductung	0:e87aa4c49e95	4931	/***************** Bit definition for I2C_OAR2 register ****************/
phungductung	0:e87aa4c49e95	4932	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
phungductung	0:e87aa4c49e95	4933	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
phungductung	0:e87aa4c49e95	4934	#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /!< No mask /
phungductung	0:e87aa4c49e95	4935	#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /!< OA2[1] is masked, Only OA2[7:2] are compared /
phungductung	0:e87aa4c49e95	4936	#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
phungductung	0:e87aa4c49e95	4937	#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
phungductung	0:e87aa4c49e95	4938	#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
phungductung	0:e87aa4c49e95	4939	#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
phungductung	0:e87aa4c49e95	4940	#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /!< OA2[6:1] is masked, Only OA2[7] are compared /
phungductung	0:e87aa4c49e95	4941	#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /!< OA2[7:1] is masked, No comparison is done /
phungductung	0:e87aa4c49e95	4942	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
phungductung	0:e87aa4c49e95	4943
phungductung	0:e87aa4c49e95	4944	/***************** Bit definition for I2C_TIMINGR register *****************/
phungductung	0:e87aa4c49e95	4945	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
phungductung	0:e87aa4c49e95	4946	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
phungductung	0:e87aa4c49e95	4947	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
phungductung	0:e87aa4c49e95	4948	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
phungductung	0:e87aa4c49e95	4949	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
phungductung	0:e87aa4c49e95	4950
phungductung	0:e87aa4c49e95	4951	/***************** Bit definition for I2C_TIMEOUTR register *****************/
phungductung	0:e87aa4c49e95	4952	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
phungductung	0:e87aa4c49e95	4953	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
phungductung	0:e87aa4c49e95	4954	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
phungductung	0:e87aa4c49e95	4955	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B /
phungductung	0:e87aa4c49e95	4956	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
phungductung	0:e87aa4c49e95	4957
phungductung	0:e87aa4c49e95	4958	/**************** Bit definition for I2C_ISR register *******************/
phungductung	0:e87aa4c49e95	4959	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
phungductung	0:e87aa4c49e95	4960	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
phungductung	0:e87aa4c49e95	4961	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
phungductung	0:e87aa4c49e95	4962	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode) /
phungductung	0:e87aa4c49e95	4963	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
phungductung	0:e87aa4c49e95	4964	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
phungductung	0:e87aa4c49e95	4965	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
phungductung	0:e87aa4c49e95	4966	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
phungductung	0:e87aa4c49e95	4967	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
phungductung	0:e87aa4c49e95	4968	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
phungductung	0:e87aa4c49e95	4969	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
phungductung	0:e87aa4c49e95	4970	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
phungductung	0:e87aa4c49e95	4971	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
phungductung	0:e87aa4c49e95	4972	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
phungductung	0:e87aa4c49e95	4973	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
phungductung	0:e87aa4c49e95	4974	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
phungductung	0:e87aa4c49e95	4975	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
phungductung	0:e87aa4c49e95	4976
phungductung	0:e87aa4c49e95	4977	/**************** Bit definition for I2C_ICR register *******************/
phungductung	0:e87aa4c49e95	4978	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
phungductung	0:e87aa4c49e95	4979	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
phungductung	0:e87aa4c49e95	4980	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
phungductung	0:e87aa4c49e95	4981	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
phungductung	0:e87aa4c49e95	4982	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
phungductung	0:e87aa4c49e95	4983	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
phungductung	0:e87aa4c49e95	4984	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
phungductung	0:e87aa4c49e95	4985	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
phungductung	0:e87aa4c49e95	4986	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
phungductung	0:e87aa4c49e95	4987
phungductung	0:e87aa4c49e95	4988	/**************** Bit definition for I2C_PECR register *******************/
phungductung	0:e87aa4c49e95	4989	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
phungductung	0:e87aa4c49e95	4990
phungductung	0:e87aa4c49e95	4991	/**************** Bit definition for I2C_RXDR register *******************/
phungductung	0:e87aa4c49e95	4992	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
phungductung	0:e87aa4c49e95	4993
phungductung	0:e87aa4c49e95	4994	/**************** Bit definition for I2C_TXDR register *******************/
phungductung	0:e87aa4c49e95	4995	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
phungductung	0:e87aa4c49e95	4996
phungductung	0:e87aa4c49e95	4997
phungductung	0:e87aa4c49e95	4998	/******************************************************************************/
phungductung	0:e87aa4c49e95	4999	/* */
phungductung	0:e87aa4c49e95	5000	/* Independent WATCHDOG */
phungductung	0:e87aa4c49e95	5001	/* */
phungductung	0:e87aa4c49e95	5002	/******************************************************************************/
phungductung	0:e87aa4c49e95	5003	/***************** Bit definition for IWDG_KR register ******************/
phungductung	0:e87aa4c49e95	5004	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!<Key value (write only, read 0000h) /
phungductung	0:e87aa4c49e95	5005
phungductung	0:e87aa4c49e95	5006	/***************** Bit definition for IWDG_PR register ******************/
phungductung	0:e87aa4c49e95	5007	#define IWDG_PR_PR ((uint32_t)0x07) /!<PR[2:0] (Prescaler divider) /
phungductung	0:e87aa4c49e95	5008	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!<Bit 0 /
phungductung	0:e87aa4c49e95	5009	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!<Bit 1 /
phungductung	0:e87aa4c49e95	5010	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!<Bit 2 /
phungductung	0:e87aa4c49e95	5011
phungductung	0:e87aa4c49e95	5012	/***************** Bit definition for IWDG_RLR register *****************/
phungductung	0:e87aa4c49e95	5013	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!<Watchdog counter reload value /
phungductung	0:e87aa4c49e95	5014
phungductung	0:e87aa4c49e95	5015	/***************** Bit definition for IWDG_SR register ******************/
phungductung	0:e87aa4c49e95	5016	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
phungductung	0:e87aa4c49e95	5017	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
phungductung	0:e87aa4c49e95	5018	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
phungductung	0:e87aa4c49e95	5019
phungductung	0:e87aa4c49e95	5020	/***************** Bit definition for IWDG_KR register ******************/
phungductung	0:e87aa4c49e95	5021	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
phungductung	0:e87aa4c49e95	5022
phungductung	0:e87aa4c49e95	5023	/******************************************************************************/
phungductung	0:e87aa4c49e95	5024	/* */
phungductung	0:e87aa4c49e95	5025	/* LCD-TFT Display Controller (LTDC) */
phungductung	0:e87aa4c49e95	5026	/* */
phungductung	0:e87aa4c49e95	5027	/******************************************************************************/
phungductung	0:e87aa4c49e95	5028
phungductung	0:e87aa4c49e95	5029	/****************** Bit definition for LTDC_SSCR register ***************/
phungductung	0:e87aa4c49e95	5030
phungductung	0:e87aa4c49e95	5031	#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /!< Vertical Synchronization Height /
phungductung	0:e87aa4c49e95	5032	#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /!< Horizontal Synchronization Width /
phungductung	0:e87aa4c49e95	5033
phungductung	0:e87aa4c49e95	5034	/****************** Bit definition for LTDC_BPCR register ***************/
phungductung	0:e87aa4c49e95	5035
phungductung	0:e87aa4c49e95	5036	#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /!< Accumulated Vertical Back Porch /
phungductung	0:e87aa4c49e95	5037	#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /!< Accumulated Horizontal Back Porch /
phungductung	0:e87aa4c49e95	5038
phungductung	0:e87aa4c49e95	5039	/****************** Bit definition for LTDC_AWCR register ***************/
phungductung	0:e87aa4c49e95	5040
phungductung	0:e87aa4c49e95	5041	#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /!< Accumulated Active heigh /
phungductung	0:e87aa4c49e95	5042	#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /!< Accumulated Active Width /
phungductung	0:e87aa4c49e95	5043
phungductung	0:e87aa4c49e95	5044	/****************** Bit definition for LTDC_TWCR register ***************/
phungductung	0:e87aa4c49e95	5045
phungductung	0:e87aa4c49e95	5046	#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /!< Total Heigh /
phungductung	0:e87aa4c49e95	5047	#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /!< Total Width /
phungductung	0:e87aa4c49e95	5048
phungductung	0:e87aa4c49e95	5049	/****************** Bit definition for LTDC_GCR register ****************/
phungductung	0:e87aa4c49e95	5050
phungductung	0:e87aa4c49e95	5051	#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /!< LCD-TFT controller enable bit /
phungductung	0:e87aa4c49e95	5052	#define LTDC_GCR_DBW ((uint32_t)0x00000070) /!< Dither Blue Width /
phungductung	0:e87aa4c49e95	5053	#define LTDC_GCR_DGW ((uint32_t)0x00000700) /!< Dither Green Width /
phungductung	0:e87aa4c49e95	5054	#define LTDC_GCR_DRW ((uint32_t)0x00007000) /!< Dither Red Width /
phungductung	0:e87aa4c49e95	5055	#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /!< Dither Enable /
phungductung	0:e87aa4c49e95	5056	#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /!< Pixel Clock Polarity /
phungductung	0:e87aa4c49e95	5057	#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /!< Data Enable Polarity /
phungductung	0:e87aa4c49e95	5058	#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /!< Vertical Synchronization Polarity /
phungductung	0:e87aa4c49e95	5059	#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /!< Horizontal Synchronization Polarity /
phungductung	0:e87aa4c49e95	5060
phungductung	0:e87aa4c49e95	5061	/****************** Bit definition for LTDC_SRCR register ***************/
phungductung	0:e87aa4c49e95	5062
phungductung	0:e87aa4c49e95	5063	#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /!< Immediate Reload /
phungductung	0:e87aa4c49e95	5064	#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /!< Vertical Blanking Reload /
phungductung	0:e87aa4c49e95	5065
phungductung	0:e87aa4c49e95	5066	/****************** Bit definition for LTDC_BCCR register ***************/
phungductung	0:e87aa4c49e95	5067
phungductung	0:e87aa4c49e95	5068	#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /!< Background Blue value /
phungductung	0:e87aa4c49e95	5069	#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /!< Background Green value /
phungductung	0:e87aa4c49e95	5070	#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /!< Background Red value /
phungductung	0:e87aa4c49e95	5071
phungductung	0:e87aa4c49e95	5072	/****************** Bit definition for LTDC_IER register ****************/
phungductung	0:e87aa4c49e95	5073
phungductung	0:e87aa4c49e95	5074	#define LTDC_IER_LIE ((uint32_t)0x00000001) /!< Line Interrupt Enable /
phungductung	0:e87aa4c49e95	5075	#define LTDC_IER_FUIE ((uint32_t)0x00000002) /!< FIFO Underrun Interrupt Enable /
phungductung	0:e87aa4c49e95	5076	#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /!< Transfer Error Interrupt Enable /
phungductung	0:e87aa4c49e95	5077	#define LTDC_IER_RRIE ((uint32_t)0x00000008) /!< Register Reload interrupt enable /
phungductung	0:e87aa4c49e95	5078
phungductung	0:e87aa4c49e95	5079	/****************** Bit definition for LTDC_ISR register ****************/
phungductung	0:e87aa4c49e95	5080
phungductung	0:e87aa4c49e95	5081	#define LTDC_ISR_LIF ((uint32_t)0x00000001) /!< Line Interrupt Flag /
phungductung	0:e87aa4c49e95	5082	#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /!< FIFO Underrun Interrupt Flag /
phungductung	0:e87aa4c49e95	5083	#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /!< Transfer Error Interrupt Flag /
phungductung	0:e87aa4c49e95	5084	#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /!< Register Reload interrupt Flag /
phungductung	0:e87aa4c49e95	5085
phungductung	0:e87aa4c49e95	5086	/****************** Bit definition for LTDC_ICR register ****************/
phungductung	0:e87aa4c49e95	5087
phungductung	0:e87aa4c49e95	5088	#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /!< Clears the Line Interrupt Flag /
phungductung	0:e87aa4c49e95	5089	#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /!< Clears the FIFO Underrun Interrupt Flag /
phungductung	0:e87aa4c49e95	5090	#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /!< Clears the Transfer Error Interrupt Flag /
phungductung	0:e87aa4c49e95	5091	#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /!< Clears Register Reload interrupt Flag /
phungductung	0:e87aa4c49e95	5092
phungductung	0:e87aa4c49e95	5093	/****************** Bit definition for LTDC_LIPCR register **************/
phungductung	0:e87aa4c49e95	5094
phungductung	0:e87aa4c49e95	5095	#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /!< Line Interrupt Position /
phungductung	0:e87aa4c49e95	5096
phungductung	0:e87aa4c49e95	5097	/****************** Bit definition for LTDC_CPSR register ***************/
phungductung	0:e87aa4c49e95	5098
phungductung	0:e87aa4c49e95	5099	#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /!< Current Y Position /
phungductung	0:e87aa4c49e95	5100	#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /!< Current X Position /
phungductung	0:e87aa4c49e95	5101
phungductung	0:e87aa4c49e95	5102	/****************** Bit definition for LTDC_CDSR register ***************/
phungductung	0:e87aa4c49e95	5103
phungductung	0:e87aa4c49e95	5104	#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /!< Vertical Data Enable Status /
phungductung	0:e87aa4c49e95	5105	#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /!< Horizontal Data Enable Status /
phungductung	0:e87aa4c49e95	5106	#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /!< Vertical Synchronization Status /
phungductung	0:e87aa4c49e95	5107	#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /!< Horizontal Synchronization Status /
phungductung	0:e87aa4c49e95	5108
phungductung	0:e87aa4c49e95	5109	/****************** Bit definition for LTDC_LxCR register ***************/
phungductung	0:e87aa4c49e95	5110
phungductung	0:e87aa4c49e95	5111	#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /!< Layer Enable /
phungductung	0:e87aa4c49e95	5112	#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /!< Color Keying Enable /
phungductung	0:e87aa4c49e95	5113	#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /!< Color Lockup Table Enable /
phungductung	0:e87aa4c49e95	5114
phungductung	0:e87aa4c49e95	5115	/****************** Bit definition for LTDC_LxWHPCR register ************/
phungductung	0:e87aa4c49e95	5116
phungductung	0:e87aa4c49e95	5117	#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /!< Window Horizontal Start Position /
phungductung	0:e87aa4c49e95	5118	#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /!< Window Horizontal Stop Position /
phungductung	0:e87aa4c49e95	5119
phungductung	0:e87aa4c49e95	5120	/****************** Bit definition for LTDC_LxWVPCR register ************/
phungductung	0:e87aa4c49e95	5121
phungductung	0:e87aa4c49e95	5122	#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /!< Window Vertical Start Position /
phungductung	0:e87aa4c49e95	5123	#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /!< Window Vertical Stop Position /
phungductung	0:e87aa4c49e95	5124
phungductung	0:e87aa4c49e95	5125	/****************** Bit definition for LTDC_LxCKCR register *************/
phungductung	0:e87aa4c49e95	5126
phungductung	0:e87aa4c49e95	5127	#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /!< Color Key Blue value /
phungductung	0:e87aa4c49e95	5128	#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /!< Color Key Green value /
phungductung	0:e87aa4c49e95	5129	#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /!< Color Key Red value /
phungductung	0:e87aa4c49e95	5130
phungductung	0:e87aa4c49e95	5131	/****************** Bit definition for LTDC_LxPFCR register *************/
phungductung	0:e87aa4c49e95	5132
phungductung	0:e87aa4c49e95	5133	#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /!< Pixel Format /
phungductung	0:e87aa4c49e95	5134
phungductung	0:e87aa4c49e95	5135	/****************** Bit definition for LTDC_LxCACR register *************/
phungductung	0:e87aa4c49e95	5136
phungductung	0:e87aa4c49e95	5137	#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /!< Constant Alpha /
phungductung	0:e87aa4c49e95	5138
phungductung	0:e87aa4c49e95	5139	/****************** Bit definition for LTDC_LxDCCR register *************/
phungductung	0:e87aa4c49e95	5140
phungductung	0:e87aa4c49e95	5141	#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /!< Default Color Blue /
phungductung	0:e87aa4c49e95	5142	#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /!< Default Color Green /
phungductung	0:e87aa4c49e95	5143	#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /!< Default Color Red /
phungductung	0:e87aa4c49e95	5144	#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /!< Default Color Alpha /
phungductung	0:e87aa4c49e95	5145
phungductung	0:e87aa4c49e95	5146	/****************** Bit definition for LTDC_LxBFCR register *************/
phungductung	0:e87aa4c49e95	5147
phungductung	0:e87aa4c49e95	5148	#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /!< Blending Factor 2 /
phungductung	0:e87aa4c49e95	5149	#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /!< Blending Factor 1 /
phungductung	0:e87aa4c49e95	5150
phungductung	0:e87aa4c49e95	5151	/****************** Bit definition for LTDC_LxCFBAR register ************/
phungductung	0:e87aa4c49e95	5152
phungductung	0:e87aa4c49e95	5153	#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /!< Color Frame Buffer Start Address /
phungductung	0:e87aa4c49e95	5154
phungductung	0:e87aa4c49e95	5155	/****************** Bit definition for LTDC_LxCFBLR register ************/
phungductung	0:e87aa4c49e95	5156
phungductung	0:e87aa4c49e95	5157	#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /!< Color Frame Buffer Line Length /
phungductung	0:e87aa4c49e95	5158	#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /!< Color Frame Buffer Pitch in bytes /
phungductung	0:e87aa4c49e95	5159
phungductung	0:e87aa4c49e95	5160	/****************** Bit definition for LTDC_LxCFBLNR register ***********/
phungductung	0:e87aa4c49e95	5161
phungductung	0:e87aa4c49e95	5162	#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /!< Frame Buffer Line Number /
phungductung	0:e87aa4c49e95	5163
phungductung	0:e87aa4c49e95	5164	/****************** Bit definition for LTDC_LxCLUTWR register ***********/
phungductung	0:e87aa4c49e95	5165
phungductung	0:e87aa4c49e95	5166	#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /!< Blue value /
phungductung	0:e87aa4c49e95	5167	#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /!< Green value /
phungductung	0:e87aa4c49e95	5168	#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /!< Red value /
phungductung	0:e87aa4c49e95	5169	#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /!< CLUT address /
phungductung	0:e87aa4c49e95	5170
phungductung	0:e87aa4c49e95	5171	/******************************************************************************/
phungductung	0:e87aa4c49e95	5172	/* */
phungductung	0:e87aa4c49e95	5173	/* Power Control */
phungductung	0:e87aa4c49e95	5174	/* */
phungductung	0:e87aa4c49e95	5175	/******************************************************************************/
phungductung	0:e87aa4c49e95	5176	/****************** Bit definition for PWR_CR1 register ******************/
phungductung	0:e87aa4c49e95	5177	#define PWR_CR1_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
phungductung	0:e87aa4c49e95	5178	#define PWR_CR1_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
phungductung	0:e87aa4c49e95	5179	#define PWR_CR1_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
phungductung	0:e87aa4c49e95	5180	#define PWR_CR1_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
phungductung	0:e87aa4c49e95	5181
phungductung	0:e87aa4c49e95	5182	#define PWR_CR1_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
phungductung	0:e87aa4c49e95	5183	#define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5184	#define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5185	#define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5186
phungductung	0:e87aa4c49e95	5187	/!< PVD level configuration /
phungductung	0:e87aa4c49e95	5188	#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
phungductung	0:e87aa4c49e95	5189	#define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
phungductung	0:e87aa4c49e95	5190	#define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
phungductung	0:e87aa4c49e95	5191	#define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
phungductung	0:e87aa4c49e95	5192	#define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
phungductung	0:e87aa4c49e95	5193	#define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
phungductung	0:e87aa4c49e95	5194	#define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
phungductung	0:e87aa4c49e95	5195	#define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
phungductung	0:e87aa4c49e95	5196
phungductung	0:e87aa4c49e95	5197	#define PWR_CR1_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
phungductung	0:e87aa4c49e95	5198	#define PWR_CR1_FPDS ((uint32_t)0x00000200) /!< Flash power down in Stop mode /
phungductung	0:e87aa4c49e95	5199
phungductung	0:e87aa4c49e95	5200	#define PWR_CR1_LPUDS ((uint32_t)0x00000400) /!< Low-power regulator in deepsleep under-drive mode /
phungductung	0:e87aa4c49e95	5201	#define PWR_CR1_MRUDS ((uint32_t)0x00000800) /!< Main regulator in deepsleep under-drive mode /
phungductung	0:e87aa4c49e95	5202
phungductung	0:e87aa4c49e95	5203	#define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /!< Refer to AN4073 on how to use this bit /
phungductung	0:e87aa4c49e95	5204
phungductung	0:e87aa4c49e95	5205	#define PWR_CR1_VOS ((uint32_t)0x0000C000) /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
phungductung	0:e87aa4c49e95	5206	#define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5207	#define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5208
phungductung	0:e87aa4c49e95	5209	#define PWR_CR1_ODEN ((uint32_t)0x00010000) /!< Over Drive enable /
phungductung	0:e87aa4c49e95	5210	#define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /!< Over Drive switch enabled /
phungductung	0:e87aa4c49e95	5211	#define PWR_CR1_UDEN ((uint32_t)0x000C0000) /!< Under Drive enable in stop mode /
phungductung	0:e87aa4c49e95	5212	#define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5213	#define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5214
phungductung	0:e87aa4c49e95	5215	/***************** Bit definition for PWR_CSR1 register ******************/
phungductung	0:e87aa4c49e95	5216	#define PWR_CSR1_WUIF ((uint32_t)0x00000001) /!< Wake up internal Flag /
phungductung	0:e87aa4c49e95	5217	#define PWR_CSR1_SBF ((uint32_t)0x00000002) /!< Standby Flag /
phungductung	0:e87aa4c49e95	5218	#define PWR_CSR1_PVDO ((uint32_t)0x00000004) /!< PVD Output /
phungductung	0:e87aa4c49e95	5219	#define PWR_CSR1_BRR ((uint32_t)0x00000008) /!< Backup regulator ready /
phungductung	0:e87aa4c49e95	5220	#define PWR_CSR1_BRE ((uint32_t)0x00000200) /!< Backup regulator enable /
phungductung	0:e87aa4c49e95	5221	#define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /!< Regulator voltage scaling output selection ready /
phungductung	0:e87aa4c49e95	5222
phungductung	0:e87aa4c49e95	5223	#define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /!< Over Drive generator ready /
phungductung	0:e87aa4c49e95	5224	#define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /!< Over Drive Switch ready /
phungductung	0:e87aa4c49e95	5225	#define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /!< Under Drive ready /
phungductung	0:e87aa4c49e95	5226
phungductung	0:e87aa4c49e95	5227	/****************** Bit definition for PWR_CR2 register ******************/
phungductung	0:e87aa4c49e95	5228	#define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /!< Clear Wakeup Pin Flag for PA0 /
phungductung	0:e87aa4c49e95	5229	#define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /!< Clear Wakeup Pin Flag for PA2 /
phungductung	0:e87aa4c49e95	5230	#define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /!< Clear Wakeup Pin Flag for PC1 /
phungductung	0:e87aa4c49e95	5231	#define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /!< Clear Wakeup Pin Flag for PC13 /
phungductung	0:e87aa4c49e95	5232	#define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /!< Clear Wakeup Pin Flag for PI8 /
phungductung	0:e87aa4c49e95	5233	#define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /!< Clear Wakeup Pin Flag for PI11 /
phungductung	0:e87aa4c49e95	5234
phungductung	0:e87aa4c49e95	5235	#define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /!< Wakeup Pin Polarity bit for PA0 /
phungductung	0:e87aa4c49e95	5236	#define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /!< Wakeup Pin Polarity bit for PA2 /
phungductung	0:e87aa4c49e95	5237	#define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /!< Wakeup Pin Polarity bit for PC1 /
phungductung	0:e87aa4c49e95	5238	#define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /!< Wakeup Pin Polarity bit for PC13 /
phungductung	0:e87aa4c49e95	5239	#define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /!< Wakeup Pin Polarity bit for PI8 /
phungductung	0:e87aa4c49e95	5240	#define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /!< Wakeup Pin Polarity bit for PI11 /
phungductung	0:e87aa4c49e95	5241
phungductung	0:e87aa4c49e95	5242	/***************** Bit definition for PWR_CSR2 register ******************/
phungductung	0:e87aa4c49e95	5243	#define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /!< Wakeup Pin Flag for PA0 /
phungductung	0:e87aa4c49e95	5244	#define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /!< Wakeup Pin Flag for PA2 /
phungductung	0:e87aa4c49e95	5245	#define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /!< Wakeup Pin Flag for PC1 /
phungductung	0:e87aa4c49e95	5246	#define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /!< Wakeup Pin Flag for PC13 /
phungductung	0:e87aa4c49e95	5247	#define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /!< Wakeup Pin Flag for PI8 /
phungductung	0:e87aa4c49e95	5248	#define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /!< Wakeup Pin Flag for PI11 /
phungductung	0:e87aa4c49e95	5249
phungductung	0:e87aa4c49e95	5250	#define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /!< Enable Wakeup Pin PA0 /
phungductung	0:e87aa4c49e95	5251	#define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /!< Enable Wakeup Pin PA2 /
phungductung	0:e87aa4c49e95	5252	#define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /!< Enable Wakeup Pin PC1 /
phungductung	0:e87aa4c49e95	5253	#define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /!< Enable Wakeup Pin PC13 /
phungductung	0:e87aa4c49e95	5254	#define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /!< Enable Wakeup Pin PI8 /
phungductung	0:e87aa4c49e95	5255	#define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /!< Enable Wakeup Pin PI11 /
phungductung	0:e87aa4c49e95	5256
phungductung	0:e87aa4c49e95	5257	/******************************************************************************/
phungductung	0:e87aa4c49e95	5258	/* */
phungductung	0:e87aa4c49e95	5259	/* QUADSPI */
phungductung	0:e87aa4c49e95	5260	/* */
phungductung	0:e87aa4c49e95	5261	/******************************************************************************/
phungductung	0:e87aa4c49e95	5262	/*************** Bit definition for QUADSPI_CR register *****************/
phungductung	0:e87aa4c49e95	5263	#define QUADSPI_CR_EN ((uint32_t)0x00000001) /!< Enable /
phungductung	0:e87aa4c49e95	5264	#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /!< Abort request /
phungductung	0:e87aa4c49e95	5265	#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /!< DMA Enable /
phungductung	0:e87aa4c49e95	5266	#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /!< Timeout Counter Enable /
phungductung	0:e87aa4c49e95	5267	#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /!< Sample Shift /
phungductung	0:e87aa4c49e95	5268	#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /!< Dual Flash Mode /
phungductung	0:e87aa4c49e95	5269	#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /!< Flash Select /
phungductung	0:e87aa4c49e95	5270	#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /!< FTHRES[3:0] FIFO Level /
phungductung	0:e87aa4c49e95	5271	#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5272	#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5273	#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5274	#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5275	#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /!< Transfer Error Interrupt Enable /
phungductung	0:e87aa4c49e95	5276	#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /!< Transfer Complete Interrupt Enable /
phungductung	0:e87aa4c49e95	5277	#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /!< FIFO Threshold Interrupt Enable /
phungductung	0:e87aa4c49e95	5278	#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /!< Status Match Interrupt Enable /
phungductung	0:e87aa4c49e95	5279	#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /!< TimeOut Interrupt Enable /
phungductung	0:e87aa4c49e95	5280	#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5281	#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /!< Polling Match Mode /
phungductung	0:e87aa4c49e95	5282	#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /!< PRESCALER[7:0] Clock prescaler /
phungductung	0:e87aa4c49e95	5283	#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5284	#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5285	#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5286	#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5287	#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /!< Bit 4 /
phungductung	0:e87aa4c49e95	5288	#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /!< Bit 5 /
phungductung	0:e87aa4c49e95	5289	#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /!< Bit 6 /
phungductung	0:e87aa4c49e95	5290	#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /!< Bit 7 /
phungductung	0:e87aa4c49e95	5291
phungductung	0:e87aa4c49e95	5292	/*************** Bit definition for QUADSPI_DCR register ****************/
phungductung	0:e87aa4c49e95	5293	#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /!< Mode 0 / Mode 3 /
phungductung	0:e87aa4c49e95	5294	#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /!< CSHT[2:0]: ChipSelect High Time /
phungductung	0:e87aa4c49e95	5295	#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5296	#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5297	#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5298	#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /!< FSIZE[4:0]: Flash Size /
phungductung	0:e87aa4c49e95	5299	#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5300	#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5301	#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5302	#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5303	#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /!< Bit 4 /
phungductung	0:e87aa4c49e95	5304
phungductung	0:e87aa4c49e95	5305	/**************** Bit definition for QUADSPI_SR register *****************/
phungductung	0:e87aa4c49e95	5306	#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /!< Transfer Error Flag /
phungductung	0:e87aa4c49e95	5307	#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /!< Transfer Complete Flag /
phungductung	0:e87aa4c49e95	5308	#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /!< FIFO Threshlod Flag /
phungductung	0:e87aa4c49e95	5309	#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /!< Status Match Flag /
phungductung	0:e87aa4c49e95	5310	#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /!< Timeout Flag /
phungductung	0:e87aa4c49e95	5311	#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /!< Busy /
phungductung	0:e87aa4c49e95	5312	#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /!< FIFO Threshlod Flag /
phungductung	0:e87aa4c49e95	5313	#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5314	#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5315	#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5316	#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5317	#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /!< Bit 4 /
phungductung	0:e87aa4c49e95	5318
phungductung	0:e87aa4c49e95	5319	/**************** Bit definition for QUADSPI_FCR register ****************/
phungductung	0:e87aa4c49e95	5320	#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /!< Clear Transfer Error Flag /
phungductung	0:e87aa4c49e95	5321	#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /!< Clear Transfer Complete Flag /
phungductung	0:e87aa4c49e95	5322	#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /!< Clear Status Match Flag /
phungductung	0:e87aa4c49e95	5323	#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /!< Clear Timeout Flag /
phungductung	0:e87aa4c49e95	5324
phungductung	0:e87aa4c49e95	5325	/**************** Bit definition for QUADSPI_DLR register ****************/
phungductung	0:e87aa4c49e95	5326	#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /!< DL[31:0]: Data Length /
phungductung	0:e87aa4c49e95	5327
phungductung	0:e87aa4c49e95	5328	/**************** Bit definition for QUADSPI_CCR register ****************/
phungductung	0:e87aa4c49e95	5329	#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /!< INSTRUCTION[7:0]: Instruction /
phungductung	0:e87aa4c49e95	5330	#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5331	#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5332	#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5333	#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5334	#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /!< Bit 4 /
phungductung	0:e87aa4c49e95	5335	#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /!< Bit 5 /
phungductung	0:e87aa4c49e95	5336	#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /!< Bit 6 /
phungductung	0:e87aa4c49e95	5337	#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /!< Bit 7 /
phungductung	0:e87aa4c49e95	5338	#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /!< IMODE[1:0]: Instruction Mode /
phungductung	0:e87aa4c49e95	5339	#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5340	#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5341	#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /!< ADMODE[1:0]: Address Mode /
phungductung	0:e87aa4c49e95	5342	#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5343	#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5344	#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /!< ADSIZE[1:0]: Address Size /
phungductung	0:e87aa4c49e95	5345	#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5346	#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5347	#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /!< ABMODE[1:0]: Alternate Bytes Mode /
phungductung	0:e87aa4c49e95	5348	#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5349	#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5350	#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /!< ABSIZE[1:0]: Instruction Mode /
phungductung	0:e87aa4c49e95	5351	#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5352	#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5353	#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /!< DCYC[4:0]: Dummy Cycles /
phungductung	0:e87aa4c49e95	5354	#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5355	#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5356	#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5357	#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5358	#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /!< Bit 4 /
phungductung	0:e87aa4c49e95	5359	#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /!< DMODE[1:0]: Data Mode /
phungductung	0:e87aa4c49e95	5360	#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5361	#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5362	#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /!< FMODE[1:0]: Functional Mode /
phungductung	0:e87aa4c49e95	5363	#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5364	#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5365	#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /!< SIOO: Send Instruction Only Once Mode /
phungductung	0:e87aa4c49e95	5366	#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /!< DHHC: Delay Half Hclk Cycle /
phungductung	0:e87aa4c49e95	5367	#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /!< DDRM: Double Data Rate Mode /
phungductung	0:e87aa4c49e95	5368	/**************** Bit definition for QUADSPI_AR register *****************/
phungductung	0:e87aa4c49e95	5369	#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< ADDRESS[31:0]: Address /
phungductung	0:e87aa4c49e95	5370
phungductung	0:e87aa4c49e95	5371	/**************** Bit definition for QUADSPI_ABR register ****************/
phungductung	0:e87aa4c49e95	5372	#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /!< ALTERNATE[31:0]: Alternate Bytes /
phungductung	0:e87aa4c49e95	5373
phungductung	0:e87aa4c49e95	5374	/**************** Bit definition for QUADSPI_DR register *****************/
phungductung	0:e87aa4c49e95	5375	#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /!< DATA[31:0]: Data /
phungductung	0:e87aa4c49e95	5376
phungductung	0:e87aa4c49e95	5377	/**************** Bit definition for QUADSPI_PSMKR register **************/
phungductung	0:e87aa4c49e95	5378	#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /!< MASK[31:0]: Status Mask /
phungductung	0:e87aa4c49e95	5379
phungductung	0:e87aa4c49e95	5380	/**************** Bit definition for QUADSPI_PSMAR register **************/
phungductung	0:e87aa4c49e95	5381	#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /!< MATCH[31:0]: Status Match /
phungductung	0:e87aa4c49e95	5382
phungductung	0:e87aa4c49e95	5383	/**************** Bit definition for QUADSPI_PIR register ***************/
phungductung	0:e87aa4c49e95	5384	#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /!< INTERVAL[15:0]: Polling Interval /
phungductung	0:e87aa4c49e95	5385
phungductung	0:e87aa4c49e95	5386	/**************** Bit definition for QUADSPI_LPTR register ***************/
phungductung	0:e87aa4c49e95	5387	#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /!< TIMEOUT[15:0]: Timeout period /
phungductung	0:e87aa4c49e95	5388
phungductung	0:e87aa4c49e95	5389	/******************************************************************************/
phungductung	0:e87aa4c49e95	5390	/* */
phungductung	0:e87aa4c49e95	5391	/* Reset and Clock Control */
phungductung	0:e87aa4c49e95	5392	/* */
phungductung	0:e87aa4c49e95	5393	/******************************************************************************/
phungductung	0:e87aa4c49e95	5394	/****************** Bit definition for RCC_CR register ******************/
phungductung	0:e87aa4c49e95	5395	#define RCC_CR_HSION ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5396	#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5397
phungductung	0:e87aa4c49e95	5398	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
phungductung	0:e87aa4c49e95	5399	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
phungductung	0:e87aa4c49e95	5400	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
phungductung	0:e87aa4c49e95	5401	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
phungductung	0:e87aa4c49e95	5402	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
phungductung	0:e87aa4c49e95	5403	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
phungductung	0:e87aa4c49e95	5404
phungductung	0:e87aa4c49e95	5405	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
phungductung	0:e87aa4c49e95	5406	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	5407	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	5408	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	5409	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	5410	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	5411	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	5412	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	5413	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	5414
phungductung	0:e87aa4c49e95	5415	#define RCC_CR_HSEON ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5416	#define RCC_CR_HSERDY ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5417	#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5418	#define RCC_CR_CSSON ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5419	#define RCC_CR_PLLON ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5420	#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5421	#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5422	#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5423	#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5424	#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5425
phungductung	0:e87aa4c49e95	5426	/****************** Bit definition for RCC_PLLCFGR register *************/
phungductung	0:e87aa4c49e95	5427	#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
phungductung	0:e87aa4c49e95	5428	#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5429	#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5430	#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5431	#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5432	#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5433	#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5434
phungductung	0:e87aa4c49e95	5435	#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
phungductung	0:e87aa4c49e95	5436	#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5437	#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5438	#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5439	#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5440	#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5441	#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5442	#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5443	#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5444	#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5445
phungductung	0:e87aa4c49e95	5446	#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	5447	#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5448	#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5449
phungductung	0:e87aa4c49e95	5450	#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5451	#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5452	#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
phungductung	0:e87aa4c49e95	5453
phungductung	0:e87aa4c49e95	5454	#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	5455	#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5456	#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5457	#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5458	#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5459
phungductung	0:e87aa4c49e95	5460
phungductung	0:e87aa4c49e95	5461	/****************** Bit definition for RCC_CFGR register ****************/
phungductung	0:e87aa4c49e95	5462	/!< SW configuration /
phungductung	0:e87aa4c49e95	5463	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
phungductung	0:e87aa4c49e95	5464	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5465	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5466
phungductung	0:e87aa4c49e95	5467	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
phungductung	0:e87aa4c49e95	5468	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
phungductung	0:e87aa4c49e95	5469	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
phungductung	0:e87aa4c49e95	5470
phungductung	0:e87aa4c49e95	5471	/!< SWS configuration /
phungductung	0:e87aa4c49e95	5472	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
phungductung	0:e87aa4c49e95	5473	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5474	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5475
phungductung	0:e87aa4c49e95	5476	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
phungductung	0:e87aa4c49e95	5477	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
phungductung	0:e87aa4c49e95	5478	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
phungductung	0:e87aa4c49e95	5479
phungductung	0:e87aa4c49e95	5480	/!< HPRE configuration /
phungductung	0:e87aa4c49e95	5481	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
phungductung	0:e87aa4c49e95	5482	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5483	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5484	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5485	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
phungductung	0:e87aa4c49e95	5486
phungductung	0:e87aa4c49e95	5487	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
phungductung	0:e87aa4c49e95	5488	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
phungductung	0:e87aa4c49e95	5489	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
phungductung	0:e87aa4c49e95	5490	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
phungductung	0:e87aa4c49e95	5491	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
phungductung	0:e87aa4c49e95	5492	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
phungductung	0:e87aa4c49e95	5493	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
phungductung	0:e87aa4c49e95	5494	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
phungductung	0:e87aa4c49e95	5495	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
phungductung	0:e87aa4c49e95	5496
phungductung	0:e87aa4c49e95	5497	/!< PPRE1 configuration /
phungductung	0:e87aa4c49e95	5498	#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /!< PRE1[2:0] bits (APB1 prescaler) /
phungductung	0:e87aa4c49e95	5499	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5500	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5501	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5502
phungductung	0:e87aa4c49e95	5503	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
phungductung	0:e87aa4c49e95	5504	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /!< HCLK divided by 2 /
phungductung	0:e87aa4c49e95	5505	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /!< HCLK divided by 4 /
phungductung	0:e87aa4c49e95	5506	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /!< HCLK divided by 8 /
phungductung	0:e87aa4c49e95	5507	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /!< HCLK divided by 16 /
phungductung	0:e87aa4c49e95	5508
phungductung	0:e87aa4c49e95	5509	/!< PPRE2 configuration /
phungductung	0:e87aa4c49e95	5510	#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /!< PRE2[2:0] bits (APB2 prescaler) /
phungductung	0:e87aa4c49e95	5511	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	5512	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	5513	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	5514
phungductung	0:e87aa4c49e95	5515	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
phungductung	0:e87aa4c49e95	5516	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /!< HCLK divided by 2 /
phungductung	0:e87aa4c49e95	5517	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /!< HCLK divided by 4 /
phungductung	0:e87aa4c49e95	5518	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /!< HCLK divided by 8 /
phungductung	0:e87aa4c49e95	5519	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /!< HCLK divided by 16 /
phungductung	0:e87aa4c49e95	5520
phungductung	0:e87aa4c49e95	5521	/!< RTCPRE configuration /
phungductung	0:e87aa4c49e95	5522	#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
phungductung	0:e87aa4c49e95	5523	#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5524	#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5525	#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5526	#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5527	#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5528
phungductung	0:e87aa4c49e95	5529	/!< MCO1 configuration /
phungductung	0:e87aa4c49e95	5530	#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
phungductung	0:e87aa4c49e95	5531	#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5532	#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5533
phungductung	0:e87aa4c49e95	5534	#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5535
phungductung	0:e87aa4c49e95	5536	#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
phungductung	0:e87aa4c49e95	5537	#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5538	#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5539	#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5540
phungductung	0:e87aa4c49e95	5541	#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
phungductung	0:e87aa4c49e95	5542	#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5543	#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5544	#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5545
phungductung	0:e87aa4c49e95	5546	#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
phungductung	0:e87aa4c49e95	5547	#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5548	#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	5549
phungductung	0:e87aa4c49e95	5550	/****************** Bit definition for RCC_CIR register *****************/
phungductung	0:e87aa4c49e95	5551	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5552	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5553	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5554	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5555	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5556	#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5557	#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5558	#define RCC_CIR_CSSF ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5559	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5560	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5561	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5562	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5563	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5564	#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5565	#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5566	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5567	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5568	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5569	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5570	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5571	#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5572	#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5573	#define RCC_CIR_CSSC ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5574
phungductung	0:e87aa4c49e95	5575	/****************** Bit definition for RCC_AHB1RSTR register ************/
phungductung	0:e87aa4c49e95	5576	#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5577	#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5578	#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5579	#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5580	#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5581	#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5582	#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5583	#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5584	#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5585	#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5586	#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5587	#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5588	#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5589	#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5590	#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5591	#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5592	#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5593
phungductung	0:e87aa4c49e95	5594	/****************** Bit definition for RCC_AHB2RSTR register ************/
phungductung	0:e87aa4c49e95	5595	#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5596	#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5597	#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5598
phungductung	0:e87aa4c49e95	5599	/****************** Bit definition for RCC_AHB3RSTR register ************/
phungductung	0:e87aa4c49e95	5600
phungductung	0:e87aa4c49e95	5601	#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5602	#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5603
phungductung	0:e87aa4c49e95	5604	/****************** Bit definition for RCC_APB1RSTR register ************/
phungductung	0:e87aa4c49e95	5605	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5606	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5607	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5608	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5609	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5610	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5611	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5612	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5613	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5614	#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5615	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5616	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5617	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	5618	#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5619	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5620	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5621	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5622	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5623	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5624	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5625	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5626	#define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5627	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5628	#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5629	#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5630	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5631	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5632	#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5633	#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	5634
phungductung	0:e87aa4c49e95	5635	/****************** Bit definition for RCC_APB2RSTR register ************/
phungductung	0:e87aa4c49e95	5636	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5637	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5638	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5639	#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5640	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5641	#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5642	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5643	#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5644	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5645	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5646	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5647	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5648	#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5649	#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5650	#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5651	#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5652	#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5653
phungductung	0:e87aa4c49e95	5654	/****************** Bit definition for RCC_AHB1ENR register *************/
phungductung	0:e87aa4c49e95	5655	#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5656	#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5657	#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5658	#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5659	#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5660	#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5661	#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5662	#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5663	#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5664	#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5665	#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5666	#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5667	#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5668	#define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5669	#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5670	#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5671	#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5672	#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5673	#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5674	#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5675	#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5676	#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5677	#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5678
phungductung	0:e87aa4c49e95	5679	/****************** Bit definition for RCC_AHB2ENR register *************/
phungductung	0:e87aa4c49e95	5680	#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5681	#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5682	#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5683
phungductung	0:e87aa4c49e95	5684	/****************** Bit definition for RCC_AHB3ENR register *************/
phungductung	0:e87aa4c49e95	5685
phungductung	0:e87aa4c49e95	5686	#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5687	#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5688
phungductung	0:e87aa4c49e95	5689	/****************** Bit definition for RCC_APB1ENR register *************/
phungductung	0:e87aa4c49e95	5690	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5691	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5692	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5693	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5694	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5695	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5696	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5697	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5698	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5699	#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5700	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5701	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5702	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	5703	#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5704	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5705	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5706	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5707	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5708	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5709	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5710	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5711	#define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5712	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5713	#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5714	#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5715	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5716	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5717	#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5718	#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	5719
phungductung	0:e87aa4c49e95	5720	/****************** Bit definition for RCC_APB2ENR register *************/
phungductung	0:e87aa4c49e95	5721	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5722	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5723	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5724	#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5725	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5726	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5727	#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5728	#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5729	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5730	#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5731	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5732	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5733	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5734	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5735	#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5736	#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5737	#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5738	#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5739	#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5740
phungductung	0:e87aa4c49e95	5741	/****************** Bit definition for RCC_AHB1LPENR register ***********/
phungductung	0:e87aa4c49e95	5742	#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5743	#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5744	#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5745	#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5746	#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5747	#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5748	#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5749	#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5750	#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5751	#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5752	#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5753
phungductung	0:e87aa4c49e95	5754	#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5755	#define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5756	#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	5757	#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5758	#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5759	#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5760	#define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5761	#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5762	#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5763	#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5764	#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5765	#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5766	#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5767	#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5768	#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5769	#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5770
phungductung	0:e87aa4c49e95	5771	/****************** Bit definition for RCC_AHB2LPENR register ***********/
phungductung	0:e87aa4c49e95	5772	#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5773	#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5774	#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5775
phungductung	0:e87aa4c49e95	5776	/****************** Bit definition for RCC_AHB3LPENR register ***********/
phungductung	0:e87aa4c49e95	5777	#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5778	#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5779	/****************** Bit definition for RCC_APB1LPENR register ***********/
phungductung	0:e87aa4c49e95	5780	#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5781	#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5782	#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5783	#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5784	#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5785	#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5786	#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5787	#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5788	#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5789	#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5790	#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5791	#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5792	#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	5793	#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5794	#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5795	#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5796	#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5797	#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5798	#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5799	#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5800	#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5801	#define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5802	#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5803	#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5804	#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5805	#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5806	#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5807	#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5808	#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	5809
phungductung	0:e87aa4c49e95	5810	/****************** Bit definition for RCC_APB2LPENR register ***********/
phungductung	0:e87aa4c49e95	5811	#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5812	#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5813	#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5814	#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5815	#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5816	#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5817	#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5818	#define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5819	#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5820	#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5821	#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5822	#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5823	#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5824	#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5825	#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5826	#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5827	#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5828	#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5829	#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5830
phungductung	0:e87aa4c49e95	5831	/****************** Bit definition for RCC_BDCR register ****************/
phungductung	0:e87aa4c49e95	5832	#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5833	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5834	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5835	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
phungductung	0:e87aa4c49e95	5836	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5837	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5838	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	5839	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5840	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5841	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	5842	#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5843
phungductung	0:e87aa4c49e95	5844	/****************** Bit definition for RCC_CSR register *****************/
phungductung	0:e87aa4c49e95	5845	#define RCC_CSR_LSION ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5846	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5847	#define RCC_CSR_RMVF ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5848	#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5849	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5850	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5851	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5852	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5853	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5854	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	5855
phungductung	0:e87aa4c49e95	5856	/****************** Bit definition for RCC_SSCGR register ***************/
phungductung	0:e87aa4c49e95	5857	#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
phungductung	0:e87aa4c49e95	5858	#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
phungductung	0:e87aa4c49e95	5859	#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5860	#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	5861
phungductung	0:e87aa4c49e95	5862	/****************** Bit definition for RCC_PLLI2SCFGR register **********/
phungductung	0:e87aa4c49e95	5863	#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
phungductung	0:e87aa4c49e95	5864	#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5865	#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5866	#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5867	#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5868	#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5869	#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5870	#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5871	#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5872	#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5873
phungductung	0:e87aa4c49e95	5874	#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	5875	#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5876	#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5877
phungductung	0:e87aa4c49e95	5878	#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	5879	#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5880	#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5881	#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5882	#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5883
phungductung	0:e87aa4c49e95	5884	#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
phungductung	0:e87aa4c49e95	5885	#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5886	#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5887	#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5888
phungductung	0:e87aa4c49e95	5889	/****************** Bit definition for RCC_PLLSAICFGR register **********/
phungductung	0:e87aa4c49e95	5890	#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
phungductung	0:e87aa4c49e95	5891	#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5892	#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5893	#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5894	#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5895	#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5896	#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5897	#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5898	#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5899	#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5900
phungductung	0:e87aa4c49e95	5901	#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	5902	#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5903	#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5904
phungductung	0:e87aa4c49e95	5905	#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	5906	#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5907	#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5908	#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5909	#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5910
phungductung	0:e87aa4c49e95	5911	#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
phungductung	0:e87aa4c49e95	5912	#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5913	#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	5914	#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	5915
phungductung	0:e87aa4c49e95	5916	/****************** Bit definition for RCC_DCKCFGR1 register *************/
phungductung	0:e87aa4c49e95	5917	#define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
phungductung	0:e87aa4c49e95	5918	#define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5919	#define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5920	#define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5921	#define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5922	#define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5923
phungductung	0:e87aa4c49e95	5924	#define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
phungductung	0:e87aa4c49e95	5925	#define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5926	#define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5927	#define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5928	#define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5929	#define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5930
phungductung	0:e87aa4c49e95	5931	#define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	5932	#define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5933	#define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5934
phungductung	0:e87aa4c49e95	5935	#define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	5936	#define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5937	#define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5938
phungductung	0:e87aa4c49e95	5939	#define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
phungductung	0:e87aa4c49e95	5940	#define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5941	#define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5942
phungductung	0:e87aa4c49e95	5943	#define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5944
phungductung	0:e87aa4c49e95	5945	/****************** Bit definition for RCC_DCKCFGR2 register *************/
phungductung	0:e87aa4c49e95	5946	#define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
phungductung	0:e87aa4c49e95	5947	#define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	5948	#define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	5949	#define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
phungductung	0:e87aa4c49e95	5950	#define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5951	#define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5952	#define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
phungductung	0:e87aa4c49e95	5953	#define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	5954	#define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	5955	#define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
phungductung	0:e87aa4c49e95	5956	#define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	5957	#define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	5958	#define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
phungductung	0:e87aa4c49e95	5959	#define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	5960	#define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	5961	#define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
phungductung	0:e87aa4c49e95	5962	#define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	5963	#define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	5964	#define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
phungductung	0:e87aa4c49e95	5965	#define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	5966	#define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	5967	#define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
phungductung	0:e87aa4c49e95	5968	#define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	5969	#define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	5970	#define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
phungductung	0:e87aa4c49e95	5971	#define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	5972	#define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	5973	#define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
phungductung	0:e87aa4c49e95	5974	#define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	5975	#define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	5976	#define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	5977	#define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	5978	#define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	5979	#define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
phungductung	0:e87aa4c49e95	5980	#define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	5981	#define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	5982	#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
phungductung	0:e87aa4c49e95	5983	#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	5984	#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	5985	#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	5986	#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	5987	#define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	5988
phungductung	0:e87aa4c49e95	5989	/******************************************************************************/
phungductung	0:e87aa4c49e95	5990	/* */
phungductung	0:e87aa4c49e95	5991	/* RNG */
phungductung	0:e87aa4c49e95	5992	/* */
phungductung	0:e87aa4c49e95	5993	/******************************************************************************/
phungductung	0:e87aa4c49e95	5994	/****************** Bits definition for RNG_CR register *****************/
phungductung	0:e87aa4c49e95	5995	#define RNG_CR_RNGEN ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	5996	#define RNG_CR_IE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	5997
phungductung	0:e87aa4c49e95	5998	/****************** Bits definition for RNG_SR register *****************/
phungductung	0:e87aa4c49e95	5999	#define RNG_SR_DRDY ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6000	#define RNG_SR_CECS ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6001	#define RNG_SR_SECS ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6002	#define RNG_SR_CEIS ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6003	#define RNG_SR_SEIS ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6004
phungductung	0:e87aa4c49e95	6005	/******************************************************************************/
phungductung	0:e87aa4c49e95	6006	/* */
phungductung	0:e87aa4c49e95	6007	/* Real-Time Clock (RTC) */
phungductung	0:e87aa4c49e95	6008	/* */
phungductung	0:e87aa4c49e95	6009	/******************************************************************************/
phungductung	0:e87aa4c49e95	6010	/****************** Bits definition for RTC_TR register *****************/
phungductung	0:e87aa4c49e95	6011	#define RTC_TR_PM ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6012	#define RTC_TR_HT ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	6013	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6014	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6015	#define RTC_TR_HU ((uint32_t)0x000F0000)
phungductung	0:e87aa4c49e95	6016	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6017	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6018	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6019	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6020	#define RTC_TR_MNT ((uint32_t)0x00007000)
phungductung	0:e87aa4c49e95	6021	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6022	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6023	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6024	#define RTC_TR_MNU ((uint32_t)0x00000F00)
phungductung	0:e87aa4c49e95	6025	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6026	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6027	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6028	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6029	#define RTC_TR_ST ((uint32_t)0x00000070)
phungductung	0:e87aa4c49e95	6030	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6031	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6032	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6033	#define RTC_TR_SU ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	6034	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6035	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6036	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6037	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6038
phungductung	0:e87aa4c49e95	6039	/****************** Bits definition for RTC_DR register *****************/
phungductung	0:e87aa4c49e95	6040	#define RTC_DR_YT ((uint32_t)0x00F00000)
phungductung	0:e87aa4c49e95	6041	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6042	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6043	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6044	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	6045	#define RTC_DR_YU ((uint32_t)0x000F0000)
phungductung	0:e87aa4c49e95	6046	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6047	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6048	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6049	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6050	#define RTC_DR_WDU ((uint32_t)0x0000E000)
phungductung	0:e87aa4c49e95	6051	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6052	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6053	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6054	#define RTC_DR_MT ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6055	#define RTC_DR_MU ((uint32_t)0x00000F00)
phungductung	0:e87aa4c49e95	6056	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6057	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6058	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6059	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6060	#define RTC_DR_DT ((uint32_t)0x00000030)
phungductung	0:e87aa4c49e95	6061	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6062	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6063	#define RTC_DR_DU ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	6064	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6065	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6066	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6067	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6068
phungductung	0:e87aa4c49e95	6069	/****************** Bits definition for RTC_CR register *****************/
phungductung	0:e87aa4c49e95	6070	#define RTC_CR_ITSE ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	6071	#define RTC_CR_COE ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	6072	#define RTC_CR_OSEL ((uint32_t)0x00600000)
phungductung	0:e87aa4c49e95	6073	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6074	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6075	#define RTC_CR_POL ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6076	#define RTC_CR_COSEL ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6077	#define RTC_CR_BCK ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6078	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6079	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6080	#define RTC_CR_TSIE ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6081	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6082	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6083	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6084	#define RTC_CR_TSE ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6085	#define RTC_CR_WUTE ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6086	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6087	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6088	#define RTC_CR_FMT ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6089	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6090	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6091	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6092	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
phungductung	0:e87aa4c49e95	6093	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6094	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6095	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6096
phungductung	0:e87aa4c49e95	6097	/****************** Bits definition for RTC_ISR register ****************/
phungductung	0:e87aa4c49e95	6098	#define RTC_ISR_ITSF ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6099	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6100	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6101	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6102	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6103	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6104	#define RTC_ISR_TSF ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6105	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6106	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6107	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6108	#define RTC_ISR_INIT ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	6109	#define RTC_ISR_INITF ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6110	#define RTC_ISR_RSF ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6111	#define RTC_ISR_INITS ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6112	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6113	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6114	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6115	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6116
phungductung	0:e87aa4c49e95	6117	/****************** Bits definition for RTC_PRER register ***************/
phungductung	0:e87aa4c49e95	6118	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
phungductung	0:e87aa4c49e95	6119	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
phungductung	0:e87aa4c49e95	6120
phungductung	0:e87aa4c49e95	6121	/****************** Bits definition for RTC_WUTR register ***************/
phungductung	0:e87aa4c49e95	6122	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
phungductung	0:e87aa4c49e95	6123
phungductung	0:e87aa4c49e95	6124	/****************** Bits definition for RTC_ALRMAR register *************/
phungductung	0:e87aa4c49e95	6125	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	6126	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	6127	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
phungductung	0:e87aa4c49e95	6128	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	6129	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	6130	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	6131	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	6132	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	6133	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	6134	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	6135	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	6136	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6137	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	6138	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6139	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6140	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
phungductung	0:e87aa4c49e95	6141	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6142	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6143	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6144	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6145	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6146	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
phungductung	0:e87aa4c49e95	6147	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6148	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6149	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6150	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
phungductung	0:e87aa4c49e95	6151	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6152	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6153	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6154	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6155	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	6156	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
phungductung	0:e87aa4c49e95	6157	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6158	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6159	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6160	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	6161	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6162	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6163	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6164	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6165
phungductung	0:e87aa4c49e95	6166	/****************** Bits definition for RTC_ALRMBR register *************/
phungductung	0:e87aa4c49e95	6167	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	6168	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
phungductung	0:e87aa4c49e95	6169	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
phungductung	0:e87aa4c49e95	6170	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
phungductung	0:e87aa4c49e95	6171	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
phungductung	0:e87aa4c49e95	6172	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	6173	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	6174	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	6175	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	6176	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	6177	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	6178	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6179	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	6180	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6181	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6182	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
phungductung	0:e87aa4c49e95	6183	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6184	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6185	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6186	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6187	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6188	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
phungductung	0:e87aa4c49e95	6189	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6190	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6191	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6192	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
phungductung	0:e87aa4c49e95	6193	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6194	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6195	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6196	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6197	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	6198	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
phungductung	0:e87aa4c49e95	6199	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6200	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6201	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6202	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	6203	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6204	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6205	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6206	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6207
phungductung	0:e87aa4c49e95	6208	/****************** Bits definition for RTC_WPR register ****************/
phungductung	0:e87aa4c49e95	6209	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
phungductung	0:e87aa4c49e95	6210
phungductung	0:e87aa4c49e95	6211	/****************** Bits definition for RTC_SSR register ****************/
phungductung	0:e87aa4c49e95	6212	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
phungductung	0:e87aa4c49e95	6213
phungductung	0:e87aa4c49e95	6214	/****************** Bits definition for RTC_SHIFTR register *************/
phungductung	0:e87aa4c49e95	6215	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
phungductung	0:e87aa4c49e95	6216	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
phungductung	0:e87aa4c49e95	6217
phungductung	0:e87aa4c49e95	6218	/****************** Bits definition for RTC_TSTR register ***************/
phungductung	0:e87aa4c49e95	6219	#define RTC_TSTR_PM ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6220	#define RTC_TSTR_HT ((uint32_t)0x00300000)
phungductung	0:e87aa4c49e95	6221	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6222	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6223	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
phungductung	0:e87aa4c49e95	6224	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6225	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6226	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6227	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6228	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
phungductung	0:e87aa4c49e95	6229	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6230	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6231	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6232	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
phungductung	0:e87aa4c49e95	6233	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6234	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6235	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6236	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6237	#define RTC_TSTR_ST ((uint32_t)0x00000070)
phungductung	0:e87aa4c49e95	6238	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6239	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6240	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6241	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	6242	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6243	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6244	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6245	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6246
phungductung	0:e87aa4c49e95	6247	/****************** Bits definition for RTC_TSDR register ***************/
phungductung	0:e87aa4c49e95	6248	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
phungductung	0:e87aa4c49e95	6249	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6250	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6251	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6252	#define RTC_TSDR_MT ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6253	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
phungductung	0:e87aa4c49e95	6254	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6255	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6256	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6257	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6258	#define RTC_TSDR_DT ((uint32_t)0x00000030)
phungductung	0:e87aa4c49e95	6259	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6260	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6261	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
phungductung	0:e87aa4c49e95	6262	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6263	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6264	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6265	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6266
phungductung	0:e87aa4c49e95	6267	/****************** Bits definition for RTC_TSSSR register **************/
phungductung	0:e87aa4c49e95	6268	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
phungductung	0:e87aa4c49e95	6269
phungductung	0:e87aa4c49e95	6270	/****************** Bits definition for RTC_CAL register ***************/
phungductung	0:e87aa4c49e95	6271	#define RTC_CALR_CALP ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6272	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6273	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6274	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
phungductung	0:e87aa4c49e95	6275	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6276	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6277	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6278	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6279	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6280	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6281	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6282	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	6283	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6284
phungductung	0:e87aa4c49e95	6285	/****************** Bits definition for RTC_TAMPCR register **************/
phungductung	0:e87aa4c49e95	6286	#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	6287	#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	6288	#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	6289	#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	6290	#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
phungductung	0:e87aa4c49e95	6291	#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
phungductung	0:e87aa4c49e95	6292	#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	6293	#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	6294	#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	6295	#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
phungductung	0:e87aa4c49e95	6296	#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
phungductung	0:e87aa4c49e95	6297	#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
phungductung	0:e87aa4c49e95	6298	#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
phungductung	0:e87aa4c49e95	6299	#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
phungductung	0:e87aa4c49e95	6300	#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6301	#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	6302	#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
phungductung	0:e87aa4c49e95	6303	#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	6304	#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
phungductung	0:e87aa4c49e95	6305	#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6306	#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	6307	#define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	6308	#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6309	#define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	6310	#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6311	#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6312	#define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6313	#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	6314
phungductung	0:e87aa4c49e95	6315	/****************** Bits definition for RTC_ALRMASSR register ***********/
phungductung	0:e87aa4c49e95	6316	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	6317	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	6318	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	6319	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	6320	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	6321	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
phungductung	0:e87aa4c49e95	6322
phungductung	0:e87aa4c49e95	6323	/****************** Bits definition for RTC_ALRMBSSR register ***********/
phungductung	0:e87aa4c49e95	6324	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
phungductung	0:e87aa4c49e95	6325	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
phungductung	0:e87aa4c49e95	6326	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	6327	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	6328	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
phungductung	0:e87aa4c49e95	6329	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
phungductung	0:e87aa4c49e95	6330
phungductung	0:e87aa4c49e95	6331	/****************** Bits definition for RTC_OR register **************/
phungductung	0:e87aa4c49e95	6332	#define RTC_OR_TSINSEL ((uint32_t)0x00000006)
phungductung	0:e87aa4c49e95	6333	#define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	6334	#define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	6335	#define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	6336
phungductung	0:e87aa4c49e95	6337
phungductung	0:e87aa4c49e95	6338	/****************** Bits definition for RTC_BKP0R register **************/
phungductung	0:e87aa4c49e95	6339	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6340
phungductung	0:e87aa4c49e95	6341	/****************** Bits definition for RTC_BKP1R register **************/
phungductung	0:e87aa4c49e95	6342	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6343
phungductung	0:e87aa4c49e95	6344	/****************** Bits definition for RTC_BKP2R register **************/
phungductung	0:e87aa4c49e95	6345	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6346
phungductung	0:e87aa4c49e95	6347	/****************** Bits definition for RTC_BKP3R register **************/
phungductung	0:e87aa4c49e95	6348	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6349
phungductung	0:e87aa4c49e95	6350	/****************** Bits definition for RTC_BKP4R register **************/
phungductung	0:e87aa4c49e95	6351	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6352
phungductung	0:e87aa4c49e95	6353	/****************** Bits definition for RTC_BKP5R register **************/
phungductung	0:e87aa4c49e95	6354	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6355
phungductung	0:e87aa4c49e95	6356	/****************** Bits definition for RTC_BKP6R register **************/
phungductung	0:e87aa4c49e95	6357	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6358
phungductung	0:e87aa4c49e95	6359	/****************** Bits definition for RTC_BKP7R register **************/
phungductung	0:e87aa4c49e95	6360	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6361
phungductung	0:e87aa4c49e95	6362	/****************** Bits definition for RTC_BKP8R register **************/
phungductung	0:e87aa4c49e95	6363	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6364
phungductung	0:e87aa4c49e95	6365	/****************** Bits definition for RTC_BKP9R register **************/
phungductung	0:e87aa4c49e95	6366	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6367
phungductung	0:e87aa4c49e95	6368	/****************** Bits definition for RTC_BKP10R register *************/
phungductung	0:e87aa4c49e95	6369	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6370
phungductung	0:e87aa4c49e95	6371	/****************** Bits definition for RTC_BKP11R register *************/
phungductung	0:e87aa4c49e95	6372	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6373
phungductung	0:e87aa4c49e95	6374	/****************** Bits definition for RTC_BKP12R register *************/
phungductung	0:e87aa4c49e95	6375	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6376
phungductung	0:e87aa4c49e95	6377	/****************** Bits definition for RTC_BKP13R register *************/
phungductung	0:e87aa4c49e95	6378	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6379
phungductung	0:e87aa4c49e95	6380	/****************** Bits definition for RTC_BKP14R register *************/
phungductung	0:e87aa4c49e95	6381	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6382
phungductung	0:e87aa4c49e95	6383	/****************** Bits definition for RTC_BKP15R register *************/
phungductung	0:e87aa4c49e95	6384	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6385
phungductung	0:e87aa4c49e95	6386	/****************** Bits definition for RTC_BKP16R register *************/
phungductung	0:e87aa4c49e95	6387	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6388
phungductung	0:e87aa4c49e95	6389	/****************** Bits definition for RTC_BKP17R register *************/
phungductung	0:e87aa4c49e95	6390	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6391
phungductung	0:e87aa4c49e95	6392	/****************** Bits definition for RTC_BKP18R register *************/
phungductung	0:e87aa4c49e95	6393	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6394
phungductung	0:e87aa4c49e95	6395	/****************** Bits definition for RTC_BKP19R register *************/
phungductung	0:e87aa4c49e95	6396	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6397
phungductung	0:e87aa4c49e95	6398	/****************** Bits definition for RTC_BKP20R register *************/
phungductung	0:e87aa4c49e95	6399	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6400
phungductung	0:e87aa4c49e95	6401	/****************** Bits definition for RTC_BKP21R register *************/
phungductung	0:e87aa4c49e95	6402	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6403
phungductung	0:e87aa4c49e95	6404	/****************** Bits definition for RTC_BKP22R register *************/
phungductung	0:e87aa4c49e95	6405	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6406
phungductung	0:e87aa4c49e95	6407	/****************** Bits definition for RTC_BKP23R register *************/
phungductung	0:e87aa4c49e95	6408	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6409
phungductung	0:e87aa4c49e95	6410	/****************** Bits definition for RTC_BKP24R register *************/
phungductung	0:e87aa4c49e95	6411	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6412
phungductung	0:e87aa4c49e95	6413	/****************** Bits definition for RTC_BKP25R register *************/
phungductung	0:e87aa4c49e95	6414	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6415
phungductung	0:e87aa4c49e95	6416	/****************** Bits definition for RTC_BKP26R register *************/
phungductung	0:e87aa4c49e95	6417	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6418
phungductung	0:e87aa4c49e95	6419	/****************** Bits definition for RTC_BKP27R register *************/
phungductung	0:e87aa4c49e95	6420	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6421
phungductung	0:e87aa4c49e95	6422	/****************** Bits definition for RTC_BKP28R register *************/
phungductung	0:e87aa4c49e95	6423	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6424
phungductung	0:e87aa4c49e95	6425	/****************** Bits definition for RTC_BKP29R register *************/
phungductung	0:e87aa4c49e95	6426	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6427
phungductung	0:e87aa4c49e95	6428	/****************** Bits definition for RTC_BKP30R register *************/
phungductung	0:e87aa4c49e95	6429	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6430
phungductung	0:e87aa4c49e95	6431	/****************** Bits definition for RTC_BKP31R register *************/
phungductung	0:e87aa4c49e95	6432	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6433
phungductung	0:e87aa4c49e95	6434	/****************** Number of backup registers ****************************/
phungductung	0:e87aa4c49e95	6435	#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	6436
phungductung	0:e87aa4c49e95	6437
phungductung	0:e87aa4c49e95	6438	/******************************************************************************/
phungductung	0:e87aa4c49e95	6439	/* */
phungductung	0:e87aa4c49e95	6440	/* Serial Audio Interface */
phungductung	0:e87aa4c49e95	6441	/* */
phungductung	0:e87aa4c49e95	6442	/******************************************************************************/
phungductung	0:e87aa4c49e95	6443	/****************** Bit definition for SAI_GCR register *****************/
phungductung	0:e87aa4c49e95	6444	#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /!<SYNCIN[1:0] bits (Synchronization Inputs) /
phungductung	0:e87aa4c49e95	6445	#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6446	#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6447
phungductung	0:e87aa4c49e95	6448	#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /!<SYNCOUT[1:0] bits (Synchronization Outputs) /
phungductung	0:e87aa4c49e95	6449	#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6450	#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6451
phungductung	0:e87aa4c49e95	6452	/***************** Bit definition for SAI_xCR1 register *****************/
phungductung	0:e87aa4c49e95	6453	#define SAI_xCR1_MODE ((uint32_t)0x00000003) /!<MODE[1:0] bits (Audio Block Mode) /
phungductung	0:e87aa4c49e95	6454	#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6455	#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6456
phungductung	0:e87aa4c49e95	6457	#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /!<PRTCFG[1:0] bits (Protocol Configuration) /
phungductung	0:e87aa4c49e95	6458	#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6459	#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6460
phungductung	0:e87aa4c49e95	6461	#define SAI_xCR1_DS ((uint32_t)0x000000E0) /!<DS[1:0] bits (Data Size) /
phungductung	0:e87aa4c49e95	6462	#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6463	#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6464	#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6465
phungductung	0:e87aa4c49e95	6466	#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /!<LSB First Configuration /
phungductung	0:e87aa4c49e95	6467	#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /!<ClocK STRobing edge /
phungductung	0:e87aa4c49e95	6468
phungductung	0:e87aa4c49e95	6469	#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /!<SYNCEN[1:0](SYNChronization ENable) /
phungductung	0:e87aa4c49e95	6470	#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6471	#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6472
phungductung	0:e87aa4c49e95	6473	#define SAI_xCR1_MONO ((uint32_t)0x00001000) /!<Mono mode /
phungductung	0:e87aa4c49e95	6474	#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /!<Output Drive /
phungductung	0:e87aa4c49e95	6475	#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /!<Audio Block enable /
phungductung	0:e87aa4c49e95	6476	#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /!<DMA enable /
phungductung	0:e87aa4c49e95	6477	#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /!<No Divider Configuration /
phungductung	0:e87aa4c49e95	6478
phungductung	0:e87aa4c49e95	6479	#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /!<MCKDIV[3:0] (Master ClocK Divider) /
phungductung	0:e87aa4c49e95	6480	#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6481	#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6482	#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6483	#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6484
phungductung	0:e87aa4c49e95	6485	/***************** Bit definition for SAI_xCR2 register *****************/
phungductung	0:e87aa4c49e95	6486	#define SAI_xCR2_FTH ((uint32_t)0x00000007) /!<FTH[2:0](Fifo THreshold) /
phungductung	0:e87aa4c49e95	6487	#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6488	#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6489	#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6490
phungductung	0:e87aa4c49e95	6491	#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /!<Fifo FLUSH /
phungductung	0:e87aa4c49e95	6492	#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /!<TRIState Management on data line /
phungductung	0:e87aa4c49e95	6493	#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /!<Mute mode /
phungductung	0:e87aa4c49e95	6494	#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /!<Muate value /
phungductung	0:e87aa4c49e95	6495
phungductung	0:e87aa4c49e95	6496	#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /!<MUTECNT[5:0] (MUTE counter) /
phungductung	0:e87aa4c49e95	6497	#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6498	#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6499	#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6500	#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6501	#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /!<Bit 4 /
phungductung	0:e87aa4c49e95	6502	#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	6503
phungductung	0:e87aa4c49e95	6504	#define SAI_xCR2_CPL ((uint32_t)0x00002000) /!< Complement Bit /
phungductung	0:e87aa4c49e95	6505
phungductung	0:e87aa4c49e95	6506	#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /!<COMP[1:0] (Companding mode) /
phungductung	0:e87aa4c49e95	6507	#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6508	#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6509
phungductung	0:e87aa4c49e95	6510	/**************** Bit definition for SAI_xFRCR register *****************/
phungductung	0:e87aa4c49e95	6511	#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /!<FRL[1:0](Frame length) /
phungductung	0:e87aa4c49e95	6512	#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6513	#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6514	#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6515	#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6516	#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	6517	#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /!<Bit 5 /
phungductung	0:e87aa4c49e95	6518	#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /!<Bit 6 /
phungductung	0:e87aa4c49e95	6519	#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /!<Bit 7 /
phungductung	0:e87aa4c49e95	6520
phungductung	0:e87aa4c49e95	6521	#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /!<FRL[1:0] (Frame synchronization active level length) /
phungductung	0:e87aa4c49e95	6522	#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6523	#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6524	#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6525	#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6526	#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	6527	#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	6528	#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	6529
phungductung	0:e87aa4c49e95	6530	#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /!< Frame Synchronization Definition /
phungductung	0:e87aa4c49e95	6531	#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /!<Frame Synchronization POLarity /
phungductung	0:e87aa4c49e95	6532	#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /!<Frame Synchronization OFFset /
phungductung	0:e87aa4c49e95	6533
phungductung	0:e87aa4c49e95	6534	/**************** Bit definition for SAI_xSLOTR register *****************/
phungductung	0:e87aa4c49e95	6535	#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /!<FRL[4:0](First Bit Offset) /
phungductung	0:e87aa4c49e95	6536	#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6537	#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6538	#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6539	#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6540	#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	6541
phungductung	0:e87aa4c49e95	6542	#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /!<SLOTSZ[1:0] (Slot size) /
phungductung	0:e87aa4c49e95	6543	#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6544	#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6545
phungductung	0:e87aa4c49e95	6546	#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /!<NBSLOT[3:0] (Number of Slot in audio Frame) /
phungductung	0:e87aa4c49e95	6547	#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6548	#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6549	#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6550	#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6551
phungductung	0:e87aa4c49e95	6552	#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /!<SLOTEN[15:0] (Slot Enable) /
phungductung	0:e87aa4c49e95	6553
phungductung	0:e87aa4c49e95	6554	/***************** Bit definition for SAI_xIMR register *****************/
phungductung	0:e87aa4c49e95	6555	#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /!<Overrun underrun interrupt enable /
phungductung	0:e87aa4c49e95	6556	#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /!<Mute detection interrupt enable /
phungductung	0:e87aa4c49e95	6557	#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /!<Wrong Clock Configuration interrupt enable /
phungductung	0:e87aa4c49e95	6558	#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /!<FIFO request interrupt enable /
phungductung	0:e87aa4c49e95	6559	#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /!<Codec not ready interrupt enable /
phungductung	0:e87aa4c49e95	6560	#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection interrupt enable /
phungductung	0:e87aa4c49e95	6561	#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /!<Late frame synchronization detection interrupt enable /
phungductung	0:e87aa4c49e95	6562
phungductung	0:e87aa4c49e95	6563	/****************** Bit definition for SAI_xSR register *****************/
phungductung	0:e87aa4c49e95	6564	#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /!<Overrun underrun /
phungductung	0:e87aa4c49e95	6565	#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /!<Mute detection /
phungductung	0:e87aa4c49e95	6566	#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /!<Wrong Clock Configuration /
phungductung	0:e87aa4c49e95	6567	#define SAI_xSR_FREQ ((uint32_t)0x00000008) /!<FIFO request /
phungductung	0:e87aa4c49e95	6568	#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /!<Codec not ready /
phungductung	0:e87aa4c49e95	6569	#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection /
phungductung	0:e87aa4c49e95	6570	#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /!<Late frame synchronization detection /
phungductung	0:e87aa4c49e95	6571
phungductung	0:e87aa4c49e95	6572	#define SAI_xSR_FLVL ((uint32_t)0x00070000) /!<FLVL[2:0] (FIFO Level Threshold) /
phungductung	0:e87aa4c49e95	6573	#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6574	#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6575	#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6576
phungductung	0:e87aa4c49e95	6577	/**************** Bit definition for SAI_xCLRFR register ****************/
phungductung	0:e87aa4c49e95	6578	#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /!<Clear Overrun underrun /
phungductung	0:e87aa4c49e95	6579	#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /!<Clear Mute detection /
phungductung	0:e87aa4c49e95	6580	#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /!<Clear Wrong Clock Configuration /
phungductung	0:e87aa4c49e95	6581	#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /!<Clear FIFO request /
phungductung	0:e87aa4c49e95	6582	#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /!<Clear Codec not ready /
phungductung	0:e87aa4c49e95	6583	#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /!<Clear Anticipated frame synchronization detection /
phungductung	0:e87aa4c49e95	6584	#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /!<Clear Late frame synchronization detection /
phungductung	0:e87aa4c49e95	6585
phungductung	0:e87aa4c49e95	6586	/**************** Bit definition for SAI_xDR register *******************/
phungductung	0:e87aa4c49e95	6587	#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
phungductung	0:e87aa4c49e95	6588
phungductung	0:e87aa4c49e95	6589	/******************************************************************************/
phungductung	0:e87aa4c49e95	6590	/* */
phungductung	0:e87aa4c49e95	6591	/* SPDIF-RX Interface */
phungductung	0:e87aa4c49e95	6592	/* */
phungductung	0:e87aa4c49e95	6593	/******************************************************************************/
phungductung	0:e87aa4c49e95	6594	/****************** Bit definition for SPDIF_CR register *****************/
phungductung	0:e87aa4c49e95	6595	#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /!<Peripheral Block Enable /
phungductung	0:e87aa4c49e95	6596	#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /!<Receiver DMA Enable for data flow /
phungductung	0:e87aa4c49e95	6597	#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /!<Stereo Mode /
phungductung	0:e87aa4c49e95	6598	#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /!<RX Data format /
phungductung	0:e87aa4c49e95	6599	#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /!<Mask Parity error bit /
phungductung	0:e87aa4c49e95	6600	#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /!<Mask of Validity bit /
phungductung	0:e87aa4c49e95	6601	#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /!<Mask of channel status and user bits /
phungductung	0:e87aa4c49e95	6602	#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /!<Mask of Preamble Type bits /
phungductung	0:e87aa4c49e95	6603	#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /!<Control Buffer DMA ENable for control flow /
phungductung	0:e87aa4c49e95	6604	#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /!<Channel Selection /
phungductung	0:e87aa4c49e95	6605	#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /!<Maximum allowed re-tries during synchronization phase /
phungductung	0:e87aa4c49e95	6606	#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /!<Wait For Activity /
phungductung	0:e87aa4c49e95	6607	#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /!<SPDIF input selection /
phungductung	0:e87aa4c49e95	6608
phungductung	0:e87aa4c49e95	6609	/***************** Bit definition for SPDIFRX_IMR register *****************/
phungductung	0:e87aa4c49e95	6610	#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /!<RXNE interrupt enable /
phungductung	0:e87aa4c49e95	6611	#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /!<Control Buffer Ready Interrupt Enable /
phungductung	0:e87aa4c49e95	6612	#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /!<Parity error interrupt enable /
phungductung	0:e87aa4c49e95	6613	#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /!<Overrun error Interrupt Enable /
phungductung	0:e87aa4c49e95	6614	#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /!<Synchronization Block Detected Interrupt Enable /
phungductung	0:e87aa4c49e95	6615	#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /!<Synchronization Done /
phungductung	0:e87aa4c49e95	6616	#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /!<Serial Interface Error Interrupt Enable /
phungductung	0:e87aa4c49e95	6617
phungductung	0:e87aa4c49e95	6618	/***************** Bit definition for SPDIFRX_SR register *****************/
phungductung	0:e87aa4c49e95	6619	#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /!<Read data register not empty /
phungductung	0:e87aa4c49e95	6620	#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /!<The Control Buffer register is not empty /
phungductung	0:e87aa4c49e95	6621	#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /!<Parity error /
phungductung	0:e87aa4c49e95	6622	#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /!<Overrun error /
phungductung	0:e87aa4c49e95	6623	#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /!<Synchronization Block Detected /
phungductung	0:e87aa4c49e95	6624	#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /!<Synchronization Done /
phungductung	0:e87aa4c49e95	6625	#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /!<Framing error /
phungductung	0:e87aa4c49e95	6626	#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /!<Synchronization error /
phungductung	0:e87aa4c49e95	6627	#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /!<Time-out error /
phungductung	0:e87aa4c49e95	6628	#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /!<Duration of 5 symbols counted with spdif_clk /
phungductung	0:e87aa4c49e95	6629
phungductung	0:e87aa4c49e95	6630	/***************** Bit definition for SPDIFRX_IFCR register *****************/
phungductung	0:e87aa4c49e95	6631	#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /!<Clears the Parity error flag /
phungductung	0:e87aa4c49e95	6632	#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /!<Clears the Overrun error flag /
phungductung	0:e87aa4c49e95	6633	#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /!<Clears the Synchronization Block Detected flag /
phungductung	0:e87aa4c49e95	6634	#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /!<Clears the Synchronization Done flag /
phungductung	0:e87aa4c49e95	6635
phungductung	0:e87aa4c49e95	6636	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *****************/
phungductung	0:e87aa4c49e95	6637	#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /!<Data value /
phungductung	0:e87aa4c49e95	6638	#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /!<Parity Error bit /
phungductung	0:e87aa4c49e95	6639	#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /!<Validity bit /
phungductung	0:e87aa4c49e95	6640	#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /!<User bit /
phungductung	0:e87aa4c49e95	6641	#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /!<Channel Status bit /
phungductung	0:e87aa4c49e95	6642	#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /!<Preamble Type /
phungductung	0:e87aa4c49e95	6643
phungductung	0:e87aa4c49e95	6644	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *****************/
phungductung	0:e87aa4c49e95	6645	#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /!<Data value /
phungductung	0:e87aa4c49e95	6646	#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /!<Preamble Type /
phungductung	0:e87aa4c49e95	6647	#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /!<Channel Status bit /
phungductung	0:e87aa4c49e95	6648	#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /!<User bit /
phungductung	0:e87aa4c49e95	6649	#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /!<Validity bit /
phungductung	0:e87aa4c49e95	6650	#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /!<Parity Error bit /
phungductung	0:e87aa4c49e95	6651
phungductung	0:e87aa4c49e95	6652	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *****************/
phungductung	0:e87aa4c49e95	6653	#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /!<Data value Channel B /
phungductung	0:e87aa4c49e95	6654	#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /!<Data value Channel A /
phungductung	0:e87aa4c49e95	6655
phungductung	0:e87aa4c49e95	6656	/***************** Bit definition for SPDIFRX_CSR register *****************/
phungductung	0:e87aa4c49e95	6657	#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /!<User data information /
phungductung	0:e87aa4c49e95	6658	#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /!<Channel A status information /
phungductung	0:e87aa4c49e95	6659	#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /!<Start Of Block /
phungductung	0:e87aa4c49e95	6660
phungductung	0:e87aa4c49e95	6661	/***************** Bit definition for SPDIFRX_DIR register *****************/
phungductung	0:e87aa4c49e95	6662	#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /!<Threshold LOW /
phungductung	0:e87aa4c49e95	6663	#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /!<Threshold HIGH /
phungductung	0:e87aa4c49e95	6664
phungductung	0:e87aa4c49e95	6665
phungductung	0:e87aa4c49e95	6666	/******************************************************************************/
phungductung	0:e87aa4c49e95	6667	/* */
phungductung	0:e87aa4c49e95	6668	/* SD host Interface */
phungductung	0:e87aa4c49e95	6669	/* */
phungductung	0:e87aa4c49e95	6670	/******************************************************************************/
phungductung	0:e87aa4c49e95	6671	/**************** Bit definition for SDMMC_POWER register ****************/
phungductung	0:e87aa4c49e95	6672	#define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /!<PWRCTRL[1:0] bits (Power supply control bits) /
phungductung	0:e87aa4c49e95	6673	#define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6674	#define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6675
phungductung	0:e87aa4c49e95	6676	/**************** Bit definition for SDMMC_CLKCR register ****************/
phungductung	0:e87aa4c49e95	6677	#define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /!<Clock divide factor /
phungductung	0:e87aa4c49e95	6678	#define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /!<Clock enable bit /
phungductung	0:e87aa4c49e95	6679	#define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /!<Power saving configuration bit /
phungductung	0:e87aa4c49e95	6680	#define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /!<Clock divider bypass enable bit /
phungductung	0:e87aa4c49e95	6681
phungductung	0:e87aa4c49e95	6682	#define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
phungductung	0:e87aa4c49e95	6683	#define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6684	#define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6685
phungductung	0:e87aa4c49e95	6686	#define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /!<SDMMC_CK dephasing selection bit /
phungductung	0:e87aa4c49e95	6687	#define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /!<HW Flow Control enable /
phungductung	0:e87aa4c49e95	6688
phungductung	0:e87aa4c49e95	6689	/***************** Bit definition for SDMMC_ARG register *****************/
phungductung	0:e87aa4c49e95	6690	#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!<Command argument /
phungductung	0:e87aa4c49e95	6691
phungductung	0:e87aa4c49e95	6692	/***************** Bit definition for SDMMC_CMD register *****************/
phungductung	0:e87aa4c49e95	6693	#define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /!<Command Index /
phungductung	0:e87aa4c49e95	6694
phungductung	0:e87aa4c49e95	6695	#define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /!<WAITRESP[1:0] bits (Wait for response bits) /
phungductung	0:e87aa4c49e95	6696	#define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
phungductung	0:e87aa4c49e95	6697	#define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
phungductung	0:e87aa4c49e95	6698
phungductung	0:e87aa4c49e95	6699	#define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /!<CPSM Waits for Interrupt Request /
phungductung	0:e87aa4c49e95	6700	#define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
phungductung	0:e87aa4c49e95	6701	#define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /!<Command path state machine (CPSM) Enable bit /
phungductung	0:e87aa4c49e95	6702	#define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!<SD I/O suspend command /
phungductung	0:e87aa4c49e95	6703
phungductung	0:e87aa4c49e95	6704	/*************** Bit definition for SDMMC_RESPCMD register ***************/
phungductung	0:e87aa4c49e95	6705	#define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /!<Response command index /
phungductung	0:e87aa4c49e95	6706
phungductung	0:e87aa4c49e95	6707	/**************** Bit definition for SDMMC_RESP0 register ****************/
phungductung	0:e87aa4c49e95	6708	#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!<Card Status /
phungductung	0:e87aa4c49e95	6709
phungductung	0:e87aa4c49e95	6710	/**************** Bit definition for SDMMC_RESP1 register ****************/
phungductung	0:e87aa4c49e95	6711	#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!<Card Status /
phungductung	0:e87aa4c49e95	6712
phungductung	0:e87aa4c49e95	6713	/**************** Bit definition for SDMMC_RESP2 register ****************/
phungductung	0:e87aa4c49e95	6714	#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!<Card Status /
phungductung	0:e87aa4c49e95	6715
phungductung	0:e87aa4c49e95	6716	/**************** Bit definition for SDMMC_RESP3 register ****************/
phungductung	0:e87aa4c49e95	6717	#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!<Card Status /
phungductung	0:e87aa4c49e95	6718
phungductung	0:e87aa4c49e95	6719	/**************** Bit definition for SDMMC_RESP4 register ****************/
phungductung	0:e87aa4c49e95	6720	#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!<Card Status /
phungductung	0:e87aa4c49e95	6721
phungductung	0:e87aa4c49e95	6722	/**************** Bit definition for SDMMC_DTIMER register ***************/
phungductung	0:e87aa4c49e95	6723	#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!<Data timeout period. /
phungductung	0:e87aa4c49e95	6724
phungductung	0:e87aa4c49e95	6725	/**************** Bit definition for SDMMC_DLEN register *****************/
phungductung	0:e87aa4c49e95	6726	#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!<Data length value /
phungductung	0:e87aa4c49e95	6727
phungductung	0:e87aa4c49e95	6728	/**************** Bit definition for SDMMC_DCTRL register ****************/
phungductung	0:e87aa4c49e95	6729	#define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /!<Data transfer enabled bit /
phungductung	0:e87aa4c49e95	6730	#define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /!<Data transfer direction selection /
phungductung	0:e87aa4c49e95	6731	#define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /!<Data transfer mode selection /
phungductung	0:e87aa4c49e95	6732	#define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /!<DMA enabled bit /
phungductung	0:e87aa4c49e95	6733
phungductung	0:e87aa4c49e95	6734	#define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!<DBLOCKSIZE[3:0] bits (Data block size) /
phungductung	0:e87aa4c49e95	6735	#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6736	#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6737	#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	6738	#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	6739
phungductung	0:e87aa4c49e95	6740	#define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /!<Read wait start /
phungductung	0:e87aa4c49e95	6741	#define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /!<Read wait stop /
phungductung	0:e87aa4c49e95	6742	#define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /!<Read wait mode /
phungductung	0:e87aa4c49e95	6743	#define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /!<SD I/O enable functions /
phungductung	0:e87aa4c49e95	6744
phungductung	0:e87aa4c49e95	6745	/**************** Bit definition for SDMMC_DCOUNT register ***************/
phungductung	0:e87aa4c49e95	6746	#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!<Data count value /
phungductung	0:e87aa4c49e95	6747
phungductung	0:e87aa4c49e95	6748	/**************** Bit definition for SDMMC_STA register ******************/
phungductung	0:e87aa4c49e95	6749	#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /!<Command response received (CRC check failed) /
phungductung	0:e87aa4c49e95	6750	#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /!<Data block sent/received (CRC check failed) /
phungductung	0:e87aa4c49e95	6751	#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /!<Command response timeout /
phungductung	0:e87aa4c49e95	6752	#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /!<Data timeout /
phungductung	0:e87aa4c49e95	6753	#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /!<Transmit FIFO underrun error /
phungductung	0:e87aa4c49e95	6754	#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /!<Received FIFO overrun error /
phungductung	0:e87aa4c49e95	6755	#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /!<Command response received (CRC check passed) /
phungductung	0:e87aa4c49e95	6756	#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /!<Command sent (no response required) /
phungductung	0:e87aa4c49e95	6757	#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /!<Data end (data counter, SDIDCOUNT, is zero) /
phungductung	0:e87aa4c49e95	6758	#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /!<Data block sent/received (CRC check passed) /
phungductung	0:e87aa4c49e95	6759	#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /!<Command transfer in progress /
phungductung	0:e87aa4c49e95	6760	#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /!<Data transmit in progress /
phungductung	0:e87aa4c49e95	6761	#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /!<Data receive in progress /
phungductung	0:e87aa4c49e95	6762	#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
phungductung	0:e87aa4c49e95	6763	#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
phungductung	0:e87aa4c49e95	6764	#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /!<Transmit FIFO full /
phungductung	0:e87aa4c49e95	6765	#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /!<Receive FIFO full /
phungductung	0:e87aa4c49e95	6766	#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /!<Transmit FIFO empty /
phungductung	0:e87aa4c49e95	6767	#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /!<Receive FIFO empty /
phungductung	0:e87aa4c49e95	6768	#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /!<Data available in transmit FIFO /
phungductung	0:e87aa4c49e95	6769	#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /!<Data available in receive FIFO /
phungductung	0:e87aa4c49e95	6770	#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /!<SDMMC interrupt received /
phungductung	0:e87aa4c49e95	6771
phungductung	0:e87aa4c49e95	6772	/***************** Bit definition for SDMMC_ICR register *****************/
phungductung	0:e87aa4c49e95	6773	#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /!<CCRCFAIL flag clear bit /
phungductung	0:e87aa4c49e95	6774	#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /!<DCRCFAIL flag clear bit /
phungductung	0:e87aa4c49e95	6775	#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!<CTIMEOUT flag clear bit /
phungductung	0:e87aa4c49e95	6776	#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!<DTIMEOUT flag clear bit /
phungductung	0:e87aa4c49e95	6777	#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /!<TXUNDERR flag clear bit /
phungductung	0:e87aa4c49e95	6778	#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /!<RXOVERR flag clear bit /
phungductung	0:e87aa4c49e95	6779	#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /!<CMDREND flag clear bit /
phungductung	0:e87aa4c49e95	6780	#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /!<CMDSENT flag clear bit /
phungductung	0:e87aa4c49e95	6781	#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /!<DATAEND flag clear bit /
phungductung	0:e87aa4c49e95	6782	#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /!<DBCKEND flag clear bit /
phungductung	0:e87aa4c49e95	6783	#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /!<SDMMCIT flag clear bit /
phungductung	0:e87aa4c49e95	6784
phungductung	0:e87aa4c49e95	6785	/**************** Bit definition for SDMMC_MASK register *****************/
phungductung	0:e87aa4c49e95	6786	#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!<Command CRC Fail Interrupt Enable /
phungductung	0:e87aa4c49e95	6787	#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!<Data CRC Fail Interrupt Enable /
phungductung	0:e87aa4c49e95	6788	#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!<Command TimeOut Interrupt Enable /
phungductung	0:e87aa4c49e95	6789	#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!<Data TimeOut Interrupt Enable /
phungductung	0:e87aa4c49e95	6790	#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!<Tx FIFO UnderRun Error Interrupt Enable /
phungductung	0:e87aa4c49e95	6791	#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /!<Rx FIFO OverRun Error Interrupt Enable /
phungductung	0:e87aa4c49e95	6792	#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /!<Command Response Received Interrupt Enable /
phungductung	0:e87aa4c49e95	6793	#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /!<Command Sent Interrupt Enable /
phungductung	0:e87aa4c49e95	6794	#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /!<Data End Interrupt Enable /
phungductung	0:e87aa4c49e95	6795	#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /!<Data Block End Interrupt Enable /
phungductung	0:e87aa4c49e95	6796	#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /!<CCommand Acting Interrupt Enable /
phungductung	0:e87aa4c49e95	6797	#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /!<Data Transmit Acting Interrupt Enable /
phungductung	0:e87aa4c49e95	6798	#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /!<Data receive acting interrupt enabled /
phungductung	0:e87aa4c49e95	6799	#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!<Tx FIFO Half Empty interrupt Enable /
phungductung	0:e87aa4c49e95	6800	#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!<Rx FIFO Half Full interrupt Enable /
phungductung	0:e87aa4c49e95	6801	#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!<Tx FIFO Full interrupt Enable /
phungductung	0:e87aa4c49e95	6802	#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!<Rx FIFO Full interrupt Enable /
phungductung	0:e87aa4c49e95	6803	#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!<Tx FIFO Empty interrupt Enable /
phungductung	0:e87aa4c49e95	6804	#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!<Rx FIFO Empty interrupt Enable /
phungductung	0:e87aa4c49e95	6805	#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /!<Data available in Tx FIFO interrupt Enable /
phungductung	0:e87aa4c49e95	6806	#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /!<Data available in Rx FIFO interrupt Enable /
phungductung	0:e87aa4c49e95	6807	#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /!<SDMMC Mode Interrupt Received interrupt Enable /
phungductung	0:e87aa4c49e95	6808
phungductung	0:e87aa4c49e95	6809	/*************** Bit definition for SDMMC_FIFOCNT register ***************/
phungductung	0:e87aa4c49e95	6810	#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!<Remaining number of words to be written to or read from the FIFO /
phungductung	0:e87aa4c49e95	6811
phungductung	0:e87aa4c49e95	6812	/**************** Bit definition for SDMMC_FIFO register *****************/
phungductung	0:e87aa4c49e95	6813	#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!<Receive and transmit FIFO data /
phungductung	0:e87aa4c49e95	6814
phungductung	0:e87aa4c49e95	6815	/******************************************************************************/
phungductung	0:e87aa4c49e95	6816	/* */
phungductung	0:e87aa4c49e95	6817	/* Serial Peripheral Interface (SPI) */
phungductung	0:e87aa4c49e95	6818	/* */
phungductung	0:e87aa4c49e95	6819	/******************************************************************************/
phungductung	0:e87aa4c49e95	6820	/***************** Bit definition for SPI_CR1 register ******************/
phungductung	0:e87aa4c49e95	6821	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
phungductung	0:e87aa4c49e95	6822	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
phungductung	0:e87aa4c49e95	6823	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
phungductung	0:e87aa4c49e95	6824	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
phungductung	0:e87aa4c49e95	6825	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
phungductung	0:e87aa4c49e95	6826	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
phungductung	0:e87aa4c49e95	6827	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
phungductung	0:e87aa4c49e95	6828	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
phungductung	0:e87aa4c49e95	6829	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
phungductung	0:e87aa4c49e95	6830	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
phungductung	0:e87aa4c49e95	6831	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
phungductung	0:e87aa4c49e95	6832	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
phungductung	0:e87aa4c49e95	6833	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
phungductung	0:e87aa4c49e95	6834	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
phungductung	0:e87aa4c49e95	6835	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
phungductung	0:e87aa4c49e95	6836	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
phungductung	0:e87aa4c49e95	6837	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
phungductung	0:e87aa4c49e95	6838
phungductung	0:e87aa4c49e95	6839	/***************** Bit definition for SPI_CR2 register ******************/
phungductung	0:e87aa4c49e95	6840	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
phungductung	0:e87aa4c49e95	6841	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
phungductung	0:e87aa4c49e95	6842	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
phungductung	0:e87aa4c49e95	6843	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
phungductung	0:e87aa4c49e95	6844	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
phungductung	0:e87aa4c49e95	6845	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
phungductung	0:e87aa4c49e95	6846	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
phungductung	0:e87aa4c49e95	6847	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
phungductung	0:e87aa4c49e95	6848	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
phungductung	0:e87aa4c49e95	6849	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
phungductung	0:e87aa4c49e95	6850	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
phungductung	0:e87aa4c49e95	6851	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
phungductung	0:e87aa4c49e95	6852	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
phungductung	0:e87aa4c49e95	6853	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
phungductung	0:e87aa4c49e95	6854	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
phungductung	0:e87aa4c49e95	6855	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
phungductung	0:e87aa4c49e95	6856
phungductung	0:e87aa4c49e95	6857	/****************** Bit definition for SPI_SR register ******************/
phungductung	0:e87aa4c49e95	6858	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
phungductung	0:e87aa4c49e95	6859	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
phungductung	0:e87aa4c49e95	6860	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
phungductung	0:e87aa4c49e95	6861	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
phungductung	0:e87aa4c49e95	6862	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
phungductung	0:e87aa4c49e95	6863	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
phungductung	0:e87aa4c49e95	6864	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
phungductung	0:e87aa4c49e95	6865	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
phungductung	0:e87aa4c49e95	6866	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
phungductung	0:e87aa4c49e95	6867	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
phungductung	0:e87aa4c49e95	6868	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
phungductung	0:e87aa4c49e95	6869	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
phungductung	0:e87aa4c49e95	6870	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
phungductung	0:e87aa4c49e95	6871	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
phungductung	0:e87aa4c49e95	6872	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	6873
phungductung	0:e87aa4c49e95	6874	/****************** Bit definition for SPI_DR register ******************/
phungductung	0:e87aa4c49e95	6875	#define SPI_DR_DR ((uint32_t)0xFFFF) /!< Data Register /
phungductung	0:e87aa4c49e95	6876
phungductung	0:e87aa4c49e95	6877	/***************** Bit definition for SPI_CRCPR register ****************/
phungductung	0:e87aa4c49e95	6878	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /!< CRC polynomial register /
phungductung	0:e87aa4c49e95	6879
phungductung	0:e87aa4c49e95	6880	/**************** Bit definition for SPI_RXCRCR register ****************/
phungductung	0:e87aa4c49e95	6881	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /!< Rx CRC Register /
phungductung	0:e87aa4c49e95	6882
phungductung	0:e87aa4c49e95	6883	/**************** Bit definition for SPI_TXCRCR register ****************/
phungductung	0:e87aa4c49e95	6884	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /!< Tx CRC Register /
phungductung	0:e87aa4c49e95	6885
phungductung	0:e87aa4c49e95	6886	/**************** Bit definition for SPI_I2SCFGR register ***************/
phungductung	0:e87aa4c49e95	6887	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
phungductung	0:e87aa4c49e95	6888	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
phungductung	0:e87aa4c49e95	6889	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6890	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6891	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
phungductung	0:e87aa4c49e95	6892	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
phungductung	0:e87aa4c49e95	6893	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6894	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6895	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
phungductung	0:e87aa4c49e95	6896	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
phungductung	0:e87aa4c49e95	6897	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	6898	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	6899	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
phungductung	0:e87aa4c49e95	6900	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
phungductung	0:e87aa4c49e95	6901	#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /!<Asynchronous start enable /
phungductung	0:e87aa4c49e95	6902
phungductung	0:e87aa4c49e95	6903	/**************** Bit definition for SPI_I2SPR register *****************/
phungductung	0:e87aa4c49e95	6904	#define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /!<I2S Linear prescaler /
phungductung	0:e87aa4c49e95	6905	#define SPI_I2SPR_ODD ((uint32_t)0x0100) /!<Odd factor for the prescaler /
phungductung	0:e87aa4c49e95	6906	#define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /!<Master Clock Output Enable /
phungductung	0:e87aa4c49e95	6907
phungductung	0:e87aa4c49e95	6908
phungductung	0:e87aa4c49e95	6909	/******************************************************************************/
phungductung	0:e87aa4c49e95	6910	/* */
phungductung	0:e87aa4c49e95	6911	/* SYSCFG */
phungductung	0:e87aa4c49e95	6912	/* */
phungductung	0:e87aa4c49e95	6913	/******************************************************************************/
phungductung	0:e87aa4c49e95	6914	/**************** Bit definition for SYSCFG_MEMRMP register *************/
phungductung	0:e87aa4c49e95	6915	#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /!< Boot information after Reset /
phungductung	0:e87aa4c49e95	6916
phungductung	0:e87aa4c49e95	6917
phungductung	0:e87aa4c49e95	6918	#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /!< FMC Memory Mapping swapping /
phungductung	0:e87aa4c49e95	6919	#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	6920	#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	6921
phungductung	0:e87aa4c49e95	6922	/**************** Bit definition for SYSCFG_PMC register ****************/
phungductung	0:e87aa4c49e95	6923
phungductung	0:e87aa4c49e95	6924	#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /!< Refer to AN4073 on how to use this bit /
phungductung	0:e87aa4c49e95	6925	#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /!< Refer to AN4073 on how to use this bit /
phungductung	0:e87aa4c49e95	6926	#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /!< Refer to AN4073 on how to use this bit /
phungductung	0:e87aa4c49e95	6927	#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /!< Refer to AN4073 on how to use this bit /
phungductung	0:e87aa4c49e95	6928
phungductung	0:e87aa4c49e95	6929	#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /!<Ethernet PHY interface selection /
phungductung	0:e87aa4c49e95	6930
phungductung	0:e87aa4c49e95	6931	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
phungductung	0:e87aa4c49e95	6932	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /!<EXTI 0 configuration /
phungductung	0:e87aa4c49e95	6933	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /!<EXTI 1 configuration /
phungductung	0:e87aa4c49e95	6934	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /!<EXTI 2 configuration /
phungductung	0:e87aa4c49e95	6935	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /!<EXTI 3 configuration /
phungductung	0:e87aa4c49e95	6936	/**
phungductung	0:e87aa4c49e95	6937	* @brief EXTI0 configuration
phungductung	0:e87aa4c49e95	6938	*/
phungductung	0:e87aa4c49e95	6939	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /!<PA[0] pin /
phungductung	0:e87aa4c49e95	6940	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /!<PB[0] pin /
phungductung	0:e87aa4c49e95	6941	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /!<PC[0] pin /
phungductung	0:e87aa4c49e95	6942	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /!<PD[0] pin /
phungductung	0:e87aa4c49e95	6943	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /!<PE[0] pin /
phungductung	0:e87aa4c49e95	6944	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /!<PF[0] pin /
phungductung	0:e87aa4c49e95	6945	#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /!<PG[0] pin /
phungductung	0:e87aa4c49e95	6946	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /!<PH[0] pin /
phungductung	0:e87aa4c49e95	6947	#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /!<PI[0] pin /
phungductung	0:e87aa4c49e95	6948	#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /!<PJ[0] pin /
phungductung	0:e87aa4c49e95	6949	#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /!<PK[0] pin /
phungductung	0:e87aa4c49e95	6950
phungductung	0:e87aa4c49e95	6951	/**
phungductung	0:e87aa4c49e95	6952	* @brief EXTI1 configuration
phungductung	0:e87aa4c49e95	6953	*/
phungductung	0:e87aa4c49e95	6954	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /!<PA[1] pin /
phungductung	0:e87aa4c49e95	6955	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /!<PB[1] pin /
phungductung	0:e87aa4c49e95	6956	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /!<PC[1] pin /
phungductung	0:e87aa4c49e95	6957	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /!<PD[1] pin /
phungductung	0:e87aa4c49e95	6958	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /!<PE[1] pin /
phungductung	0:e87aa4c49e95	6959	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /!<PF[1] pin /
phungductung	0:e87aa4c49e95	6960	#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /!<PG[1] pin /
phungductung	0:e87aa4c49e95	6961	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /!<PH[1] pin /
phungductung	0:e87aa4c49e95	6962	#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /!<PI[1] pin /
phungductung	0:e87aa4c49e95	6963	#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /!<PJ[1] pin /
phungductung	0:e87aa4c49e95	6964	#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /!<PK[1] pin /
phungductung	0:e87aa4c49e95	6965
phungductung	0:e87aa4c49e95	6966	/**
phungductung	0:e87aa4c49e95	6967	* @brief EXTI2 configuration
phungductung	0:e87aa4c49e95	6968	*/
phungductung	0:e87aa4c49e95	6969	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /!<PA[2] pin /
phungductung	0:e87aa4c49e95	6970	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /!<PB[2] pin /
phungductung	0:e87aa4c49e95	6971	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /!<PC[2] pin /
phungductung	0:e87aa4c49e95	6972	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /!<PD[2] pin /
phungductung	0:e87aa4c49e95	6973	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /!<PE[2] pin /
phungductung	0:e87aa4c49e95	6974	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /!<PF[2] pin /
phungductung	0:e87aa4c49e95	6975	#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /!<PG[2] pin /
phungductung	0:e87aa4c49e95	6976	#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /!<PH[2] pin /
phungductung	0:e87aa4c49e95	6977	#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /!<PI[2] pin /
phungductung	0:e87aa4c49e95	6978	#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /!<PJ[2] pin /
phungductung	0:e87aa4c49e95	6979	#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /!<PK[2] pin /
phungductung	0:e87aa4c49e95	6980
phungductung	0:e87aa4c49e95	6981	/**
phungductung	0:e87aa4c49e95	6982	* @brief EXTI3 configuration
phungductung	0:e87aa4c49e95	6983	*/
phungductung	0:e87aa4c49e95	6984	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /!<PA[3] pin /
phungductung	0:e87aa4c49e95	6985	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /!<PB[3] pin /
phungductung	0:e87aa4c49e95	6986	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /!<PC[3] pin /
phungductung	0:e87aa4c49e95	6987	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /!<PD[3] pin /
phungductung	0:e87aa4c49e95	6988	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /!<PE[3] pin /
phungductung	0:e87aa4c49e95	6989	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /!<PF[3] pin /
phungductung	0:e87aa4c49e95	6990	#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /!<PG[3] pin /
phungductung	0:e87aa4c49e95	6991	#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /!<PH[3] pin /
phungductung	0:e87aa4c49e95	6992	#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /!<PI[3] pin /
phungductung	0:e87aa4c49e95	6993	#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /!<PJ[3] pin /
phungductung	0:e87aa4c49e95	6994	#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /!<PK[3] pin /
phungductung	0:e87aa4c49e95	6995
phungductung	0:e87aa4c49e95	6996	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
phungductung	0:e87aa4c49e95	6997	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /!<EXTI 4 configuration /
phungductung	0:e87aa4c49e95	6998	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /!<EXTI 5 configuration /
phungductung	0:e87aa4c49e95	6999	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /!<EXTI 6 configuration /
phungductung	0:e87aa4c49e95	7000	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /!<EXTI 7 configuration /
phungductung	0:e87aa4c49e95	7001	/**
phungductung	0:e87aa4c49e95	7002	* @brief EXTI4 configuration
phungductung	0:e87aa4c49e95	7003	*/
phungductung	0:e87aa4c49e95	7004	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /!<PA[4] pin /
phungductung	0:e87aa4c49e95	7005	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /!<PB[4] pin /
phungductung	0:e87aa4c49e95	7006	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /!<PC[4] pin /
phungductung	0:e87aa4c49e95	7007	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /!<PD[4] pin /
phungductung	0:e87aa4c49e95	7008	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /!<PE[4] pin /
phungductung	0:e87aa4c49e95	7009	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /!<PF[4] pin /
phungductung	0:e87aa4c49e95	7010	#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /!<PG[4] pin /
phungductung	0:e87aa4c49e95	7011	#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /!<PH[4] pin /
phungductung	0:e87aa4c49e95	7012	#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /!<PI[4] pin /
phungductung	0:e87aa4c49e95	7013	#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /!<PJ[4] pin /
phungductung	0:e87aa4c49e95	7014	#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /!<PK[4] pin /
phungductung	0:e87aa4c49e95	7015
phungductung	0:e87aa4c49e95	7016	/**
phungductung	0:e87aa4c49e95	7017	* @brief EXTI5 configuration
phungductung	0:e87aa4c49e95	7018	*/
phungductung	0:e87aa4c49e95	7019	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /!<PA[5] pin /
phungductung	0:e87aa4c49e95	7020	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /!<PB[5] pin /
phungductung	0:e87aa4c49e95	7021	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /!<PC[5] pin /
phungductung	0:e87aa4c49e95	7022	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /!<PD[5] pin /
phungductung	0:e87aa4c49e95	7023	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /!<PE[5] pin /
phungductung	0:e87aa4c49e95	7024	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /!<PF[5] pin /
phungductung	0:e87aa4c49e95	7025	#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /!<PG[5] pin /
phungductung	0:e87aa4c49e95	7026	#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /!<PH[5] pin /
phungductung	0:e87aa4c49e95	7027	#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /!<PI[5] pin /
phungductung	0:e87aa4c49e95	7028	#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /!<PJ[5] pin /
phungductung	0:e87aa4c49e95	7029	#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /!<PK[5] pin /
phungductung	0:e87aa4c49e95	7030
phungductung	0:e87aa4c49e95	7031	/**
phungductung	0:e87aa4c49e95	7032	* @brief EXTI6 configuration
phungductung	0:e87aa4c49e95	7033	*/
phungductung	0:e87aa4c49e95	7034	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /!<PA[6] pin /
phungductung	0:e87aa4c49e95	7035	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /!<PB[6] pin /
phungductung	0:e87aa4c49e95	7036	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /!<PC[6] pin /
phungductung	0:e87aa4c49e95	7037	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /!<PD[6] pin /
phungductung	0:e87aa4c49e95	7038	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /!<PE[6] pin /
phungductung	0:e87aa4c49e95	7039	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /!<PF[6] pin /
phungductung	0:e87aa4c49e95	7040	#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /!<PG[6] pin /
phungductung	0:e87aa4c49e95	7041	#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /!<PH[6] pin /
phungductung	0:e87aa4c49e95	7042	#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /!<PI[6] pin /
phungductung	0:e87aa4c49e95	7043	#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /!<PJ[6] pin /
phungductung	0:e87aa4c49e95	7044	#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /!<PK[6] pin /
phungductung	0:e87aa4c49e95	7045
phungductung	0:e87aa4c49e95	7046	/**
phungductung	0:e87aa4c49e95	7047	* @brief EXTI7 configuration
phungductung	0:e87aa4c49e95	7048	*/
phungductung	0:e87aa4c49e95	7049	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /!<PA[7] pin /
phungductung	0:e87aa4c49e95	7050	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /!<PB[7] pin /
phungductung	0:e87aa4c49e95	7051	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /!<PC[7] pin /
phungductung	0:e87aa4c49e95	7052	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /!<PD[7] pin /
phungductung	0:e87aa4c49e95	7053	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /!<PE[7] pin /
phungductung	0:e87aa4c49e95	7054	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /!<PF[7] pin /
phungductung	0:e87aa4c49e95	7055	#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /!<PG[7] pin /
phungductung	0:e87aa4c49e95	7056	#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /!<PH[7] pin /
phungductung	0:e87aa4c49e95	7057	#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /!<PI[7] pin /
phungductung	0:e87aa4c49e95	7058	#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /!<PJ[7] pin /
phungductung	0:e87aa4c49e95	7059	#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /!<PK[7] pin /
phungductung	0:e87aa4c49e95	7060
phungductung	0:e87aa4c49e95	7061	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
phungductung	0:e87aa4c49e95	7062	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /!<EXTI 8 configuration /
phungductung	0:e87aa4c49e95	7063	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /!<EXTI 9 configuration /
phungductung	0:e87aa4c49e95	7064	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /!<EXTI 10 configuration /
phungductung	0:e87aa4c49e95	7065	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /!<EXTI 11 configuration /
phungductung	0:e87aa4c49e95	7066
phungductung	0:e87aa4c49e95	7067	/**
phungductung	0:e87aa4c49e95	7068	* @brief EXTI8 configuration
phungductung	0:e87aa4c49e95	7069	*/
phungductung	0:e87aa4c49e95	7070	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /!<PA[8] pin /
phungductung	0:e87aa4c49e95	7071	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /!<PB[8] pin /
phungductung	0:e87aa4c49e95	7072	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /!<PC[8] pin /
phungductung	0:e87aa4c49e95	7073	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /!<PD[8] pin /
phungductung	0:e87aa4c49e95	7074	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /!<PE[8] pin /
phungductung	0:e87aa4c49e95	7075	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /!<PF[8] pin /
phungductung	0:e87aa4c49e95	7076	#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /!<PG[8] pin /
phungductung	0:e87aa4c49e95	7077	#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /!<PH[8] pin /
phungductung	0:e87aa4c49e95	7078	#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /!<PI[8] pin /
phungductung	0:e87aa4c49e95	7079	#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /!<PJ[8] pin /
phungductung	0:e87aa4c49e95	7080
phungductung	0:e87aa4c49e95	7081	/**
phungductung	0:e87aa4c49e95	7082	* @brief EXTI9 configuration
phungductung	0:e87aa4c49e95	7083	*/
phungductung	0:e87aa4c49e95	7084	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /!<PA[9] pin /
phungductung	0:e87aa4c49e95	7085	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /!<PB[9] pin /
phungductung	0:e87aa4c49e95	7086	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /!<PC[9] pin /
phungductung	0:e87aa4c49e95	7087	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /!<PD[9] pin /
phungductung	0:e87aa4c49e95	7088	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /!<PE[9] pin /
phungductung	0:e87aa4c49e95	7089	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /!<PF[9] pin /
phungductung	0:e87aa4c49e95	7090	#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /!<PG[9] pin /
phungductung	0:e87aa4c49e95	7091	#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /!<PH[9] pin /
phungductung	0:e87aa4c49e95	7092	#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /!<PI[9] pin /
phungductung	0:e87aa4c49e95	7093	#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /!<PJ[9] pin /
phungductung	0:e87aa4c49e95	7094
phungductung	0:e87aa4c49e95	7095	/**
phungductung	0:e87aa4c49e95	7096	* @brief EXTI10 configuration
phungductung	0:e87aa4c49e95	7097	*/
phungductung	0:e87aa4c49e95	7098	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /!<PA[10] pin /
phungductung	0:e87aa4c49e95	7099	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /!<PB[10] pin /
phungductung	0:e87aa4c49e95	7100	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /!<PC[10] pin /
phungductung	0:e87aa4c49e95	7101	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /!<PD[10] pin /
phungductung	0:e87aa4c49e95	7102	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /!<PE[10] pin /
phungductung	0:e87aa4c49e95	7103	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /!<PF[10] pin /
phungductung	0:e87aa4c49e95	7104	#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /!<PG[10] pin /
phungductung	0:e87aa4c49e95	7105	#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /!<PH[10] pin /
phungductung	0:e87aa4c49e95	7106	#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /!<PI[10] pin /
phungductung	0:e87aa4c49e95	7107	#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /!<PJ[10] pin /
phungductung	0:e87aa4c49e95	7108
phungductung	0:e87aa4c49e95	7109	/**
phungductung	0:e87aa4c49e95	7110	* @brief EXTI11 configuration
phungductung	0:e87aa4c49e95	7111	*/
phungductung	0:e87aa4c49e95	7112	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /!<PA[11] pin /
phungductung	0:e87aa4c49e95	7113	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /!<PB[11] pin /
phungductung	0:e87aa4c49e95	7114	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /!<PC[11] pin /
phungductung	0:e87aa4c49e95	7115	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /!<PD[11] pin /
phungductung	0:e87aa4c49e95	7116	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /!<PE[11] pin /
phungductung	0:e87aa4c49e95	7117	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /!<PF[11] pin /
phungductung	0:e87aa4c49e95	7118	#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /!<PG[11] pin /
phungductung	0:e87aa4c49e95	7119	#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /!<PH[11] pin /
phungductung	0:e87aa4c49e95	7120	#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /!<PI[11] pin /
phungductung	0:e87aa4c49e95	7121	#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /!<PJ[11] pin /
phungductung	0:e87aa4c49e95	7122
phungductung	0:e87aa4c49e95	7123
phungductung	0:e87aa4c49e95	7124	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
phungductung	0:e87aa4c49e95	7125	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /!<EXTI 12 configuration /
phungductung	0:e87aa4c49e95	7126	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /!<EXTI 13 configuration /
phungductung	0:e87aa4c49e95	7127	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /!<EXTI 14 configuration /
phungductung	0:e87aa4c49e95	7128	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /!<EXTI 15 configuration /
phungductung	0:e87aa4c49e95	7129	/**
phungductung	0:e87aa4c49e95	7130	* @brief EXTI12 configuration
phungductung	0:e87aa4c49e95	7131	*/
phungductung	0:e87aa4c49e95	7132	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /!<PA[12] pin /
phungductung	0:e87aa4c49e95	7133	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /!<PB[12] pin /
phungductung	0:e87aa4c49e95	7134	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /!<PC[12] pin /
phungductung	0:e87aa4c49e95	7135	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /!<PD[12] pin /
phungductung	0:e87aa4c49e95	7136	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /!<PE[12] pin /
phungductung	0:e87aa4c49e95	7137	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /!<PF[12] pin /
phungductung	0:e87aa4c49e95	7138	#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /!<PG[12] pin /
phungductung	0:e87aa4c49e95	7139	#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /!<PH[12] pin /
phungductung	0:e87aa4c49e95	7140	#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /!<PI[12] pin /
phungductung	0:e87aa4c49e95	7141	#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /!<PJ[12] pin /
phungductung	0:e87aa4c49e95	7142
phungductung	0:e87aa4c49e95	7143	/**
phungductung	0:e87aa4c49e95	7144	* @brief EXTI13 configuration
phungductung	0:e87aa4c49e95	7145	*/
phungductung	0:e87aa4c49e95	7146	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /!<PA[13] pin /
phungductung	0:e87aa4c49e95	7147	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /!<PB[13] pin /
phungductung	0:e87aa4c49e95	7148	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /!<PC[13] pin /
phungductung	0:e87aa4c49e95	7149	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /!<PD[13] pin /
phungductung	0:e87aa4c49e95	7150	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /!<PE[13] pin /
phungductung	0:e87aa4c49e95	7151	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /!<PF[13] pin /
phungductung	0:e87aa4c49e95	7152	#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /!<PG[13] pin /
phungductung	0:e87aa4c49e95	7153	#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /!<PH[13] pin /
phungductung	0:e87aa4c49e95	7154	#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /!<PI[13] pin /
phungductung	0:e87aa4c49e95	7155	#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /!<PJ[13] pin /
phungductung	0:e87aa4c49e95	7156
phungductung	0:e87aa4c49e95	7157	/**
phungductung	0:e87aa4c49e95	7158	* @brief EXTI14 configuration
phungductung	0:e87aa4c49e95	7159	*/
phungductung	0:e87aa4c49e95	7160	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /!<PA[14] pin /
phungductung	0:e87aa4c49e95	7161	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /!<PB[14] pin /
phungductung	0:e87aa4c49e95	7162	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /!<PC[14] pin /
phungductung	0:e87aa4c49e95	7163	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /!<PD[14] pin /
phungductung	0:e87aa4c49e95	7164	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /!<PE[14] pin /
phungductung	0:e87aa4c49e95	7165	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /!<PF[14] pin /
phungductung	0:e87aa4c49e95	7166	#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /!<PG[14] pin /
phungductung	0:e87aa4c49e95	7167	#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /!<PH[14] pin /
phungductung	0:e87aa4c49e95	7168	#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /!<PI[14] pin /
phungductung	0:e87aa4c49e95	7169	#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /!<PJ[14] pin /
phungductung	0:e87aa4c49e95	7170
phungductung	0:e87aa4c49e95	7171	/**
phungductung	0:e87aa4c49e95	7172	* @brief EXTI15 configuration
phungductung	0:e87aa4c49e95	7173	*/
phungductung	0:e87aa4c49e95	7174	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /!<PA[15] pin /
phungductung	0:e87aa4c49e95	7175	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /!<PB[15] pin /
phungductung	0:e87aa4c49e95	7176	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /!<PC[15] pin /
phungductung	0:e87aa4c49e95	7177	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /!<PD[15] pin /
phungductung	0:e87aa4c49e95	7178	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /!<PE[15] pin /
phungductung	0:e87aa4c49e95	7179	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /!<PF[15] pin /
phungductung	0:e87aa4c49e95	7180	#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /!<PG[15] pin /
phungductung	0:e87aa4c49e95	7181	#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /!<PH[15] pin /
phungductung	0:e87aa4c49e95	7182	#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /!<PI[15] pin /
phungductung	0:e87aa4c49e95	7183	#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /!<PJ[15] pin /
phungductung	0:e87aa4c49e95	7184
phungductung	0:e87aa4c49e95	7185	/**************** Bit definition for SYSCFG_CMPCR register **************/
phungductung	0:e87aa4c49e95	7186	#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /!<Compensation cell power-down /
phungductung	0:e87aa4c49e95	7187	#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /!<Compensation cell ready flag/
phungductung	0:e87aa4c49e95	7188
phungductung	0:e87aa4c49e95	7189	/******************************************************************************/
phungductung	0:e87aa4c49e95	7190	/* */
phungductung	0:e87aa4c49e95	7191	/* TIM */
phungductung	0:e87aa4c49e95	7192	/* */
phungductung	0:e87aa4c49e95	7193	/******************************************************************************/
phungductung	0:e87aa4c49e95	7194	/***************** Bit definition for TIM_CR1 register ******************/
phungductung	0:e87aa4c49e95	7195	#define TIM_CR1_CEN ((uint32_t)0x0001) /!<Counter enable /
phungductung	0:e87aa4c49e95	7196	#define TIM_CR1_UDIS ((uint32_t)0x0002) /!<Update disable /
phungductung	0:e87aa4c49e95	7197	#define TIM_CR1_URS ((uint32_t)0x0004) /!<Update request source /
phungductung	0:e87aa4c49e95	7198	#define TIM_CR1_OPM ((uint32_t)0x0008) /!<One pulse mode /
phungductung	0:e87aa4c49e95	7199	#define TIM_CR1_DIR ((uint32_t)0x0010) /!<Direction /
phungductung	0:e87aa4c49e95	7200
phungductung	0:e87aa4c49e95	7201	#define TIM_CR1_CMS ((uint32_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
phungductung	0:e87aa4c49e95	7202	#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7203	#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7204
phungductung	0:e87aa4c49e95	7205	#define TIM_CR1_ARPE ((uint32_t)0x0080) /!<Auto-reload preload enable /
phungductung	0:e87aa4c49e95	7206
phungductung	0:e87aa4c49e95	7207	#define TIM_CR1_CKD ((uint32_t)0x0300) /!<CKD[1:0] bits (clock division) /
phungductung	0:e87aa4c49e95	7208	#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7209	#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7210	#define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /!<UIF status bit /
phungductung	0:e87aa4c49e95	7211
phungductung	0:e87aa4c49e95	7212	/***************** Bit definition for TIM_CR2 register ******************/
phungductung	0:e87aa4c49e95	7213	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
phungductung	0:e87aa4c49e95	7214	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
phungductung	0:e87aa4c49e95	7215	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
phungductung	0:e87aa4c49e95	7216
phungductung	0:e87aa4c49e95	7217	#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /!<Output Idle state 4 (OC4 output) /
phungductung	0:e87aa4c49e95	7218	#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /!<Output Idle state 4 (OC4 output) /
phungductung	0:e87aa4c49e95	7219
phungductung	0:e87aa4c49e95	7220	#define TIM_CR2_MMS ((uint32_t)0x0070) /!<MMS[2:0] bits (Master Mode Selection) /
phungductung	0:e87aa4c49e95	7221	#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7222	#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7223	#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7224
phungductung	0:e87aa4c49e95	7225	#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /!<MMS[2:0] bits (Master Mode Selection) /
phungductung	0:e87aa4c49e95	7226	#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7227	#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7228	#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7229	#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7230
phungductung	0:e87aa4c49e95	7231	#define TIM_CR2_TI1S ((uint32_t)0x0080) /!<TI1 Selection /
phungductung	0:e87aa4c49e95	7232	#define TIM_CR2_OIS1 ((uint32_t)0x0100) /!<Output Idle state 1 (OC1 output) /
phungductung	0:e87aa4c49e95	7233	#define TIM_CR2_OIS1N ((uint32_t)0x0200) /!<Output Idle state 1 (OC1N output) /
phungductung	0:e87aa4c49e95	7234	#define TIM_CR2_OIS2 ((uint32_t)0x0400) /!<Output Idle state 2 (OC2 output) /
phungductung	0:e87aa4c49e95	7235	#define TIM_CR2_OIS2N ((uint32_t)0x0800) /!<Output Idle state 2 (OC2N output) /
phungductung	0:e87aa4c49e95	7236	#define TIM_CR2_OIS3 ((uint32_t)0x1000) /!<Output Idle state 3 (OC3 output) /
phungductung	0:e87aa4c49e95	7237	#define TIM_CR2_OIS3N ((uint32_t)0x2000) /!<Output Idle state 3 (OC3N output) /
phungductung	0:e87aa4c49e95	7238	#define TIM_CR2_OIS4 ((uint32_t)0x4000) /!<Output Idle state 4 (OC4 output) /
phungductung	0:e87aa4c49e95	7239
phungductung	0:e87aa4c49e95	7240	/***************** Bit definition for TIM_SMCR register *****************/
phungductung	0:e87aa4c49e95	7241	#define TIM_SMCR_SMS ((uint32_t)0x00010007) /!<SMS[2:0] bits (Slave mode selection) /
phungductung	0:e87aa4c49e95	7242	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7243	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7244	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7245	#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7246	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
phungductung	0:e87aa4c49e95	7247
phungductung	0:e87aa4c49e95	7248	#define TIM_SMCR_TS ((uint32_t)0x0070) /!<TS[2:0] bits (Trigger selection) /
phungductung	0:e87aa4c49e95	7249	#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7250	#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7251	#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7252
phungductung	0:e87aa4c49e95	7253	#define TIM_SMCR_MSM ((uint32_t)0x0080) /!<Master/slave mode /
phungductung	0:e87aa4c49e95	7254
phungductung	0:e87aa4c49e95	7255	#define TIM_SMCR_ETF ((uint32_t)0x0F00) /!<ETF[3:0] bits (External trigger filter) /
phungductung	0:e87aa4c49e95	7256	#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7257	#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7258	#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7259	#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7260
phungductung	0:e87aa4c49e95	7261	#define TIM_SMCR_ETPS ((uint32_t)0x3000) /!<ETPS[1:0] bits (External trigger prescaler) /
phungductung	0:e87aa4c49e95	7262	#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7263	#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7264
phungductung	0:e87aa4c49e95	7265
phungductung	0:e87aa4c49e95	7266	#define TIM_SMCR_ECE ((uint32_t)0x4000) /!<External clock enable /
phungductung	0:e87aa4c49e95	7267	#define TIM_SMCR_ETP ((uint32_t)0x8000) /!<External trigger polarity /
phungductung	0:e87aa4c49e95	7268
phungductung	0:e87aa4c49e95	7269	/***************** Bit definition for TIM_DIER register *****************/
phungductung	0:e87aa4c49e95	7270	#define TIM_DIER_UIE ((uint32_t)0x0001) /!<Update interrupt enable /
phungductung	0:e87aa4c49e95	7271	#define TIM_DIER_CC1IE ((uint32_t)0x0002) /!<Capture/Compare 1 interrupt enable /
phungductung	0:e87aa4c49e95	7272	#define TIM_DIER_CC2IE ((uint32_t)0x0004) /!<Capture/Compare 2 interrupt enable /
phungductung	0:e87aa4c49e95	7273	#define TIM_DIER_CC3IE ((uint32_t)0x0008) /!<Capture/Compare 3 interrupt enable /
phungductung	0:e87aa4c49e95	7274	#define TIM_DIER_CC4IE ((uint32_t)0x0010) /!<Capture/Compare 4 interrupt enable /
phungductung	0:e87aa4c49e95	7275	#define TIM_DIER_COMIE ((uint32_t)0x0020) /!<COM interrupt enable /
phungductung	0:e87aa4c49e95	7276	#define TIM_DIER_TIE ((uint32_t)0x0040) /!<Trigger interrupt enable /
phungductung	0:e87aa4c49e95	7277	#define TIM_DIER_BIE ((uint32_t)0x0080) /!<Break interrupt enable /
phungductung	0:e87aa4c49e95	7278	#define TIM_DIER_UDE ((uint32_t)0x0100) /!<Update DMA request enable /
phungductung	0:e87aa4c49e95	7279	#define TIM_DIER_CC1DE ((uint32_t)0x0200) /!<Capture/Compare 1 DMA request enable /
phungductung	0:e87aa4c49e95	7280	#define TIM_DIER_CC2DE ((uint32_t)0x0400) /!<Capture/Compare 2 DMA request enable /
phungductung	0:e87aa4c49e95	7281	#define TIM_DIER_CC3DE ((uint32_t)0x0800) /!<Capture/Compare 3 DMA request enable /
phungductung	0:e87aa4c49e95	7282	#define TIM_DIER_CC4DE ((uint32_t)0x1000) /!<Capture/Compare 4 DMA request enable /
phungductung	0:e87aa4c49e95	7283	#define TIM_DIER_COMDE ((uint32_t)0x2000) /!<COM DMA request enable /
phungductung	0:e87aa4c49e95	7284	#define TIM_DIER_TDE ((uint32_t)0x4000) /!<Trigger DMA request enable /
phungductung	0:e87aa4c49e95	7285
phungductung	0:e87aa4c49e95	7286	/****************** Bit definition for TIM_SR register ******************/
phungductung	0:e87aa4c49e95	7287	#define TIM_SR_UIF ((uint32_t)0x0001) /!<Update interrupt Flag /
phungductung	0:e87aa4c49e95	7288	#define TIM_SR_CC1IF ((uint32_t)0x0002) /!<Capture/Compare 1 interrupt Flag /
phungductung	0:e87aa4c49e95	7289	#define TIM_SR_CC2IF ((uint32_t)0x0004) /!<Capture/Compare 2 interrupt Flag /
phungductung	0:e87aa4c49e95	7290	#define TIM_SR_CC3IF ((uint32_t)0x0008) /!<Capture/Compare 3 interrupt Flag /
phungductung	0:e87aa4c49e95	7291	#define TIM_SR_CC4IF ((uint32_t)0x0010) /!<Capture/Compare 4 interrupt Flag /
phungductung	0:e87aa4c49e95	7292	#define TIM_SR_COMIF ((uint32_t)0x0020) /!<COM interrupt Flag /
phungductung	0:e87aa4c49e95	7293	#define TIM_SR_TIF ((uint32_t)0x0040) /!<Trigger interrupt Flag /
phungductung	0:e87aa4c49e95	7294	#define TIM_SR_BIF ((uint32_t)0x0080) /!<Break interrupt Flag /
phungductung	0:e87aa4c49e95	7295	#define TIM_SR_B2IF ((uint32_t)0x0100) /!<Break2 interrupt Flag /
phungductung	0:e87aa4c49e95	7296	#define TIM_SR_CC1OF ((uint32_t)0x0200) /!<Capture/Compare 1 Overcapture Flag /
phungductung	0:e87aa4c49e95	7297	#define TIM_SR_CC2OF ((uint32_t)0x0400) /!<Capture/Compare 2 Overcapture Flag /
phungductung	0:e87aa4c49e95	7298	#define TIM_SR_CC3OF ((uint32_t)0x0800) /!<Capture/Compare 3 Overcapture Flag /
phungductung	0:e87aa4c49e95	7299	#define TIM_SR_CC4OF ((uint32_t)0x1000) /!<Capture/Compare 4 Overcapture Flag /
phungductung	0:e87aa4c49e95	7300
phungductung	0:e87aa4c49e95	7301	/***************** Bit definition for TIM_EGR register ******************/
phungductung	0:e87aa4c49e95	7302	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
phungductung	0:e87aa4c49e95	7303	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
phungductung	0:e87aa4c49e95	7304	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
phungductung	0:e87aa4c49e95	7305	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
phungductung	0:e87aa4c49e95	7306	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
phungductung	0:e87aa4c49e95	7307	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
phungductung	0:e87aa4c49e95	7308	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
phungductung	0:e87aa4c49e95	7309	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
phungductung	0:e87aa4c49e95	7310	#define TIM_EGR_B2G ((uint32_t)0x00000100) /!<Break2 Generation /
phungductung	0:e87aa4c49e95	7311
phungductung	0:e87aa4c49e95	7312	/**************** Bit definition for TIM_CCMR1 register *****************/
phungductung	0:e87aa4c49e95	7313	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
phungductung	0:e87aa4c49e95	7314	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7315	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7316
phungductung	0:e87aa4c49e95	7317	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
phungductung	0:e87aa4c49e95	7318	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
phungductung	0:e87aa4c49e95	7319
phungductung	0:e87aa4c49e95	7320	#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
phungductung	0:e87aa4c49e95	7321	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7322	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7323	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7324	#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7325
phungductung	0:e87aa4c49e95	7326	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
phungductung	0:e87aa4c49e95	7327
phungductung	0:e87aa4c49e95	7328	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
phungductung	0:e87aa4c49e95	7329	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7330	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7331
phungductung	0:e87aa4c49e95	7332	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
phungductung	0:e87aa4c49e95	7333	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
phungductung	0:e87aa4c49e95	7334
phungductung	0:e87aa4c49e95	7335	#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
phungductung	0:e87aa4c49e95	7336	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7337	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7338	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7339	#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7340
phungductung	0:e87aa4c49e95	7341	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
phungductung	0:e87aa4c49e95	7342
phungductung	0:e87aa4c49e95	7343	/----------------------------------------------------------------------------/
phungductung	0:e87aa4c49e95	7344
phungductung	0:e87aa4c49e95	7345	#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
phungductung	0:e87aa4c49e95	7346	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7347	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7348
phungductung	0:e87aa4c49e95	7349	#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
phungductung	0:e87aa4c49e95	7350	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7351	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7352	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7353	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7354
phungductung	0:e87aa4c49e95	7355	#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
phungductung	0:e87aa4c49e95	7356	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7357	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7358
phungductung	0:e87aa4c49e95	7359	#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
phungductung	0:e87aa4c49e95	7360	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7361	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7362	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7363	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7364
phungductung	0:e87aa4c49e95	7365	/**************** Bit definition for TIM_CCMR2 register *****************/
phungductung	0:e87aa4c49e95	7366	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
phungductung	0:e87aa4c49e95	7367	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7368	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7369
phungductung	0:e87aa4c49e95	7370	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
phungductung	0:e87aa4c49e95	7371	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
phungductung	0:e87aa4c49e95	7372
phungductung	0:e87aa4c49e95	7373	#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
phungductung	0:e87aa4c49e95	7374	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7375	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7376	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7377	#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7378
phungductung	0:e87aa4c49e95	7379
phungductung	0:e87aa4c49e95	7380
phungductung	0:e87aa4c49e95	7381	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
phungductung	0:e87aa4c49e95	7382
phungductung	0:e87aa4c49e95	7383	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
phungductung	0:e87aa4c49e95	7384	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7385	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7386
phungductung	0:e87aa4c49e95	7387	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
phungductung	0:e87aa4c49e95	7388	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
phungductung	0:e87aa4c49e95	7389
phungductung	0:e87aa4c49e95	7390	#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
phungductung	0:e87aa4c49e95	7391	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7392	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7393	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7394	#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7395
phungductung	0:e87aa4c49e95	7396	#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /!<Output Compare 4 Clear Enable /
phungductung	0:e87aa4c49e95	7397
phungductung	0:e87aa4c49e95	7398	/----------------------------------------------------------------------------/
phungductung	0:e87aa4c49e95	7399
phungductung	0:e87aa4c49e95	7400	#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
phungductung	0:e87aa4c49e95	7401	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7402	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7403
phungductung	0:e87aa4c49e95	7404	#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
phungductung	0:e87aa4c49e95	7405	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7406	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7407	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7408	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7409
phungductung	0:e87aa4c49e95	7410	#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
phungductung	0:e87aa4c49e95	7411	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7412	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7413
phungductung	0:e87aa4c49e95	7414	#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
phungductung	0:e87aa4c49e95	7415	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7416	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7417	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7418	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7419
phungductung	0:e87aa4c49e95	7420	/***************** Bit definition for TIM_CCER register *****************/
phungductung	0:e87aa4c49e95	7421	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
phungductung	0:e87aa4c49e95	7422	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
phungductung	0:e87aa4c49e95	7423	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
phungductung	0:e87aa4c49e95	7424	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
phungductung	0:e87aa4c49e95	7425	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
phungductung	0:e87aa4c49e95	7426	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
phungductung	0:e87aa4c49e95	7427	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
phungductung	0:e87aa4c49e95	7428	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
phungductung	0:e87aa4c49e95	7429	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
phungductung	0:e87aa4c49e95	7430	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
phungductung	0:e87aa4c49e95	7431	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
phungductung	0:e87aa4c49e95	7432	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
phungductung	0:e87aa4c49e95	7433	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
phungductung	0:e87aa4c49e95	7434	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
phungductung	0:e87aa4c49e95	7435	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
phungductung	0:e87aa4c49e95	7436	#define TIM_CCER_CC5E ((uint32_t)0x00010000) /!<Capture/Compare 5 output enable /
phungductung	0:e87aa4c49e95	7437	#define TIM_CCER_CC5P ((uint32_t)0x00020000) /!<Capture/Compare 5 output Polarity /
phungductung	0:e87aa4c49e95	7438	#define TIM_CCER_CC6E ((uint32_t)0x00100000) /!<Capture/Compare 6 output enable /
phungductung	0:e87aa4c49e95	7439	#define TIM_CCER_CC6P ((uint32_t)0x00200000) /!<Capture/Compare 6 output Polarity /
phungductung	0:e87aa4c49e95	7440
phungductung	0:e87aa4c49e95	7441
phungductung	0:e87aa4c49e95	7442	/***************** Bit definition for TIM_CNT register ******************/
phungductung	0:e87aa4c49e95	7443	#define TIM_CNT_CNT ((uint32_t)0xFFFF) /!<Counter Value /
phungductung	0:e87aa4c49e95	7444
phungductung	0:e87aa4c49e95	7445	/***************** Bit definition for TIM_PSC register ******************/
phungductung	0:e87aa4c49e95	7446	#define TIM_PSC_PSC ((uint32_t)0xFFFF) /!<Prescaler Value /
phungductung	0:e87aa4c49e95	7447
phungductung	0:e87aa4c49e95	7448	/***************** Bit definition for TIM_ARR register ******************/
phungductung	0:e87aa4c49e95	7449	#define TIM_ARR_ARR ((uint32_t)0xFFFF) /!<actual auto-reload Value /
phungductung	0:e87aa4c49e95	7450
phungductung	0:e87aa4c49e95	7451	/***************** Bit definition for TIM_RCR register ******************/
phungductung	0:e87aa4c49e95	7452	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
phungductung	0:e87aa4c49e95	7453
phungductung	0:e87aa4c49e95	7454	/***************** Bit definition for TIM_CCR1 register *****************/
phungductung	0:e87aa4c49e95	7455	#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /!<Capture/Compare 1 Value /
phungductung	0:e87aa4c49e95	7456
phungductung	0:e87aa4c49e95	7457	/***************** Bit definition for TIM_CCR2 register *****************/
phungductung	0:e87aa4c49e95	7458	#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /!<Capture/Compare 2 Value /
phungductung	0:e87aa4c49e95	7459
phungductung	0:e87aa4c49e95	7460	/***************** Bit definition for TIM_CCR3 register *****************/
phungductung	0:e87aa4c49e95	7461	#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /!<Capture/Compare 3 Value /
phungductung	0:e87aa4c49e95	7462
phungductung	0:e87aa4c49e95	7463	/***************** Bit definition for TIM_CCR4 register *****************/
phungductung	0:e87aa4c49e95	7464	#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /!<Capture/Compare 4 Value /
phungductung	0:e87aa4c49e95	7465
phungductung	0:e87aa4c49e95	7466	/***************** Bit definition for TIM_BDTR register *****************/
phungductung	0:e87aa4c49e95	7467	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
phungductung	0:e87aa4c49e95	7468	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7469	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7470	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7471	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7472	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	7473	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
phungductung	0:e87aa4c49e95	7474	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
phungductung	0:e87aa4c49e95	7475	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
phungductung	0:e87aa4c49e95	7476
phungductung	0:e87aa4c49e95	7477	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
phungductung	0:e87aa4c49e95	7478	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7479	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7480
phungductung	0:e87aa4c49e95	7481	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
phungductung	0:e87aa4c49e95	7482	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
phungductung	0:e87aa4c49e95	7483	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
phungductung	0:e87aa4c49e95	7484	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
phungductung	0:e87aa4c49e95	7485	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
phungductung	0:e87aa4c49e95	7486	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
phungductung	0:e87aa4c49e95	7487	#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /!<Break Filter for Break1 /
phungductung	0:e87aa4c49e95	7488	#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /!<Break Filter for Break2 /
phungductung	0:e87aa4c49e95	7489	#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /!<Break enable for Break2 /
phungductung	0:e87aa4c49e95	7490	#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /!<Break Polarity for Break2 /
phungductung	0:e87aa4c49e95	7491
phungductung	0:e87aa4c49e95	7492	/***************** Bit definition for TIM_DCR register ******************/
phungductung	0:e87aa4c49e95	7493	#define TIM_DCR_DBA ((uint32_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
phungductung	0:e87aa4c49e95	7494	#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7495	#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7496	#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7497	#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7498	#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	7499
phungductung	0:e87aa4c49e95	7500	#define TIM_DCR_DBL ((uint32_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
phungductung	0:e87aa4c49e95	7501	#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7502	#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7503	#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7504	#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7505	#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	7506
phungductung	0:e87aa4c49e95	7507	/***************** Bit definition for TIM_DMAR register *****************/
phungductung	0:e87aa4c49e95	7508	#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /!<DMA register for burst accesses /
phungductung	0:e87aa4c49e95	7509
phungductung	0:e87aa4c49e95	7510	/***************** Bit definition for TIM_OR register *******************/
phungductung	0:e87aa4c49e95	7511	#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) /
phungductung	0:e87aa4c49e95	7512	#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7513	#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7514	#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) /
phungductung	0:e87aa4c49e95	7515	#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7516	#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7517
phungductung	0:e87aa4c49e95	7518	/**************** Bit definition for TIM_CCMR3 register *****************/
phungductung	0:e87aa4c49e95	7519	#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /!<Output Compare 5 Fast enable /
phungductung	0:e87aa4c49e95	7520	#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /!<Output Compare 5 Preload enable /
phungductung	0:e87aa4c49e95	7521
phungductung	0:e87aa4c49e95	7522	#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /!<OC5M[2:0] bits (Output Compare 5 Mode) /
phungductung	0:e87aa4c49e95	7523	#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7524	#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7525	#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7526	#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7527
phungductung	0:e87aa4c49e95	7528	#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /!<Output Compare 5 Clear Enable /
phungductung	0:e87aa4c49e95	7529
phungductung	0:e87aa4c49e95	7530	#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
phungductung	0:e87aa4c49e95	7531	#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
phungductung	0:e87aa4c49e95	7532
phungductung	0:e87aa4c49e95	7533	#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
phungductung	0:e87aa4c49e95	7534	#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7535	#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7536	#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7537	#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7538
phungductung	0:e87aa4c49e95	7539	#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
phungductung	0:e87aa4c49e95	7540
phungductung	0:e87aa4c49e95	7541	/***************** Bit definition for TIM_CCR5 register *****************/
phungductung	0:e87aa4c49e95	7542	#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /!<Capture/Compare 5 Value /
phungductung	0:e87aa4c49e95	7543	#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /!<Group Channel 5 and Channel 1 /
phungductung	0:e87aa4c49e95	7544	#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /!<Group Channel 5 and Channel 2 /
phungductung	0:e87aa4c49e95	7545	#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /!<Group Channel 5 and Channel 3 /
phungductung	0:e87aa4c49e95	7546
phungductung	0:e87aa4c49e95	7547	/***************** Bit definition for TIM_CCR6 register *****************/
phungductung	0:e87aa4c49e95	7548	#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /!<Capture/Compare 6 Value /
phungductung	0:e87aa4c49e95	7549
phungductung	0:e87aa4c49e95	7550
phungductung	0:e87aa4c49e95	7551	/******************************************************************************/
phungductung	0:e87aa4c49e95	7552	/* */
phungductung	0:e87aa4c49e95	7553	/* Low Power Timer (LPTIM) */
phungductung	0:e87aa4c49e95	7554	/* */
phungductung	0:e87aa4c49e95	7555	/******************************************************************************/
phungductung	0:e87aa4c49e95	7556	/**************** Bit definition for LPTIM_ISR register *****************/
phungductung	0:e87aa4c49e95	7557	#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /!< Compare match /
phungductung	0:e87aa4c49e95	7558	#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /!< Autoreload match /
phungductung	0:e87aa4c49e95	7559	#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /!< External trigger edge event /
phungductung	0:e87aa4c49e95	7560	#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /!< Compare register update OK /
phungductung	0:e87aa4c49e95	7561	#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /!< Autoreload register update OK /
phungductung	0:e87aa4c49e95	7562	#define LPTIM_ISR_UP ((uint32_t)0x00000020) /!< Counter direction change down to up /
phungductung	0:e87aa4c49e95	7563	#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /!< Counter direction change up to down /
phungductung	0:e87aa4c49e95	7564
phungductung	0:e87aa4c49e95	7565	/**************** Bit definition for LPTIM_ICR register *****************/
phungductung	0:e87aa4c49e95	7566	#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /!< Compare match Clear Flag /
phungductung	0:e87aa4c49e95	7567	#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /!< Autoreload match Clear Flag /
phungductung	0:e87aa4c49e95	7568	#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /!< External trigger edge event Clear Flag /
phungductung	0:e87aa4c49e95	7569	#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /!< Compare register update OK Clear Flag /
phungductung	0:e87aa4c49e95	7570	#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /!< Autoreload register update OK Clear Flag /
phungductung	0:e87aa4c49e95	7571	#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /!< Counter direction change down to up Clear Flag /
phungductung	0:e87aa4c49e95	7572	#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /!< Counter direction change up to down Clear Flag /
phungductung	0:e87aa4c49e95	7573
phungductung	0:e87aa4c49e95	7574	/**************** Bit definition for LPTIM_IER register ******************/
phungductung	0:e87aa4c49e95	7575	#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /!< Compare match Interrupt Enable /
phungductung	0:e87aa4c49e95	7576	#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /!< Autoreload match Interrupt Enable /
phungductung	0:e87aa4c49e95	7577	#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /!< External trigger edge event Interrupt Enable /
phungductung	0:e87aa4c49e95	7578	#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /!< Compare register update OK Interrupt Enable /
phungductung	0:e87aa4c49e95	7579	#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /!< Autoreload register update OK Interrupt Enable /
phungductung	0:e87aa4c49e95	7580	#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /!< Counter direction change down to up Interrupt Enable /
phungductung	0:e87aa4c49e95	7581	#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /!< Counter direction change up to down Interrupt Enable /
phungductung	0:e87aa4c49e95	7582
phungductung	0:e87aa4c49e95	7583	/**************** Bit definition for LPTIM_CFGR register *****************/
phungductung	0:e87aa4c49e95	7584	#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /!< Clock selector /
phungductung	0:e87aa4c49e95	7585
phungductung	0:e87aa4c49e95	7586	#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /!< CKPOL[1:0] bits (Clock polarity) /
phungductung	0:e87aa4c49e95	7587	#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7588	#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7589
phungductung	0:e87aa4c49e95	7590	#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
phungductung	0:e87aa4c49e95	7591	#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7592	#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7593
phungductung	0:e87aa4c49e95	7594	#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
phungductung	0:e87aa4c49e95	7595	#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7596	#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7597
phungductung	0:e87aa4c49e95	7598	#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /!< PRESC[2:0] bits (Clock prescaler) /
phungductung	0:e87aa4c49e95	7599	#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7600	#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7601	#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /!< Bit 2 /
phungductung	0:e87aa4c49e95	7602
phungductung	0:e87aa4c49e95	7603	#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /!< TRIGSEL[2:0]] bits (Trigger selector) /
phungductung	0:e87aa4c49e95	7604	#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7605	#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7606	#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	7607
phungductung	0:e87aa4c49e95	7608	#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
phungductung	0:e87aa4c49e95	7609	#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7610	#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7611
phungductung	0:e87aa4c49e95	7612	#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /!< Timout enable /
phungductung	0:e87aa4c49e95	7613	#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /!< Waveform shape /
phungductung	0:e87aa4c49e95	7614	#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /!< Waveform shape polarity /
phungductung	0:e87aa4c49e95	7615	#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /!< Reg update mode /
phungductung	0:e87aa4c49e95	7616	#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /!< Counter mode enable /
phungductung	0:e87aa4c49e95	7617	#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /!< Encoder mode enable /
phungductung	0:e87aa4c49e95	7618
phungductung	0:e87aa4c49e95	7619	/**************** Bit definition for LPTIM_CR register ******************/
phungductung	0:e87aa4c49e95	7620	#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /!< LPTIMer enable /
phungductung	0:e87aa4c49e95	7621	#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /!< Timer start in single mode /
phungductung	0:e87aa4c49e95	7622	#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /!< Timer start in continuous mode /
phungductung	0:e87aa4c49e95	7623
phungductung	0:e87aa4c49e95	7624	/**************** Bit definition for LPTIM_CMP register *****************/
phungductung	0:e87aa4c49e95	7625	#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /!< Compare register /
phungductung	0:e87aa4c49e95	7626
phungductung	0:e87aa4c49e95	7627	/**************** Bit definition for LPTIM_ARR register *****************/
phungductung	0:e87aa4c49e95	7628	#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /!< Auto reload register /
phungductung	0:e87aa4c49e95	7629
phungductung	0:e87aa4c49e95	7630	/**************** Bit definition for LPTIM_CNT register *****************/
phungductung	0:e87aa4c49e95	7631	#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /!< Counter register /
phungductung	0:e87aa4c49e95	7632	/******************************************************************************/
phungductung	0:e87aa4c49e95	7633	/* */
phungductung	0:e87aa4c49e95	7634	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
phungductung	0:e87aa4c49e95	7635	/* */
phungductung	0:e87aa4c49e95	7636	/******************************************************************************/
phungductung	0:e87aa4c49e95	7637	/**************** Bit definition for USART_CR1 register *****************/
phungductung	0:e87aa4c49e95	7638	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
phungductung	0:e87aa4c49e95	7639	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
phungductung	0:e87aa4c49e95	7640	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
phungductung	0:e87aa4c49e95	7641	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
phungductung	0:e87aa4c49e95	7642	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
phungductung	0:e87aa4c49e95	7643	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
phungductung	0:e87aa4c49e95	7644	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
phungductung	0:e87aa4c49e95	7645	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
phungductung	0:e87aa4c49e95	7646	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
phungductung	0:e87aa4c49e95	7647	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
phungductung	0:e87aa4c49e95	7648	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
phungductung	0:e87aa4c49e95	7649	#define USART_CR1_M ((uint32_t)0x10001000) /!< Word length /
phungductung	0:e87aa4c49e95	7650	#define USART_CR1_M_0 ((uint32_t)0x00001000) /!< Word length - Bit 0 /
phungductung	0:e87aa4c49e95	7651	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
phungductung	0:e87aa4c49e95	7652	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
phungductung	0:e87aa4c49e95	7653	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
phungductung	0:e87aa4c49e95	7654	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
phungductung	0:e87aa4c49e95	7655	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7656	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7657	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	7658	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
phungductung	0:e87aa4c49e95	7659	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
phungductung	0:e87aa4c49e95	7660	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
phungductung	0:e87aa4c49e95	7661	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7662	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7663	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	7664	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
phungductung	0:e87aa4c49e95	7665	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
phungductung	0:e87aa4c49e95	7666	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
phungductung	0:e87aa4c49e95	7667	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
phungductung	0:e87aa4c49e95	7668	#define USART_CR1_M_1 ((uint32_t)0x10000000) /!< Word length - Bit 1 /
phungductung	0:e87aa4c49e95	7669
phungductung	0:e87aa4c49e95	7670	/**************** Bit definition for USART_CR2 register *****************/
phungductung	0:e87aa4c49e95	7671	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
phungductung	0:e87aa4c49e95	7672	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
phungductung	0:e87aa4c49e95	7673	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
phungductung	0:e87aa4c49e95	7674	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
phungductung	0:e87aa4c49e95	7675	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
phungductung	0:e87aa4c49e95	7676	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
phungductung	0:e87aa4c49e95	7677	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
phungductung	0:e87aa4c49e95	7678	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
phungductung	0:e87aa4c49e95	7679	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7680	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7681	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
phungductung	0:e87aa4c49e95	7682	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
phungductung	0:e87aa4c49e95	7683	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
phungductung	0:e87aa4c49e95	7684	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
phungductung	0:e87aa4c49e95	7685	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
phungductung	0:e87aa4c49e95	7686	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
phungductung	0:e87aa4c49e95	7687	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable /
phungductung	0:e87aa4c49e95	7688	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
phungductung	0:e87aa4c49e95	7689	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7690	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7691	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
phungductung	0:e87aa4c49e95	7692	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
phungductung	0:e87aa4c49e95	7693
phungductung	0:e87aa4c49e95	7694	/**************** Bit definition for USART_CR3 register *****************/
phungductung	0:e87aa4c49e95	7695	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
phungductung	0:e87aa4c49e95	7696	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
phungductung	0:e87aa4c49e95	7697	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
phungductung	0:e87aa4c49e95	7698	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
phungductung	0:e87aa4c49e95	7699	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
phungductung	0:e87aa4c49e95	7700	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
phungductung	0:e87aa4c49e95	7701	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
phungductung	0:e87aa4c49e95	7702	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
phungductung	0:e87aa4c49e95	7703	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
phungductung	0:e87aa4c49e95	7704	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
phungductung	0:e87aa4c49e95	7705	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
phungductung	0:e87aa4c49e95	7706	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
phungductung	0:e87aa4c49e95	7707	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
phungductung	0:e87aa4c49e95	7708	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
phungductung	0:e87aa4c49e95	7709	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
phungductung	0:e87aa4c49e95	7710	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
phungductung	0:e87aa4c49e95	7711	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
phungductung	0:e87aa4c49e95	7712	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
phungductung	0:e87aa4c49e95	7713	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
phungductung	0:e87aa4c49e95	7714	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
phungductung	0:e87aa4c49e95	7715
phungductung	0:e87aa4c49e95	7716
phungductung	0:e87aa4c49e95	7717	/**************** Bit definition for USART_BRR register *****************/
phungductung	0:e87aa4c49e95	7718	#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /!< Fraction of USARTDIV /
phungductung	0:e87aa4c49e95	7719	#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /!< Mantissa of USARTDIV /
phungductung	0:e87aa4c49e95	7720
phungductung	0:e87aa4c49e95	7721	/**************** Bit definition for USART_GTPR register ****************/
phungductung	0:e87aa4c49e95	7722	#define USART_GTPR_PSC ((uint32_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
phungductung	0:e87aa4c49e95	7723	#define USART_GTPR_GT ((uint32_t)0xFF00) /!< GT[7:0] bits (Guard time value) /
phungductung	0:e87aa4c49e95	7724
phungductung	0:e87aa4c49e95	7725
phungductung	0:e87aa4c49e95	7726	/***************** Bit definition for USART_RTOR register ***************/
phungductung	0:e87aa4c49e95	7727	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
phungductung	0:e87aa4c49e95	7728	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
phungductung	0:e87aa4c49e95	7729
phungductung	0:e87aa4c49e95	7730	/***************** Bit definition for USART_RQR register ****************/
phungductung	0:e87aa4c49e95	7731	#define USART_RQR_ABRRQ ((uint32_t)0x0001) /!< Auto-Baud Rate Request /
phungductung	0:e87aa4c49e95	7732	#define USART_RQR_SBKRQ ((uint32_t)0x0002) /!< Send Break Request /
phungductung	0:e87aa4c49e95	7733	#define USART_RQR_MMRQ ((uint32_t)0x0004) /!< Mute Mode Request /
phungductung	0:e87aa4c49e95	7734	#define USART_RQR_RXFRQ ((uint32_t)0x0008) /!< Receive Data flush Request /
phungductung	0:e87aa4c49e95	7735	#define USART_RQR_TXFRQ ((uint32_t)0x0010) /!< Transmit data flush Request /
phungductung	0:e87aa4c49e95	7736
phungductung	0:e87aa4c49e95	7737	/***************** Bit definition for USART_ISR register ****************/
phungductung	0:e87aa4c49e95	7738	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
phungductung	0:e87aa4c49e95	7739	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
phungductung	0:e87aa4c49e95	7740	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
phungductung	0:e87aa4c49e95	7741	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
phungductung	0:e87aa4c49e95	7742	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
phungductung	0:e87aa4c49e95	7743	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
phungductung	0:e87aa4c49e95	7744	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
phungductung	0:e87aa4c49e95	7745	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
phungductung	0:e87aa4c49e95	7746	#define USART_ISR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
phungductung	0:e87aa4c49e95	7747	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
phungductung	0:e87aa4c49e95	7748	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
phungductung	0:e87aa4c49e95	7749	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
phungductung	0:e87aa4c49e95	7750	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
phungductung	0:e87aa4c49e95	7751	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
phungductung	0:e87aa4c49e95	7752	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
phungductung	0:e87aa4c49e95	7753	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
phungductung	0:e87aa4c49e95	7754	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
phungductung	0:e87aa4c49e95	7755	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
phungductung	0:e87aa4c49e95	7756	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
phungductung	0:e87aa4c49e95	7757	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
phungductung	0:e87aa4c49e95	7758	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
phungductung	0:e87aa4c49e95	7759	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
phungductung	0:e87aa4c49e95	7760
phungductung	0:e87aa4c49e95	7761	/***************** Bit definition for USART_ICR register ****************/
phungductung	0:e87aa4c49e95	7762	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
phungductung	0:e87aa4c49e95	7763	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
phungductung	0:e87aa4c49e95	7764	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
phungductung	0:e87aa4c49e95	7765	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
phungductung	0:e87aa4c49e95	7766	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
phungductung	0:e87aa4c49e95	7767	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
phungductung	0:e87aa4c49e95	7768	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
phungductung	0:e87aa4c49e95	7769	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
phungductung	0:e87aa4c49e95	7770	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
phungductung	0:e87aa4c49e95	7771	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
phungductung	0:e87aa4c49e95	7772	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
phungductung	0:e87aa4c49e95	7773	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
phungductung	0:e87aa4c49e95	7774
phungductung	0:e87aa4c49e95	7775	/***************** Bit definition for USART_RDR register ****************/
phungductung	0:e87aa4c49e95	7776	#define USART_RDR_RDR ((uint32_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
phungductung	0:e87aa4c49e95	7777
phungductung	0:e87aa4c49e95	7778	/***************** Bit definition for USART_TDR register ****************/
phungductung	0:e87aa4c49e95	7779	#define USART_TDR_TDR ((uint32_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
phungductung	0:e87aa4c49e95	7780
phungductung	0:e87aa4c49e95	7781	/******************************************************************************/
phungductung	0:e87aa4c49e95	7782	/* */
phungductung	0:e87aa4c49e95	7783	/* Window WATCHDOG */
phungductung	0:e87aa4c49e95	7784	/* */
phungductung	0:e87aa4c49e95	7785	/******************************************************************************/
phungductung	0:e87aa4c49e95	7786	/***************** Bit definition for WWDG_CR register ******************/
phungductung	0:e87aa4c49e95	7787	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
phungductung	0:e87aa4c49e95	7788	#define WWDG_CR_T_0 ((uint32_t)0x01) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7789	#define WWDG_CR_T_1 ((uint32_t)0x02) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7790	#define WWDG_CR_T_2 ((uint32_t)0x04) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7791	#define WWDG_CR_T_3 ((uint32_t)0x08) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7792	#define WWDG_CR_T_4 ((uint32_t)0x10) /!<Bit 4 /
phungductung	0:e87aa4c49e95	7793	#define WWDG_CR_T_5 ((uint32_t)0x20) /!<Bit 5 /
phungductung	0:e87aa4c49e95	7794	#define WWDG_CR_T_6 ((uint32_t)0x40) /!<Bit 6 /
phungductung	0:e87aa4c49e95	7795
phungductung	0:e87aa4c49e95	7796	/* Legacy defines */
phungductung	0:e87aa4c49e95	7797	#define WWDG_CR_T0 WWDG_CR_T_0 /!<Bit 0 /
phungductung	0:e87aa4c49e95	7798	#define WWDG_CR_T1 WWDG_CR_T_1 /!<Bit 1 /
phungductung	0:e87aa4c49e95	7799	#define WWDG_CR_T2 WWDG_CR_T_2 /!<Bit 2 /
phungductung	0:e87aa4c49e95	7800	#define WWDG_CR_T3 WWDG_CR_T_3 /!<Bit 3 /
phungductung	0:e87aa4c49e95	7801	#define WWDG_CR_T4 WWDG_CR_T_4 /!<Bit 4 /
phungductung	0:e87aa4c49e95	7802	#define WWDG_CR_T5 WWDG_CR_T_5 /!<Bit 5 /
phungductung	0:e87aa4c49e95	7803	#define WWDG_CR_T6 WWDG_CR_T_6 /!<Bit 6 /
phungductung	0:e87aa4c49e95	7804
phungductung	0:e87aa4c49e95	7805	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
phungductung	0:e87aa4c49e95	7806
phungductung	0:e87aa4c49e95	7807	/***************** Bit definition for WWDG_CFR register *****************/
phungductung	0:e87aa4c49e95	7808	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
phungductung	0:e87aa4c49e95	7809	#define WWDG_CFR_W_0 ((uint32_t)0x0001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7810	#define WWDG_CFR_W_1 ((uint32_t)0x0002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7811	#define WWDG_CFR_W_2 ((uint32_t)0x0004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	7812	#define WWDG_CFR_W_3 ((uint32_t)0x0008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	7813	#define WWDG_CFR_W_4 ((uint32_t)0x0010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	7814	#define WWDG_CFR_W_5 ((uint32_t)0x0020) /!<Bit 5 /
phungductung	0:e87aa4c49e95	7815	#define WWDG_CFR_W_6 ((uint32_t)0x0040) /!<Bit 6 /
phungductung	0:e87aa4c49e95	7816
phungductung	0:e87aa4c49e95	7817	/* Legacy defines */
phungductung	0:e87aa4c49e95	7818	#define WWDG_CFR_W0 WWDG_CFR_W_0 /!<Bit 0 /
phungductung	0:e87aa4c49e95	7819	#define WWDG_CFR_W1 WWDG_CFR_W_1 /!<Bit 1 /
phungductung	0:e87aa4c49e95	7820	#define WWDG_CFR_W2 WWDG_CFR_W_2 /!<Bit 2 /
phungductung	0:e87aa4c49e95	7821	#define WWDG_CFR_W3 WWDG_CFR_W_3 /!<Bit 3 /
phungductung	0:e87aa4c49e95	7822	#define WWDG_CFR_W4 WWDG_CFR_W_4 /!<Bit 4 /
phungductung	0:e87aa4c49e95	7823	#define WWDG_CFR_W5 WWDG_CFR_W_5 /!<Bit 5 /
phungductung	0:e87aa4c49e95	7824	#define WWDG_CFR_W6 WWDG_CFR_W_6 /!<Bit 6 /
phungductung	0:e87aa4c49e95	7825
phungductung	0:e87aa4c49e95	7826	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
phungductung	0:e87aa4c49e95	7827	#define WWDG_CFR_WDGTB_0 ((uint32_t)0x0080) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7828	#define WWDG_CFR_WDGTB_1 ((uint32_t)0x0100) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7829
phungductung	0:e87aa4c49e95	7830	/* Legacy defines */
phungductung	0:e87aa4c49e95	7831	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /!<Bit 0 /
phungductung	0:e87aa4c49e95	7832	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /!<Bit 1 /
phungductung	0:e87aa4c49e95	7833
phungductung	0:e87aa4c49e95	7834	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
phungductung	0:e87aa4c49e95	7835
phungductung	0:e87aa4c49e95	7836	/***************** Bit definition for WWDG_SR register ******************/
phungductung	0:e87aa4c49e95	7837	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
phungductung	0:e87aa4c49e95	7838
phungductung	0:e87aa4c49e95	7839	/******************************************************************************/
phungductung	0:e87aa4c49e95	7840	/* */
phungductung	0:e87aa4c49e95	7841	/* DBG */
phungductung	0:e87aa4c49e95	7842	/* */
phungductung	0:e87aa4c49e95	7843	/******************************************************************************/
phungductung	0:e87aa4c49e95	7844	/****************** Bit definition for DBGMCU_IDCODE register ***********/
phungductung	0:e87aa4c49e95	7845	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
phungductung	0:e87aa4c49e95	7846	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
phungductung	0:e87aa4c49e95	7847
phungductung	0:e87aa4c49e95	7848	/****************** Bit definition for DBGMCU_CR register ***************/
phungductung	0:e87aa4c49e95	7849	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	7850	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	7851	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	7852	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	7853
phungductung	0:e87aa4c49e95	7854	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
phungductung	0:e87aa4c49e95	7855	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	7856	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	7857
phungductung	0:e87aa4c49e95	7858	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
phungductung	0:e87aa4c49e95	7859	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	7860	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	7861	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
phungductung	0:e87aa4c49e95	7862	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
phungductung	0:e87aa4c49e95	7863	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
phungductung	0:e87aa4c49e95	7864	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
phungductung	0:e87aa4c49e95	7865	#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
phungductung	0:e87aa4c49e95	7866	#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
phungductung	0:e87aa4c49e95	7867	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
phungductung	0:e87aa4c49e95	7868	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
phungductung	0:e87aa4c49e95	7869	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
phungductung	0:e87aa4c49e95	7870	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
phungductung	0:e87aa4c49e95	7871	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
phungductung	0:e87aa4c49e95	7872	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
phungductung	0:e87aa4c49e95	7873	#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
phungductung	0:e87aa4c49e95	7874	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
phungductung	0:e87aa4c49e95	7875	#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
phungductung	0:e87aa4c49e95	7876
phungductung	0:e87aa4c49e95	7877	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
phungductung	0:e87aa4c49e95	7878	#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
phungductung	0:e87aa4c49e95	7879	#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
phungductung	0:e87aa4c49e95	7880	#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
phungductung	0:e87aa4c49e95	7881	#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
phungductung	0:e87aa4c49e95	7882	#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
phungductung	0:e87aa4c49e95	7883
phungductung	0:e87aa4c49e95	7884	/******************************************************************************/
phungductung	0:e87aa4c49e95	7885	/* */
phungductung	0:e87aa4c49e95	7886	/* Ethernet MAC Registers bits definitions */
phungductung	0:e87aa4c49e95	7887	/* */
phungductung	0:e87aa4c49e95	7888	/******************************************************************************/
phungductung	0:e87aa4c49e95	7889	/* Bit definition for Ethernet MAC Control Register register */
phungductung	0:e87aa4c49e95	7890	#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
phungductung	0:e87aa4c49e95	7891	#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
phungductung	0:e87aa4c49e95	7892	#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
phungductung	0:e87aa4c49e95	7893	#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
phungductung	0:e87aa4c49e95	7894	#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
phungductung	0:e87aa4c49e95	7895	#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
phungductung	0:e87aa4c49e95	7896	#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
phungductung	0:e87aa4c49e95	7897	#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
phungductung	0:e87aa4c49e95	7898	#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
phungductung	0:e87aa4c49e95	7899	#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
phungductung	0:e87aa4c49e95	7900	#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
phungductung	0:e87aa4c49e95	7901	#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
phungductung	0:e87aa4c49e95	7902	#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
phungductung	0:e87aa4c49e95	7903	#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
phungductung	0:e87aa4c49e95	7904	#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
phungductung	0:e87aa4c49e95	7905	#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
phungductung	0:e87aa4c49e95	7906	#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
phungductung	0:e87aa4c49e95	7907	#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
phungductung	0:e87aa4c49e95	7908	#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
phungductung	0:e87aa4c49e95	7909	#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
phungductung	0:e87aa4c49e95	7910	a transmission attempt during retries after a collision: 0 =< r <2^k */
phungductung	0:e87aa4c49e95	7911	#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
phungductung	0:e87aa4c49e95	7912	#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
phungductung	0:e87aa4c49e95	7913	#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
phungductung	0:e87aa4c49e95	7914	#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
phungductung	0:e87aa4c49e95	7915	#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
phungductung	0:e87aa4c49e95	7916	#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
phungductung	0:e87aa4c49e95	7917	#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
phungductung	0:e87aa4c49e95	7918
phungductung	0:e87aa4c49e95	7919	/* Bit definition for Ethernet MAC Frame Filter Register */
phungductung	0:e87aa4c49e95	7920	#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
phungductung	0:e87aa4c49e95	7921	#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
phungductung	0:e87aa4c49e95	7922	#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
phungductung	0:e87aa4c49e95	7923	#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
phungductung	0:e87aa4c49e95	7924	#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
phungductung	0:e87aa4c49e95	7925	#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
phungductung	0:e87aa4c49e95	7926	#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
phungductung	0:e87aa4c49e95	7927	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
phungductung	0:e87aa4c49e95	7928	#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
phungductung	0:e87aa4c49e95	7929	#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
phungductung	0:e87aa4c49e95	7930	#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
phungductung	0:e87aa4c49e95	7931	#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
phungductung	0:e87aa4c49e95	7932	#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
phungductung	0:e87aa4c49e95	7933	#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
phungductung	0:e87aa4c49e95	7934
phungductung	0:e87aa4c49e95	7935	/* Bit definition for Ethernet MAC Hash Table High Register */
phungductung	0:e87aa4c49e95	7936	#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
phungductung	0:e87aa4c49e95	7937
phungductung	0:e87aa4c49e95	7938	/* Bit definition for Ethernet MAC Hash Table Low Register */
phungductung	0:e87aa4c49e95	7939	#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
phungductung	0:e87aa4c49e95	7940
phungductung	0:e87aa4c49e95	7941	/* Bit definition for Ethernet MAC MII Address Register */
phungductung	0:e87aa4c49e95	7942	#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
phungductung	0:e87aa4c49e95	7943	#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
phungductung	0:e87aa4c49e95	7944	#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
phungductung	0:e87aa4c49e95	7945	#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
phungductung	0:e87aa4c49e95	7946	#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
phungductung	0:e87aa4c49e95	7947	#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
phungductung	0:e87aa4c49e95	7948	#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
phungductung	0:e87aa4c49e95	7949	#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
phungductung	0:e87aa4c49e95	7950	#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
phungductung	0:e87aa4c49e95	7951	#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
phungductung	0:e87aa4c49e95	7952
phungductung	0:e87aa4c49e95	7953	/* Bit definition for Ethernet MAC MII Data Register */
phungductung	0:e87aa4c49e95	7954	#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
phungductung	0:e87aa4c49e95	7955
phungductung	0:e87aa4c49e95	7956	/* Bit definition for Ethernet MAC Flow Control Register */
phungductung	0:e87aa4c49e95	7957	#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
phungductung	0:e87aa4c49e95	7958	#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
phungductung	0:e87aa4c49e95	7959	#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
phungductung	0:e87aa4c49e95	7960	#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
phungductung	0:e87aa4c49e95	7961	#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
phungductung	0:e87aa4c49e95	7962	#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
phungductung	0:e87aa4c49e95	7963	#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
phungductung	0:e87aa4c49e95	7964	#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
phungductung	0:e87aa4c49e95	7965	#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
phungductung	0:e87aa4c49e95	7966	#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
phungductung	0:e87aa4c49e95	7967	#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
phungductung	0:e87aa4c49e95	7968
phungductung	0:e87aa4c49e95	7969	/* Bit definition for Ethernet MAC VLAN Tag Register */
phungductung	0:e87aa4c49e95	7970	#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
phungductung	0:e87aa4c49e95	7971	#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
phungductung	0:e87aa4c49e95	7972
phungductung	0:e87aa4c49e95	7973	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
phungductung	0:e87aa4c49e95	7974	#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
phungductung	0:e87aa4c49e95	7975	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
phungductung	0:e87aa4c49e95	7976	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
phungductung	0:e87aa4c49e95	7977	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
phungductung	0:e87aa4c49e95	7978	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
phungductung	0:e87aa4c49e95	7979	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
phungductung	0:e87aa4c49e95	7980	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
phungductung	0:e87aa4c49e95	7981	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
phungductung	0:e87aa4c49e95	7982	RSVD - Filter1 Command - RSVD - Filter0 Command
phungductung	0:e87aa4c49e95	7983	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
phungductung	0:e87aa4c49e95	7984	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
phungductung	0:e87aa4c49e95	7985	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
phungductung	0:e87aa4c49e95	7986
phungductung	0:e87aa4c49e95	7987	/* Bit definition for Ethernet MAC PMT Control and Status Register */
phungductung	0:e87aa4c49e95	7988	#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
phungductung	0:e87aa4c49e95	7989	#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
phungductung	0:e87aa4c49e95	7990	#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
phungductung	0:e87aa4c49e95	7991	#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
phungductung	0:e87aa4c49e95	7992	#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
phungductung	0:e87aa4c49e95	7993	#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
phungductung	0:e87aa4c49e95	7994	#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
phungductung	0:e87aa4c49e95	7995
phungductung	0:e87aa4c49e95	7996	/* Bit definition for Ethernet MAC Status Register */
phungductung	0:e87aa4c49e95	7997	#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
phungductung	0:e87aa4c49e95	7998	#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
phungductung	0:e87aa4c49e95	7999	#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
phungductung	0:e87aa4c49e95	8000	#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
phungductung	0:e87aa4c49e95	8001	#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
phungductung	0:e87aa4c49e95	8002
phungductung	0:e87aa4c49e95	8003	/* Bit definition for Ethernet MAC Interrupt Mask Register */
phungductung	0:e87aa4c49e95	8004	#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
phungductung	0:e87aa4c49e95	8005	#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
phungductung	0:e87aa4c49e95	8006
phungductung	0:e87aa4c49e95	8007	/* Bit definition for Ethernet MAC Address0 High Register */
phungductung	0:e87aa4c49e95	8008	#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
phungductung	0:e87aa4c49e95	8009
phungductung	0:e87aa4c49e95	8010	/* Bit definition for Ethernet MAC Address0 Low Register */
phungductung	0:e87aa4c49e95	8011	#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
phungductung	0:e87aa4c49e95	8012
phungductung	0:e87aa4c49e95	8013	/* Bit definition for Ethernet MAC Address1 High Register */
phungductung	0:e87aa4c49e95	8014	#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
phungductung	0:e87aa4c49e95	8015	#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
phungductung	0:e87aa4c49e95	8016	#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
phungductung	0:e87aa4c49e95	8017	#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
phungductung	0:e87aa4c49e95	8018	#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
phungductung	0:e87aa4c49e95	8019	#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
phungductung	0:e87aa4c49e95	8020	#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
phungductung	0:e87aa4c49e95	8021	#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
phungductung	0:e87aa4c49e95	8022	#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
phungductung	0:e87aa4c49e95	8023	#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
phungductung	0:e87aa4c49e95	8024
phungductung	0:e87aa4c49e95	8025	/* Bit definition for Ethernet MAC Address1 Low Register */
phungductung	0:e87aa4c49e95	8026	#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
phungductung	0:e87aa4c49e95	8027
phungductung	0:e87aa4c49e95	8028	/* Bit definition for Ethernet MAC Address2 High Register */
phungductung	0:e87aa4c49e95	8029	#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
phungductung	0:e87aa4c49e95	8030	#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
phungductung	0:e87aa4c49e95	8031	#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
phungductung	0:e87aa4c49e95	8032	#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
phungductung	0:e87aa4c49e95	8033	#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
phungductung	0:e87aa4c49e95	8034	#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
phungductung	0:e87aa4c49e95	8035	#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
phungductung	0:e87aa4c49e95	8036	#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
phungductung	0:e87aa4c49e95	8037	#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
phungductung	0:e87aa4c49e95	8038	#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
phungductung	0:e87aa4c49e95	8039
phungductung	0:e87aa4c49e95	8040	/* Bit definition for Ethernet MAC Address2 Low Register */
phungductung	0:e87aa4c49e95	8041	#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
phungductung	0:e87aa4c49e95	8042
phungductung	0:e87aa4c49e95	8043	/* Bit definition for Ethernet MAC Address3 High Register */
phungductung	0:e87aa4c49e95	8044	#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
phungductung	0:e87aa4c49e95	8045	#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
phungductung	0:e87aa4c49e95	8046	#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
phungductung	0:e87aa4c49e95	8047	#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
phungductung	0:e87aa4c49e95	8048	#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
phungductung	0:e87aa4c49e95	8049	#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
phungductung	0:e87aa4c49e95	8050	#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
phungductung	0:e87aa4c49e95	8051	#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
phungductung	0:e87aa4c49e95	8052	#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
phungductung	0:e87aa4c49e95	8053	#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
phungductung	0:e87aa4c49e95	8054
phungductung	0:e87aa4c49e95	8055	/* Bit definition for Ethernet MAC Address3 Low Register */
phungductung	0:e87aa4c49e95	8056	#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
phungductung	0:e87aa4c49e95	8057
phungductung	0:e87aa4c49e95	8058	/******************************************************************************/
phungductung	0:e87aa4c49e95	8059	/* Ethernet MMC Registers bits definition */
phungductung	0:e87aa4c49e95	8060	/******************************************************************************/
phungductung	0:e87aa4c49e95	8061
phungductung	0:e87aa4c49e95	8062	/* Bit definition for Ethernet MMC Contol Register */
phungductung	0:e87aa4c49e95	8063	#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
phungductung	0:e87aa4c49e95	8064	#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
phungductung	0:e87aa4c49e95	8065	#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
phungductung	0:e87aa4c49e95	8066	#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
phungductung	0:e87aa4c49e95	8067	#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
phungductung	0:e87aa4c49e95	8068	#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
phungductung	0:e87aa4c49e95	8069
phungductung	0:e87aa4c49e95	8070	/* Bit definition for Ethernet MMC Receive Interrupt Register */
phungductung	0:e87aa4c49e95	8071	#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8072	#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8073	#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8074
phungductung	0:e87aa4c49e95	8075	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
phungductung	0:e87aa4c49e95	8076	#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8077	#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8078	#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8079
phungductung	0:e87aa4c49e95	8080	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
phungductung	0:e87aa4c49e95	8081	#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8082	#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8083	#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8084
phungductung	0:e87aa4c49e95	8085	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
phungductung	0:e87aa4c49e95	8086	#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8087	#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8088	#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
phungductung	0:e87aa4c49e95	8089
phungductung	0:e87aa4c49e95	8090	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
phungductung	0:e87aa4c49e95	8091	#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
phungductung	0:e87aa4c49e95	8092
phungductung	0:e87aa4c49e95	8093	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
phungductung	0:e87aa4c49e95	8094	#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
phungductung	0:e87aa4c49e95	8095
phungductung	0:e87aa4c49e95	8096	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
phungductung	0:e87aa4c49e95	8097	#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
phungductung	0:e87aa4c49e95	8098
phungductung	0:e87aa4c49e95	8099	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
phungductung	0:e87aa4c49e95	8100	#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
phungductung	0:e87aa4c49e95	8101
phungductung	0:e87aa4c49e95	8102	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
phungductung	0:e87aa4c49e95	8103	#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
phungductung	0:e87aa4c49e95	8104
phungductung	0:e87aa4c49e95	8105	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
phungductung	0:e87aa4c49e95	8106	#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
phungductung	0:e87aa4c49e95	8107
phungductung	0:e87aa4c49e95	8108	/******************************************************************************/
phungductung	0:e87aa4c49e95	8109	/* Ethernet PTP Registers bits definition */
phungductung	0:e87aa4c49e95	8110	/******************************************************************************/
phungductung	0:e87aa4c49e95	8111
phungductung	0:e87aa4c49e95	8112	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
phungductung	0:e87aa4c49e95	8113	#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
phungductung	0:e87aa4c49e95	8114	#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
phungductung	0:e87aa4c49e95	8115	#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
phungductung	0:e87aa4c49e95	8116	#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
phungductung	0:e87aa4c49e95	8117	#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
phungductung	0:e87aa4c49e95	8118	#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
phungductung	0:e87aa4c49e95	8119	#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
phungductung	0:e87aa4c49e95	8120	#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
phungductung	0:e87aa4c49e95	8121	#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
phungductung	0:e87aa4c49e95	8122
phungductung	0:e87aa4c49e95	8123	#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
phungductung	0:e87aa4c49e95	8124	#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
phungductung	0:e87aa4c49e95	8125	#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
phungductung	0:e87aa4c49e95	8126	#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
phungductung	0:e87aa4c49e95	8127	#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
phungductung	0:e87aa4c49e95	8128	#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
phungductung	0:e87aa4c49e95	8129
phungductung	0:e87aa4c49e95	8130	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
phungductung	0:e87aa4c49e95	8131	#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
phungductung	0:e87aa4c49e95	8132
phungductung	0:e87aa4c49e95	8133	/* Bit definition for Ethernet PTP Time Stamp High Register */
phungductung	0:e87aa4c49e95	8134	#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
phungductung	0:e87aa4c49e95	8135
phungductung	0:e87aa4c49e95	8136	/* Bit definition for Ethernet PTP Time Stamp Low Register */
phungductung	0:e87aa4c49e95	8137	#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
phungductung	0:e87aa4c49e95	8138	#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
phungductung	0:e87aa4c49e95	8139
phungductung	0:e87aa4c49e95	8140	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
phungductung	0:e87aa4c49e95	8141	#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
phungductung	0:e87aa4c49e95	8142
phungductung	0:e87aa4c49e95	8143	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
phungductung	0:e87aa4c49e95	8144	#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
phungductung	0:e87aa4c49e95	8145	#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
phungductung	0:e87aa4c49e95	8146
phungductung	0:e87aa4c49e95	8147	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
phungductung	0:e87aa4c49e95	8148	#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
phungductung	0:e87aa4c49e95	8149
phungductung	0:e87aa4c49e95	8150	/* Bit definition for Ethernet PTP Target Time High Register */
phungductung	0:e87aa4c49e95	8151	#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
phungductung	0:e87aa4c49e95	8152
phungductung	0:e87aa4c49e95	8153	/* Bit definition for Ethernet PTP Target Time Low Register */
phungductung	0:e87aa4c49e95	8154	#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
phungductung	0:e87aa4c49e95	8155
phungductung	0:e87aa4c49e95	8156	/* Bit definition for Ethernet PTP Time Stamp Status Register */
phungductung	0:e87aa4c49e95	8157	#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
phungductung	0:e87aa4c49e95	8158	#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
phungductung	0:e87aa4c49e95	8159
phungductung	0:e87aa4c49e95	8160	/******************************************************************************/
phungductung	0:e87aa4c49e95	8161	/* Ethernet DMA Registers bits definition */
phungductung	0:e87aa4c49e95	8162	/******************************************************************************/
phungductung	0:e87aa4c49e95	8163
phungductung	0:e87aa4c49e95	8164	/* Bit definition for Ethernet DMA Bus Mode Register */
phungductung	0:e87aa4c49e95	8165	#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
phungductung	0:e87aa4c49e95	8166	#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
phungductung	0:e87aa4c49e95	8167	#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
phungductung	0:e87aa4c49e95	8168	#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
phungductung	0:e87aa4c49e95	8169	#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
phungductung	0:e87aa4c49e95	8170	#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
phungductung	0:e87aa4c49e95	8171	#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
phungductung	0:e87aa4c49e95	8172	#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
phungductung	0:e87aa4c49e95	8173	#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
phungductung	0:e87aa4c49e95	8174	#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
phungductung	0:e87aa4c49e95	8175	#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
phungductung	0:e87aa4c49e95	8176	#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
phungductung	0:e87aa4c49e95	8177	#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
phungductung	0:e87aa4c49e95	8178	#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
phungductung	0:e87aa4c49e95	8179	#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
phungductung	0:e87aa4c49e95	8180	#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
phungductung	0:e87aa4c49e95	8181	#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
phungductung	0:e87aa4c49e95	8182	#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
phungductung	0:e87aa4c49e95	8183	#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
phungductung	0:e87aa4c49e95	8184	#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
phungductung	0:e87aa4c49e95	8185	#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
phungductung	0:e87aa4c49e95	8186	#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
phungductung	0:e87aa4c49e95	8187	#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
phungductung	0:e87aa4c49e95	8188	#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
phungductung	0:e87aa4c49e95	8189	#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
phungductung	0:e87aa4c49e95	8190	#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
phungductung	0:e87aa4c49e95	8191	#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
phungductung	0:e87aa4c49e95	8192	#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
phungductung	0:e87aa4c49e95	8193	#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
phungductung	0:e87aa4c49e95	8194	#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
phungductung	0:e87aa4c49e95	8195	#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
phungductung	0:e87aa4c49e95	8196	#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
phungductung	0:e87aa4c49e95	8197	#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
phungductung	0:e87aa4c49e95	8198	#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
phungductung	0:e87aa4c49e95	8199	#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
phungductung	0:e87aa4c49e95	8200	#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
phungductung	0:e87aa4c49e95	8201	#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
phungductung	0:e87aa4c49e95	8202	#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
phungductung	0:e87aa4c49e95	8203	#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
phungductung	0:e87aa4c49e95	8204
phungductung	0:e87aa4c49e95	8205	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
phungductung	0:e87aa4c49e95	8206	#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
phungductung	0:e87aa4c49e95	8207
phungductung	0:e87aa4c49e95	8208	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
phungductung	0:e87aa4c49e95	8209	#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
phungductung	0:e87aa4c49e95	8210
phungductung	0:e87aa4c49e95	8211	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
phungductung	0:e87aa4c49e95	8212	#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
phungductung	0:e87aa4c49e95	8213
phungductung	0:e87aa4c49e95	8214	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
phungductung	0:e87aa4c49e95	8215	#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
phungductung	0:e87aa4c49e95	8216
phungductung	0:e87aa4c49e95	8217	/* Bit definition for Ethernet DMA Status Register */
phungductung	0:e87aa4c49e95	8218	#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
phungductung	0:e87aa4c49e95	8219	#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
phungductung	0:e87aa4c49e95	8220	#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
phungductung	0:e87aa4c49e95	8221	#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
phungductung	0:e87aa4c49e95	8222	/* combination with EBS[2:0] for GetFlagStatus function */
phungductung	0:e87aa4c49e95	8223	#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
phungductung	0:e87aa4c49e95	8224	#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
phungductung	0:e87aa4c49e95	8225	#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
phungductung	0:e87aa4c49e95	8226	#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
phungductung	0:e87aa4c49e95	8227	#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
phungductung	0:e87aa4c49e95	8228	#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
phungductung	0:e87aa4c49e95	8229	#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
phungductung	0:e87aa4c49e95	8230	#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
phungductung	0:e87aa4c49e95	8231	#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
phungductung	0:e87aa4c49e95	8232	#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
phungductung	0:e87aa4c49e95	8233	#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
phungductung	0:e87aa4c49e95	8234	#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
phungductung	0:e87aa4c49e95	8235	#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
phungductung	0:e87aa4c49e95	8236	#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
phungductung	0:e87aa4c49e95	8237	#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
phungductung	0:e87aa4c49e95	8238	#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
phungductung	0:e87aa4c49e95	8239	#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
phungductung	0:e87aa4c49e95	8240	#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
phungductung	0:e87aa4c49e95	8241	#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
phungductung	0:e87aa4c49e95	8242	#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
phungductung	0:e87aa4c49e95	8243	#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
phungductung	0:e87aa4c49e95	8244	#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
phungductung	0:e87aa4c49e95	8245	#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
phungductung	0:e87aa4c49e95	8246	#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
phungductung	0:e87aa4c49e95	8247	#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
phungductung	0:e87aa4c49e95	8248	#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
phungductung	0:e87aa4c49e95	8249	#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
phungductung	0:e87aa4c49e95	8250	#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
phungductung	0:e87aa4c49e95	8251	#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
phungductung	0:e87aa4c49e95	8252	#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
phungductung	0:e87aa4c49e95	8253	#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
phungductung	0:e87aa4c49e95	8254	#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
phungductung	0:e87aa4c49e95	8255
phungductung	0:e87aa4c49e95	8256	/* Bit definition for Ethernet DMA Operation Mode Register */
phungductung	0:e87aa4c49e95	8257	#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
phungductung	0:e87aa4c49e95	8258	#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
phungductung	0:e87aa4c49e95	8259	#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
phungductung	0:e87aa4c49e95	8260	#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
phungductung	0:e87aa4c49e95	8261	#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
phungductung	0:e87aa4c49e95	8262	#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
phungductung	0:e87aa4c49e95	8263	#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
phungductung	0:e87aa4c49e95	8264	#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
phungductung	0:e87aa4c49e95	8265	#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
phungductung	0:e87aa4c49e95	8266	#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
phungductung	0:e87aa4c49e95	8267	#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
phungductung	0:e87aa4c49e95	8268	#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
phungductung	0:e87aa4c49e95	8269	#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
phungductung	0:e87aa4c49e95	8270	#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
phungductung	0:e87aa4c49e95	8271	#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
phungductung	0:e87aa4c49e95	8272	#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
phungductung	0:e87aa4c49e95	8273	#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
phungductung	0:e87aa4c49e95	8274	#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
phungductung	0:e87aa4c49e95	8275	#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
phungductung	0:e87aa4c49e95	8276	#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
phungductung	0:e87aa4c49e95	8277	#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
phungductung	0:e87aa4c49e95	8278	#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
phungductung	0:e87aa4c49e95	8279	#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
phungductung	0:e87aa4c49e95	8280	#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
phungductung	0:e87aa4c49e95	8281
phungductung	0:e87aa4c49e95	8282	/* Bit definition for Ethernet DMA Interrupt Enable Register */
phungductung	0:e87aa4c49e95	8283	#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
phungductung	0:e87aa4c49e95	8284	#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
phungductung	0:e87aa4c49e95	8285	#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
phungductung	0:e87aa4c49e95	8286	#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
phungductung	0:e87aa4c49e95	8287	#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
phungductung	0:e87aa4c49e95	8288	#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
phungductung	0:e87aa4c49e95	8289	#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
phungductung	0:e87aa4c49e95	8290	#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
phungductung	0:e87aa4c49e95	8291	#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
phungductung	0:e87aa4c49e95	8292	#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
phungductung	0:e87aa4c49e95	8293	#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
phungductung	0:e87aa4c49e95	8294	#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
phungductung	0:e87aa4c49e95	8295	#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
phungductung	0:e87aa4c49e95	8296	#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
phungductung	0:e87aa4c49e95	8297	#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
phungductung	0:e87aa4c49e95	8298
phungductung	0:e87aa4c49e95	8299	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
phungductung	0:e87aa4c49e95	8300	#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
phungductung	0:e87aa4c49e95	8301	#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
phungductung	0:e87aa4c49e95	8302	#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
phungductung	0:e87aa4c49e95	8303	#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
phungductung	0:e87aa4c49e95	8304
phungductung	0:e87aa4c49e95	8305	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
phungductung	0:e87aa4c49e95	8306	#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
phungductung	0:e87aa4c49e95	8307
phungductung	0:e87aa4c49e95	8308	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
phungductung	0:e87aa4c49e95	8309	#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
phungductung	0:e87aa4c49e95	8310
phungductung	0:e87aa4c49e95	8311	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
phungductung	0:e87aa4c49e95	8312	#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
phungductung	0:e87aa4c49e95	8313
phungductung	0:e87aa4c49e95	8314	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
phungductung	0:e87aa4c49e95	8315	#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
phungductung	0:e87aa4c49e95	8316
phungductung	0:e87aa4c49e95	8317	/******************************************************************************/
phungductung	0:e87aa4c49e95	8318	/* */
phungductung	0:e87aa4c49e95	8319	/* USB_OTG */
phungductung	0:e87aa4c49e95	8320	/* */
phungductung	0:e87aa4c49e95	8321	/******************************************************************************/
phungductung	0:e87aa4c49e95	8322	/****************** Bit definition for USB_OTG_GOTGCTL register ******************/
phungductung	0:e87aa4c49e95	8323	#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /!< Session request success /
phungductung	0:e87aa4c49e95	8324	#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /!< Session request /
phungductung	0:e87aa4c49e95	8325	#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /!< VBUS valid override enable /
phungductung	0:e87aa4c49e95	8326	#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /!< VBUS valid override value /
phungductung	0:e87aa4c49e95	8327	#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /!< A-peripheral session valid override enable /
phungductung	0:e87aa4c49e95	8328	#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /!< A-peripheral session valid override value /
phungductung	0:e87aa4c49e95	8329	#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /!< B-peripheral session valid override enable /
phungductung	0:e87aa4c49e95	8330	#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /!< B-peripheral session valid override value /
phungductung	0:e87aa4c49e95	8331	#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /!< Host set HNP enable /
phungductung	0:e87aa4c49e95	8332	#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /!< HNP request /
phungductung	0:e87aa4c49e95	8333	#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /!< Host set HNP enable /
phungductung	0:e87aa4c49e95	8334	#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /!< Device HNP enabled /
phungductung	0:e87aa4c49e95	8335	#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /!< Embedded host enable /
phungductung	0:e87aa4c49e95	8336	#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /!< Connector ID status /
phungductung	0:e87aa4c49e95	8337	#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /!< Long/short debounce time /
phungductung	0:e87aa4c49e95	8338	#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /!< A-session valid /
phungductung	0:e87aa4c49e95	8339	#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /!< B-session valid /
phungductung	0:e87aa4c49e95	8340	#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /!< OTG version /
phungductung	0:e87aa4c49e95	8341
phungductung	0:e87aa4c49e95	8342	/****************** Bit definition for USB_OTG_HCFG register ******************/
phungductung	0:e87aa4c49e95	8343	#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /!< FS/LS PHY clock select /
phungductung	0:e87aa4c49e95	8344	#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8345	#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8346	#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /!< FS- and LS-only support /
phungductung	0:e87aa4c49e95	8347
phungductung	0:e87aa4c49e95	8348	/****************** Bit definition for USB_OTG_DCFG register ******************/
phungductung	0:e87aa4c49e95	8349	#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /!< Device speed /
phungductung	0:e87aa4c49e95	8350	#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8351	#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8352	#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /!< Nonzero-length status OUT handshake /
phungductung	0:e87aa4c49e95	8353
phungductung	0:e87aa4c49e95	8354	#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /!< Device address /
phungductung	0:e87aa4c49e95	8355	#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8356	#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8357	#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8358	#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8359	#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8360	#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8361	#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8362
phungductung	0:e87aa4c49e95	8363	#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /!< Periodic (micro)frame interval /
phungductung	0:e87aa4c49e95	8364	#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8365	#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8366
phungductung	0:e87aa4c49e95	8367	#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /!< Periodic scheduling interval /
phungductung	0:e87aa4c49e95	8368	#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8369	#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8370
phungductung	0:e87aa4c49e95	8371	/****************** Bit definition for USB_OTG_PCGCR register ******************/
phungductung	0:e87aa4c49e95	8372	#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /!< Stop PHY clock /
phungductung	0:e87aa4c49e95	8373	#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /!< Gate HCLK /
phungductung	0:e87aa4c49e95	8374	#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /!< PHY suspended /
phungductung	0:e87aa4c49e95	8375
phungductung	0:e87aa4c49e95	8376	/****************** Bit definition for USB_OTG_GOTGINT register ******************/
phungductung	0:e87aa4c49e95	8377	#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /!< Session end detected /
phungductung	0:e87aa4c49e95	8378	#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /!< Session request success status change /
phungductung	0:e87aa4c49e95	8379	#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /!< Host negotiation success status change /
phungductung	0:e87aa4c49e95	8380	#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /!< Host negotiation detected /
phungductung	0:e87aa4c49e95	8381	#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /!< A-device timeout change /
phungductung	0:e87aa4c49e95	8382	#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /!< Debounce done /
phungductung	0:e87aa4c49e95	8383	#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /!< Change in ID pin input value /
phungductung	0:e87aa4c49e95	8384
phungductung	0:e87aa4c49e95	8385	/****************** Bit definition for USB_OTG_DCTL register ******************/
phungductung	0:e87aa4c49e95	8386	#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /!< Remote wakeup signaling /
phungductung	0:e87aa4c49e95	8387	#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /!< Soft disconnect /
phungductung	0:e87aa4c49e95	8388	#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /!< Global IN NAK status /
phungductung	0:e87aa4c49e95	8389	#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /!< Global OUT NAK status /
phungductung	0:e87aa4c49e95	8390
phungductung	0:e87aa4c49e95	8391	#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /!< Test control /
phungductung	0:e87aa4c49e95	8392	#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8393	#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8394	#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8395	#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /!< Set global IN NAK /
phungductung	0:e87aa4c49e95	8396	#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /!< Clear global IN NAK /
phungductung	0:e87aa4c49e95	8397	#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /!< Set global OUT NAK /
phungductung	0:e87aa4c49e95	8398	#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /!< Clear global OUT NAK /
phungductung	0:e87aa4c49e95	8399	#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /!< Power-on programming done /
phungductung	0:e87aa4c49e95	8400
phungductung	0:e87aa4c49e95	8401	/****************** Bit definition for USB_OTG_HFIR register ******************/
phungductung	0:e87aa4c49e95	8402	#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /!< Frame interval /
phungductung	0:e87aa4c49e95	8403
phungductung	0:e87aa4c49e95	8404	/****************** Bit definition for USB_OTG_HFNUM register ******************/
phungductung	0:e87aa4c49e95	8405	#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /!< Frame number /
phungductung	0:e87aa4c49e95	8406	#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /!< Frame time remaining /
phungductung	0:e87aa4c49e95	8407
phungductung	0:e87aa4c49e95	8408	/****************** Bit definition for USB_OTG_DSTS register ******************/
phungductung	0:e87aa4c49e95	8409	#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /!< Suspend status /
phungductung	0:e87aa4c49e95	8410
phungductung	0:e87aa4c49e95	8411	#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /!< Enumerated speed /
phungductung	0:e87aa4c49e95	8412	#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8413	#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8414	#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /!< Erratic error /
phungductung	0:e87aa4c49e95	8415	#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /!< Frame number of the received SOF /
phungductung	0:e87aa4c49e95	8416
phungductung	0:e87aa4c49e95	8417	/****************** Bit definition for USB_OTG_GAHBCFG register ******************/
phungductung	0:e87aa4c49e95	8418	#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /!< Global interrupt mask /
phungductung	0:e87aa4c49e95	8419	#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /!< Burst length/type /
phungductung	0:e87aa4c49e95	8420	#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8421	#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8422	#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8423	#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8424	#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /!< DMA enable /
phungductung	0:e87aa4c49e95	8425	#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /!< TxFIFO empty level /
phungductung	0:e87aa4c49e95	8426	#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /!< Periodic TxFIFO empty level /
phungductung	0:e87aa4c49e95	8427
phungductung	0:e87aa4c49e95	8428	/****************** Bit definition for USB_OTG_GUSBCFG register ******************/
phungductung	0:e87aa4c49e95	8429	#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /!< FS timeout calibration /
phungductung	0:e87aa4c49e95	8430	#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8431	#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8432	#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8433	#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
phungductung	0:e87aa4c49e95	8434	#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /!< SRP-capable /
phungductung	0:e87aa4c49e95	8435	#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /!< HNP-capable /
phungductung	0:e87aa4c49e95	8436	#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /!< USB turnaround time /
phungductung	0:e87aa4c49e95	8437	#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8438	#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8439	#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8440	#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8441	#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /!< PHY Low-power clock select /
phungductung	0:e87aa4c49e95	8442	#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /!< ULPI FS/LS select /
phungductung	0:e87aa4c49e95	8443	#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /!< ULPI Auto-resume /
phungductung	0:e87aa4c49e95	8444	#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /!< ULPI Clock SuspendM /
phungductung	0:e87aa4c49e95	8445	#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /!< ULPI External VBUS Drive /
phungductung	0:e87aa4c49e95	8446	#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /!< ULPI external VBUS indicator /
phungductung	0:e87aa4c49e95	8447	#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /!< TermSel DLine pulsing selection /
phungductung	0:e87aa4c49e95	8448	#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /!< Indicator complement /
phungductung	0:e87aa4c49e95	8449	#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /!< Indicator pass through /
phungductung	0:e87aa4c49e95	8450	#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /!< ULPI interface protect disable /
phungductung	0:e87aa4c49e95	8451	#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /!< Forced host mode /
phungductung	0:e87aa4c49e95	8452	#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /!< Forced peripheral mode /
phungductung	0:e87aa4c49e95	8453	#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /!< Corrupt Tx packet /
phungductung	0:e87aa4c49e95	8454
phungductung	0:e87aa4c49e95	8455	/****************** Bit definition for USB_OTG_GRSTCTL register ******************/
phungductung	0:e87aa4c49e95	8456	#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /!< Core soft reset /
phungductung	0:e87aa4c49e95	8457	#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /!< HCLK soft reset /
phungductung	0:e87aa4c49e95	8458	#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /!< Host frame counter reset /
phungductung	0:e87aa4c49e95	8459	#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /!< RxFIFO flush /
phungductung	0:e87aa4c49e95	8460	#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /!< TxFIFO flush /
phungductung	0:e87aa4c49e95	8461	#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /!< TxFIFO number /
phungductung	0:e87aa4c49e95	8462	#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8463	#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8464	#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8465	#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8466	#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8467	#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /!< DMA request signal /
phungductung	0:e87aa4c49e95	8468	#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /!< AHB master idle /
phungductung	0:e87aa4c49e95	8469
phungductung	0:e87aa4c49e95	8470	/****************** Bit definition for USB_OTG_DIEPMSK register ******************/
phungductung	0:e87aa4c49e95	8471	#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
phungductung	0:e87aa4c49e95	8472	#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
phungductung	0:e87aa4c49e95	8473	#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
phungductung	0:e87aa4c49e95	8474	#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
phungductung	0:e87aa4c49e95	8475	#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
phungductung	0:e87aa4c49e95	8476	#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
phungductung	0:e87aa4c49e95	8477	#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
phungductung	0:e87aa4c49e95	8478	#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
phungductung	0:e87aa4c49e95	8479
phungductung	0:e87aa4c49e95	8480	/****************** Bit definition for USB_OTG_HPTXSTS register ******************/
phungductung	0:e87aa4c49e95	8481	#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /!< Periodic transmit data FIFO space available /
phungductung	0:e87aa4c49e95	8482	#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /!< Periodic transmit request queue space available /
phungductung	0:e87aa4c49e95	8483	#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8484	#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8485	#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8486	#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8487	#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8488	#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8489	#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8490	#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	8491
phungductung	0:e87aa4c49e95	8492	#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /!< Top of the periodic transmit request queue /
phungductung	0:e87aa4c49e95	8493	#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8494	#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8495	#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8496	#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8497	#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8498	#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8499	#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8500	#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	8501
phungductung	0:e87aa4c49e95	8502	/****************** Bit definition for USB_OTG_HAINT register ******************/
phungductung	0:e87aa4c49e95	8503	#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /!< Channel interrupts /
phungductung	0:e87aa4c49e95	8504
phungductung	0:e87aa4c49e95	8505	/****************** Bit definition for USB_OTG_DOEPMSK register ******************/
phungductung	0:e87aa4c49e95	8506	#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
phungductung	0:e87aa4c49e95	8507	#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
phungductung	0:e87aa4c49e95	8508	#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /!< SETUP phase done mask /
phungductung	0:e87aa4c49e95	8509	#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled mask /
phungductung	0:e87aa4c49e95	8510	#define USB_OTG_DOEPMSK_OTEPSPRM ((uint32_t)0x00000020) /!< Status Phase Received mask /
phungductung	0:e87aa4c49e95	8511	#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received mask /
phungductung	0:e87aa4c49e95	8512	#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /!< OUT packet error mask /
phungductung	0:e87aa4c49e95	8513	#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
phungductung	0:e87aa4c49e95	8514
phungductung	0:e87aa4c49e95	8515	/****************** Bit definition for USB_OTG_GINTSTS register ******************/
phungductung	0:e87aa4c49e95	8516	#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /!< Current mode of operation /
phungductung	0:e87aa4c49e95	8517	#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /!< Mode mismatch interrupt /
phungductung	0:e87aa4c49e95	8518	#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt /
phungductung	0:e87aa4c49e95	8519	#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /!< Start of frame /
phungductung	0:e87aa4c49e95	8520	#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /!< RxFIFO nonempty /
phungductung	0:e87aa4c49e95	8521	#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty /
phungductung	0:e87aa4c49e95	8522	#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /!< Global IN nonperiodic NAK effective /
phungductung	0:e87aa4c49e95	8523	#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /!< Global OUT NAK effective /
phungductung	0:e87aa4c49e95	8524	#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /!< Early suspend /
phungductung	0:e87aa4c49e95	8525	#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /!< USB suspend /
phungductung	0:e87aa4c49e95	8526	#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /!< USB reset /
phungductung	0:e87aa4c49e95	8527	#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /!< Enumeration done /
phungductung	0:e87aa4c49e95	8528	#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt /
phungductung	0:e87aa4c49e95	8529	#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /!< End of periodic frame interrupt /
phungductung	0:e87aa4c49e95	8530	#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /!< IN endpoint interrupt /
phungductung	0:e87aa4c49e95	8531	#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /!< OUT endpoint interrupt /
phungductung	0:e87aa4c49e95	8532	#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer /
phungductung	0:e87aa4c49e95	8533	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /!< Incomplete periodic transfer /
phungductung	0:e87aa4c49e95	8534	#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /!< Data fetch suspended /
phungductung	0:e87aa4c49e95	8535	#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /!< Reset detected interrupt /
phungductung	0:e87aa4c49e95	8536	#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /!< Host port interrupt /
phungductung	0:e87aa4c49e95	8537	#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /!< Host channels interrupt /
phungductung	0:e87aa4c49e95	8538	#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /!< Periodic TxFIFO empty /
phungductung	0:e87aa4c49e95	8539	#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /!< LPM interrupt /
phungductung	0:e87aa4c49e95	8540	#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /!< Connector ID status change /
phungductung	0:e87aa4c49e95	8541	#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt /
phungductung	0:e87aa4c49e95	8542	#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /!< Session request/new session detected interrupt /
phungductung	0:e87aa4c49e95	8543	#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt /
phungductung	0:e87aa4c49e95	8544
phungductung	0:e87aa4c49e95	8545	/****************** Bit definition for USB_OTG_GINTMSK register ******************/
phungductung	0:e87aa4c49e95	8546	#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /!< Mode mismatch interrupt mask /
phungductung	0:e87aa4c49e95	8547	#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt mask /
phungductung	0:e87aa4c49e95	8548	#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /!< Start of frame mask /
phungductung	0:e87aa4c49e95	8549	#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /!< Receive FIFO nonempty mask /
phungductung	0:e87aa4c49e95	8550	#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty mask /
phungductung	0:e87aa4c49e95	8551	#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /!< Global nonperiodic IN NAK effective mask /
phungductung	0:e87aa4c49e95	8552	#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /!< Global OUT NAK effective mask /
phungductung	0:e87aa4c49e95	8553	#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /!< Early suspend mask /
phungductung	0:e87aa4c49e95	8554	#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /!< USB suspend mask /
phungductung	0:e87aa4c49e95	8555	#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /!< USB reset mask /
phungductung	0:e87aa4c49e95	8556	#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /!< Enumeration done mask /
phungductung	0:e87aa4c49e95	8557	#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt mask /
phungductung	0:e87aa4c49e95	8558	#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /!< End of periodic frame interrupt mask /
phungductung	0:e87aa4c49e95	8559	#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /!< Endpoint mismatch interrupt mask /
phungductung	0:e87aa4c49e95	8560	#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /!< IN endpoints interrupt mask /
phungductung	0:e87aa4c49e95	8561	#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /!< OUT endpoints interrupt mask /
phungductung	0:e87aa4c49e95	8562	#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer mask /
phungductung	0:e87aa4c49e95	8563	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /!< Incomplete periodic transfer mask /
phungductung	0:e87aa4c49e95	8564	#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /!< Data fetch suspended mask /
phungductung	0:e87aa4c49e95	8565	#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /!< Reset detected interrupt mask /
phungductung	0:e87aa4c49e95	8566	#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /!< Host port interrupt mask /
phungductung	0:e87aa4c49e95	8567	#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /!< Host channels interrupt mask /
phungductung	0:e87aa4c49e95	8568	#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /!< Periodic TxFIFO empty mask /
phungductung	0:e87aa4c49e95	8569	#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /!< LPM interrupt Mask /
phungductung	0:e87aa4c49e95	8570	#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /!< Connector ID status change mask /
phungductung	0:e87aa4c49e95	8571	#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt mask /
phungductung	0:e87aa4c49e95	8572	#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /!< Session request/new session detected interrupt mask /
phungductung	0:e87aa4c49e95	8573	#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt mask /
phungductung	0:e87aa4c49e95	8574
phungductung	0:e87aa4c49e95	8575	/****************** Bit definition for USB_OTG_DAINT register ******************/
phungductung	0:e87aa4c49e95	8576	#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /!< IN endpoint interrupt bits /
phungductung	0:e87aa4c49e95	8577	#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /!< OUT endpoint interrupt bits /
phungductung	0:e87aa4c49e95	8578
phungductung	0:e87aa4c49e95	8579	/****************** Bit definition for USB_OTG_HAINTMSK register ******************/
phungductung	0:e87aa4c49e95	8580	#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /!< Channel interrupt mask /
phungductung	0:e87aa4c49e95	8581
phungductung	0:e87aa4c49e95	8582	/****************** Bit definition for USB_OTG_GRXSTSP register ******************/
phungductung	0:e87aa4c49e95	8583	#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /!< IN EP interrupt mask bits /
phungductung	0:e87aa4c49e95	8584	#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /!< OUT EP interrupt mask bits /
phungductung	0:e87aa4c49e95	8585	#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /!< OUT EP interrupt mask bits /
phungductung	0:e87aa4c49e95	8586	#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /!< OUT EP interrupt mask bits /
phungductung	0:e87aa4c49e95	8587
phungductung	0:e87aa4c49e95	8588	/****************** Bit definition for USB_OTG_DAINTMSK register ******************/
phungductung	0:e87aa4c49e95	8589	#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /!< IN EP interrupt mask bits /
phungductung	0:e87aa4c49e95	8590	#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /!< OUT EP interrupt mask bits /
phungductung	0:e87aa4c49e95	8591
phungductung	0:e87aa4c49e95	8592	/****************** Bit definition for OTG register ******************/
phungductung	0:e87aa4c49e95	8593
phungductung	0:e87aa4c49e95	8594	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
phungductung	0:e87aa4c49e95	8595	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8596	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8597	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8598	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8599	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
phungductung	0:e87aa4c49e95	8600
phungductung	0:e87aa4c49e95	8601	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
phungductung	0:e87aa4c49e95	8602	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8603	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8604
phungductung	0:e87aa4c49e95	8605	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
phungductung	0:e87aa4c49e95	8606	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8607	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8608	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8609	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8610
phungductung	0:e87aa4c49e95	8611	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
phungductung	0:e87aa4c49e95	8612	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8613	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8614	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8615	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8616
phungductung	0:e87aa4c49e95	8617	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
phungductung	0:e87aa4c49e95	8618	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8619	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8620	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8621	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8622
phungductung	0:e87aa4c49e95	8623	/****************** Bit definition for OTG register ******************/
phungductung	0:e87aa4c49e95	8624
phungductung	0:e87aa4c49e95	8625	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
phungductung	0:e87aa4c49e95	8626	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8627	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8628	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8629	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8630	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
phungductung	0:e87aa4c49e95	8631
phungductung	0:e87aa4c49e95	8632	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
phungductung	0:e87aa4c49e95	8633	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8634	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8635
phungductung	0:e87aa4c49e95	8636	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
phungductung	0:e87aa4c49e95	8637	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8638	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8639	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8640	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8641
phungductung	0:e87aa4c49e95	8642	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
phungductung	0:e87aa4c49e95	8643	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8644	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8645	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8646	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8647
phungductung	0:e87aa4c49e95	8648	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
phungductung	0:e87aa4c49e95	8649	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8650	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8651	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8652	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8653
phungductung	0:e87aa4c49e95	8654	/****************** Bit definition for USB_OTG_GRXFSIZ register ******************/
phungductung	0:e87aa4c49e95	8655	#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /!< RxFIFO depth /
phungductung	0:e87aa4c49e95	8656
phungductung	0:e87aa4c49e95	8657	/****************** Bit definition for USB_OTG_DVBUSDIS register ******************/
phungductung	0:e87aa4c49e95	8658	#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /!< Device VBUS discharge time /
phungductung	0:e87aa4c49e95	8659
phungductung	0:e87aa4c49e95	8660	/****************** Bit definition for OTG register ******************/
phungductung	0:e87aa4c49e95	8661	#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /!< Nonperiodic transmit RAM start address /
phungductung	0:e87aa4c49e95	8662	#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /!< Nonperiodic TxFIFO depth /
phungductung	0:e87aa4c49e95	8663	#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /!< Endpoint 0 transmit RAM start address /
phungductung	0:e87aa4c49e95	8664	#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /!< Endpoint 0 TxFIFO depth /
phungductung	0:e87aa4c49e95	8665
phungductung	0:e87aa4c49e95	8666	/****************** Bit definition for USB_OTG_DVBUSPULSE register ******************/
phungductung	0:e87aa4c49e95	8667	#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /!< Device VBUS pulsing time /
phungductung	0:e87aa4c49e95	8668
phungductung	0:e87aa4c49e95	8669	/****************** Bit definition for USB_OTG_GNPTXSTS register ******************/
phungductung	0:e87aa4c49e95	8670	#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /!< Nonperiodic TxFIFO space available /
phungductung	0:e87aa4c49e95	8671
phungductung	0:e87aa4c49e95	8672	#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /!< Nonperiodic transmit request queue space available /
phungductung	0:e87aa4c49e95	8673	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8674	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8675	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8676	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8677	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8678	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8679	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8680	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	8681
phungductung	0:e87aa4c49e95	8682	#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /!< Top of the nonperiodic transmit request queue /
phungductung	0:e87aa4c49e95	8683	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8684	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8685	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8686	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8687	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8688	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8689	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8690
phungductung	0:e87aa4c49e95	8691	/****************** Bit definition for USB_OTG_DTHRCTL register ******************/
phungductung	0:e87aa4c49e95	8692	#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /!< Nonisochronous IN endpoints threshold enable /
phungductung	0:e87aa4c49e95	8693	#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /!< ISO IN endpoint threshold enable /
phungductung	0:e87aa4c49e95	8694
phungductung	0:e87aa4c49e95	8695	#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /!< Transmit threshold length /
phungductung	0:e87aa4c49e95	8696	#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8697	#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8698	#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8699	#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8700	#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8701	#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8702	#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8703	#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /!<Bit 7 /
phungductung	0:e87aa4c49e95	8704	#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /!<Bit 8 /
phungductung	0:e87aa4c49e95	8705	#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /!< Receive threshold enable /
phungductung	0:e87aa4c49e95	8706
phungductung	0:e87aa4c49e95	8707	#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /!< Receive threshold length /
phungductung	0:e87aa4c49e95	8708	#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8709	#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8710	#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8711	#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8712	#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8713	#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8714	#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8715	#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /!<Bit 7 /
phungductung	0:e87aa4c49e95	8716	#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /!<Bit 8 /
phungductung	0:e87aa4c49e95	8717	#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /!< Arbiter parking enable /
phungductung	0:e87aa4c49e95	8718
phungductung	0:e87aa4c49e95	8719	/****************** Bit definition for USB_OTG_DIEPEMPMSK register ******************/
phungductung	0:e87aa4c49e95	8720	#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /!< IN EP Tx FIFO empty interrupt mask bits /
phungductung	0:e87aa4c49e95	8721
phungductung	0:e87aa4c49e95	8722	/****************** Bit definition for USB_OTG_DEACHINT register ******************/
phungductung	0:e87aa4c49e95	8723	#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /!< IN endpoint 1interrupt bit /
phungductung	0:e87aa4c49e95	8724	#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /!< OUT endpoint 1 interrupt bit /
phungductung	0:e87aa4c49e95	8725
phungductung	0:e87aa4c49e95	8726	/****************** Bit definition for USB_OTG_GCCFG register ******************/
phungductung	0:e87aa4c49e95	8727	#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /!< Power down /
phungductung	0:e87aa4c49e95	8728	#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /!< USB VBUS Detection Enable /
phungductung	0:e87aa4c49e95	8729
phungductung	0:e87aa4c49e95	8730	/****************** Bit definition for USB_OTG_GPWRDN) register ******************/
phungductung	0:e87aa4c49e95	8731	#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /!< ADP module enable /
phungductung	0:e87aa4c49e95	8732	#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /!< ADP Interrupt flag /
phungductung	0:e87aa4c49e95	8733
phungductung	0:e87aa4c49e95	8734	/****************** Bit definition for USB_OTG_DEACHINTMSK register ******************/
phungductung	0:e87aa4c49e95	8735	#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /!< IN Endpoint 1 interrupt mask bit /
phungductung	0:e87aa4c49e95	8736	#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /!< OUT Endpoint 1 interrupt mask bit /
phungductung	0:e87aa4c49e95	8737
phungductung	0:e87aa4c49e95	8738	/****************** Bit definition for USB_OTG_CID register ******************/
phungductung	0:e87aa4c49e95	8739	#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /!< Product ID field /
phungductung	0:e87aa4c49e95	8740
phungductung	0:e87aa4c49e95	8741	/****************** Bit definition for USB_OTG_GLPMCFG register ******************/
phungductung	0:e87aa4c49e95	8742	#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /!< LPM support enable /
phungductung	0:e87aa4c49e95	8743	#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /!< LPM Token acknowledge enable /
phungductung	0:e87aa4c49e95	8744	#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /!< BESL value received with last ACKed LPM Token /
phungductung	0:e87aa4c49e95	8745	#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /!< bRemoteWake value received with last ACKed LPM Token /
phungductung	0:e87aa4c49e95	8746	#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /!< L1 shallow sleep enable /
phungductung	0:e87aa4c49e95	8747	#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /!< BESL threshold /
phungductung	0:e87aa4c49e95	8748	#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /!< L1 deep sleep enable /
phungductung	0:e87aa4c49e95	8749	#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /!< LPM response /
phungductung	0:e87aa4c49e95	8750	#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /!< Port sleep status /
phungductung	0:e87aa4c49e95	8751	#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /!< Sleep State Resume OK /
phungductung	0:e87aa4c49e95	8752	#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /!< LPM Channel Index /
phungductung	0:e87aa4c49e95	8753	#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /!< LPM retry count /
phungductung	0:e87aa4c49e95	8754	#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /!< Send LPM transaction /
phungductung	0:e87aa4c49e95	8755	#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /!< LPM retry count status /
phungductung	0:e87aa4c49e95	8756	#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /!< Enable best effort service latency /
phungductung	0:e87aa4c49e95	8757
phungductung	0:e87aa4c49e95	8758	/****************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******************/
phungductung	0:e87aa4c49e95	8759	#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
phungductung	0:e87aa4c49e95	8760	#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
phungductung	0:e87aa4c49e95	8761	#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
phungductung	0:e87aa4c49e95	8762	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
phungductung	0:e87aa4c49e95	8763	#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
phungductung	0:e87aa4c49e95	8764	#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
phungductung	0:e87aa4c49e95	8765	#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
phungductung	0:e87aa4c49e95	8766	#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
phungductung	0:e87aa4c49e95	8767	#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
phungductung	0:e87aa4c49e95	8768
phungductung	0:e87aa4c49e95	8769	/****************** Bit definition for USB_OTG_HPRT register ******************/
phungductung	0:e87aa4c49e95	8770	#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /!< Port connect status /
phungductung	0:e87aa4c49e95	8771	#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /!< Port connect detected /
phungductung	0:e87aa4c49e95	8772	#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /!< Port enable /
phungductung	0:e87aa4c49e95	8773	#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /!< Port enable/disable change /
phungductung	0:e87aa4c49e95	8774	#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /!< Port overcurrent active /
phungductung	0:e87aa4c49e95	8775	#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /!< Port overcurrent change /
phungductung	0:e87aa4c49e95	8776	#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /!< Port resume /
phungductung	0:e87aa4c49e95	8777	#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /!< Port suspend /
phungductung	0:e87aa4c49e95	8778	#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /!< Port reset /
phungductung	0:e87aa4c49e95	8779
phungductung	0:e87aa4c49e95	8780	#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /!< Port line status /
phungductung	0:e87aa4c49e95	8781	#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8782	#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8783	#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /!< Port power /
phungductung	0:e87aa4c49e95	8784
phungductung	0:e87aa4c49e95	8785	#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /!< Port test control /
phungductung	0:e87aa4c49e95	8786	#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8787	#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8788	#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8789	#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8790
phungductung	0:e87aa4c49e95	8791	#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /!< Port speed /
phungductung	0:e87aa4c49e95	8792	#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8793	#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8794
phungductung	0:e87aa4c49e95	8795	/****************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******************/
phungductung	0:e87aa4c49e95	8796	#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
phungductung	0:e87aa4c49e95	8797	#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
phungductung	0:e87aa4c49e95	8798	#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask /
phungductung	0:e87aa4c49e95	8799	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
phungductung	0:e87aa4c49e95	8800	#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
phungductung	0:e87aa4c49e95	8801	#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
phungductung	0:e87aa4c49e95	8802	#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< OUT packet error mask /
phungductung	0:e87aa4c49e95	8803	#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
phungductung	0:e87aa4c49e95	8804	#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /!< Bubble error interrupt mask /
phungductung	0:e87aa4c49e95	8805	#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
phungductung	0:e87aa4c49e95	8806	#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /!< NYET interrupt mask /
phungductung	0:e87aa4c49e95	8807
phungductung	0:e87aa4c49e95	8808	/****************** Bit definition for USB_OTG_HPTXFSIZ register ******************/
phungductung	0:e87aa4c49e95	8809	#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /!< Host periodic TxFIFO start address /
phungductung	0:e87aa4c49e95	8810	#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /!< Host periodic TxFIFO depth /
phungductung	0:e87aa4c49e95	8811
phungductung	0:e87aa4c49e95	8812	/****************** Bit definition for USB_OTG_DIEPCTL register ******************/
phungductung	0:e87aa4c49e95	8813	#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
phungductung	0:e87aa4c49e95	8814	#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
phungductung	0:e87aa4c49e95	8815	#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /!< Even/odd frame /
phungductung	0:e87aa4c49e95	8816	#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
phungductung	0:e87aa4c49e95	8817
phungductung	0:e87aa4c49e95	8818	#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
phungductung	0:e87aa4c49e95	8819	#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8820	#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8821	#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
phungductung	0:e87aa4c49e95	8822
phungductung	0:e87aa4c49e95	8823	#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /!< TxFIFO number /
phungductung	0:e87aa4c49e95	8824	#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8825	#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8826	#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8827	#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8828	#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
phungductung	0:e87aa4c49e95	8829	#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
phungductung	0:e87aa4c49e95	8830	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
phungductung	0:e87aa4c49e95	8831	#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
phungductung	0:e87aa4c49e95	8832	#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
phungductung	0:e87aa4c49e95	8833	#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
phungductung	0:e87aa4c49e95	8834
phungductung	0:e87aa4c49e95	8835	/****************** Bit definition for USB_OTG_HCCHAR register ******************/
phungductung	0:e87aa4c49e95	8836	#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
phungductung	0:e87aa4c49e95	8837
phungductung	0:e87aa4c49e95	8838	#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /!< Endpoint number /
phungductung	0:e87aa4c49e95	8839	#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8840	#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8841	#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8842	#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8843	#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /!< Endpoint direction /
phungductung	0:e87aa4c49e95	8844	#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /!< Low-speed device /
phungductung	0:e87aa4c49e95	8845
phungductung	0:e87aa4c49e95	8846	#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
phungductung	0:e87aa4c49e95	8847	#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8848	#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8849
phungductung	0:e87aa4c49e95	8850	#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /!< Multi Count (MC) / Error Count (EC) /
phungductung	0:e87aa4c49e95	8851	#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8852	#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8853
phungductung	0:e87aa4c49e95	8854	#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /!< Device address /
phungductung	0:e87aa4c49e95	8855	#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8856	#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8857	#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8858	#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8859	#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8860	#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8861	#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8862	#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /!< Odd frame /
phungductung	0:e87aa4c49e95	8863	#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /!< Channel disable /
phungductung	0:e87aa4c49e95	8864	#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /!< Channel enable /
phungductung	0:e87aa4c49e95	8865
phungductung	0:e87aa4c49e95	8866	/****************** Bit definition for USB_OTG_HCSPLT register ******************/
phungductung	0:e87aa4c49e95	8867
phungductung	0:e87aa4c49e95	8868	#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /!< Port address /
phungductung	0:e87aa4c49e95	8869	#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8870	#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8871	#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8872	#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8873	#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8874	#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8875	#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8876
phungductung	0:e87aa4c49e95	8877	#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /!< Hub address /
phungductung	0:e87aa4c49e95	8878	#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8879	#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8880	#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /!<Bit 2 /
phungductung	0:e87aa4c49e95	8881	#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /!<Bit 3 /
phungductung	0:e87aa4c49e95	8882	#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /!<Bit 4 /
phungductung	0:e87aa4c49e95	8883	#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /!<Bit 5 /
phungductung	0:e87aa4c49e95	8884	#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /!<Bit 6 /
phungductung	0:e87aa4c49e95	8885
phungductung	0:e87aa4c49e95	8886	#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /!< XACTPOS /
phungductung	0:e87aa4c49e95	8887	#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8888	#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8889	#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /!< Do complete split /
phungductung	0:e87aa4c49e95	8890	#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /!< Split enable /
phungductung	0:e87aa4c49e95	8891
phungductung	0:e87aa4c49e95	8892	/****************** Bit definition for USB_OTG_HCINT register ******************/
phungductung	0:e87aa4c49e95	8893	#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed /
phungductung	0:e87aa4c49e95	8894	#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /!< Channel halted /
phungductung	0:e87aa4c49e95	8895	#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /!< AHB error /
phungductung	0:e87aa4c49e95	8896	#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /!< STALL response received interrupt /
phungductung	0:e87aa4c49e95	8897	#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /!< NAK response received interrupt /
phungductung	0:e87aa4c49e95	8898	#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt /
phungductung	0:e87aa4c49e95	8899	#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /!< Response received interrupt /
phungductung	0:e87aa4c49e95	8900	#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /!< Transaction error /
phungductung	0:e87aa4c49e95	8901	#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /!< Babble error /
phungductung	0:e87aa4c49e95	8902	#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /!< Frame overrun /
phungductung	0:e87aa4c49e95	8903	#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /!< Data toggle error /
phungductung	0:e87aa4c49e95	8904
phungductung	0:e87aa4c49e95	8905	/****************** Bit definition for USB_OTG_DIEPINT register ******************/
phungductung	0:e87aa4c49e95	8906	#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
phungductung	0:e87aa4c49e95	8907	#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
phungductung	0:e87aa4c49e95	8908	#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /!< Timeout condition /
phungductung	0:e87aa4c49e95	8909	#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /!< IN token received when TxFIFO is empty /
phungductung	0:e87aa4c49e95	8910	#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /!< IN endpoint NAK effective /
phungductung	0:e87aa4c49e95	8911	#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /!< Transmit FIFO empty /
phungductung	0:e87aa4c49e95	8912	#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /!< Transmit Fifo Underrun /
phungductung	0:e87aa4c49e95	8913	#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /!< Buffer not available interrupt /
phungductung	0:e87aa4c49e95	8914	#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /!< Packet dropped status /
phungductung	0:e87aa4c49e95	8915	#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /!< Babble error interrupt /
phungductung	0:e87aa4c49e95	8916	#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /!< NAK interrupt /
phungductung	0:e87aa4c49e95	8917
phungductung	0:e87aa4c49e95	8918	/****************** Bit definition for USB_OTG_HCINTMSK register ******************/
phungductung	0:e87aa4c49e95	8919	#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed mask /
phungductung	0:e87aa4c49e95	8920	#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /!< Channel halted mask /
phungductung	0:e87aa4c49e95	8921	#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /!< AHB error /
phungductung	0:e87aa4c49e95	8922	#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /!< STALL response received interrupt mask /
phungductung	0:e87aa4c49e95	8923	#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /!< NAK response received interrupt mask /
phungductung	0:e87aa4c49e95	8924	#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt mask /
phungductung	0:e87aa4c49e95	8925	#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /!< response received interrupt mask /
phungductung	0:e87aa4c49e95	8926	#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /!< Transaction error mask /
phungductung	0:e87aa4c49e95	8927	#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /!< Babble error mask /
phungductung	0:e87aa4c49e95	8928	#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /!< Frame overrun mask /
phungductung	0:e87aa4c49e95	8929	#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /!< Data toggle error mask /
phungductung	0:e87aa4c49e95	8930
phungductung	0:e87aa4c49e95	8931	/****************** Bit definition for USB_OTG_DIEPTSIZ register ******************/
phungductung	0:e87aa4c49e95	8932
phungductung	0:e87aa4c49e95	8933	#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
phungductung	0:e87aa4c49e95	8934	#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
phungductung	0:e87aa4c49e95	8935	#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /!< Packet count /
phungductung	0:e87aa4c49e95	8936	/****************** Bit definition for USB_OTG_HCTSIZ register ******************/
phungductung	0:e87aa4c49e95	8937	#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
phungductung	0:e87aa4c49e95	8938	#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
phungductung	0:e87aa4c49e95	8939	#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /!< Do PING /
phungductung	0:e87aa4c49e95	8940	#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /!< Data PID /
phungductung	0:e87aa4c49e95	8941	#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8942	#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8943
phungductung	0:e87aa4c49e95	8944	/****************** Bit definition for USB_OTG_DIEPDMA register ******************/
phungductung	0:e87aa4c49e95	8945	#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
phungductung	0:e87aa4c49e95	8946
phungductung	0:e87aa4c49e95	8947	/****************** Bit definition for USB_OTG_HCDMA register ******************/
phungductung	0:e87aa4c49e95	8948	#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
phungductung	0:e87aa4c49e95	8949
phungductung	0:e87aa4c49e95	8950	/****************** Bit definition for USB_OTG_DTXFSTS register ******************/
phungductung	0:e87aa4c49e95	8951	#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /!< IN endpoint TxFIFO space available /
phungductung	0:e87aa4c49e95	8952
phungductung	0:e87aa4c49e95	8953	/****************** Bit definition for USB_OTG_DIEPTXF register ******************/
phungductung	0:e87aa4c49e95	8954	#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /!< IN endpoint FIFOx transmit RAM start address /
phungductung	0:e87aa4c49e95	8955	#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /!< IN endpoint TxFIFO depth /
phungductung	0:e87aa4c49e95	8956
phungductung	0:e87aa4c49e95	8957	/****************** Bit definition for USB_OTG_DOEPCTL register ******************/
phungductung	0:e87aa4c49e95	8958	#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size / /!<Bit 1 /
phungductung	0:e87aa4c49e95	8959	#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
phungductung	0:e87aa4c49e95	8960	#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
phungductung	0:e87aa4c49e95	8961	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
phungductung	0:e87aa4c49e95	8962	#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
phungductung	0:e87aa4c49e95	8963	#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
phungductung	0:e87aa4c49e95	8964	#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8965	#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8966	#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /!< Snoop mode /
phungductung	0:e87aa4c49e95	8967	#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
phungductung	0:e87aa4c49e95	8968	#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
phungductung	0:e87aa4c49e95	8969	#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
phungductung	0:e87aa4c49e95	8970	#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
phungductung	0:e87aa4c49e95	8971	#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
phungductung	0:e87aa4c49e95	8972
phungductung	0:e87aa4c49e95	8973	/****************** Bit definition for USB_OTG_DOEPINT register ******************/
phungductung	0:e87aa4c49e95	8974	#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
phungductung	0:e87aa4c49e95	8975	#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
phungductung	0:e87aa4c49e95	8976	#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /!< SETUP phase done /
phungductung	0:e87aa4c49e95	8977	#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled /
phungductung	0:e87aa4c49e95	8978	#define USB_OTG_DOEPINT_OTEPSPR ((uint32_t)0x00000020) /!< Status Phase Received For Control Write /
phungductung	0:e87aa4c49e95	8979	#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received /
phungductung	0:e87aa4c49e95	8980	#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /!< NYET interrupt /
phungductung	0:e87aa4c49e95	8981
phungductung	0:e87aa4c49e95	8982	/****************** Bit definition for USB_OTG_DOEPTSIZ register ******************/
phungductung	0:e87aa4c49e95	8983	#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
phungductung	0:e87aa4c49e95	8984	#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
phungductung	0:e87aa4c49e95	8985
phungductung	0:e87aa4c49e95	8986	#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /!< SETUP packet count /
phungductung	0:e87aa4c49e95	8987	#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8988	#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8989
phungductung	0:e87aa4c49e95	8990	/****************** Bit definition for PCGCCTL register ******************/
phungductung	0:e87aa4c49e95	8991	#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /!< SETUP packet count /
phungductung	0:e87aa4c49e95	8992	#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /!<Bit 0 /
phungductung	0:e87aa4c49e95	8993	#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /!<Bit 1 /
phungductung	0:e87aa4c49e95	8994
phungductung	0:e87aa4c49e95	8995	/**
phungductung	0:e87aa4c49e95	8996	* @}
phungductung	0:e87aa4c49e95	8997	*/
phungductung	0:e87aa4c49e95	8998
phungductung	0:e87aa4c49e95	8999	/**
phungductung	0:e87aa4c49e95	9000	* @}
phungductung	0:e87aa4c49e95	9001	*/
phungductung	0:e87aa4c49e95	9002
phungductung	0:e87aa4c49e95	9003	/** @addtogroup Exported_macros
phungductung	0:e87aa4c49e95	9004	* @{
phungductung	0:e87aa4c49e95	9005	*/
phungductung	0:e87aa4c49e95	9006
phungductung	0:e87aa4c49e95	9007	/***************************** ADC Instances ******************************/
phungductung	0:e87aa4c49e95	9008	#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \
phungductung	0:e87aa4c49e95	9009	((__INSTANCE__) == ADC2) \|\| \
phungductung	0:e87aa4c49e95	9010	((__INSTANCE__) == ADC3))
phungductung	0:e87aa4c49e95	9011
phungductung	0:e87aa4c49e95	9012	/***************************** CAN Instances ******************************/
phungductung	0:e87aa4c49e95	9013	#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) \|\| \
phungductung	0:e87aa4c49e95	9014	((__INSTANCE__) == CAN2))
phungductung	0:e87aa4c49e95	9015
phungductung	0:e87aa4c49e95	9016	/***************************** CRC Instances ******************************/
phungductung	0:e87aa4c49e95	9017	#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
phungductung	0:e87aa4c49e95	9018
phungductung	0:e87aa4c49e95	9019	/***************************** DAC Instances ******************************/
phungductung	0:e87aa4c49e95	9020	#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
phungductung	0:e87aa4c49e95	9021
phungductung	0:e87aa4c49e95	9022	/***************************** DCMI Instances *****************************/
phungductung	0:e87aa4c49e95	9023	#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
phungductung	0:e87aa4c49e95	9024
phungductung	0:e87aa4c49e95	9025
phungductung	0:e87aa4c49e95	9026	/***************************** DMA2D Instances *****************************/
phungductung	0:e87aa4c49e95	9027	#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
phungductung	0:e87aa4c49e95	9028
phungductung	0:e87aa4c49e95	9029	/****************************** DMA Instances *****************************/
phungductung	0:e87aa4c49e95	9030	#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \
phungductung	0:e87aa4c49e95	9031	((__INSTANCE__) == DMA1_Stream1) \|\| \
phungductung	0:e87aa4c49e95	9032	((__INSTANCE__) == DMA1_Stream2) \|\| \
phungductung	0:e87aa4c49e95	9033	((__INSTANCE__) == DMA1_Stream3) \|\| \
phungductung	0:e87aa4c49e95	9034	((__INSTANCE__) == DMA1_Stream4) \|\| \
phungductung	0:e87aa4c49e95	9035	((__INSTANCE__) == DMA1_Stream5) \|\| \
phungductung	0:e87aa4c49e95	9036	((__INSTANCE__) == DMA1_Stream6) \|\| \
phungductung	0:e87aa4c49e95	9037	((__INSTANCE__) == DMA1_Stream7) \|\| \
phungductung	0:e87aa4c49e95	9038	((__INSTANCE__) == DMA2_Stream0) \|\| \
phungductung	0:e87aa4c49e95	9039	((__INSTANCE__) == DMA2_Stream1) \|\| \
phungductung	0:e87aa4c49e95	9040	((__INSTANCE__) == DMA2_Stream2) \|\| \
phungductung	0:e87aa4c49e95	9041	((__INSTANCE__) == DMA2_Stream3) \|\| \
phungductung	0:e87aa4c49e95	9042	((__INSTANCE__) == DMA2_Stream4) \|\| \
phungductung	0:e87aa4c49e95	9043	((__INSTANCE__) == DMA2_Stream5) \|\| \
phungductung	0:e87aa4c49e95	9044	((__INSTANCE__) == DMA2_Stream6) \|\| \
phungductung	0:e87aa4c49e95	9045	((__INSTANCE__) == DMA2_Stream7))
phungductung	0:e87aa4c49e95	9046
phungductung	0:e87aa4c49e95	9047	/***************************** GPIO Instances *****************************/
phungductung	0:e87aa4c49e95	9048	#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) \|\| \
phungductung	0:e87aa4c49e95	9049	((__INSTANCE__) == GPIOB) \|\| \
phungductung	0:e87aa4c49e95	9050	((__INSTANCE__) == GPIOC) \|\| \
phungductung	0:e87aa4c49e95	9051	((__INSTANCE__) == GPIOD) \|\| \
phungductung	0:e87aa4c49e95	9052	((__INSTANCE__) == GPIOE) \|\| \
phungductung	0:e87aa4c49e95	9053	((__INSTANCE__) == GPIOF) \|\| \
phungductung	0:e87aa4c49e95	9054	((__INSTANCE__) == GPIOG) \|\| \
phungductung	0:e87aa4c49e95	9055	((__INSTANCE__) == GPIOH) \|\| \
phungductung	0:e87aa4c49e95	9056	((__INSTANCE__) == GPIOI) \|\| \
phungductung	0:e87aa4c49e95	9057	((__INSTANCE__) == GPIOJ) \|\| \
phungductung	0:e87aa4c49e95	9058	((__INSTANCE__) == GPIOK))
phungductung	0:e87aa4c49e95	9059
phungductung	0:e87aa4c49e95	9060	#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) \|\| \
phungductung	0:e87aa4c49e95	9061	((__INSTANCE__) == GPIOB) \|\| \
phungductung	0:e87aa4c49e95	9062	((__INSTANCE__) == GPIOC) \|\| \
phungductung	0:e87aa4c49e95	9063	((__INSTANCE__) == GPIOD) \|\| \
phungductung	0:e87aa4c49e95	9064	((__INSTANCE__) == GPIOE) \|\| \
phungductung	0:e87aa4c49e95	9065	((__INSTANCE__) == GPIOF) \|\| \
phungductung	0:e87aa4c49e95	9066	((__INSTANCE__) == GPIOG) \|\| \
phungductung	0:e87aa4c49e95	9067	((__INSTANCE__) == GPIOH) \|\| \
phungductung	0:e87aa4c49e95	9068	((__INSTANCE__) == GPIOI) \|\| \
phungductung	0:e87aa4c49e95	9069	((__INSTANCE__) == GPIOJ) \|\| \
phungductung	0:e87aa4c49e95	9070	((__INSTANCE__) == GPIOK))
phungductung	0:e87aa4c49e95	9071
phungductung	0:e87aa4c49e95	9072	/**************************** CEC Instances *******************************/
phungductung	0:e87aa4c49e95	9073	#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
phungductung	0:e87aa4c49e95	9074
phungductung	0:e87aa4c49e95	9075	/**************************** QSPI Instances *******************************/
phungductung	0:e87aa4c49e95	9076	#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
phungductung	0:e87aa4c49e95	9077
phungductung	0:e87aa4c49e95	9078
phungductung	0:e87aa4c49e95	9079	/****************************** I2C Instances *****************************/
phungductung	0:e87aa4c49e95	9080	#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) \|\| \
phungductung	0:e87aa4c49e95	9081	((__INSTANCE__) == I2C2) \|\| \
phungductung	0:e87aa4c49e95	9082	((__INSTANCE__) == I2C3) \|\| \
phungductung	0:e87aa4c49e95	9083	((__INSTANCE__) == I2C4))
phungductung	0:e87aa4c49e95	9084
phungductung	0:e87aa4c49e95	9085	/****************************** I2S Instances *****************************/
phungductung	0:e87aa4c49e95	9086	#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) \|\| \
phungductung	0:e87aa4c49e95	9087	((__INSTANCE__) == SPI2) \|\| \
phungductung	0:e87aa4c49e95	9088	((__INSTANCE__) == SPI3))
phungductung	0:e87aa4c49e95	9089
phungductung	0:e87aa4c49e95	9090	/***************************** LPTIM Instances ******************************/
phungductung	0:e87aa4c49e95	9091	#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
phungductung	0:e87aa4c49e95	9092
phungductung	0:e87aa4c49e95	9093	/**************************** LTDC Instances ******************************/
phungductung	0:e87aa4c49e95	9094	#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
phungductung	0:e87aa4c49e95	9095
phungductung	0:e87aa4c49e95	9096
phungductung	0:e87aa4c49e95	9097	/***************************** RNG Instances ******************************/
phungductung	0:e87aa4c49e95	9098	#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
phungductung	0:e87aa4c49e95	9099
phungductung	0:e87aa4c49e95	9100	/**************************** RTC Instances *******************************/
phungductung	0:e87aa4c49e95	9101	#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
phungductung	0:e87aa4c49e95	9102
phungductung	0:e87aa4c49e95	9103	/***************************** SAI Instances ******************************/
phungductung	0:e87aa4c49e95	9104	#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) \|\| \
phungductung	0:e87aa4c49e95	9105	((__PERIPH__) == SAI1_Block_B) \|\| \
phungductung	0:e87aa4c49e95	9106	((__PERIPH__) == SAI2_Block_A) \|\| \
phungductung	0:e87aa4c49e95	9107	((__PERIPH__) == SAI2_Block_B))
phungductung	0:e87aa4c49e95	9108
phungductung	0:e87aa4c49e95	9109
phungductung	0:e87aa4c49e95	9110	/****************************** SDMMC Instances *****************************/
phungductung	0:e87aa4c49e95	9111	#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
phungductung	0:e87aa4c49e95	9112
phungductung	0:e87aa4c49e95	9113	/**************************** SPDIFRX Instances *******************************/
phungductung	0:e87aa4c49e95	9114	#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
phungductung	0:e87aa4c49e95	9115
phungductung	0:e87aa4c49e95	9116	/****************************** SPI Instances *****************************/
phungductung	0:e87aa4c49e95	9117	#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) \|\| \
phungductung	0:e87aa4c49e95	9118	((__INSTANCE__) == SPI2) \|\| \
phungductung	0:e87aa4c49e95	9119	((__INSTANCE__) == SPI3) \|\| \
phungductung	0:e87aa4c49e95	9120	((__INSTANCE__) == SPI4) \|\| \
phungductung	0:e87aa4c49e95	9121	((__INSTANCE__) == SPI5) \|\| \
phungductung	0:e87aa4c49e95	9122	((__INSTANCE__) == SPI6))
phungductung	0:e87aa4c49e95	9123
phungductung	0:e87aa4c49e95	9124	/**************** TIM Instances : All supported instances *****************/
phungductung	0:e87aa4c49e95	9125	#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9126	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9127	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9128	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9129	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9130	((__INSTANCE__) == TIM6) \|\| \
phungductung	0:e87aa4c49e95	9131	((__INSTANCE__) == TIM7) \|\| \
phungductung	0:e87aa4c49e95	9132	((__INSTANCE__) == TIM8) \|\| \
phungductung	0:e87aa4c49e95	9133	((__INSTANCE__) == TIM9) \|\| \
phungductung	0:e87aa4c49e95	9134	((__INSTANCE__) == TIM10) \|\| \
phungductung	0:e87aa4c49e95	9135	((__INSTANCE__) == TIM11) \|\| \
phungductung	0:e87aa4c49e95	9136	((__INSTANCE__) == TIM12) \|\| \
phungductung	0:e87aa4c49e95	9137	((__INSTANCE__) == TIM13) \|\| \
phungductung	0:e87aa4c49e95	9138	((__INSTANCE__) == TIM14))
phungductung	0:e87aa4c49e95	9139
phungductung	0:e87aa4c49e95	9140	/*********** TIM Instances : at least 1 capture/compare channel ***********/
phungductung	0:e87aa4c49e95	9141	#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9142	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9143	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9144	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9145	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9146	((__INSTANCE__) == TIM8) \|\| \
phungductung	0:e87aa4c49e95	9147	((__INSTANCE__) == TIM9) \|\| \
phungductung	0:e87aa4c49e95	9148	((__INSTANCE__) == TIM10) \|\| \
phungductung	0:e87aa4c49e95	9149	((__INSTANCE__) == TIM11) \|\| \
phungductung	0:e87aa4c49e95	9150	((__INSTANCE__) == TIM12) \|\| \
phungductung	0:e87aa4c49e95	9151	((__INSTANCE__) == TIM13) \|\| \
phungductung	0:e87aa4c49e95	9152	((__INSTANCE__) == TIM14))
phungductung	0:e87aa4c49e95	9153
phungductung	0:e87aa4c49e95	9154	/********** TIM Instances : at least 2 capture/compare channels ***********/
phungductung	0:e87aa4c49e95	9155	#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9156	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9157	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9158	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9159	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9160	((__INSTANCE__) == TIM8) \|\| \
phungductung	0:e87aa4c49e95	9161	((__INSTANCE__) == TIM9) \|\| \
phungductung	0:e87aa4c49e95	9162	((__INSTANCE__) == TIM12))
phungductung	0:e87aa4c49e95	9163
phungductung	0:e87aa4c49e95	9164	/********** TIM Instances : at least 3 capture/compare channels ***********/
phungductung	0:e87aa4c49e95	9165	#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9166	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9167	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9168	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9169	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9170	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9171
phungductung	0:e87aa4c49e95	9172	/********** TIM Instances : at least 4 capture/compare channels ***********/
phungductung	0:e87aa4c49e95	9173	#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9174	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9175	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9176	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9177	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9178	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9179
phungductung	0:e87aa4c49e95	9180	/**************** TIM Instances : supporting combined 3-phase PWM mode ****/
phungductung	0:e87aa4c49e95	9181	#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
phungductung	0:e87aa4c49e95	9182	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9183	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9184
phungductung	0:e87aa4c49e95	9185	/**************** TIM Instances : supporting OCxREF clear *****************/
phungductung	0:e87aa4c49e95	9186	#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9187	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9188	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9189	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9190	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9191	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9192
phungductung	0:e87aa4c49e95	9193	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
phungductung	0:e87aa4c49e95	9194	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9195	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9196	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9197	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9198	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9199	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9200	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9201
phungductung	0:e87aa4c49e95	9202	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
phungductung	0:e87aa4c49e95	9203	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9204	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9205	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9206	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9207	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9208	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9209	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9210	/**************** TIM Instances : at least 5 capture/compare channels *****/
phungductung	0:e87aa4c49e95	9211	#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9212	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9213	((__INSTANCE__) == TIM8) )
phungductung	0:e87aa4c49e95	9214
phungductung	0:e87aa4c49e95	9215	/**************** TIM Instances : at least 6 capture/compare channels *****/
phungductung	0:e87aa4c49e95	9216	#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9217	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9218	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9219
phungductung	0:e87aa4c49e95	9220
phungductung	0:e87aa4c49e95	9221	/****************** TIM Instances : Advanced-control timers ***************/
phungductung	0:e87aa4c49e95	9222	#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9223	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9224
phungductung	0:e87aa4c49e95	9225	/**************** TIM Instances : supporting 2 break inputs ***************/
phungductung	0:e87aa4c49e95	9226	#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9227	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9228	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9229
phungductung	0:e87aa4c49e95	9230	/***************** TIM Instances : Timer input XOR function ***************/
phungductung	0:e87aa4c49e95	9231	#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9232	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9233	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9234	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9235	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9236	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9237
phungductung	0:e87aa4c49e95	9238	/**************** TIM Instances : DMA requests generation (UDE) ***********/
phungductung	0:e87aa4c49e95	9239	#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9240	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9241	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9242	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9243	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9244	((__INSTANCE__) == TIM6) \|\| \
phungductung	0:e87aa4c49e95	9245	((__INSTANCE__) == TIM7) \|\| \
phungductung	0:e87aa4c49e95	9246	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9247
phungductung	0:e87aa4c49e95	9248	/********** TIM Instances : DMA requests generation (CCxDE) ***************/
phungductung	0:e87aa4c49e95	9249	#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9250	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9251	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9252	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9253	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9254	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9255
phungductung	0:e87aa4c49e95	9256	/********** TIM Instances : DMA requests generation (COMDE) ***************/
phungductung	0:e87aa4c49e95	9257	#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9258	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9259	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9260	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9261	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9262	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9263
phungductung	0:e87aa4c49e95	9264	/****************** TIM Instances : DMA burst feature *********************/
phungductung	0:e87aa4c49e95	9265	#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9266	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9267	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9268	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9269	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9270	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9271
phungductung	0:e87aa4c49e95	9272	/**** TIM Instances : master mode available (TIMx_CR2.MMS available )******/
phungductung	0:e87aa4c49e95	9273	#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9274	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9275	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9276	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9277	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9278	((__INSTANCE__) == TIM6) \|\| \
phungductung	0:e87aa4c49e95	9279	((__INSTANCE__) == TIM7) \|\| \
phungductung	0:e87aa4c49e95	9280	((__INSTANCE__) == TIM8) \|\| \
phungductung	0:e87aa4c49e95	9281	((__INSTANCE__) == TIM13) \|\| \
phungductung	0:e87aa4c49e95	9282	((__INSTANCE__) == TIM14))
phungductung	0:e87aa4c49e95	9283
phungductung	0:e87aa4c49e95	9284	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
phungductung	0:e87aa4c49e95	9285	#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9286	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9287	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9288	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9289	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9290	((__INSTANCE__) == TIM8) \|\| \
phungductung	0:e87aa4c49e95	9291	((__INSTANCE__) == TIM9) \|\| \
phungductung	0:e87aa4c49e95	9292	((__INSTANCE__) == TIM12))
phungductung	0:e87aa4c49e95	9293
phungductung	0:e87aa4c49e95	9294	/******************** TIM Instances : 32 bit Counter **********************/
phungductung	0:e87aa4c49e95	9295	#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9296	((__INSTANCE__) == TIM5))
phungductung	0:e87aa4c49e95	9297
phungductung	0:e87aa4c49e95	9298	/*************** TIM Instances : external trigger input available **********/
phungductung	0:e87aa4c49e95	9299	#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9300	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9301	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9302	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9303	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9304	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9305
phungductung	0:e87aa4c49e95	9306	/**************** TIM Instances : remapping capability ********************/
phungductung	0:e87aa4c49e95	9307	#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9308	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9309	((__INSTANCE__) == TIM11))
phungductung	0:e87aa4c49e95	9310
phungductung	0:e87aa4c49e95	9311	/***************** TIM Instances : output(s) available ********************/
phungductung	0:e87aa4c49e95	9312	#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
phungductung	0:e87aa4c49e95	9313	((((__INSTANCE__) == TIM1) && \
phungductung	0:e87aa4c49e95	9314	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9315	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9316	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
phungductung	0:e87aa4c49e95	9317	((__CHANNEL__) == TIM_CHANNEL_4))) \
phungductung	0:e87aa4c49e95	9318	\|\| \
phungductung	0:e87aa4c49e95	9319	(((__INSTANCE__) == TIM2) && \
phungductung	0:e87aa4c49e95	9320	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9321	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9322	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
phungductung	0:e87aa4c49e95	9323	((__CHANNEL__) == TIM_CHANNEL_4))) \
phungductung	0:e87aa4c49e95	9324	\|\| \
phungductung	0:e87aa4c49e95	9325	(((__INSTANCE__) == TIM3) && \
phungductung	0:e87aa4c49e95	9326	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9327	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9328	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
phungductung	0:e87aa4c49e95	9329	((__CHANNEL__) == TIM_CHANNEL_4))) \
phungductung	0:e87aa4c49e95	9330	\|\| \
phungductung	0:e87aa4c49e95	9331	(((__INSTANCE__) == TIM4) && \
phungductung	0:e87aa4c49e95	9332	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9333	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9334	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
phungductung	0:e87aa4c49e95	9335	((__CHANNEL__) == TIM_CHANNEL_4))) \
phungductung	0:e87aa4c49e95	9336	\|\| \
phungductung	0:e87aa4c49e95	9337	(((__INSTANCE__) == TIM5) && \
phungductung	0:e87aa4c49e95	9338	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9339	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9340	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
phungductung	0:e87aa4c49e95	9341	((__CHANNEL__) == TIM_CHANNEL_4))) \
phungductung	0:e87aa4c49e95	9342	\|\| \
phungductung	0:e87aa4c49e95	9343	(((__INSTANCE__) == TIM8) && \
phungductung	0:e87aa4c49e95	9344	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9345	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9346	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
phungductung	0:e87aa4c49e95	9347	((__CHANNEL__) == TIM_CHANNEL_4))) \
phungductung	0:e87aa4c49e95	9348	\|\| \
phungductung	0:e87aa4c49e95	9349	(((__INSTANCE__) == TIM9) && \
phungductung	0:e87aa4c49e95	9350	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9351	((__CHANNEL__) == TIM_CHANNEL_2))) \
phungductung	0:e87aa4c49e95	9352	\|\| \
phungductung	0:e87aa4c49e95	9353	(((__INSTANCE__) == TIM10) && \
phungductung	0:e87aa4c49e95	9354	(((__CHANNEL__) == TIM_CHANNEL_1))) \
phungductung	0:e87aa4c49e95	9355	\|\| \
phungductung	0:e87aa4c49e95	9356	(((__INSTANCE__) == TIM11) && \
phungductung	0:e87aa4c49e95	9357	(((__CHANNEL__) == TIM_CHANNEL_1))) \
phungductung	0:e87aa4c49e95	9358	\|\| \
phungductung	0:e87aa4c49e95	9359	(((__INSTANCE__) == TIM12) && \
phungductung	0:e87aa4c49e95	9360	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9361	((__CHANNEL__) == TIM_CHANNEL_2))) \
phungductung	0:e87aa4c49e95	9362	\|\| \
phungductung	0:e87aa4c49e95	9363	(((__INSTANCE__) == TIM13) && \
phungductung	0:e87aa4c49e95	9364	(((__CHANNEL__) == TIM_CHANNEL_1))) \
phungductung	0:e87aa4c49e95	9365	\|\| \
phungductung	0:e87aa4c49e95	9366	(((__INSTANCE__) == TIM14) && \
phungductung	0:e87aa4c49e95	9367	(((__CHANNEL__) == TIM_CHANNEL_1))))
phungductung	0:e87aa4c49e95	9368
phungductung	0:e87aa4c49e95	9369	/********** TIM Instances : complementary output(s) available *************/
phungductung	0:e87aa4c49e95	9370	#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
phungductung	0:e87aa4c49e95	9371	((((__INSTANCE__) == TIM1) && \
phungductung	0:e87aa4c49e95	9372	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9373	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9374	((__CHANNEL__) == TIM_CHANNEL_3))) \
phungductung	0:e87aa4c49e95	9375	\|\| \
phungductung	0:e87aa4c49e95	9376	(((__INSTANCE__) == TIM8) && \
phungductung	0:e87aa4c49e95	9377	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
phungductung	0:e87aa4c49e95	9378	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
phungductung	0:e87aa4c49e95	9379	((__CHANNEL__) == TIM_CHANNEL_3))))
phungductung	0:e87aa4c49e95	9380
phungductung	0:e87aa4c49e95	9381	/**************** TIM Instances : supporting ADC triggering through TRGO2 */
phungductung	0:e87aa4c49e95	9382	#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9383	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9384	((__INSTANCE__) == TIM8) )
phungductung	0:e87aa4c49e95	9385
phungductung	0:e87aa4c49e95	9386	/**************** TIM Instances : supporting synchronization **************/
phungductung	0:e87aa4c49e95	9387	#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
phungductung	0:e87aa4c49e95	9388	(((__INSTANCE__) == TIM1) \|\| \
phungductung	0:e87aa4c49e95	9389	((__INSTANCE__) == TIM2) \|\| \
phungductung	0:e87aa4c49e95	9390	((__INSTANCE__) == TIM3) \|\| \
phungductung	0:e87aa4c49e95	9391	((__INSTANCE__) == TIM4) \|\| \
phungductung	0:e87aa4c49e95	9392	((__INSTANCE__) == TIM5) \|\| \
phungductung	0:e87aa4c49e95	9393	((__INSTANCE__) == TIM6) \|\| \
phungductung	0:e87aa4c49e95	9394	((__INSTANCE__) == TIM7) \|\| \
phungductung	0:e87aa4c49e95	9395	((__INSTANCE__) == TIM8))
phungductung	0:e87aa4c49e95	9396
phungductung	0:e87aa4c49e95	9397	/****************** USART Instances : Synchronous mode ********************/
phungductung	0:e87aa4c49e95	9398	#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
phungductung	0:e87aa4c49e95	9399	((__INSTANCE__) == USART2) \|\| \
phungductung	0:e87aa4c49e95	9400	((__INSTANCE__) == USART3) \|\| \
phungductung	0:e87aa4c49e95	9401	((__INSTANCE__) == USART6))
phungductung	0:e87aa4c49e95	9402
phungductung	0:e87aa4c49e95	9403	/****************** UART Instances : Asynchronous mode ********************/
phungductung	0:e87aa4c49e95	9404	#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
phungductung	0:e87aa4c49e95	9405	((__INSTANCE__) == USART2) \|\| \
phungductung	0:e87aa4c49e95	9406	((__INSTANCE__) == USART3) \|\| \
phungductung	0:e87aa4c49e95	9407	((__INSTANCE__) == UART4) \|\| \
phungductung	0:e87aa4c49e95	9408	((__INSTANCE__) == UART5) \|\| \
phungductung	0:e87aa4c49e95	9409	((__INSTANCE__) == USART6) \|\| \
phungductung	0:e87aa4c49e95	9410	((__INSTANCE__) == UART7) \|\| \
phungductung	0:e87aa4c49e95	9411	((__INSTANCE__) == UART8))
phungductung	0:e87aa4c49e95	9412
phungductung	0:e87aa4c49e95	9413	/**************** UART Instances : Hardware Flow control ******************/
phungductung	0:e87aa4c49e95	9414	#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
phungductung	0:e87aa4c49e95	9415	((__INSTANCE__) == USART2) \|\| \
phungductung	0:e87aa4c49e95	9416	((__INSTANCE__) == USART3) \|\| \
phungductung	0:e87aa4c49e95	9417	((__INSTANCE__) == UART4) \|\| \
phungductung	0:e87aa4c49e95	9418	((__INSTANCE__) == UART5) \|\| \
phungductung	0:e87aa4c49e95	9419	((__INSTANCE__) == USART6) \|\| \
phungductung	0:e87aa4c49e95	9420	((__INSTANCE__) == UART7) \|\| \
phungductung	0:e87aa4c49e95	9421	((__INSTANCE__) == UART8))
phungductung	0:e87aa4c49e95	9422
phungductung	0:e87aa4c49e95	9423	/******************* UART Instances : Smart card mode *********************/
phungductung	0:e87aa4c49e95	9424	#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
phungductung	0:e87aa4c49e95	9425	((__INSTANCE__) == USART2) \|\| \
phungductung	0:e87aa4c49e95	9426	((__INSTANCE__) == USART3) \|\| \
phungductung	0:e87aa4c49e95	9427	((__INSTANCE__) == USART6))
phungductung	0:e87aa4c49e95	9428
phungductung	0:e87aa4c49e95	9429	/********************* UART Instances : IRDA mode *************************/
phungductung	0:e87aa4c49e95	9430	#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
phungductung	0:e87aa4c49e95	9431	((__INSTANCE__) == USART2) \|\| \
phungductung	0:e87aa4c49e95	9432	((__INSTANCE__) == USART3) \|\| \
phungductung	0:e87aa4c49e95	9433	((__INSTANCE__) == UART4) \|\| \
phungductung	0:e87aa4c49e95	9434	((__INSTANCE__) == UART5) \|\| \
phungductung	0:e87aa4c49e95	9435	((__INSTANCE__) == USART6) \|\| \
phungductung	0:e87aa4c49e95	9436	((__INSTANCE__) == UART7) \|\| \
phungductung	0:e87aa4c49e95	9437	((__INSTANCE__) == UART8))
phungductung	0:e87aa4c49e95	9438
phungductung	0:e87aa4c49e95	9439	/**************************** IWDG Instances ******************************/
phungductung	0:e87aa4c49e95	9440	#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
phungductung	0:e87aa4c49e95	9441
phungductung	0:e87aa4c49e95	9442	/**************************** WWDG Instances ******************************/
phungductung	0:e87aa4c49e95	9443	#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
phungductung	0:e87aa4c49e95	9444
phungductung	0:e87aa4c49e95	9445
phungductung	0:e87aa4c49e95	9446	/******************************************************************************/
phungductung	0:e87aa4c49e95	9447	/* For a painless codes migration between the STM32F7xx device product */
phungductung	0:e87aa4c49e95	9448	/* lines, the aliases defined below are put in place to overcome the */
phungductung	0:e87aa4c49e95	9449	/* differences in the interrupt handlers and IRQn definitions. */
phungductung	0:e87aa4c49e95	9450	/* No need to update developed interrupt code when moving across */
phungductung	0:e87aa4c49e95	9451	/* product lines within the same STM32F7 Family */
phungductung	0:e87aa4c49e95	9452	/******************************************************************************/
phungductung	0:e87aa4c49e95	9453
phungductung	0:e87aa4c49e95	9454	/* Aliases for __IRQn */
phungductung	0:e87aa4c49e95	9455	#define HASH_RNG_IRQn RNG_IRQn
phungductung	0:e87aa4c49e95	9456
phungductung	0:e87aa4c49e95	9457	/* Aliases for __IRQHandler */
phungductung	0:e87aa4c49e95	9458	#define HASH_RNG_IRQHandler RNG_IRQHandler
phungductung	0:e87aa4c49e95	9459
phungductung	0:e87aa4c49e95	9460	/**
phungductung	0:e87aa4c49e95	9461	* @}
phungductung	0:e87aa4c49e95	9462	*/
phungductung	0:e87aa4c49e95	9463
phungductung	0:e87aa4c49e95	9464	/**
phungductung	0:e87aa4c49e95	9465	* @}
phungductung	0:e87aa4c49e95	9466	*/
phungductung	0:e87aa4c49e95	9467
phungductung	0:e87aa4c49e95	9468	/**
phungductung	0:e87aa4c49e95	9469	* @}
phungductung	0:e87aa4c49e95	9470	*/
phungductung	0:e87aa4c49e95	9471
phungductung	0:e87aa4c49e95	9472	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	9473	}
phungductung	0:e87aa4c49e95	9474	#endif /* __cplusplus */
phungductung	0:e87aa4c49e95	9475
phungductung	0:e87aa4c49e95	9476	#endif /* __STM32F746xx_H */
phungductung	0:e87aa4c49e95	9477
phungductung	0:e87aa4c49e95	9478
phungductung	0:e87aa4c49e95	9479	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Jun 2019
Imports:	8
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h@0:e87aa4c49e95, 2019-06-04 (annotated)

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