SRC_STM32F7 - SPKT

Users » phungductung » Code » SRC_STM32F7

SPKT

targets/cmsis/core_cm7.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

libray

Who changed what in which revision?

User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/************************************************************************//
phungductung	0:e87aa4c49e95	2	* @file core_cm7.h
phungductung	0:e87aa4c49e95	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
phungductung	0:e87aa4c49e95	4	* @version V4.10
phungductung	0:e87aa4c49e95	5	* @date 18. March 2015
phungductung	0:e87aa4c49e95	6	*
phungductung	0:e87aa4c49e95	7	* @note
phungductung	0:e87aa4c49e95	8	*
phungductung	0:e87aa4c49e95	9	******************************************************************************/
phungductung	0:e87aa4c49e95	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
phungductung	0:e87aa4c49e95	11
phungductung	0:e87aa4c49e95	12	All rights reserved.
phungductung	0:e87aa4c49e95	13	Redistribution and use in source and binary forms, with or without
phungductung	0:e87aa4c49e95	14	modification, are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	15	- Redistributions of source code must retain the above copyright
phungductung	0:e87aa4c49e95	16	notice, this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	17	- Redistributions in binary form must reproduce the above copyright
phungductung	0:e87aa4c49e95	18	notice, this list of conditions and the following disclaimer in the
phungductung	0:e87aa4c49e95	19	documentation and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	20	- Neither the name of ARM nor the names of its contributors may be used
phungductung	0:e87aa4c49e95	21	to endorse or promote products derived from this software without
phungductung	0:e87aa4c49e95	22	specific prior written permission.
phungductung	0:e87aa4c49e95	23	*
phungductung	0:e87aa4c49e95	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
phungductung	0:e87aa4c49e95	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
phungductung	0:e87aa4c49e95	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
phungductung	0:e87aa4c49e95	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
phungductung	0:e87aa4c49e95	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
phungductung	0:e87aa4c49e95	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
phungductung	0:e87aa4c49e95	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
phungductung	0:e87aa4c49e95	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
phungductung	0:e87aa4c49e95	34	POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	35	---------------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	36
phungductung	0:e87aa4c49e95	37
phungductung	0:e87aa4c49e95	38	#if defined ( __ICCARM__ )
phungductung	0:e87aa4c49e95	39	#pragma system_include /* treat file as system include file for MISRA check */
phungductung	0:e87aa4c49e95	40	#endif
phungductung	0:e87aa4c49e95	41
phungductung	0:e87aa4c49e95	42	#ifndef __CORE_CM7_H_GENERIC
phungductung	0:e87aa4c49e95	43	#define __CORE_CM7_H_GENERIC
phungductung	0:e87aa4c49e95	44
phungductung	0:e87aa4c49e95	45	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	46	extern "C" {
phungductung	0:e87aa4c49e95	47	#endif
phungductung	0:e87aa4c49e95	48
phungductung	0:e87aa4c49e95	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
phungductung	0:e87aa4c49e95	50	CMSIS violates the following MISRA-C:2004 rules:
phungductung	0:e87aa4c49e95	51
phungductung	0:e87aa4c49e95	52	\li Required Rule 8.5, object/function definition in header file.<br>
phungductung	0:e87aa4c49e95	53	Function definitions in header files are used to allow 'inlining'.
phungductung	0:e87aa4c49e95	54
phungductung	0:e87aa4c49e95	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
phungductung	0:e87aa4c49e95	56	Unions are used for effective representation of core registers.
phungductung	0:e87aa4c49e95	57
phungductung	0:e87aa4c49e95	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
phungductung	0:e87aa4c49e95	59	Function-like macros are used to allow more efficient code.
phungductung	0:e87aa4c49e95	60	*/
phungductung	0:e87aa4c49e95	61
phungductung	0:e87aa4c49e95	62
phungductung	0:e87aa4c49e95	63	/*******************************************************************************
phungductung	0:e87aa4c49e95	64	* CMSIS definitions
phungductung	0:e87aa4c49e95	65	******************************************************************************/
phungductung	0:e87aa4c49e95	66	/** \ingroup Cortex_M7
phungductung	0:e87aa4c49e95	67	@{
phungductung	0:e87aa4c49e95	68	*/
phungductung	0:e87aa4c49e95	69
phungductung	0:e87aa4c49e95	70	/* CMSIS CM7 definitions */
phungductung	0:e87aa4c49e95	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
phungductung	0:e87aa4c49e95	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
phungductung	0:e87aa4c49e95	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
phungductung	0:e87aa4c49e95	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
phungductung	0:e87aa4c49e95	75
phungductung	0:e87aa4c49e95	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
phungductung	0:e87aa4c49e95	77
phungductung	0:e87aa4c49e95	78
phungductung	0:e87aa4c49e95	79	#if defined ( __CC_ARM )
phungductung	0:e87aa4c49e95	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
phungductung	0:e87aa4c49e95	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
phungductung	0:e87aa4c49e95	82	#define __STATIC_INLINE static __inline
phungductung	0:e87aa4c49e95	83
phungductung	0:e87aa4c49e95	84	#elif defined ( __GNUC__ )
phungductung	0:e87aa4c49e95	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
phungductung	0:e87aa4c49e95	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
phungductung	0:e87aa4c49e95	87	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	88
phungductung	0:e87aa4c49e95	89	#elif defined ( __ICCARM__ )
phungductung	0:e87aa4c49e95	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
phungductung	0:e87aa4c49e95	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
phungductung	0:e87aa4c49e95	92	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	93
phungductung	0:e87aa4c49e95	94	#elif defined ( __TMS470__ )
phungductung	0:e87aa4c49e95	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
phungductung	0:e87aa4c49e95	96	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	97
phungductung	0:e87aa4c49e95	98	#elif defined ( __TASKING__ )
phungductung	0:e87aa4c49e95	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
phungductung	0:e87aa4c49e95	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
phungductung	0:e87aa4c49e95	101	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	102
phungductung	0:e87aa4c49e95	103	#elif defined ( __CSMC__ )
phungductung	0:e87aa4c49e95	104	#define __packed
phungductung	0:e87aa4c49e95	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
phungductung	0:e87aa4c49e95	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
phungductung	0:e87aa4c49e95	107	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	108
phungductung	0:e87aa4c49e95	109	#endif
phungductung	0:e87aa4c49e95	110
phungductung	0:e87aa4c49e95	111	/** __FPU_USED indicates whether an FPU is used or not.
phungductung	0:e87aa4c49e95	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
phungductung	0:e87aa4c49e95	113	*/
phungductung	0:e87aa4c49e95	114	#if defined ( __CC_ARM )
phungductung	0:e87aa4c49e95	115	#if defined __TARGET_FPU_VFP
phungductung	0:e87aa4c49e95	116	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	117	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	118	#else
phungductung	0:e87aa4c49e95	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	120	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	121	#endif
phungductung	0:e87aa4c49e95	122	#else
phungductung	0:e87aa4c49e95	123	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	124	#endif
phungductung	0:e87aa4c49e95	125
phungductung	0:e87aa4c49e95	126	#elif defined ( __GNUC__ )
phungductung	0:e87aa4c49e95	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
phungductung	0:e87aa4c49e95	128	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	129	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	130	#else
phungductung	0:e87aa4c49e95	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	132	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	133	#endif
phungductung	0:e87aa4c49e95	134	#else
phungductung	0:e87aa4c49e95	135	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	136	#endif
phungductung	0:e87aa4c49e95	137
phungductung	0:e87aa4c49e95	138	#elif defined ( __ICCARM__ )
phungductung	0:e87aa4c49e95	139	#if defined __ARMVFP__
phungductung	0:e87aa4c49e95	140	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	141	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	142	#else
phungductung	0:e87aa4c49e95	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	144	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	145	#endif
phungductung	0:e87aa4c49e95	146	#else
phungductung	0:e87aa4c49e95	147	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	148	#endif
phungductung	0:e87aa4c49e95	149
phungductung	0:e87aa4c49e95	150	#elif defined ( __TMS470__ )
phungductung	0:e87aa4c49e95	151	#if defined __TI_VFP_SUPPORT__
phungductung	0:e87aa4c49e95	152	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	153	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	154	#else
phungductung	0:e87aa4c49e95	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	156	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	157	#endif
phungductung	0:e87aa4c49e95	158	#else
phungductung	0:e87aa4c49e95	159	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	160	#endif
phungductung	0:e87aa4c49e95	161
phungductung	0:e87aa4c49e95	162	#elif defined ( __TASKING__ )
phungductung	0:e87aa4c49e95	163	#if defined __FPU_VFP__
phungductung	0:e87aa4c49e95	164	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	165	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	166	#else
phungductung	0:e87aa4c49e95	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	168	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	169	#endif
phungductung	0:e87aa4c49e95	170	#else
phungductung	0:e87aa4c49e95	171	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	172	#endif
phungductung	0:e87aa4c49e95	173
phungductung	0:e87aa4c49e95	174	#elif defined ( __CSMC__ ) /* Cosmic */
phungductung	0:e87aa4c49e95	175	#if ( __CSMC__ & 0x400) // FPU present for parser
phungductung	0:e87aa4c49e95	176	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	177	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	178	#else
phungductung	0:e87aa4c49e95	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	180	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	181	#endif
phungductung	0:e87aa4c49e95	182	#else
phungductung	0:e87aa4c49e95	183	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	184	#endif
phungductung	0:e87aa4c49e95	185	#endif
phungductung	0:e87aa4c49e95	186
phungductung	0:e87aa4c49e95	187	#include <stdint.h> /* standard types definitions */
phungductung	0:e87aa4c49e95	188	#include <core_cmInstr.h> /* Core Instruction Access */
phungductung	0:e87aa4c49e95	189	#include <core_cmFunc.h> /* Core Function Access */
phungductung	0:e87aa4c49e95	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
phungductung	0:e87aa4c49e95	191
phungductung	0:e87aa4c49e95	192	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	193	}
phungductung	0:e87aa4c49e95	194	#endif
phungductung	0:e87aa4c49e95	195
phungductung	0:e87aa4c49e95	196	#endif /* __CORE_CM7_H_GENERIC */
phungductung	0:e87aa4c49e95	197
phungductung	0:e87aa4c49e95	198	#ifndef __CMSIS_GENERIC
phungductung	0:e87aa4c49e95	199
phungductung	0:e87aa4c49e95	200	#ifndef __CORE_CM7_H_DEPENDANT
phungductung	0:e87aa4c49e95	201	#define __CORE_CM7_H_DEPENDANT
phungductung	0:e87aa4c49e95	202
phungductung	0:e87aa4c49e95	203	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	204	extern "C" {
phungductung	0:e87aa4c49e95	205	#endif
phungductung	0:e87aa4c49e95	206
phungductung	0:e87aa4c49e95	207	/* check device defines and use defaults */
phungductung	0:e87aa4c49e95	208	#if defined __CHECK_DEVICE_DEFINES
phungductung	0:e87aa4c49e95	209	#ifndef __CM7_REV
phungductung	0:e87aa4c49e95	210	#define __CM7_REV 0x0000
phungductung	0:e87aa4c49e95	211	#warning "__CM7_REV not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	212	#endif
phungductung	0:e87aa4c49e95	213
phungductung	0:e87aa4c49e95	214	#ifndef __FPU_PRESENT
phungductung	0:e87aa4c49e95	215	#define __FPU_PRESENT 0
phungductung	0:e87aa4c49e95	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	217	#endif
phungductung	0:e87aa4c49e95	218
phungductung	0:e87aa4c49e95	219	#ifndef __MPU_PRESENT
phungductung	0:e87aa4c49e95	220	#define __MPU_PRESENT 0
phungductung	0:e87aa4c49e95	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	222	#endif
phungductung	0:e87aa4c49e95	223
phungductung	0:e87aa4c49e95	224	#ifndef __ICACHE_PRESENT
phungductung	0:e87aa4c49e95	225	#define __ICACHE_PRESENT 0
phungductung	0:e87aa4c49e95	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	227	#endif
phungductung	0:e87aa4c49e95	228
phungductung	0:e87aa4c49e95	229	#ifndef __DCACHE_PRESENT
phungductung	0:e87aa4c49e95	230	#define __DCACHE_PRESENT 0
phungductung	0:e87aa4c49e95	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	232	#endif
phungductung	0:e87aa4c49e95	233
phungductung	0:e87aa4c49e95	234	#ifndef __DTCM_PRESENT
phungductung	0:e87aa4c49e95	235	#define __DTCM_PRESENT 0
phungductung	0:e87aa4c49e95	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	237	#endif
phungductung	0:e87aa4c49e95	238
phungductung	0:e87aa4c49e95	239	#ifndef __NVIC_PRIO_BITS
phungductung	0:e87aa4c49e95	240	#define __NVIC_PRIO_BITS 3
phungductung	0:e87aa4c49e95	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	242	#endif
phungductung	0:e87aa4c49e95	243
phungductung	0:e87aa4c49e95	244	#ifndef __Vendor_SysTickConfig
phungductung	0:e87aa4c49e95	245	#define __Vendor_SysTickConfig 0
phungductung	0:e87aa4c49e95	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	247	#endif
phungductung	0:e87aa4c49e95	248	#endif
phungductung	0:e87aa4c49e95	249
phungductung	0:e87aa4c49e95	250	/* IO definitions (access restrictions to peripheral registers) */
phungductung	0:e87aa4c49e95	251	/**
phungductung	0:e87aa4c49e95	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
phungductung	0:e87aa4c49e95	253
phungductung	0:e87aa4c49e95	254	<strong>IO Type Qualifiers</strong> are used
phungductung	0:e87aa4c49e95	255	\li to specify the access to peripheral variables.
phungductung	0:e87aa4c49e95	256	\li for automatic generation of peripheral register debug information.
phungductung	0:e87aa4c49e95	257	*/
phungductung	0:e87aa4c49e95	258	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	259	#define __I volatile /!< Defines 'read only' permissions /
phungductung	0:e87aa4c49e95	260	#else
phungductung	0:e87aa4c49e95	261	#define __I volatile const /!< Defines 'read only' permissions /
phungductung	0:e87aa4c49e95	262	#endif
phungductung	0:e87aa4c49e95	263	#define __O volatile /!< Defines 'write only' permissions /
phungductung	0:e87aa4c49e95	264	#define __IO volatile /!< Defines 'read / write' permissions /
phungductung	0:e87aa4c49e95	265
phungductung	0:e87aa4c49e95	266	/@} end of group Cortex_M7 /
phungductung	0:e87aa4c49e95	267
phungductung	0:e87aa4c49e95	268
phungductung	0:e87aa4c49e95	269
phungductung	0:e87aa4c49e95	270	/*******************************************************************************
phungductung	0:e87aa4c49e95	271	* Register Abstraction
phungductung	0:e87aa4c49e95	272	Core Register contain:
phungductung	0:e87aa4c49e95	273	- Core Register
phungductung	0:e87aa4c49e95	274	- Core NVIC Register
phungductung	0:e87aa4c49e95	275	- Core SCB Register
phungductung	0:e87aa4c49e95	276	- Core SysTick Register
phungductung	0:e87aa4c49e95	277	- Core Debug Register
phungductung	0:e87aa4c49e95	278	- Core MPU Register
phungductung	0:e87aa4c49e95	279	- Core FPU Register
phungductung	0:e87aa4c49e95	280	******************************************************************************/
phungductung	0:e87aa4c49e95	281	/** \defgroup CMSIS_core_register Defines and Type Definitions
phungductung	0:e87aa4c49e95	282	\brief Type definitions and defines for Cortex-M processor based devices.
phungductung	0:e87aa4c49e95	283	*/
phungductung	0:e87aa4c49e95	284
phungductung	0:e87aa4c49e95	285	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	286	\defgroup CMSIS_CORE Status and Control Registers
phungductung	0:e87aa4c49e95	287	\brief Core Register type definitions.
phungductung	0:e87aa4c49e95	288	@{
phungductung	0:e87aa4c49e95	289	*/
phungductung	0:e87aa4c49e95	290
phungductung	0:e87aa4c49e95	291	/** \brief Union type to access the Application Program Status Register (APSR).
phungductung	0:e87aa4c49e95	292	*/
phungductung	0:e87aa4c49e95	293	typedef union
phungductung	0:e87aa4c49e95	294	{
phungductung	0:e87aa4c49e95	295	struct
phungductung	0:e87aa4c49e95	296	{
phungductung	0:e87aa4c49e95	297	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
phungductung	0:e87aa4c49e95	298	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
phungductung	0:e87aa4c49e95	299	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
phungductung	0:e87aa4c49e95	300	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
phungductung	0:e87aa4c49e95	301	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
phungductung	0:e87aa4c49e95	302	uint32_t C:1; /!< bit: 29 Carry condition code flag /
phungductung	0:e87aa4c49e95	303	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
phungductung	0:e87aa4c49e95	304	uint32_t N:1; /!< bit: 31 Negative condition code flag /
phungductung	0:e87aa4c49e95	305	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	306	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	307	} APSR_Type;
phungductung	0:e87aa4c49e95	308
phungductung	0:e87aa4c49e95	309	/* APSR Register Definitions */
phungductung	0:e87aa4c49e95	310	#define APSR_N_Pos 31 /!< APSR: N Position /
phungductung	0:e87aa4c49e95	311	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
phungductung	0:e87aa4c49e95	312
phungductung	0:e87aa4c49e95	313	#define APSR_Z_Pos 30 /!< APSR: Z Position /
phungductung	0:e87aa4c49e95	314	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
phungductung	0:e87aa4c49e95	315
phungductung	0:e87aa4c49e95	316	#define APSR_C_Pos 29 /!< APSR: C Position /
phungductung	0:e87aa4c49e95	317	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
phungductung	0:e87aa4c49e95	318
phungductung	0:e87aa4c49e95	319	#define APSR_V_Pos 28 /!< APSR: V Position /
phungductung	0:e87aa4c49e95	320	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
phungductung	0:e87aa4c49e95	321
phungductung	0:e87aa4c49e95	322	#define APSR_Q_Pos 27 /!< APSR: Q Position /
phungductung	0:e87aa4c49e95	323	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
phungductung	0:e87aa4c49e95	324
phungductung	0:e87aa4c49e95	325	#define APSR_GE_Pos 16 /!< APSR: GE Position /
phungductung	0:e87aa4c49e95	326	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
phungductung	0:e87aa4c49e95	327
phungductung	0:e87aa4c49e95	328
phungductung	0:e87aa4c49e95	329	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
phungductung	0:e87aa4c49e95	330	*/
phungductung	0:e87aa4c49e95	331	typedef union
phungductung	0:e87aa4c49e95	332	{
phungductung	0:e87aa4c49e95	333	struct
phungductung	0:e87aa4c49e95	334	{
phungductung	0:e87aa4c49e95	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
phungductung	0:e87aa4c49e95	336	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
phungductung	0:e87aa4c49e95	337	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	338	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	339	} IPSR_Type;
phungductung	0:e87aa4c49e95	340
phungductung	0:e87aa4c49e95	341	/* IPSR Register Definitions */
phungductung	0:e87aa4c49e95	342	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
phungductung	0:e87aa4c49e95	343	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
phungductung	0:e87aa4c49e95	344
phungductung	0:e87aa4c49e95	345
phungductung	0:e87aa4c49e95	346	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
phungductung	0:e87aa4c49e95	347	*/
phungductung	0:e87aa4c49e95	348	typedef union
phungductung	0:e87aa4c49e95	349	{
phungductung	0:e87aa4c49e95	350	struct
phungductung	0:e87aa4c49e95	351	{
phungductung	0:e87aa4c49e95	352	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
phungductung	0:e87aa4c49e95	353	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
phungductung	0:e87aa4c49e95	354	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
phungductung	0:e87aa4c49e95	355	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
phungductung	0:e87aa4c49e95	356	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
phungductung	0:e87aa4c49e95	357	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
phungductung	0:e87aa4c49e95	358	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
phungductung	0:e87aa4c49e95	359	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
phungductung	0:e87aa4c49e95	360	uint32_t C:1; /!< bit: 29 Carry condition code flag /
phungductung	0:e87aa4c49e95	361	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
phungductung	0:e87aa4c49e95	362	uint32_t N:1; /!< bit: 31 Negative condition code flag /
phungductung	0:e87aa4c49e95	363	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	364	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	365	} xPSR_Type;
phungductung	0:e87aa4c49e95	366
phungductung	0:e87aa4c49e95	367	/* xPSR Register Definitions */
phungductung	0:e87aa4c49e95	368	#define xPSR_N_Pos 31 /!< xPSR: N Position /
phungductung	0:e87aa4c49e95	369	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
phungductung	0:e87aa4c49e95	370
phungductung	0:e87aa4c49e95	371	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
phungductung	0:e87aa4c49e95	372	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
phungductung	0:e87aa4c49e95	373
phungductung	0:e87aa4c49e95	374	#define xPSR_C_Pos 29 /!< xPSR: C Position /
phungductung	0:e87aa4c49e95	375	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
phungductung	0:e87aa4c49e95	376
phungductung	0:e87aa4c49e95	377	#define xPSR_V_Pos 28 /!< xPSR: V Position /
phungductung	0:e87aa4c49e95	378	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
phungductung	0:e87aa4c49e95	379
phungductung	0:e87aa4c49e95	380	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
phungductung	0:e87aa4c49e95	381	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
phungductung	0:e87aa4c49e95	382
phungductung	0:e87aa4c49e95	383	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
phungductung	0:e87aa4c49e95	384	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
phungductung	0:e87aa4c49e95	385
phungductung	0:e87aa4c49e95	386	#define xPSR_T_Pos 24 /!< xPSR: T Position /
phungductung	0:e87aa4c49e95	387	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
phungductung	0:e87aa4c49e95	388
phungductung	0:e87aa4c49e95	389	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
phungductung	0:e87aa4c49e95	390	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
phungductung	0:e87aa4c49e95	391
phungductung	0:e87aa4c49e95	392	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
phungductung	0:e87aa4c49e95	393	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
phungductung	0:e87aa4c49e95	394
phungductung	0:e87aa4c49e95	395
phungductung	0:e87aa4c49e95	396	/** \brief Union type to access the Control Registers (CONTROL).
phungductung	0:e87aa4c49e95	397	*/
phungductung	0:e87aa4c49e95	398	typedef union
phungductung	0:e87aa4c49e95	399	{
phungductung	0:e87aa4c49e95	400	struct
phungductung	0:e87aa4c49e95	401	{
phungductung	0:e87aa4c49e95	402	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
phungductung	0:e87aa4c49e95	403	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
phungductung	0:e87aa4c49e95	404	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
phungductung	0:e87aa4c49e95	405	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
phungductung	0:e87aa4c49e95	406	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	407	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	408	} CONTROL_Type;
phungductung	0:e87aa4c49e95	409
phungductung	0:e87aa4c49e95	410	/* CONTROL Register Definitions */
phungductung	0:e87aa4c49e95	411	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
phungductung	0:e87aa4c49e95	412	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
phungductung	0:e87aa4c49e95	413
phungductung	0:e87aa4c49e95	414	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
phungductung	0:e87aa4c49e95	415	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
phungductung	0:e87aa4c49e95	416
phungductung	0:e87aa4c49e95	417	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
phungductung	0:e87aa4c49e95	418	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
phungductung	0:e87aa4c49e95	419
phungductung	0:e87aa4c49e95	420	/@} end of group CMSIS_CORE /
phungductung	0:e87aa4c49e95	421
phungductung	0:e87aa4c49e95	422
phungductung	0:e87aa4c49e95	423	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	424	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
phungductung	0:e87aa4c49e95	425	\brief Type definitions for the NVIC Registers
phungductung	0:e87aa4c49e95	426	@{
phungductung	0:e87aa4c49e95	427	*/
phungductung	0:e87aa4c49e95	428
phungductung	0:e87aa4c49e95	429	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
phungductung	0:e87aa4c49e95	430	*/
phungductung	0:e87aa4c49e95	431	typedef struct
phungductung	0:e87aa4c49e95	432	{
phungductung	0:e87aa4c49e95	433	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
phungductung	0:e87aa4c49e95	434	uint32_t RESERVED0[24];
phungductung	0:e87aa4c49e95	435	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
phungductung	0:e87aa4c49e95	436	uint32_t RSERVED1[24];
phungductung	0:e87aa4c49e95	437	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
phungductung	0:e87aa4c49e95	438	uint32_t RESERVED2[24];
phungductung	0:e87aa4c49e95	439	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
phungductung	0:e87aa4c49e95	440	uint32_t RESERVED3[24];
phungductung	0:e87aa4c49e95	441	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
phungductung	0:e87aa4c49e95	442	uint32_t RESERVED4[56];
phungductung	0:e87aa4c49e95	443	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
phungductung	0:e87aa4c49e95	444	uint32_t RESERVED5[644];
phungductung	0:e87aa4c49e95	445	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
phungductung	0:e87aa4c49e95	446	} NVIC_Type;
phungductung	0:e87aa4c49e95	447
phungductung	0:e87aa4c49e95	448	/* Software Triggered Interrupt Register Definitions */
phungductung	0:e87aa4c49e95	449	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
phungductung	0:e87aa4c49e95	450	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
phungductung	0:e87aa4c49e95	451
phungductung	0:e87aa4c49e95	452	/@} end of group CMSIS_NVIC /
phungductung	0:e87aa4c49e95	453
phungductung	0:e87aa4c49e95	454
phungductung	0:e87aa4c49e95	455	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	456	\defgroup CMSIS_SCB System Control Block (SCB)
phungductung	0:e87aa4c49e95	457	\brief Type definitions for the System Control Block Registers
phungductung	0:e87aa4c49e95	458	@{
phungductung	0:e87aa4c49e95	459	*/
phungductung	0:e87aa4c49e95	460
phungductung	0:e87aa4c49e95	461	/** \brief Structure type to access the System Control Block (SCB).
phungductung	0:e87aa4c49e95	462	*/
phungductung	0:e87aa4c49e95	463	typedef struct
phungductung	0:e87aa4c49e95	464	{
phungductung	0:e87aa4c49e95	465	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
phungductung	0:e87aa4c49e95	466	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
phungductung	0:e87aa4c49e95	467	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
phungductung	0:e87aa4c49e95	468	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
phungductung	0:e87aa4c49e95	469	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
phungductung	0:e87aa4c49e95	470	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
phungductung	0:e87aa4c49e95	471	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
phungductung	0:e87aa4c49e95	472	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
phungductung	0:e87aa4c49e95	473	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
phungductung	0:e87aa4c49e95	474	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
phungductung	0:e87aa4c49e95	475	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
phungductung	0:e87aa4c49e95	476	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
phungductung	0:e87aa4c49e95	477	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
phungductung	0:e87aa4c49e95	478	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
phungductung	0:e87aa4c49e95	479	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
phungductung	0:e87aa4c49e95	480	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
phungductung	0:e87aa4c49e95	481	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
phungductung	0:e87aa4c49e95	482	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
phungductung	0:e87aa4c49e95	483	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
phungductung	0:e87aa4c49e95	484	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	485	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
phungductung	0:e87aa4c49e95	486	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
phungductung	0:e87aa4c49e95	487	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
phungductung	0:e87aa4c49e95	488	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
phungductung	0:e87aa4c49e95	489	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
phungductung	0:e87aa4c49e95	490	uint32_t RESERVED3[93];
phungductung	0:e87aa4c49e95	491	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
phungductung	0:e87aa4c49e95	492	uint32_t RESERVED4[15];
phungductung	0:e87aa4c49e95	493	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
phungductung	0:e87aa4c49e95	494	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
phungductung	0:e87aa4c49e95	495	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
phungductung	0:e87aa4c49e95	496	uint32_t RESERVED5[1];
phungductung	0:e87aa4c49e95	497	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
phungductung	0:e87aa4c49e95	498	uint32_t RESERVED6[1];
phungductung	0:e87aa4c49e95	499	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
phungductung	0:e87aa4c49e95	500	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
phungductung	0:e87aa4c49e95	501	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
phungductung	0:e87aa4c49e95	502	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
phungductung	0:e87aa4c49e95	503	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
phungductung	0:e87aa4c49e95	504	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
phungductung	0:e87aa4c49e95	505	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
phungductung	0:e87aa4c49e95	506	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
phungductung	0:e87aa4c49e95	507	uint32_t RESERVED7[6];
phungductung	0:e87aa4c49e95	508	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
phungductung	0:e87aa4c49e95	509	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
phungductung	0:e87aa4c49e95	510	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
phungductung	0:e87aa4c49e95	511	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
phungductung	0:e87aa4c49e95	512	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
phungductung	0:e87aa4c49e95	513	uint32_t RESERVED8[1];
phungductung	0:e87aa4c49e95	514	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
phungductung	0:e87aa4c49e95	515	} SCB_Type;
phungductung	0:e87aa4c49e95	516
phungductung	0:e87aa4c49e95	517	/* SCB CPUID Register Definitions */
phungductung	0:e87aa4c49e95	518	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
phungductung	0:e87aa4c49e95	519	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
phungductung	0:e87aa4c49e95	520
phungductung	0:e87aa4c49e95	521	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
phungductung	0:e87aa4c49e95	522	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
phungductung	0:e87aa4c49e95	523
phungductung	0:e87aa4c49e95	524	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
phungductung	0:e87aa4c49e95	525	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
phungductung	0:e87aa4c49e95	526
phungductung	0:e87aa4c49e95	527	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
phungductung	0:e87aa4c49e95	528	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
phungductung	0:e87aa4c49e95	529
phungductung	0:e87aa4c49e95	530	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
phungductung	0:e87aa4c49e95	531	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
phungductung	0:e87aa4c49e95	532
phungductung	0:e87aa4c49e95	533	/* SCB Interrupt Control State Register Definitions */
phungductung	0:e87aa4c49e95	534	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
phungductung	0:e87aa4c49e95	535	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
phungductung	0:e87aa4c49e95	536
phungductung	0:e87aa4c49e95	537	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
phungductung	0:e87aa4c49e95	538	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
phungductung	0:e87aa4c49e95	539
phungductung	0:e87aa4c49e95	540	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
phungductung	0:e87aa4c49e95	541	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
phungductung	0:e87aa4c49e95	542
phungductung	0:e87aa4c49e95	543	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
phungductung	0:e87aa4c49e95	544	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
phungductung	0:e87aa4c49e95	545
phungductung	0:e87aa4c49e95	546	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
phungductung	0:e87aa4c49e95	547	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
phungductung	0:e87aa4c49e95	548
phungductung	0:e87aa4c49e95	549	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
phungductung	0:e87aa4c49e95	550	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
phungductung	0:e87aa4c49e95	551
phungductung	0:e87aa4c49e95	552	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
phungductung	0:e87aa4c49e95	553	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
phungductung	0:e87aa4c49e95	554
phungductung	0:e87aa4c49e95	555	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
phungductung	0:e87aa4c49e95	556	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
phungductung	0:e87aa4c49e95	557
phungductung	0:e87aa4c49e95	558	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
phungductung	0:e87aa4c49e95	559	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
phungductung	0:e87aa4c49e95	560
phungductung	0:e87aa4c49e95	561	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
phungductung	0:e87aa4c49e95	562	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
phungductung	0:e87aa4c49e95	563
phungductung	0:e87aa4c49e95	564	/* SCB Vector Table Offset Register Definitions */
phungductung	0:e87aa4c49e95	565	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
phungductung	0:e87aa4c49e95	566	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
phungductung	0:e87aa4c49e95	567
phungductung	0:e87aa4c49e95	568	/* SCB Application Interrupt and Reset Control Register Definitions */
phungductung	0:e87aa4c49e95	569	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
phungductung	0:e87aa4c49e95	570	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
phungductung	0:e87aa4c49e95	571
phungductung	0:e87aa4c49e95	572	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
phungductung	0:e87aa4c49e95	573	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
phungductung	0:e87aa4c49e95	574
phungductung	0:e87aa4c49e95	575	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
phungductung	0:e87aa4c49e95	576	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
phungductung	0:e87aa4c49e95	577
phungductung	0:e87aa4c49e95	578	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
phungductung	0:e87aa4c49e95	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
phungductung	0:e87aa4c49e95	580
phungductung	0:e87aa4c49e95	581	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
phungductung	0:e87aa4c49e95	582	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
phungductung	0:e87aa4c49e95	583
phungductung	0:e87aa4c49e95	584	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
phungductung	0:e87aa4c49e95	585	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
phungductung	0:e87aa4c49e95	586
phungductung	0:e87aa4c49e95	587	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
phungductung	0:e87aa4c49e95	588	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
phungductung	0:e87aa4c49e95	589
phungductung	0:e87aa4c49e95	590	/* SCB System Control Register Definitions */
phungductung	0:e87aa4c49e95	591	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
phungductung	0:e87aa4c49e95	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
phungductung	0:e87aa4c49e95	593
phungductung	0:e87aa4c49e95	594	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
phungductung	0:e87aa4c49e95	595	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
phungductung	0:e87aa4c49e95	596
phungductung	0:e87aa4c49e95	597	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
phungductung	0:e87aa4c49e95	598	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
phungductung	0:e87aa4c49e95	599
phungductung	0:e87aa4c49e95	600	/* SCB Configuration Control Register Definitions */
phungductung	0:e87aa4c49e95	601	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
phungductung	0:e87aa4c49e95	602	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
phungductung	0:e87aa4c49e95	603
phungductung	0:e87aa4c49e95	604	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
phungductung	0:e87aa4c49e95	605	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
phungductung	0:e87aa4c49e95	606
phungductung	0:e87aa4c49e95	607	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
phungductung	0:e87aa4c49e95	608	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
phungductung	0:e87aa4c49e95	609
phungductung	0:e87aa4c49e95	610	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
phungductung	0:e87aa4c49e95	611	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
phungductung	0:e87aa4c49e95	612
phungductung	0:e87aa4c49e95	613	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
phungductung	0:e87aa4c49e95	614	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
phungductung	0:e87aa4c49e95	615
phungductung	0:e87aa4c49e95	616	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
phungductung	0:e87aa4c49e95	617	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
phungductung	0:e87aa4c49e95	618
phungductung	0:e87aa4c49e95	619	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
phungductung	0:e87aa4c49e95	620	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
phungductung	0:e87aa4c49e95	621
phungductung	0:e87aa4c49e95	622	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
phungductung	0:e87aa4c49e95	623	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
phungductung	0:e87aa4c49e95	624
phungductung	0:e87aa4c49e95	625	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
phungductung	0:e87aa4c49e95	626	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
phungductung	0:e87aa4c49e95	627
phungductung	0:e87aa4c49e95	628	/* SCB System Handler Control and State Register Definitions */
phungductung	0:e87aa4c49e95	629	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
phungductung	0:e87aa4c49e95	630	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
phungductung	0:e87aa4c49e95	631
phungductung	0:e87aa4c49e95	632	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
phungductung	0:e87aa4c49e95	633	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
phungductung	0:e87aa4c49e95	634
phungductung	0:e87aa4c49e95	635	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
phungductung	0:e87aa4c49e95	636	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
phungductung	0:e87aa4c49e95	637
phungductung	0:e87aa4c49e95	638	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
phungductung	0:e87aa4c49e95	639	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
phungductung	0:e87aa4c49e95	640
phungductung	0:e87aa4c49e95	641	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
phungductung	0:e87aa4c49e95	642	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
phungductung	0:e87aa4c49e95	643
phungductung	0:e87aa4c49e95	644	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
phungductung	0:e87aa4c49e95	645	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
phungductung	0:e87aa4c49e95	646
phungductung	0:e87aa4c49e95	647	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
phungductung	0:e87aa4c49e95	648	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
phungductung	0:e87aa4c49e95	649
phungductung	0:e87aa4c49e95	650	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
phungductung	0:e87aa4c49e95	651	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
phungductung	0:e87aa4c49e95	652
phungductung	0:e87aa4c49e95	653	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
phungductung	0:e87aa4c49e95	654	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
phungductung	0:e87aa4c49e95	655
phungductung	0:e87aa4c49e95	656	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
phungductung	0:e87aa4c49e95	657	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
phungductung	0:e87aa4c49e95	658
phungductung	0:e87aa4c49e95	659	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
phungductung	0:e87aa4c49e95	660	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
phungductung	0:e87aa4c49e95	661
phungductung	0:e87aa4c49e95	662	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
phungductung	0:e87aa4c49e95	663	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
phungductung	0:e87aa4c49e95	664
phungductung	0:e87aa4c49e95	665	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
phungductung	0:e87aa4c49e95	666	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
phungductung	0:e87aa4c49e95	667
phungductung	0:e87aa4c49e95	668	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
phungductung	0:e87aa4c49e95	669	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
phungductung	0:e87aa4c49e95	670
phungductung	0:e87aa4c49e95	671	/* SCB Configurable Fault Status Registers Definitions */
phungductung	0:e87aa4c49e95	672	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
phungductung	0:e87aa4c49e95	673	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
phungductung	0:e87aa4c49e95	674
phungductung	0:e87aa4c49e95	675	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
phungductung	0:e87aa4c49e95	676	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
phungductung	0:e87aa4c49e95	677
phungductung	0:e87aa4c49e95	678	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
phungductung	0:e87aa4c49e95	679	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
phungductung	0:e87aa4c49e95	680
phungductung	0:e87aa4c49e95	681	/* SCB Hard Fault Status Registers Definitions */
phungductung	0:e87aa4c49e95	682	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
phungductung	0:e87aa4c49e95	683	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
phungductung	0:e87aa4c49e95	684
phungductung	0:e87aa4c49e95	685	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
phungductung	0:e87aa4c49e95	686	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
phungductung	0:e87aa4c49e95	687
phungductung	0:e87aa4c49e95	688	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
phungductung	0:e87aa4c49e95	689	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
phungductung	0:e87aa4c49e95	690
phungductung	0:e87aa4c49e95	691	/* SCB Debug Fault Status Register Definitions */
phungductung	0:e87aa4c49e95	692	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
phungductung	0:e87aa4c49e95	693	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
phungductung	0:e87aa4c49e95	694
phungductung	0:e87aa4c49e95	695	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
phungductung	0:e87aa4c49e95	696	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
phungductung	0:e87aa4c49e95	697
phungductung	0:e87aa4c49e95	698	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
phungductung	0:e87aa4c49e95	699	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
phungductung	0:e87aa4c49e95	700
phungductung	0:e87aa4c49e95	701	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
phungductung	0:e87aa4c49e95	702	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
phungductung	0:e87aa4c49e95	703
phungductung	0:e87aa4c49e95	704	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
phungductung	0:e87aa4c49e95	705	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
phungductung	0:e87aa4c49e95	706
phungductung	0:e87aa4c49e95	707	/* Cache Level ID register */
phungductung	0:e87aa4c49e95	708	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
phungductung	0:e87aa4c49e95	709	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
phungductung	0:e87aa4c49e95	710
phungductung	0:e87aa4c49e95	711	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
phungductung	0:e87aa4c49e95	712	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
phungductung	0:e87aa4c49e95	713
phungductung	0:e87aa4c49e95	714	/* Cache Type register */
phungductung	0:e87aa4c49e95	715	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
phungductung	0:e87aa4c49e95	716	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
phungductung	0:e87aa4c49e95	717
phungductung	0:e87aa4c49e95	718	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
phungductung	0:e87aa4c49e95	719	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
phungductung	0:e87aa4c49e95	720
phungductung	0:e87aa4c49e95	721	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
phungductung	0:e87aa4c49e95	722	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
phungductung	0:e87aa4c49e95	723
phungductung	0:e87aa4c49e95	724	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
phungductung	0:e87aa4c49e95	725	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
phungductung	0:e87aa4c49e95	726
phungductung	0:e87aa4c49e95	727	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
phungductung	0:e87aa4c49e95	728	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
phungductung	0:e87aa4c49e95	729
phungductung	0:e87aa4c49e95	730	/* Cache Size ID Register */
phungductung	0:e87aa4c49e95	731	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
phungductung	0:e87aa4c49e95	732	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
phungductung	0:e87aa4c49e95	733
phungductung	0:e87aa4c49e95	734	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
phungductung	0:e87aa4c49e95	735	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
phungductung	0:e87aa4c49e95	736
phungductung	0:e87aa4c49e95	737	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
phungductung	0:e87aa4c49e95	738	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
phungductung	0:e87aa4c49e95	739
phungductung	0:e87aa4c49e95	740	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
phungductung	0:e87aa4c49e95	741	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
phungductung	0:e87aa4c49e95	742
phungductung	0:e87aa4c49e95	743	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
phungductung	0:e87aa4c49e95	744	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
phungductung	0:e87aa4c49e95	745
phungductung	0:e87aa4c49e95	746	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
phungductung	0:e87aa4c49e95	747	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
phungductung	0:e87aa4c49e95	748
phungductung	0:e87aa4c49e95	749	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
phungductung	0:e87aa4c49e95	750	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
phungductung	0:e87aa4c49e95	751
phungductung	0:e87aa4c49e95	752	/* Cache Size Selection Register */
phungductung	0:e87aa4c49e95	753	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
phungductung	0:e87aa4c49e95	754	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
phungductung	0:e87aa4c49e95	755
phungductung	0:e87aa4c49e95	756	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
phungductung	0:e87aa4c49e95	757	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
phungductung	0:e87aa4c49e95	758
phungductung	0:e87aa4c49e95	759	/* SCB Software Triggered Interrupt Register */
phungductung	0:e87aa4c49e95	760	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
phungductung	0:e87aa4c49e95	761	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
phungductung	0:e87aa4c49e95	762
phungductung	0:e87aa4c49e95	763	/* Instruction Tightly-Coupled Memory Control Register*/
phungductung	0:e87aa4c49e95	764	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
phungductung	0:e87aa4c49e95	765	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
phungductung	0:e87aa4c49e95	766
phungductung	0:e87aa4c49e95	767	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
phungductung	0:e87aa4c49e95	768	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
phungductung	0:e87aa4c49e95	769
phungductung	0:e87aa4c49e95	770	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
phungductung	0:e87aa4c49e95	771	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
phungductung	0:e87aa4c49e95	772
phungductung	0:e87aa4c49e95	773	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
phungductung	0:e87aa4c49e95	774	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
phungductung	0:e87aa4c49e95	775
phungductung	0:e87aa4c49e95	776	/* Data Tightly-Coupled Memory Control Registers */
phungductung	0:e87aa4c49e95	777	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
phungductung	0:e87aa4c49e95	778	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
phungductung	0:e87aa4c49e95	779
phungductung	0:e87aa4c49e95	780	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
phungductung	0:e87aa4c49e95	781	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
phungductung	0:e87aa4c49e95	782
phungductung	0:e87aa4c49e95	783	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
phungductung	0:e87aa4c49e95	784	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
phungductung	0:e87aa4c49e95	785
phungductung	0:e87aa4c49e95	786	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
phungductung	0:e87aa4c49e95	787	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
phungductung	0:e87aa4c49e95	788
phungductung	0:e87aa4c49e95	789	/* AHBP Control Register */
phungductung	0:e87aa4c49e95	790	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
phungductung	0:e87aa4c49e95	791	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
phungductung	0:e87aa4c49e95	792
phungductung	0:e87aa4c49e95	793	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
phungductung	0:e87aa4c49e95	794	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
phungductung	0:e87aa4c49e95	795
phungductung	0:e87aa4c49e95	796	/* L1 Cache Control Register */
phungductung	0:e87aa4c49e95	797	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
phungductung	0:e87aa4c49e95	798	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
phungductung	0:e87aa4c49e95	799
phungductung	0:e87aa4c49e95	800	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
phungductung	0:e87aa4c49e95	801	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
phungductung	0:e87aa4c49e95	802
phungductung	0:e87aa4c49e95	803	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
phungductung	0:e87aa4c49e95	804	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
phungductung	0:e87aa4c49e95	805
phungductung	0:e87aa4c49e95	806	/* AHBS control register */
phungductung	0:e87aa4c49e95	807	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
phungductung	0:e87aa4c49e95	808	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
phungductung	0:e87aa4c49e95	809
phungductung	0:e87aa4c49e95	810	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
phungductung	0:e87aa4c49e95	811	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
phungductung	0:e87aa4c49e95	812
phungductung	0:e87aa4c49e95	813	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
phungductung	0:e87aa4c49e95	814	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
phungductung	0:e87aa4c49e95	815
phungductung	0:e87aa4c49e95	816	/* Auxiliary Bus Fault Status Register */
phungductung	0:e87aa4c49e95	817	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
phungductung	0:e87aa4c49e95	818	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
phungductung	0:e87aa4c49e95	819
phungductung	0:e87aa4c49e95	820	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
phungductung	0:e87aa4c49e95	821	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
phungductung	0:e87aa4c49e95	822
phungductung	0:e87aa4c49e95	823	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
phungductung	0:e87aa4c49e95	824	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
phungductung	0:e87aa4c49e95	825
phungductung	0:e87aa4c49e95	826	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
phungductung	0:e87aa4c49e95	827	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
phungductung	0:e87aa4c49e95	828
phungductung	0:e87aa4c49e95	829	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
phungductung	0:e87aa4c49e95	830	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
phungductung	0:e87aa4c49e95	831
phungductung	0:e87aa4c49e95	832	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
phungductung	0:e87aa4c49e95	833	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
phungductung	0:e87aa4c49e95	834
phungductung	0:e87aa4c49e95	835	/@} end of group CMSIS_SCB /
phungductung	0:e87aa4c49e95	836
phungductung	0:e87aa4c49e95	837
phungductung	0:e87aa4c49e95	838	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	839	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
phungductung	0:e87aa4c49e95	840	\brief Type definitions for the System Control and ID Register not in the SCB
phungductung	0:e87aa4c49e95	841	@{
phungductung	0:e87aa4c49e95	842	*/
phungductung	0:e87aa4c49e95	843
phungductung	0:e87aa4c49e95	844	/** \brief Structure type to access the System Control and ID Register not in the SCB.
phungductung	0:e87aa4c49e95	845	*/
phungductung	0:e87aa4c49e95	846	typedef struct
phungductung	0:e87aa4c49e95	847	{
phungductung	0:e87aa4c49e95	848	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	849	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
phungductung	0:e87aa4c49e95	850	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
phungductung	0:e87aa4c49e95	851	} SCnSCB_Type;
phungductung	0:e87aa4c49e95	852
phungductung	0:e87aa4c49e95	853	/* Interrupt Controller Type Register Definitions */
phungductung	0:e87aa4c49e95	854	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
phungductung	0:e87aa4c49e95	855	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
phungductung	0:e87aa4c49e95	856
phungductung	0:e87aa4c49e95	857	/* Auxiliary Control Register Definitions */
phungductung	0:e87aa4c49e95	858	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
phungductung	0:e87aa4c49e95	859	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
phungductung	0:e87aa4c49e95	860
phungductung	0:e87aa4c49e95	861	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
phungductung	0:e87aa4c49e95	862	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
phungductung	0:e87aa4c49e95	863
phungductung	0:e87aa4c49e95	864	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
phungductung	0:e87aa4c49e95	865	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
phungductung	0:e87aa4c49e95	866
phungductung	0:e87aa4c49e95	867	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
phungductung	0:e87aa4c49e95	868	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
phungductung	0:e87aa4c49e95	869
phungductung	0:e87aa4c49e95	870	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
phungductung	0:e87aa4c49e95	871	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
phungductung	0:e87aa4c49e95	872
phungductung	0:e87aa4c49e95	873	/@} end of group CMSIS_SCnotSCB /
phungductung	0:e87aa4c49e95	874
phungductung	0:e87aa4c49e95	875
phungductung	0:e87aa4c49e95	876	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	877	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
phungductung	0:e87aa4c49e95	878	\brief Type definitions for the System Timer Registers.
phungductung	0:e87aa4c49e95	879	@{
phungductung	0:e87aa4c49e95	880	*/
phungductung	0:e87aa4c49e95	881
phungductung	0:e87aa4c49e95	882	/** \brief Structure type to access the System Timer (SysTick).
phungductung	0:e87aa4c49e95	883	*/
phungductung	0:e87aa4c49e95	884	typedef struct
phungductung	0:e87aa4c49e95	885	{
phungductung	0:e87aa4c49e95	886	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
phungductung	0:e87aa4c49e95	887	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
phungductung	0:e87aa4c49e95	888	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
phungductung	0:e87aa4c49e95	889	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
phungductung	0:e87aa4c49e95	890	} SysTick_Type;
phungductung	0:e87aa4c49e95	891
phungductung	0:e87aa4c49e95	892	/* SysTick Control / Status Register Definitions */
phungductung	0:e87aa4c49e95	893	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
phungductung	0:e87aa4c49e95	894	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
phungductung	0:e87aa4c49e95	895
phungductung	0:e87aa4c49e95	896	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
phungductung	0:e87aa4c49e95	897	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
phungductung	0:e87aa4c49e95	898
phungductung	0:e87aa4c49e95	899	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
phungductung	0:e87aa4c49e95	900	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
phungductung	0:e87aa4c49e95	901
phungductung	0:e87aa4c49e95	902	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
phungductung	0:e87aa4c49e95	903	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
phungductung	0:e87aa4c49e95	904
phungductung	0:e87aa4c49e95	905	/* SysTick Reload Register Definitions */
phungductung	0:e87aa4c49e95	906	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
phungductung	0:e87aa4c49e95	907	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
phungductung	0:e87aa4c49e95	908
phungductung	0:e87aa4c49e95	909	/* SysTick Current Register Definitions */
phungductung	0:e87aa4c49e95	910	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
phungductung	0:e87aa4c49e95	911	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
phungductung	0:e87aa4c49e95	912
phungductung	0:e87aa4c49e95	913	/* SysTick Calibration Register Definitions */
phungductung	0:e87aa4c49e95	914	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
phungductung	0:e87aa4c49e95	915	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
phungductung	0:e87aa4c49e95	916
phungductung	0:e87aa4c49e95	917	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
phungductung	0:e87aa4c49e95	918	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
phungductung	0:e87aa4c49e95	919
phungductung	0:e87aa4c49e95	920	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
phungductung	0:e87aa4c49e95	921	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
phungductung	0:e87aa4c49e95	922
phungductung	0:e87aa4c49e95	923	/@} end of group CMSIS_SysTick /
phungductung	0:e87aa4c49e95	924
phungductung	0:e87aa4c49e95	925
phungductung	0:e87aa4c49e95	926	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	927	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
phungductung	0:e87aa4c49e95	928	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
phungductung	0:e87aa4c49e95	929	@{
phungductung	0:e87aa4c49e95	930	*/
phungductung	0:e87aa4c49e95	931
phungductung	0:e87aa4c49e95	932	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
phungductung	0:e87aa4c49e95	933	*/
phungductung	0:e87aa4c49e95	934	typedef struct
phungductung	0:e87aa4c49e95	935	{
phungductung	0:e87aa4c49e95	936	__O union
phungductung	0:e87aa4c49e95	937	{
phungductung	0:e87aa4c49e95	938	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
phungductung	0:e87aa4c49e95	939	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
phungductung	0:e87aa4c49e95	940	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
phungductung	0:e87aa4c49e95	941	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
phungductung	0:e87aa4c49e95	942	uint32_t RESERVED0[864];
phungductung	0:e87aa4c49e95	943	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
phungductung	0:e87aa4c49e95	944	uint32_t RESERVED1[15];
phungductung	0:e87aa4c49e95	945	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
phungductung	0:e87aa4c49e95	946	uint32_t RESERVED2[15];
phungductung	0:e87aa4c49e95	947	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
phungductung	0:e87aa4c49e95	948	uint32_t RESERVED3[29];
phungductung	0:e87aa4c49e95	949	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
phungductung	0:e87aa4c49e95	950	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
phungductung	0:e87aa4c49e95	951	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
phungductung	0:e87aa4c49e95	952	uint32_t RESERVED4[43];
phungductung	0:e87aa4c49e95	953	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
phungductung	0:e87aa4c49e95	954	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
phungductung	0:e87aa4c49e95	955	uint32_t RESERVED5[6];
phungductung	0:e87aa4c49e95	956	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
phungductung	0:e87aa4c49e95	957	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
phungductung	0:e87aa4c49e95	958	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
phungductung	0:e87aa4c49e95	959	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
phungductung	0:e87aa4c49e95	960	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
phungductung	0:e87aa4c49e95	961	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
phungductung	0:e87aa4c49e95	962	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
phungductung	0:e87aa4c49e95	963	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
phungductung	0:e87aa4c49e95	964	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
phungductung	0:e87aa4c49e95	965	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
phungductung	0:e87aa4c49e95	966	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
phungductung	0:e87aa4c49e95	967	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
phungductung	0:e87aa4c49e95	968	} ITM_Type;
phungductung	0:e87aa4c49e95	969
phungductung	0:e87aa4c49e95	970	/* ITM Trace Privilege Register Definitions */
phungductung	0:e87aa4c49e95	971	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
phungductung	0:e87aa4c49e95	972	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
phungductung	0:e87aa4c49e95	973
phungductung	0:e87aa4c49e95	974	/* ITM Trace Control Register Definitions */
phungductung	0:e87aa4c49e95	975	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
phungductung	0:e87aa4c49e95	976	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
phungductung	0:e87aa4c49e95	977
phungductung	0:e87aa4c49e95	978	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
phungductung	0:e87aa4c49e95	979	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
phungductung	0:e87aa4c49e95	980
phungductung	0:e87aa4c49e95	981	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
phungductung	0:e87aa4c49e95	982	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
phungductung	0:e87aa4c49e95	983
phungductung	0:e87aa4c49e95	984	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
phungductung	0:e87aa4c49e95	985	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
phungductung	0:e87aa4c49e95	986
phungductung	0:e87aa4c49e95	987	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
phungductung	0:e87aa4c49e95	988	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
phungductung	0:e87aa4c49e95	989
phungductung	0:e87aa4c49e95	990	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
phungductung	0:e87aa4c49e95	991	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
phungductung	0:e87aa4c49e95	992
phungductung	0:e87aa4c49e95	993	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
phungductung	0:e87aa4c49e95	994	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
phungductung	0:e87aa4c49e95	995
phungductung	0:e87aa4c49e95	996	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
phungductung	0:e87aa4c49e95	997	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
phungductung	0:e87aa4c49e95	998
phungductung	0:e87aa4c49e95	999	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
phungductung	0:e87aa4c49e95	1000	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
phungductung	0:e87aa4c49e95	1001
phungductung	0:e87aa4c49e95	1002	/* ITM Integration Write Register Definitions */
phungductung	0:e87aa4c49e95	1003	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
phungductung	0:e87aa4c49e95	1004	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
phungductung	0:e87aa4c49e95	1005
phungductung	0:e87aa4c49e95	1006	/* ITM Integration Read Register Definitions */
phungductung	0:e87aa4c49e95	1007	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
phungductung	0:e87aa4c49e95	1008	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
phungductung	0:e87aa4c49e95	1009
phungductung	0:e87aa4c49e95	1010	/* ITM Integration Mode Control Register Definitions */
phungductung	0:e87aa4c49e95	1011	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
phungductung	0:e87aa4c49e95	1012	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
phungductung	0:e87aa4c49e95	1013
phungductung	0:e87aa4c49e95	1014	/* ITM Lock Status Register Definitions */
phungductung	0:e87aa4c49e95	1015	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
phungductung	0:e87aa4c49e95	1016	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
phungductung	0:e87aa4c49e95	1017
phungductung	0:e87aa4c49e95	1018	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
phungductung	0:e87aa4c49e95	1019	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
phungductung	0:e87aa4c49e95	1020
phungductung	0:e87aa4c49e95	1021	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
phungductung	0:e87aa4c49e95	1022	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
phungductung	0:e87aa4c49e95	1023
phungductung	0:e87aa4c49e95	1024	/@}/ /* end of group CMSIS_ITM */
phungductung	0:e87aa4c49e95	1025
phungductung	0:e87aa4c49e95	1026
phungductung	0:e87aa4c49e95	1027	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1028	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
phungductung	0:e87aa4c49e95	1029	\brief Type definitions for the Data Watchpoint and Trace (DWT)
phungductung	0:e87aa4c49e95	1030	@{
phungductung	0:e87aa4c49e95	1031	*/
phungductung	0:e87aa4c49e95	1032
phungductung	0:e87aa4c49e95	1033	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
phungductung	0:e87aa4c49e95	1034	*/
phungductung	0:e87aa4c49e95	1035	typedef struct
phungductung	0:e87aa4c49e95	1036	{
phungductung	0:e87aa4c49e95	1037	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
phungductung	0:e87aa4c49e95	1038	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
phungductung	0:e87aa4c49e95	1039	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
phungductung	0:e87aa4c49e95	1040	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
phungductung	0:e87aa4c49e95	1041	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
phungductung	0:e87aa4c49e95	1042	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
phungductung	0:e87aa4c49e95	1043	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
phungductung	0:e87aa4c49e95	1044	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
phungductung	0:e87aa4c49e95	1045	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
phungductung	0:e87aa4c49e95	1046	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
phungductung	0:e87aa4c49e95	1047	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
phungductung	0:e87aa4c49e95	1048	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	1049	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
phungductung	0:e87aa4c49e95	1050	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
phungductung	0:e87aa4c49e95	1051	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
phungductung	0:e87aa4c49e95	1052	uint32_t RESERVED1[1];
phungductung	0:e87aa4c49e95	1053	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
phungductung	0:e87aa4c49e95	1054	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
phungductung	0:e87aa4c49e95	1055	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
phungductung	0:e87aa4c49e95	1056	uint32_t RESERVED2[1];
phungductung	0:e87aa4c49e95	1057	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
phungductung	0:e87aa4c49e95	1058	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
phungductung	0:e87aa4c49e95	1059	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
phungductung	0:e87aa4c49e95	1060	uint32_t RESERVED3[981];
phungductung	0:e87aa4c49e95	1061	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
phungductung	0:e87aa4c49e95	1062	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
phungductung	0:e87aa4c49e95	1063	} DWT_Type;
phungductung	0:e87aa4c49e95	1064
phungductung	0:e87aa4c49e95	1065	/* DWT Control Register Definitions */
phungductung	0:e87aa4c49e95	1066	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
phungductung	0:e87aa4c49e95	1067	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
phungductung	0:e87aa4c49e95	1068
phungductung	0:e87aa4c49e95	1069	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
phungductung	0:e87aa4c49e95	1070	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
phungductung	0:e87aa4c49e95	1071
phungductung	0:e87aa4c49e95	1072	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
phungductung	0:e87aa4c49e95	1073	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
phungductung	0:e87aa4c49e95	1074
phungductung	0:e87aa4c49e95	1075	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
phungductung	0:e87aa4c49e95	1076	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
phungductung	0:e87aa4c49e95	1077
phungductung	0:e87aa4c49e95	1078	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
phungductung	0:e87aa4c49e95	1079	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
phungductung	0:e87aa4c49e95	1080
phungductung	0:e87aa4c49e95	1081	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
phungductung	0:e87aa4c49e95	1082	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
phungductung	0:e87aa4c49e95	1083
phungductung	0:e87aa4c49e95	1084	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
phungductung	0:e87aa4c49e95	1085	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
phungductung	0:e87aa4c49e95	1086
phungductung	0:e87aa4c49e95	1087	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
phungductung	0:e87aa4c49e95	1088	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
phungductung	0:e87aa4c49e95	1089
phungductung	0:e87aa4c49e95	1090	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
phungductung	0:e87aa4c49e95	1091	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
phungductung	0:e87aa4c49e95	1092
phungductung	0:e87aa4c49e95	1093	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
phungductung	0:e87aa4c49e95	1094	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
phungductung	0:e87aa4c49e95	1095
phungductung	0:e87aa4c49e95	1096	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
phungductung	0:e87aa4c49e95	1097	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
phungductung	0:e87aa4c49e95	1098
phungductung	0:e87aa4c49e95	1099	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
phungductung	0:e87aa4c49e95	1100	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
phungductung	0:e87aa4c49e95	1101
phungductung	0:e87aa4c49e95	1102	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
phungductung	0:e87aa4c49e95	1103	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
phungductung	0:e87aa4c49e95	1104
phungductung	0:e87aa4c49e95	1105	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
phungductung	0:e87aa4c49e95	1106	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
phungductung	0:e87aa4c49e95	1107
phungductung	0:e87aa4c49e95	1108	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
phungductung	0:e87aa4c49e95	1109	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
phungductung	0:e87aa4c49e95	1110
phungductung	0:e87aa4c49e95	1111	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
phungductung	0:e87aa4c49e95	1112	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
phungductung	0:e87aa4c49e95	1113
phungductung	0:e87aa4c49e95	1114	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
phungductung	0:e87aa4c49e95	1115	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
phungductung	0:e87aa4c49e95	1116
phungductung	0:e87aa4c49e95	1117	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
phungductung	0:e87aa4c49e95	1118	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
phungductung	0:e87aa4c49e95	1119
phungductung	0:e87aa4c49e95	1120	/* DWT CPI Count Register Definitions */
phungductung	0:e87aa4c49e95	1121	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
phungductung	0:e87aa4c49e95	1122	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
phungductung	0:e87aa4c49e95	1123
phungductung	0:e87aa4c49e95	1124	/* DWT Exception Overhead Count Register Definitions */
phungductung	0:e87aa4c49e95	1125	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
phungductung	0:e87aa4c49e95	1126	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
phungductung	0:e87aa4c49e95	1127
phungductung	0:e87aa4c49e95	1128	/* DWT Sleep Count Register Definitions */
phungductung	0:e87aa4c49e95	1129	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
phungductung	0:e87aa4c49e95	1130	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
phungductung	0:e87aa4c49e95	1131
phungductung	0:e87aa4c49e95	1132	/* DWT LSU Count Register Definitions */
phungductung	0:e87aa4c49e95	1133	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
phungductung	0:e87aa4c49e95	1134	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
phungductung	0:e87aa4c49e95	1135
phungductung	0:e87aa4c49e95	1136	/* DWT Folded-instruction Count Register Definitions */
phungductung	0:e87aa4c49e95	1137	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
phungductung	0:e87aa4c49e95	1138	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
phungductung	0:e87aa4c49e95	1139
phungductung	0:e87aa4c49e95	1140	/* DWT Comparator Mask Register Definitions */
phungductung	0:e87aa4c49e95	1141	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
phungductung	0:e87aa4c49e95	1142	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
phungductung	0:e87aa4c49e95	1143
phungductung	0:e87aa4c49e95	1144	/* DWT Comparator Function Register Definitions */
phungductung	0:e87aa4c49e95	1145	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
phungductung	0:e87aa4c49e95	1146	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
phungductung	0:e87aa4c49e95	1147
phungductung	0:e87aa4c49e95	1148	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
phungductung	0:e87aa4c49e95	1149	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
phungductung	0:e87aa4c49e95	1150
phungductung	0:e87aa4c49e95	1151	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
phungductung	0:e87aa4c49e95	1152	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
phungductung	0:e87aa4c49e95	1153
phungductung	0:e87aa4c49e95	1154	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
phungductung	0:e87aa4c49e95	1155	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
phungductung	0:e87aa4c49e95	1156
phungductung	0:e87aa4c49e95	1157	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
phungductung	0:e87aa4c49e95	1158	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
phungductung	0:e87aa4c49e95	1159
phungductung	0:e87aa4c49e95	1160	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
phungductung	0:e87aa4c49e95	1161	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
phungductung	0:e87aa4c49e95	1162
phungductung	0:e87aa4c49e95	1163	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
phungductung	0:e87aa4c49e95	1164	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
phungductung	0:e87aa4c49e95	1165
phungductung	0:e87aa4c49e95	1166	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
phungductung	0:e87aa4c49e95	1167	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
phungductung	0:e87aa4c49e95	1168
phungductung	0:e87aa4c49e95	1169	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
phungductung	0:e87aa4c49e95	1170	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
phungductung	0:e87aa4c49e95	1171
phungductung	0:e87aa4c49e95	1172	/@}/ /* end of group CMSIS_DWT */
phungductung	0:e87aa4c49e95	1173
phungductung	0:e87aa4c49e95	1174
phungductung	0:e87aa4c49e95	1175	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1176	\defgroup CMSIS_TPI Trace Port Interface (TPI)
phungductung	0:e87aa4c49e95	1177	\brief Type definitions for the Trace Port Interface (TPI)
phungductung	0:e87aa4c49e95	1178	@{
phungductung	0:e87aa4c49e95	1179	*/
phungductung	0:e87aa4c49e95	1180
phungductung	0:e87aa4c49e95	1181	/** \brief Structure type to access the Trace Port Interface Register (TPI).
phungductung	0:e87aa4c49e95	1182	*/
phungductung	0:e87aa4c49e95	1183	typedef struct
phungductung	0:e87aa4c49e95	1184	{
phungductung	0:e87aa4c49e95	1185	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
phungductung	0:e87aa4c49e95	1186	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
phungductung	0:e87aa4c49e95	1187	uint32_t RESERVED0[2];
phungductung	0:e87aa4c49e95	1188	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
phungductung	0:e87aa4c49e95	1189	uint32_t RESERVED1[55];
phungductung	0:e87aa4c49e95	1190	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
phungductung	0:e87aa4c49e95	1191	uint32_t RESERVED2[131];
phungductung	0:e87aa4c49e95	1192	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
phungductung	0:e87aa4c49e95	1193	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
phungductung	0:e87aa4c49e95	1194	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
phungductung	0:e87aa4c49e95	1195	uint32_t RESERVED3[759];
phungductung	0:e87aa4c49e95	1196	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
phungductung	0:e87aa4c49e95	1197	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
phungductung	0:e87aa4c49e95	1198	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
phungductung	0:e87aa4c49e95	1199	uint32_t RESERVED4[1];
phungductung	0:e87aa4c49e95	1200	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
phungductung	0:e87aa4c49e95	1201	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
phungductung	0:e87aa4c49e95	1202	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
phungductung	0:e87aa4c49e95	1203	uint32_t RESERVED5[39];
phungductung	0:e87aa4c49e95	1204	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
phungductung	0:e87aa4c49e95	1205	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
phungductung	0:e87aa4c49e95	1206	uint32_t RESERVED7[8];
phungductung	0:e87aa4c49e95	1207	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
phungductung	0:e87aa4c49e95	1208	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
phungductung	0:e87aa4c49e95	1209	} TPI_Type;
phungductung	0:e87aa4c49e95	1210
phungductung	0:e87aa4c49e95	1211	/* TPI Asynchronous Clock Prescaler Register Definitions */
phungductung	0:e87aa4c49e95	1212	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
phungductung	0:e87aa4c49e95	1213	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
phungductung	0:e87aa4c49e95	1214
phungductung	0:e87aa4c49e95	1215	/* TPI Selected Pin Protocol Register Definitions */
phungductung	0:e87aa4c49e95	1216	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
phungductung	0:e87aa4c49e95	1217	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
phungductung	0:e87aa4c49e95	1218
phungductung	0:e87aa4c49e95	1219	/* TPI Formatter and Flush Status Register Definitions */
phungductung	0:e87aa4c49e95	1220	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
phungductung	0:e87aa4c49e95	1221	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
phungductung	0:e87aa4c49e95	1222
phungductung	0:e87aa4c49e95	1223	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
phungductung	0:e87aa4c49e95	1224	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
phungductung	0:e87aa4c49e95	1225
phungductung	0:e87aa4c49e95	1226	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
phungductung	0:e87aa4c49e95	1227	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
phungductung	0:e87aa4c49e95	1228
phungductung	0:e87aa4c49e95	1229	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
phungductung	0:e87aa4c49e95	1230	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
phungductung	0:e87aa4c49e95	1231
phungductung	0:e87aa4c49e95	1232	/* TPI Formatter and Flush Control Register Definitions */
phungductung	0:e87aa4c49e95	1233	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
phungductung	0:e87aa4c49e95	1234	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
phungductung	0:e87aa4c49e95	1235
phungductung	0:e87aa4c49e95	1236	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
phungductung	0:e87aa4c49e95	1237	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
phungductung	0:e87aa4c49e95	1238
phungductung	0:e87aa4c49e95	1239	/* TPI TRIGGER Register Definitions */
phungductung	0:e87aa4c49e95	1240	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
phungductung	0:e87aa4c49e95	1241	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
phungductung	0:e87aa4c49e95	1242
phungductung	0:e87aa4c49e95	1243	/* TPI Integration ETM Data Register Definitions (FIFO0) */
phungductung	0:e87aa4c49e95	1244	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
phungductung	0:e87aa4c49e95	1245	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1246
phungductung	0:e87aa4c49e95	1247	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
phungductung	0:e87aa4c49e95	1248	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
phungductung	0:e87aa4c49e95	1249
phungductung	0:e87aa4c49e95	1250	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
phungductung	0:e87aa4c49e95	1251	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1252
phungductung	0:e87aa4c49e95	1253	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
phungductung	0:e87aa4c49e95	1254	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
phungductung	0:e87aa4c49e95	1255
phungductung	0:e87aa4c49e95	1256	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
phungductung	0:e87aa4c49e95	1257	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
phungductung	0:e87aa4c49e95	1258
phungductung	0:e87aa4c49e95	1259	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
phungductung	0:e87aa4c49e95	1260	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
phungductung	0:e87aa4c49e95	1261
phungductung	0:e87aa4c49e95	1262	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
phungductung	0:e87aa4c49e95	1263	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
phungductung	0:e87aa4c49e95	1264
phungductung	0:e87aa4c49e95	1265	/* TPI ITATBCTR2 Register Definitions */
phungductung	0:e87aa4c49e95	1266	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
phungductung	0:e87aa4c49e95	1267	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
phungductung	0:e87aa4c49e95	1268
phungductung	0:e87aa4c49e95	1269	/* TPI Integration ITM Data Register Definitions (FIFO1) */
phungductung	0:e87aa4c49e95	1270	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
phungductung	0:e87aa4c49e95	1271	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1272
phungductung	0:e87aa4c49e95	1273	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
phungductung	0:e87aa4c49e95	1274	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
phungductung	0:e87aa4c49e95	1275
phungductung	0:e87aa4c49e95	1276	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
phungductung	0:e87aa4c49e95	1277	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1278
phungductung	0:e87aa4c49e95	1279	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
phungductung	0:e87aa4c49e95	1280	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
phungductung	0:e87aa4c49e95	1281
phungductung	0:e87aa4c49e95	1282	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
phungductung	0:e87aa4c49e95	1283	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
phungductung	0:e87aa4c49e95	1284
phungductung	0:e87aa4c49e95	1285	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
phungductung	0:e87aa4c49e95	1286	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
phungductung	0:e87aa4c49e95	1287
phungductung	0:e87aa4c49e95	1288	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
phungductung	0:e87aa4c49e95	1289	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
phungductung	0:e87aa4c49e95	1290
phungductung	0:e87aa4c49e95	1291	/* TPI ITATBCTR0 Register Definitions */
phungductung	0:e87aa4c49e95	1292	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
phungductung	0:e87aa4c49e95	1293	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
phungductung	0:e87aa4c49e95	1294
phungductung	0:e87aa4c49e95	1295	/* TPI Integration Mode Control Register Definitions */
phungductung	0:e87aa4c49e95	1296	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
phungductung	0:e87aa4c49e95	1297	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
phungductung	0:e87aa4c49e95	1298
phungductung	0:e87aa4c49e95	1299	/* TPI DEVID Register Definitions */
phungductung	0:e87aa4c49e95	1300	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
phungductung	0:e87aa4c49e95	1301	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
phungductung	0:e87aa4c49e95	1302
phungductung	0:e87aa4c49e95	1303	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
phungductung	0:e87aa4c49e95	1304	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
phungductung	0:e87aa4c49e95	1305
phungductung	0:e87aa4c49e95	1306	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
phungductung	0:e87aa4c49e95	1307	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
phungductung	0:e87aa4c49e95	1308
phungductung	0:e87aa4c49e95	1309	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
phungductung	0:e87aa4c49e95	1310	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
phungductung	0:e87aa4c49e95	1311
phungductung	0:e87aa4c49e95	1312	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
phungductung	0:e87aa4c49e95	1313	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
phungductung	0:e87aa4c49e95	1314
phungductung	0:e87aa4c49e95	1315	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
phungductung	0:e87aa4c49e95	1316	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
phungductung	0:e87aa4c49e95	1317
phungductung	0:e87aa4c49e95	1318	/* TPI DEVTYPE Register Definitions */
phungductung	0:e87aa4c49e95	1319	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
phungductung	0:e87aa4c49e95	1320	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
phungductung	0:e87aa4c49e95	1321
phungductung	0:e87aa4c49e95	1322	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
phungductung	0:e87aa4c49e95	1323	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
phungductung	0:e87aa4c49e95	1324
phungductung	0:e87aa4c49e95	1325	/@}/ /* end of group CMSIS_TPI */
phungductung	0:e87aa4c49e95	1326
phungductung	0:e87aa4c49e95	1327
phungductung	0:e87aa4c49e95	1328	#if (__MPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1329	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1330	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
phungductung	0:e87aa4c49e95	1331	\brief Type definitions for the Memory Protection Unit (MPU)
phungductung	0:e87aa4c49e95	1332	@{
phungductung	0:e87aa4c49e95	1333	*/
phungductung	0:e87aa4c49e95	1334
phungductung	0:e87aa4c49e95	1335	/** \brief Structure type to access the Memory Protection Unit (MPU).
phungductung	0:e87aa4c49e95	1336	*/
phungductung	0:e87aa4c49e95	1337	typedef struct
phungductung	0:e87aa4c49e95	1338	{
phungductung	0:e87aa4c49e95	1339	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
phungductung	0:e87aa4c49e95	1340	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
phungductung	0:e87aa4c49e95	1341	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
phungductung	0:e87aa4c49e95	1342	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
phungductung	0:e87aa4c49e95	1343	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1344	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
phungductung	0:e87aa4c49e95	1345	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1346	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
phungductung	0:e87aa4c49e95	1347	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1348	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
phungductung	0:e87aa4c49e95	1349	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1350	} MPU_Type;
phungductung	0:e87aa4c49e95	1351
phungductung	0:e87aa4c49e95	1352	/* MPU Type Register */
phungductung	0:e87aa4c49e95	1353	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
phungductung	0:e87aa4c49e95	1354	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
phungductung	0:e87aa4c49e95	1355
phungductung	0:e87aa4c49e95	1356	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
phungductung	0:e87aa4c49e95	1357	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
phungductung	0:e87aa4c49e95	1358
phungductung	0:e87aa4c49e95	1359	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
phungductung	0:e87aa4c49e95	1360	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
phungductung	0:e87aa4c49e95	1361
phungductung	0:e87aa4c49e95	1362	/* MPU Control Register */
phungductung	0:e87aa4c49e95	1363	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
phungductung	0:e87aa4c49e95	1364	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
phungductung	0:e87aa4c49e95	1365
phungductung	0:e87aa4c49e95	1366	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
phungductung	0:e87aa4c49e95	1367	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
phungductung	0:e87aa4c49e95	1368
phungductung	0:e87aa4c49e95	1369	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
phungductung	0:e87aa4c49e95	1370	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
phungductung	0:e87aa4c49e95	1371
phungductung	0:e87aa4c49e95	1372	/* MPU Region Number Register */
phungductung	0:e87aa4c49e95	1373	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
phungductung	0:e87aa4c49e95	1374	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
phungductung	0:e87aa4c49e95	1375
phungductung	0:e87aa4c49e95	1376	/* MPU Region Base Address Register */
phungductung	0:e87aa4c49e95	1377	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
phungductung	0:e87aa4c49e95	1378	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
phungductung	0:e87aa4c49e95	1379
phungductung	0:e87aa4c49e95	1380	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
phungductung	0:e87aa4c49e95	1381	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
phungductung	0:e87aa4c49e95	1382
phungductung	0:e87aa4c49e95	1383	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
phungductung	0:e87aa4c49e95	1384	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
phungductung	0:e87aa4c49e95	1385
phungductung	0:e87aa4c49e95	1386	/* MPU Region Attribute and Size Register */
phungductung	0:e87aa4c49e95	1387	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
phungductung	0:e87aa4c49e95	1388	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
phungductung	0:e87aa4c49e95	1389
phungductung	0:e87aa4c49e95	1390	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
phungductung	0:e87aa4c49e95	1391	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
phungductung	0:e87aa4c49e95	1392
phungductung	0:e87aa4c49e95	1393	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
phungductung	0:e87aa4c49e95	1394	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
phungductung	0:e87aa4c49e95	1395
phungductung	0:e87aa4c49e95	1396	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
phungductung	0:e87aa4c49e95	1397	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
phungductung	0:e87aa4c49e95	1398
phungductung	0:e87aa4c49e95	1399	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
phungductung	0:e87aa4c49e95	1400	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
phungductung	0:e87aa4c49e95	1401
phungductung	0:e87aa4c49e95	1402	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
phungductung	0:e87aa4c49e95	1403	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
phungductung	0:e87aa4c49e95	1404
phungductung	0:e87aa4c49e95	1405	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
phungductung	0:e87aa4c49e95	1406	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
phungductung	0:e87aa4c49e95	1407
phungductung	0:e87aa4c49e95	1408	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
phungductung	0:e87aa4c49e95	1409	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
phungductung	0:e87aa4c49e95	1410
phungductung	0:e87aa4c49e95	1411	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
phungductung	0:e87aa4c49e95	1412	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
phungductung	0:e87aa4c49e95	1413
phungductung	0:e87aa4c49e95	1414	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
phungductung	0:e87aa4c49e95	1415	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
phungductung	0:e87aa4c49e95	1416
phungductung	0:e87aa4c49e95	1417	/@} end of group CMSIS_MPU /
phungductung	0:e87aa4c49e95	1418	#endif
phungductung	0:e87aa4c49e95	1419
phungductung	0:e87aa4c49e95	1420
phungductung	0:e87aa4c49e95	1421	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1422	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1423	\defgroup CMSIS_FPU Floating Point Unit (FPU)
phungductung	0:e87aa4c49e95	1424	\brief Type definitions for the Floating Point Unit (FPU)
phungductung	0:e87aa4c49e95	1425	@{
phungductung	0:e87aa4c49e95	1426	*/
phungductung	0:e87aa4c49e95	1427
phungductung	0:e87aa4c49e95	1428	/** \brief Structure type to access the Floating Point Unit (FPU).
phungductung	0:e87aa4c49e95	1429	*/
phungductung	0:e87aa4c49e95	1430	typedef struct
phungductung	0:e87aa4c49e95	1431	{
phungductung	0:e87aa4c49e95	1432	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	1433	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
phungductung	0:e87aa4c49e95	1434	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
phungductung	0:e87aa4c49e95	1435	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
phungductung	0:e87aa4c49e95	1436	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
phungductung	0:e87aa4c49e95	1437	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
phungductung	0:e87aa4c49e95	1438	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
phungductung	0:e87aa4c49e95	1439	} FPU_Type;
phungductung	0:e87aa4c49e95	1440
phungductung	0:e87aa4c49e95	1441	/* Floating-Point Context Control Register */
phungductung	0:e87aa4c49e95	1442	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
phungductung	0:e87aa4c49e95	1443	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
phungductung	0:e87aa4c49e95	1444
phungductung	0:e87aa4c49e95	1445	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
phungductung	0:e87aa4c49e95	1446	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
phungductung	0:e87aa4c49e95	1447
phungductung	0:e87aa4c49e95	1448	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
phungductung	0:e87aa4c49e95	1449	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
phungductung	0:e87aa4c49e95	1450
phungductung	0:e87aa4c49e95	1451	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
phungductung	0:e87aa4c49e95	1452	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
phungductung	0:e87aa4c49e95	1453
phungductung	0:e87aa4c49e95	1454	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
phungductung	0:e87aa4c49e95	1455	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
phungductung	0:e87aa4c49e95	1456
phungductung	0:e87aa4c49e95	1457	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
phungductung	0:e87aa4c49e95	1458	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
phungductung	0:e87aa4c49e95	1459
phungductung	0:e87aa4c49e95	1460	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
phungductung	0:e87aa4c49e95	1461	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
phungductung	0:e87aa4c49e95	1462
phungductung	0:e87aa4c49e95	1463	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
phungductung	0:e87aa4c49e95	1464	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
phungductung	0:e87aa4c49e95	1465
phungductung	0:e87aa4c49e95	1466	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
phungductung	0:e87aa4c49e95	1467	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
phungductung	0:e87aa4c49e95	1468
phungductung	0:e87aa4c49e95	1469	/* Floating-Point Context Address Register */
phungductung	0:e87aa4c49e95	1470	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
phungductung	0:e87aa4c49e95	1471	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
phungductung	0:e87aa4c49e95	1472
phungductung	0:e87aa4c49e95	1473	/* Floating-Point Default Status Control Register */
phungductung	0:e87aa4c49e95	1474	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
phungductung	0:e87aa4c49e95	1475	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
phungductung	0:e87aa4c49e95	1476
phungductung	0:e87aa4c49e95	1477	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
phungductung	0:e87aa4c49e95	1478	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
phungductung	0:e87aa4c49e95	1479
phungductung	0:e87aa4c49e95	1480	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
phungductung	0:e87aa4c49e95	1481	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
phungductung	0:e87aa4c49e95	1482
phungductung	0:e87aa4c49e95	1483	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
phungductung	0:e87aa4c49e95	1484	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
phungductung	0:e87aa4c49e95	1485
phungductung	0:e87aa4c49e95	1486	/* Media and FP Feature Register 0 */
phungductung	0:e87aa4c49e95	1487	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
phungductung	0:e87aa4c49e95	1488	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
phungductung	0:e87aa4c49e95	1489
phungductung	0:e87aa4c49e95	1490	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
phungductung	0:e87aa4c49e95	1491	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
phungductung	0:e87aa4c49e95	1492
phungductung	0:e87aa4c49e95	1493	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
phungductung	0:e87aa4c49e95	1494	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
phungductung	0:e87aa4c49e95	1495
phungductung	0:e87aa4c49e95	1496	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
phungductung	0:e87aa4c49e95	1497	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
phungductung	0:e87aa4c49e95	1498
phungductung	0:e87aa4c49e95	1499	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
phungductung	0:e87aa4c49e95	1500	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
phungductung	0:e87aa4c49e95	1501
phungductung	0:e87aa4c49e95	1502	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
phungductung	0:e87aa4c49e95	1503	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
phungductung	0:e87aa4c49e95	1504
phungductung	0:e87aa4c49e95	1505	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
phungductung	0:e87aa4c49e95	1506	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
phungductung	0:e87aa4c49e95	1507
phungductung	0:e87aa4c49e95	1508	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
phungductung	0:e87aa4c49e95	1509	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
phungductung	0:e87aa4c49e95	1510
phungductung	0:e87aa4c49e95	1511	/* Media and FP Feature Register 1 */
phungductung	0:e87aa4c49e95	1512	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
phungductung	0:e87aa4c49e95	1513	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
phungductung	0:e87aa4c49e95	1514
phungductung	0:e87aa4c49e95	1515	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
phungductung	0:e87aa4c49e95	1516	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
phungductung	0:e87aa4c49e95	1517
phungductung	0:e87aa4c49e95	1518	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
phungductung	0:e87aa4c49e95	1519	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
phungductung	0:e87aa4c49e95	1520
phungductung	0:e87aa4c49e95	1521	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
phungductung	0:e87aa4c49e95	1522	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
phungductung	0:e87aa4c49e95	1523
phungductung	0:e87aa4c49e95	1524	/* Media and FP Feature Register 2 */
phungductung	0:e87aa4c49e95	1525
phungductung	0:e87aa4c49e95	1526	/@} end of group CMSIS_FPU /
phungductung	0:e87aa4c49e95	1527	#endif
phungductung	0:e87aa4c49e95	1528
phungductung	0:e87aa4c49e95	1529
phungductung	0:e87aa4c49e95	1530	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1531	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
phungductung	0:e87aa4c49e95	1532	\brief Type definitions for the Core Debug Registers
phungductung	0:e87aa4c49e95	1533	@{
phungductung	0:e87aa4c49e95	1534	*/
phungductung	0:e87aa4c49e95	1535
phungductung	0:e87aa4c49e95	1536	/** \brief Structure type to access the Core Debug Register (CoreDebug).
phungductung	0:e87aa4c49e95	1537	*/
phungductung	0:e87aa4c49e95	1538	typedef struct
phungductung	0:e87aa4c49e95	1539	{
phungductung	0:e87aa4c49e95	1540	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
phungductung	0:e87aa4c49e95	1541	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
phungductung	0:e87aa4c49e95	1542	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
phungductung	0:e87aa4c49e95	1543	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
phungductung	0:e87aa4c49e95	1544	} CoreDebug_Type;
phungductung	0:e87aa4c49e95	1545
phungductung	0:e87aa4c49e95	1546	/* Debug Halting Control and Status Register */
phungductung	0:e87aa4c49e95	1547	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
phungductung	0:e87aa4c49e95	1548	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
phungductung	0:e87aa4c49e95	1549
phungductung	0:e87aa4c49e95	1550	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
phungductung	0:e87aa4c49e95	1551	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
phungductung	0:e87aa4c49e95	1552
phungductung	0:e87aa4c49e95	1553	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
phungductung	0:e87aa4c49e95	1554	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
phungductung	0:e87aa4c49e95	1555
phungductung	0:e87aa4c49e95	1556	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
phungductung	0:e87aa4c49e95	1557	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
phungductung	0:e87aa4c49e95	1558
phungductung	0:e87aa4c49e95	1559	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
phungductung	0:e87aa4c49e95	1560	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
phungductung	0:e87aa4c49e95	1561
phungductung	0:e87aa4c49e95	1562	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
phungductung	0:e87aa4c49e95	1563	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
phungductung	0:e87aa4c49e95	1564
phungductung	0:e87aa4c49e95	1565	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
phungductung	0:e87aa4c49e95	1566	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
phungductung	0:e87aa4c49e95	1567
phungductung	0:e87aa4c49e95	1568	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
phungductung	0:e87aa4c49e95	1569	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
phungductung	0:e87aa4c49e95	1570
phungductung	0:e87aa4c49e95	1571	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
phungductung	0:e87aa4c49e95	1572	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
phungductung	0:e87aa4c49e95	1573
phungductung	0:e87aa4c49e95	1574	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
phungductung	0:e87aa4c49e95	1575	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
phungductung	0:e87aa4c49e95	1576
phungductung	0:e87aa4c49e95	1577	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
phungductung	0:e87aa4c49e95	1578	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
phungductung	0:e87aa4c49e95	1579
phungductung	0:e87aa4c49e95	1580	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
phungductung	0:e87aa4c49e95	1581	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
phungductung	0:e87aa4c49e95	1582
phungductung	0:e87aa4c49e95	1583	/* Debug Core Register Selector Register */
phungductung	0:e87aa4c49e95	1584	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
phungductung	0:e87aa4c49e95	1585	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
phungductung	0:e87aa4c49e95	1586
phungductung	0:e87aa4c49e95	1587	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
phungductung	0:e87aa4c49e95	1588	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
phungductung	0:e87aa4c49e95	1589
phungductung	0:e87aa4c49e95	1590	/* Debug Exception and Monitor Control Register */
phungductung	0:e87aa4c49e95	1591	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
phungductung	0:e87aa4c49e95	1592	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
phungductung	0:e87aa4c49e95	1593
phungductung	0:e87aa4c49e95	1594	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
phungductung	0:e87aa4c49e95	1595	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
phungductung	0:e87aa4c49e95	1596
phungductung	0:e87aa4c49e95	1597	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
phungductung	0:e87aa4c49e95	1598	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
phungductung	0:e87aa4c49e95	1599
phungductung	0:e87aa4c49e95	1600	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
phungductung	0:e87aa4c49e95	1601	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
phungductung	0:e87aa4c49e95	1602
phungductung	0:e87aa4c49e95	1603	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
phungductung	0:e87aa4c49e95	1604	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
phungductung	0:e87aa4c49e95	1605
phungductung	0:e87aa4c49e95	1606	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
phungductung	0:e87aa4c49e95	1607	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
phungductung	0:e87aa4c49e95	1608
phungductung	0:e87aa4c49e95	1609	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
phungductung	0:e87aa4c49e95	1610	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
phungductung	0:e87aa4c49e95	1611
phungductung	0:e87aa4c49e95	1612	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
phungductung	0:e87aa4c49e95	1613	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
phungductung	0:e87aa4c49e95	1614
phungductung	0:e87aa4c49e95	1615	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
phungductung	0:e87aa4c49e95	1616	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
phungductung	0:e87aa4c49e95	1617
phungductung	0:e87aa4c49e95	1618	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
phungductung	0:e87aa4c49e95	1619	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
phungductung	0:e87aa4c49e95	1620
phungductung	0:e87aa4c49e95	1621	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
phungductung	0:e87aa4c49e95	1622	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
phungductung	0:e87aa4c49e95	1623
phungductung	0:e87aa4c49e95	1624	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
phungductung	0:e87aa4c49e95	1625	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
phungductung	0:e87aa4c49e95	1626
phungductung	0:e87aa4c49e95	1627	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
phungductung	0:e87aa4c49e95	1628	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
phungductung	0:e87aa4c49e95	1629
phungductung	0:e87aa4c49e95	1630	/@} end of group CMSIS_CoreDebug /
phungductung	0:e87aa4c49e95	1631
phungductung	0:e87aa4c49e95	1632
phungductung	0:e87aa4c49e95	1633	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1634	\defgroup CMSIS_core_base Core Definitions
phungductung	0:e87aa4c49e95	1635	\brief Definitions for base addresses, unions, and structures.
phungductung	0:e87aa4c49e95	1636	@{
phungductung	0:e87aa4c49e95	1637	*/
phungductung	0:e87aa4c49e95	1638
phungductung	0:e87aa4c49e95	1639	/* Memory mapping of Cortex-M4 Hardware */
phungductung	0:e87aa4c49e95	1640	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
phungductung	0:e87aa4c49e95	1641	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
phungductung	0:e87aa4c49e95	1642	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
phungductung	0:e87aa4c49e95	1643	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
phungductung	0:e87aa4c49e95	1644	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
phungductung	0:e87aa4c49e95	1645	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
phungductung	0:e87aa4c49e95	1646	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
phungductung	0:e87aa4c49e95	1647	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
phungductung	0:e87aa4c49e95	1648
phungductung	0:e87aa4c49e95	1649	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
phungductung	0:e87aa4c49e95	1650	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
phungductung	0:e87aa4c49e95	1651	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
phungductung	0:e87aa4c49e95	1652	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
phungductung	0:e87aa4c49e95	1653	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
phungductung	0:e87aa4c49e95	1654	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
phungductung	0:e87aa4c49e95	1655	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
phungductung	0:e87aa4c49e95	1656	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
phungductung	0:e87aa4c49e95	1657
phungductung	0:e87aa4c49e95	1658	#if (__MPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1659	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
phungductung	0:e87aa4c49e95	1660	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
phungductung	0:e87aa4c49e95	1661	#endif
phungductung	0:e87aa4c49e95	1662
phungductung	0:e87aa4c49e95	1663	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1664	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
phungductung	0:e87aa4c49e95	1665	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
phungductung	0:e87aa4c49e95	1666	#endif
phungductung	0:e87aa4c49e95	1667
phungductung	0:e87aa4c49e95	1668	/@} /
phungductung	0:e87aa4c49e95	1669
phungductung	0:e87aa4c49e95	1670
phungductung	0:e87aa4c49e95	1671
phungductung	0:e87aa4c49e95	1672	/*******************************************************************************
phungductung	0:e87aa4c49e95	1673	* Hardware Abstraction Layer
phungductung	0:e87aa4c49e95	1674	Core Function Interface contains:
phungductung	0:e87aa4c49e95	1675	- Core NVIC Functions
phungductung	0:e87aa4c49e95	1676	- Core SysTick Functions
phungductung	0:e87aa4c49e95	1677	- Core Debug Functions
phungductung	0:e87aa4c49e95	1678	- Core Register Access Functions
phungductung	0:e87aa4c49e95	1679	******************************************************************************/
phungductung	0:e87aa4c49e95	1680	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
phungductung	0:e87aa4c49e95	1681	*/
phungductung	0:e87aa4c49e95	1682
phungductung	0:e87aa4c49e95	1683
phungductung	0:e87aa4c49e95	1684
phungductung	0:e87aa4c49e95	1685	/* ########################## NVIC functions #################################### */
phungductung	0:e87aa4c49e95	1686	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	1687	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
phungductung	0:e87aa4c49e95	1688	\brief Functions that manage interrupts and exceptions via the NVIC.
phungductung	0:e87aa4c49e95	1689	@{
phungductung	0:e87aa4c49e95	1690	*/
phungductung	0:e87aa4c49e95	1691
phungductung	0:e87aa4c49e95	1692	/** \brief Set Priority Grouping
phungductung	0:e87aa4c49e95	1693
phungductung	0:e87aa4c49e95	1694	The function sets the priority grouping field using the required unlock sequence.
phungductung	0:e87aa4c49e95	1695	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
phungductung	0:e87aa4c49e95	1696	Only values from 0..7 are used.
phungductung	0:e87aa4c49e95	1697	In case of a conflict between priority grouping and available
phungductung	0:e87aa4c49e95	1698	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
phungductung	0:e87aa4c49e95	1699
phungductung	0:e87aa4c49e95	1700	\param [in] PriorityGroup Priority grouping field.
phungductung	0:e87aa4c49e95	1701	*/
phungductung	0:e87aa4c49e95	1702	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
phungductung	0:e87aa4c49e95	1703	{
phungductung	0:e87aa4c49e95	1704	uint32_t reg_value;
phungductung	0:e87aa4c49e95	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung	0:e87aa4c49e95	1706
phungductung	0:e87aa4c49e95	1707	reg_value = SCB->AIRCR; /* read old register configuration */
phungductung	0:e87aa4c49e95	1708	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
phungductung	0:e87aa4c49e95	1709	reg_value = (reg_value \|
phungductung	0:e87aa4c49e95	1710	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
phungductung	0:e87aa4c49e95	1711	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
phungductung	0:e87aa4c49e95	1712	SCB->AIRCR = reg_value;
phungductung	0:e87aa4c49e95	1713	}
phungductung	0:e87aa4c49e95	1714
phungductung	0:e87aa4c49e95	1715
phungductung	0:e87aa4c49e95	1716	/** \brief Get Priority Grouping
phungductung	0:e87aa4c49e95	1717
phungductung	0:e87aa4c49e95	1718	The function reads the priority grouping field from the NVIC Interrupt Controller.
phungductung	0:e87aa4c49e95	1719
phungductung	0:e87aa4c49e95	1720	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
phungductung	0:e87aa4c49e95	1721	*/
phungductung	0:e87aa4c49e95	1722	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
phungductung	0:e87aa4c49e95	1723	{
phungductung	0:e87aa4c49e95	1724	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
phungductung	0:e87aa4c49e95	1725	}
phungductung	0:e87aa4c49e95	1726
phungductung	0:e87aa4c49e95	1727
phungductung	0:e87aa4c49e95	1728	/** \brief Enable External Interrupt
phungductung	0:e87aa4c49e95	1729
phungductung	0:e87aa4c49e95	1730	The function enables a device-specific interrupt in the NVIC interrupt controller.
phungductung	0:e87aa4c49e95	1731
phungductung	0:e87aa4c49e95	1732	\param [in] IRQn External interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1733	*/
phungductung	0:e87aa4c49e95	1734	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1735	{
phungductung	0:e87aa4c49e95	1736	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1737	}
phungductung	0:e87aa4c49e95	1738
phungductung	0:e87aa4c49e95	1739
phungductung	0:e87aa4c49e95	1740	/** \brief Disable External Interrupt
phungductung	0:e87aa4c49e95	1741
phungductung	0:e87aa4c49e95	1742	The function disables a device-specific interrupt in the NVIC interrupt controller.
phungductung	0:e87aa4c49e95	1743
phungductung	0:e87aa4c49e95	1744	\param [in] IRQn External interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1745	*/
phungductung	0:e87aa4c49e95	1746	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1747	{
phungductung	0:e87aa4c49e95	1748	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1749	}
phungductung	0:e87aa4c49e95	1750
phungductung	0:e87aa4c49e95	1751
phungductung	0:e87aa4c49e95	1752	/** \brief Get Pending Interrupt
phungductung	0:e87aa4c49e95	1753
phungductung	0:e87aa4c49e95	1754	The function reads the pending register in the NVIC and returns the pending bit
phungductung	0:e87aa4c49e95	1755	for the specified interrupt.
phungductung	0:e87aa4c49e95	1756
phungductung	0:e87aa4c49e95	1757	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1758
phungductung	0:e87aa4c49e95	1759	\return 0 Interrupt status is not pending.
phungductung	0:e87aa4c49e95	1760	\return 1 Interrupt status is pending.
phungductung	0:e87aa4c49e95	1761	*/
phungductung	0:e87aa4c49e95	1762	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1763	{
phungductung	0:e87aa4c49e95	1764	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung	0:e87aa4c49e95	1765	}
phungductung	0:e87aa4c49e95	1766
phungductung	0:e87aa4c49e95	1767
phungductung	0:e87aa4c49e95	1768	/** \brief Set Pending Interrupt
phungductung	0:e87aa4c49e95	1769
phungductung	0:e87aa4c49e95	1770	The function sets the pending bit of an external interrupt.
phungductung	0:e87aa4c49e95	1771
phungductung	0:e87aa4c49e95	1772	\param [in] IRQn Interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1773	*/
phungductung	0:e87aa4c49e95	1774	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1775	{
phungductung	0:e87aa4c49e95	1776	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1777	}
phungductung	0:e87aa4c49e95	1778
phungductung	0:e87aa4c49e95	1779
phungductung	0:e87aa4c49e95	1780	/** \brief Clear Pending Interrupt
phungductung	0:e87aa4c49e95	1781
phungductung	0:e87aa4c49e95	1782	The function clears the pending bit of an external interrupt.
phungductung	0:e87aa4c49e95	1783
phungductung	0:e87aa4c49e95	1784	\param [in] IRQn External interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1785	*/
phungductung	0:e87aa4c49e95	1786	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1787	{
phungductung	0:e87aa4c49e95	1788	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1789	}
phungductung	0:e87aa4c49e95	1790
phungductung	0:e87aa4c49e95	1791
phungductung	0:e87aa4c49e95	1792	/** \brief Get Active Interrupt
phungductung	0:e87aa4c49e95	1793
phungductung	0:e87aa4c49e95	1794	The function reads the active register in NVIC and returns the active bit.
phungductung	0:e87aa4c49e95	1795
phungductung	0:e87aa4c49e95	1796	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1797
phungductung	0:e87aa4c49e95	1798	\return 0 Interrupt status is not active.
phungductung	0:e87aa4c49e95	1799	\return 1 Interrupt status is active.
phungductung	0:e87aa4c49e95	1800	*/
phungductung	0:e87aa4c49e95	1801	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1802	{
phungductung	0:e87aa4c49e95	1803	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung	0:e87aa4c49e95	1804	}
phungductung	0:e87aa4c49e95	1805
phungductung	0:e87aa4c49e95	1806
phungductung	0:e87aa4c49e95	1807	/** \brief Set Interrupt Priority
phungductung	0:e87aa4c49e95	1808
phungductung	0:e87aa4c49e95	1809	The function sets the priority of an interrupt.
phungductung	0:e87aa4c49e95	1810
phungductung	0:e87aa4c49e95	1811	\note The priority cannot be set for every core interrupt.
phungductung	0:e87aa4c49e95	1812
phungductung	0:e87aa4c49e95	1813	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1814	\param [in] priority Priority to set.
phungductung	0:e87aa4c49e95	1815	*/
phungductung	0:e87aa4c49e95	1816	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
phungductung	0:e87aa4c49e95	1817	{
phungductung	0:e87aa4c49e95	1818	if((int32_t)IRQn < 0) {
phungductung	0:e87aa4c49e95	1819	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
phungductung	0:e87aa4c49e95	1820	}
phungductung	0:e87aa4c49e95	1821	else {
phungductung	0:e87aa4c49e95	1822	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
phungductung	0:e87aa4c49e95	1823	}
phungductung	0:e87aa4c49e95	1824	}
phungductung	0:e87aa4c49e95	1825
phungductung	0:e87aa4c49e95	1826
phungductung	0:e87aa4c49e95	1827	/** \brief Get Interrupt Priority
phungductung	0:e87aa4c49e95	1828
phungductung	0:e87aa4c49e95	1829	The function reads the priority of an interrupt. The interrupt
phungductung	0:e87aa4c49e95	1830	number can be positive to specify an external (device specific)
phungductung	0:e87aa4c49e95	1831	interrupt, or negative to specify an internal (core) interrupt.
phungductung	0:e87aa4c49e95	1832
phungductung	0:e87aa4c49e95	1833
phungductung	0:e87aa4c49e95	1834	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1835	\return Interrupt Priority. Value is aligned automatically to the implemented
phungductung	0:e87aa4c49e95	1836	priority bits of the microcontroller.
phungductung	0:e87aa4c49e95	1837	*/
phungductung	0:e87aa4c49e95	1838	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1839	{
phungductung	0:e87aa4c49e95	1840
phungductung	0:e87aa4c49e95	1841	if((int32_t)IRQn < 0) {
phungductung	0:e87aa4c49e95	1842	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
phungductung	0:e87aa4c49e95	1843	}
phungductung	0:e87aa4c49e95	1844	else {
phungductung	0:e87aa4c49e95	1845	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
phungductung	0:e87aa4c49e95	1846	}
phungductung	0:e87aa4c49e95	1847	}
phungductung	0:e87aa4c49e95	1848
phungductung	0:e87aa4c49e95	1849
phungductung	0:e87aa4c49e95	1850	/** \brief Encode Priority
phungductung	0:e87aa4c49e95	1851
phungductung	0:e87aa4c49e95	1852	The function encodes the priority for an interrupt with the given priority group,
phungductung	0:e87aa4c49e95	1853	preemptive priority value, and subpriority value.
phungductung	0:e87aa4c49e95	1854	In case of a conflict between priority grouping and available
phungductung	0:e87aa4c49e95	1855	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
phungductung	0:e87aa4c49e95	1856
phungductung	0:e87aa4c49e95	1857	\param [in] PriorityGroup Used priority group.
phungductung	0:e87aa4c49e95	1858	\param [in] PreemptPriority Preemptive priority value (starting from 0).
phungductung	0:e87aa4c49e95	1859	\param [in] SubPriority Subpriority value (starting from 0).
phungductung	0:e87aa4c49e95	1860	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
phungductung	0:e87aa4c49e95	1861	*/
phungductung	0:e87aa4c49e95	1862	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
phungductung	0:e87aa4c49e95	1863	{
phungductung	0:e87aa4c49e95	1864	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung	0:e87aa4c49e95	1865	uint32_t PreemptPriorityBits;
phungductung	0:e87aa4c49e95	1866	uint32_t SubPriorityBits;
phungductung	0:e87aa4c49e95	1867
phungductung	0:e87aa4c49e95	1868	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
phungductung	0:e87aa4c49e95	1869	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
phungductung	0:e87aa4c49e95	1870
phungductung	0:e87aa4c49e95	1871	return (
phungductung	0:e87aa4c49e95	1872	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
phungductung	0:e87aa4c49e95	1873	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
phungductung	0:e87aa4c49e95	1874	);
phungductung	0:e87aa4c49e95	1875	}
phungductung	0:e87aa4c49e95	1876
phungductung	0:e87aa4c49e95	1877
phungductung	0:e87aa4c49e95	1878	/** \brief Decode Priority
phungductung	0:e87aa4c49e95	1879
phungductung	0:e87aa4c49e95	1880	The function decodes an interrupt priority value with a given priority group to
phungductung	0:e87aa4c49e95	1881	preemptive priority value and subpriority value.
phungductung	0:e87aa4c49e95	1882	In case of a conflict between priority grouping and available
phungductung	0:e87aa4c49e95	1883	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
phungductung	0:e87aa4c49e95	1884
phungductung	0:e87aa4c49e95	1885	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
phungductung	0:e87aa4c49e95	1886	\param [in] PriorityGroup Used priority group.
phungductung	0:e87aa4c49e95	1887	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
phungductung	0:e87aa4c49e95	1888	\param [out] pSubPriority Subpriority value (starting from 0).
phungductung	0:e87aa4c49e95	1889	*/
phungductung	0:e87aa4c49e95	1890	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
phungductung	0:e87aa4c49e95	1891	{
phungductung	0:e87aa4c49e95	1892	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung	0:e87aa4c49e95	1893	uint32_t PreemptPriorityBits;
phungductung	0:e87aa4c49e95	1894	uint32_t SubPriorityBits;
phungductung	0:e87aa4c49e95	1895
phungductung	0:e87aa4c49e95	1896	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
phungductung	0:e87aa4c49e95	1897	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
phungductung	0:e87aa4c49e95	1898
phungductung	0:e87aa4c49e95	1899	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
phungductung	0:e87aa4c49e95	1900	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
phungductung	0:e87aa4c49e95	1901	}
phungductung	0:e87aa4c49e95	1902
phungductung	0:e87aa4c49e95	1903
phungductung	0:e87aa4c49e95	1904	/** \brief System Reset
phungductung	0:e87aa4c49e95	1905
phungductung	0:e87aa4c49e95	1906	The function initiates a system reset request to reset the MCU.
phungductung	0:e87aa4c49e95	1907	*/
phungductung	0:e87aa4c49e95	1908	__STATIC_INLINE void NVIC_SystemReset(void)
phungductung	0:e87aa4c49e95	1909	{
phungductung	0:e87aa4c49e95	1910	__DSB(); /* Ensure all outstanding memory accesses included
phungductung	0:e87aa4c49e95	1911	buffered write are completed before reset */
phungductung	0:e87aa4c49e95	1912	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
phungductung	0:e87aa4c49e95	1913	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
phungductung	0:e87aa4c49e95	1914	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
phungductung	0:e87aa4c49e95	1915	__DSB(); /* Ensure completion of memory access */
phungductung	0:e87aa4c49e95	1916	while(1) { __NOP(); } /* wait until reset */
phungductung	0:e87aa4c49e95	1917	}
phungductung	0:e87aa4c49e95	1918
phungductung	0:e87aa4c49e95	1919	/@} end of CMSIS_Core_NVICFunctions /
phungductung	0:e87aa4c49e95	1920
phungductung	0:e87aa4c49e95	1921
phungductung	0:e87aa4c49e95	1922	/* ########################## FPU functions #################################### */
phungductung	0:e87aa4c49e95	1923	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	1924	\defgroup CMSIS_Core_FpuFunctions FPU Functions
phungductung	0:e87aa4c49e95	1925	\brief Function that provides FPU type.
phungductung	0:e87aa4c49e95	1926	@{
phungductung	0:e87aa4c49e95	1927	*/
phungductung	0:e87aa4c49e95	1928
phungductung	0:e87aa4c49e95	1929	/**
phungductung	0:e87aa4c49e95	1930	\fn uint32_t SCB_GetFPUType(void)
phungductung	0:e87aa4c49e95	1931	\brief get FPU type
phungductung	0:e87aa4c49e95	1932	\returns
phungductung	0:e87aa4c49e95	1933	- \b 0: No FPU
phungductung	0:e87aa4c49e95	1934	- \b 1: Single precision FPU
phungductung	0:e87aa4c49e95	1935	- \b 2: Double + Single precision FPU
phungductung	0:e87aa4c49e95	1936	*/
phungductung	0:e87aa4c49e95	1937	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
phungductung	0:e87aa4c49e95	1938	{
phungductung	0:e87aa4c49e95	1939	uint32_t mvfr0;
phungductung	0:e87aa4c49e95	1940
phungductung	0:e87aa4c49e95	1941	mvfr0 = SCB->MVFR0;
phungductung	0:e87aa4c49e95	1942	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
phungductung	0:e87aa4c49e95	1943	return 2UL; // Double + Single precision FPU
phungductung	0:e87aa4c49e95	1944	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
phungductung	0:e87aa4c49e95	1945	return 1UL; // Single precision FPU
phungductung	0:e87aa4c49e95	1946	} else {
phungductung	0:e87aa4c49e95	1947	return 0UL; // No FPU
phungductung	0:e87aa4c49e95	1948	}
phungductung	0:e87aa4c49e95	1949	}
phungductung	0:e87aa4c49e95	1950
phungductung	0:e87aa4c49e95	1951
phungductung	0:e87aa4c49e95	1952	/@} end of CMSIS_Core_FpuFunctions /
phungductung	0:e87aa4c49e95	1953
phungductung	0:e87aa4c49e95	1954
phungductung	0:e87aa4c49e95	1955
phungductung	0:e87aa4c49e95	1956	/* ########################## Cache functions #################################### */
phungductung	0:e87aa4c49e95	1957	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	1958	\defgroup CMSIS_Core_CacheFunctions Cache Functions
phungductung	0:e87aa4c49e95	1959	\brief Functions that configure Instruction and Data cache.
phungductung	0:e87aa4c49e95	1960	@{
phungductung	0:e87aa4c49e95	1961	*/
phungductung	0:e87aa4c49e95	1962
phungductung	0:e87aa4c49e95	1963	/* Cache Size ID Register Macros */
phungductung	0:e87aa4c49e95	1964	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
phungductung	0:e87aa4c49e95	1965	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
phungductung	0:e87aa4c49e95	1966	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
phungductung	0:e87aa4c49e95	1967
phungductung	0:e87aa4c49e95	1968
phungductung	0:e87aa4c49e95	1969	/** \brief Enable I-Cache
phungductung	0:e87aa4c49e95	1970
phungductung	0:e87aa4c49e95	1971	The function turns on I-Cache
phungductung	0:e87aa4c49e95	1972	*/
phungductung	0:e87aa4c49e95	1973	__STATIC_INLINE void SCB_EnableICache (void)
phungductung	0:e87aa4c49e95	1974	{
phungductung	0:e87aa4c49e95	1975	#if (__ICACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	1976	__DSB();
phungductung	0:e87aa4c49e95	1977	__ISB();
phungductung	0:e87aa4c49e95	1978	SCB->ICIALLU = 0UL; // invalidate I-Cache
phungductung	0:e87aa4c49e95	1979	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
phungductung	0:e87aa4c49e95	1980	__DSB();
phungductung	0:e87aa4c49e95	1981	__ISB();
phungductung	0:e87aa4c49e95	1982	#endif
phungductung	0:e87aa4c49e95	1983	}
phungductung	0:e87aa4c49e95	1984
phungductung	0:e87aa4c49e95	1985
phungductung	0:e87aa4c49e95	1986	/** \brief Disable I-Cache
phungductung	0:e87aa4c49e95	1987
phungductung	0:e87aa4c49e95	1988	The function turns off I-Cache
phungductung	0:e87aa4c49e95	1989	*/
phungductung	0:e87aa4c49e95	1990	__STATIC_INLINE void SCB_DisableICache (void)
phungductung	0:e87aa4c49e95	1991	{
phungductung	0:e87aa4c49e95	1992	#if (__ICACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	1993	__DSB();
phungductung	0:e87aa4c49e95	1994	__ISB();
phungductung	0:e87aa4c49e95	1995	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
phungductung	0:e87aa4c49e95	1996	SCB->ICIALLU = 0UL; // invalidate I-Cache
phungductung	0:e87aa4c49e95	1997	__DSB();
phungductung	0:e87aa4c49e95	1998	__ISB();
phungductung	0:e87aa4c49e95	1999	#endif
phungductung	0:e87aa4c49e95	2000	}
phungductung	0:e87aa4c49e95	2001
phungductung	0:e87aa4c49e95	2002
phungductung	0:e87aa4c49e95	2003	/** \brief Invalidate I-Cache
phungductung	0:e87aa4c49e95	2004
phungductung	0:e87aa4c49e95	2005	The function invalidates I-Cache
phungductung	0:e87aa4c49e95	2006	*/
phungductung	0:e87aa4c49e95	2007	__STATIC_INLINE void SCB_InvalidateICache (void)
phungductung	0:e87aa4c49e95	2008	{
phungductung	0:e87aa4c49e95	2009	#if (__ICACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2010	__DSB();
phungductung	0:e87aa4c49e95	2011	__ISB();
phungductung	0:e87aa4c49e95	2012	SCB->ICIALLU = 0UL;
phungductung	0:e87aa4c49e95	2013	__DSB();
phungductung	0:e87aa4c49e95	2014	__ISB();
phungductung	0:e87aa4c49e95	2015	#endif
phungductung	0:e87aa4c49e95	2016	}
phungductung	0:e87aa4c49e95	2017
phungductung	0:e87aa4c49e95	2018
phungductung	0:e87aa4c49e95	2019	/** \brief Enable D-Cache
phungductung	0:e87aa4c49e95	2020
phungductung	0:e87aa4c49e95	2021	The function turns on D-Cache
phungductung	0:e87aa4c49e95	2022	*/
phungductung	0:e87aa4c49e95	2023	__STATIC_INLINE void SCB_EnableDCache (void)
phungductung	0:e87aa4c49e95	2024	{
phungductung	0:e87aa4c49e95	2025	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2026	uint32_t ccsidr, sshift, wshift, sw;
phungductung	0:e87aa4c49e95	2027	uint32_t sets, ways;
phungductung	0:e87aa4c49e95	2028
phungductung	0:e87aa4c49e95	2029	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
phungductung	0:e87aa4c49e95	2030	ccsidr = SCB->CCSIDR;
phungductung	0:e87aa4c49e95	2031	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
phungductung	0:e87aa4c49e95	2032	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
phungductung	0:e87aa4c49e95	2033	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
phungductung	0:e87aa4c49e95	2034	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
phungductung	0:e87aa4c49e95	2035
phungductung	0:e87aa4c49e95	2036	__DSB();
phungductung	0:e87aa4c49e95	2037
phungductung	0:e87aa4c49e95	2038	do { // invalidate D-Cache
phungductung	0:e87aa4c49e95	2039	uint32_t tmpways = ways;
phungductung	0:e87aa4c49e95	2040	do {
phungductung	0:e87aa4c49e95	2041	sw = ((tmpways << wshift) \| (sets << sshift));
phungductung	0:e87aa4c49e95	2042	SCB->DCISW = sw;
phungductung	0:e87aa4c49e95	2043	} while(tmpways--);
phungductung	0:e87aa4c49e95	2044	} while(sets--);
phungductung	0:e87aa4c49e95	2045	__DSB();
phungductung	0:e87aa4c49e95	2046
phungductung	0:e87aa4c49e95	2047	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
phungductung	0:e87aa4c49e95	2048
phungductung	0:e87aa4c49e95	2049	__DSB();
phungductung	0:e87aa4c49e95	2050	__ISB();
phungductung	0:e87aa4c49e95	2051	#endif
phungductung	0:e87aa4c49e95	2052	}
phungductung	0:e87aa4c49e95	2053
phungductung	0:e87aa4c49e95	2054
phungductung	0:e87aa4c49e95	2055	/** \brief Disable D-Cache
phungductung	0:e87aa4c49e95	2056
phungductung	0:e87aa4c49e95	2057	The function turns off D-Cache
phungductung	0:e87aa4c49e95	2058	*/
phungductung	0:e87aa4c49e95	2059	__STATIC_INLINE void SCB_DisableDCache (void)
phungductung	0:e87aa4c49e95	2060	{
phungductung	0:e87aa4c49e95	2061	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2062	uint32_t ccsidr, sshift, wshift, sw;
phungductung	0:e87aa4c49e95	2063	uint32_t sets, ways;
phungductung	0:e87aa4c49e95	2064
phungductung	0:e87aa4c49e95	2065	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
phungductung	0:e87aa4c49e95	2066	ccsidr = SCB->CCSIDR;
phungductung	0:e87aa4c49e95	2067	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
phungductung	0:e87aa4c49e95	2068	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
phungductung	0:e87aa4c49e95	2069	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
phungductung	0:e87aa4c49e95	2070	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
phungductung	0:e87aa4c49e95	2071
phungductung	0:e87aa4c49e95	2072	__DSB();
phungductung	0:e87aa4c49e95	2073
phungductung	0:e87aa4c49e95	2074	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
phungductung	0:e87aa4c49e95	2075
phungductung	0:e87aa4c49e95	2076	do { // clean & invalidate D-Cache
phungductung	0:e87aa4c49e95	2077	uint32_t tmpways = ways;
phungductung	0:e87aa4c49e95	2078	do {
phungductung	0:e87aa4c49e95	2079	sw = ((tmpways << wshift) \| (sets << sshift));
phungductung	0:e87aa4c49e95	2080	SCB->DCCISW = sw;
phungductung	0:e87aa4c49e95	2081	} while(tmpways--);
phungductung	0:e87aa4c49e95	2082	} while(sets--);
phungductung	0:e87aa4c49e95	2083
phungductung	0:e87aa4c49e95	2084
phungductung	0:e87aa4c49e95	2085	__DSB();
phungductung	0:e87aa4c49e95	2086	__ISB();
phungductung	0:e87aa4c49e95	2087	#endif
phungductung	0:e87aa4c49e95	2088	}
phungductung	0:e87aa4c49e95	2089
phungductung	0:e87aa4c49e95	2090
phungductung	0:e87aa4c49e95	2091	/** \brief Invalidate D-Cache
phungductung	0:e87aa4c49e95	2092
phungductung	0:e87aa4c49e95	2093	The function invalidates D-Cache
phungductung	0:e87aa4c49e95	2094	*/
phungductung	0:e87aa4c49e95	2095	__STATIC_INLINE void SCB_InvalidateDCache (void)
phungductung	0:e87aa4c49e95	2096	{
phungductung	0:e87aa4c49e95	2097	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2098	uint32_t ccsidr, sshift, wshift, sw;
phungductung	0:e87aa4c49e95	2099	uint32_t sets, ways;
phungductung	0:e87aa4c49e95	2100
phungductung	0:e87aa4c49e95	2101	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
phungductung	0:e87aa4c49e95	2102	ccsidr = SCB->CCSIDR;
phungductung	0:e87aa4c49e95	2103	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
phungductung	0:e87aa4c49e95	2104	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
phungductung	0:e87aa4c49e95	2105	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
phungductung	0:e87aa4c49e95	2106	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
phungductung	0:e87aa4c49e95	2107
phungductung	0:e87aa4c49e95	2108	__DSB();
phungductung	0:e87aa4c49e95	2109
phungductung	0:e87aa4c49e95	2110	do { // invalidate D-Cache
phungductung	0:e87aa4c49e95	2111	uint32_t tmpways = ways;
phungductung	0:e87aa4c49e95	2112	do {
phungductung	0:e87aa4c49e95	2113	sw = ((tmpways << wshift) \| (sets << sshift));
phungductung	0:e87aa4c49e95	2114	SCB->DCISW = sw;
phungductung	0:e87aa4c49e95	2115	} while(tmpways--);
phungductung	0:e87aa4c49e95	2116	} while(sets--);
phungductung	0:e87aa4c49e95	2117
phungductung	0:e87aa4c49e95	2118	__DSB();
phungductung	0:e87aa4c49e95	2119	__ISB();
phungductung	0:e87aa4c49e95	2120	#endif
phungductung	0:e87aa4c49e95	2121	}
phungductung	0:e87aa4c49e95	2122
phungductung	0:e87aa4c49e95	2123
phungductung	0:e87aa4c49e95	2124	/** \brief Clean D-Cache
phungductung	0:e87aa4c49e95	2125
phungductung	0:e87aa4c49e95	2126	The function cleans D-Cache
phungductung	0:e87aa4c49e95	2127	*/
phungductung	0:e87aa4c49e95	2128	__STATIC_INLINE void SCB_CleanDCache (void)
phungductung	0:e87aa4c49e95	2129	{
phungductung	0:e87aa4c49e95	2130	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2131	uint32_t ccsidr, sshift, wshift, sw;
phungductung	0:e87aa4c49e95	2132	uint32_t sets, ways;
phungductung	0:e87aa4c49e95	2133
phungductung	0:e87aa4c49e95	2134	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
phungductung	0:e87aa4c49e95	2135	ccsidr = SCB->CCSIDR;
phungductung	0:e87aa4c49e95	2136	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
phungductung	0:e87aa4c49e95	2137	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
phungductung	0:e87aa4c49e95	2138	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
phungductung	0:e87aa4c49e95	2139	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
phungductung	0:e87aa4c49e95	2140
phungductung	0:e87aa4c49e95	2141	__DSB();
phungductung	0:e87aa4c49e95	2142
phungductung	0:e87aa4c49e95	2143	do { // clean D-Cache
phungductung	0:e87aa4c49e95	2144	uint32_t tmpways = ways;
phungductung	0:e87aa4c49e95	2145	do {
phungductung	0:e87aa4c49e95	2146	sw = ((tmpways << wshift) \| (sets << sshift));
phungductung	0:e87aa4c49e95	2147	SCB->DCCSW = sw;
phungductung	0:e87aa4c49e95	2148	} while(tmpways--);
phungductung	0:e87aa4c49e95	2149	} while(sets--);
phungductung	0:e87aa4c49e95	2150
phungductung	0:e87aa4c49e95	2151	__DSB();
phungductung	0:e87aa4c49e95	2152	__ISB();
phungductung	0:e87aa4c49e95	2153	#endif
phungductung	0:e87aa4c49e95	2154	}
phungductung	0:e87aa4c49e95	2155
phungductung	0:e87aa4c49e95	2156
phungductung	0:e87aa4c49e95	2157	/** \brief Clean & Invalidate D-Cache
phungductung	0:e87aa4c49e95	2158
phungductung	0:e87aa4c49e95	2159	The function cleans and Invalidates D-Cache
phungductung	0:e87aa4c49e95	2160	*/
phungductung	0:e87aa4c49e95	2161	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
phungductung	0:e87aa4c49e95	2162	{
phungductung	0:e87aa4c49e95	2163	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2164	uint32_t ccsidr, sshift, wshift, sw;
phungductung	0:e87aa4c49e95	2165	uint32_t sets, ways;
phungductung	0:e87aa4c49e95	2166
phungductung	0:e87aa4c49e95	2167	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
phungductung	0:e87aa4c49e95	2168	ccsidr = SCB->CCSIDR;
phungductung	0:e87aa4c49e95	2169	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
phungductung	0:e87aa4c49e95	2170	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
phungductung	0:e87aa4c49e95	2171	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
phungductung	0:e87aa4c49e95	2172	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
phungductung	0:e87aa4c49e95	2173
phungductung	0:e87aa4c49e95	2174	__DSB();
phungductung	0:e87aa4c49e95	2175
phungductung	0:e87aa4c49e95	2176	do { // clean & invalidate D-Cache
phungductung	0:e87aa4c49e95	2177	uint32_t tmpways = ways;
phungductung	0:e87aa4c49e95	2178	do {
phungductung	0:e87aa4c49e95	2179	sw = ((tmpways << wshift) \| (sets << sshift));
phungductung	0:e87aa4c49e95	2180	SCB->DCCISW = sw;
phungductung	0:e87aa4c49e95	2181	} while(tmpways--);
phungductung	0:e87aa4c49e95	2182	} while(sets--);
phungductung	0:e87aa4c49e95	2183
phungductung	0:e87aa4c49e95	2184	__DSB();
phungductung	0:e87aa4c49e95	2185	__ISB();
phungductung	0:e87aa4c49e95	2186	#endif
phungductung	0:e87aa4c49e95	2187	}
phungductung	0:e87aa4c49e95	2188
phungductung	0:e87aa4c49e95	2189
phungductung	0:e87aa4c49e95	2190	/**
phungductung	0:e87aa4c49e95	2191	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
phungductung	0:e87aa4c49e95	2192	\brief D-Cache Invalidate by address
phungductung	0:e87aa4c49e95	2193	\param[in] addr address (aligned to 32-byte boundary)
phungductung	0:e87aa4c49e95	2194	\param[in] dsize size of memory block (in number of bytes)
phungductung	0:e87aa4c49e95	2195	*/
phungductung	0:e87aa4c49e95	2196	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
phungductung	0:e87aa4c49e95	2197	{
phungductung	0:e87aa4c49e95	2198	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2199	int32_t op_size = dsize;
phungductung	0:e87aa4c49e95	2200	uint32_t op_addr = (uint32_t)addr;
phungductung	0:e87aa4c49e95	2201	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
phungductung	0:e87aa4c49e95	2202
phungductung	0:e87aa4c49e95	2203	__DSB();
phungductung	0:e87aa4c49e95	2204
phungductung	0:e87aa4c49e95	2205	while (op_size > 0) {
phungductung	0:e87aa4c49e95	2206	SCB->DCIMVAC = op_addr;
phungductung	0:e87aa4c49e95	2207	op_addr += linesize;
phungductung	0:e87aa4c49e95	2208	op_size -= (int32_t)linesize;
phungductung	0:e87aa4c49e95	2209	}
phungductung	0:e87aa4c49e95	2210
phungductung	0:e87aa4c49e95	2211	__DSB();
phungductung	0:e87aa4c49e95	2212	__ISB();
phungductung	0:e87aa4c49e95	2213	#endif
phungductung	0:e87aa4c49e95	2214	}
phungductung	0:e87aa4c49e95	2215
phungductung	0:e87aa4c49e95	2216
phungductung	0:e87aa4c49e95	2217	/**
phungductung	0:e87aa4c49e95	2218	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
phungductung	0:e87aa4c49e95	2219	\brief D-Cache Clean by address
phungductung	0:e87aa4c49e95	2220	\param[in] addr address (aligned to 32-byte boundary)
phungductung	0:e87aa4c49e95	2221	\param[in] dsize size of memory block (in number of bytes)
phungductung	0:e87aa4c49e95	2222	*/
phungductung	0:e87aa4c49e95	2223	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
phungductung	0:e87aa4c49e95	2224	{
phungductung	0:e87aa4c49e95	2225	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2226	int32_t op_size = dsize;
phungductung	0:e87aa4c49e95	2227	uint32_t op_addr = (uint32_t) addr;
phungductung	0:e87aa4c49e95	2228	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
phungductung	0:e87aa4c49e95	2229
phungductung	0:e87aa4c49e95	2230	__DSB();
phungductung	0:e87aa4c49e95	2231
phungductung	0:e87aa4c49e95	2232	while (op_size > 0) {
phungductung	0:e87aa4c49e95	2233	SCB->DCCMVAC = op_addr;
phungductung	0:e87aa4c49e95	2234	op_addr += linesize;
phungductung	0:e87aa4c49e95	2235	op_size -= (int32_t)linesize;
phungductung	0:e87aa4c49e95	2236	}
phungductung	0:e87aa4c49e95	2237
phungductung	0:e87aa4c49e95	2238	__DSB();
phungductung	0:e87aa4c49e95	2239	__ISB();
phungductung	0:e87aa4c49e95	2240	#endif
phungductung	0:e87aa4c49e95	2241	}
phungductung	0:e87aa4c49e95	2242
phungductung	0:e87aa4c49e95	2243
phungductung	0:e87aa4c49e95	2244	/**
phungductung	0:e87aa4c49e95	2245	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
phungductung	0:e87aa4c49e95	2246	\brief D-Cache Clean and Invalidate by address
phungductung	0:e87aa4c49e95	2247	\param[in] addr address (aligned to 32-byte boundary)
phungductung	0:e87aa4c49e95	2248	\param[in] dsize size of memory block (in number of bytes)
phungductung	0:e87aa4c49e95	2249	*/
phungductung	0:e87aa4c49e95	2250	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
phungductung	0:e87aa4c49e95	2251	{
phungductung	0:e87aa4c49e95	2252	#if (__DCACHE_PRESENT == 1)
phungductung	0:e87aa4c49e95	2253	int32_t op_size = dsize;
phungductung	0:e87aa4c49e95	2254	uint32_t op_addr = (uint32_t) addr;
phungductung	0:e87aa4c49e95	2255	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
phungductung	0:e87aa4c49e95	2256
phungductung	0:e87aa4c49e95	2257	__DSB();
phungductung	0:e87aa4c49e95	2258
phungductung	0:e87aa4c49e95	2259	while (op_size > 0) {
phungductung	0:e87aa4c49e95	2260	SCB->DCCIMVAC = op_addr;
phungductung	0:e87aa4c49e95	2261	op_addr += linesize;
phungductung	0:e87aa4c49e95	2262	op_size -= (int32_t)linesize;
phungductung	0:e87aa4c49e95	2263	}
phungductung	0:e87aa4c49e95	2264
phungductung	0:e87aa4c49e95	2265	__DSB();
phungductung	0:e87aa4c49e95	2266	__ISB();
phungductung	0:e87aa4c49e95	2267	#endif
phungductung	0:e87aa4c49e95	2268	}
phungductung	0:e87aa4c49e95	2269
phungductung	0:e87aa4c49e95	2270
phungductung	0:e87aa4c49e95	2271	/@} end of CMSIS_Core_CacheFunctions /
phungductung	0:e87aa4c49e95	2272
phungductung	0:e87aa4c49e95	2273
phungductung	0:e87aa4c49e95	2274
phungductung	0:e87aa4c49e95	2275	/* ################################## SysTick function ############################################ */
phungductung	0:e87aa4c49e95	2276	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	2277	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
phungductung	0:e87aa4c49e95	2278	\brief Functions that configure the System.
phungductung	0:e87aa4c49e95	2279	@{
phungductung	0:e87aa4c49e95	2280	*/
phungductung	0:e87aa4c49e95	2281
phungductung	0:e87aa4c49e95	2282	#if (__Vendor_SysTickConfig == 0)
phungductung	0:e87aa4c49e95	2283
phungductung	0:e87aa4c49e95	2284	/** \brief System Tick Configuration
phungductung	0:e87aa4c49e95	2285
phungductung	0:e87aa4c49e95	2286	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
phungductung	0:e87aa4c49e95	2287	Counter is in free running mode to generate periodic interrupts.
phungductung	0:e87aa4c49e95	2288
phungductung	0:e87aa4c49e95	2289	\param [in] ticks Number of ticks between two interrupts.
phungductung	0:e87aa4c49e95	2290
phungductung	0:e87aa4c49e95	2291	\return 0 Function succeeded.
phungductung	0:e87aa4c49e95	2292	\return 1 Function failed.
phungductung	0:e87aa4c49e95	2293
phungductung	0:e87aa4c49e95	2294	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
phungductung	0:e87aa4c49e95	2295	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
phungductung	0:e87aa4c49e95	2296	must contain a vendor-specific implementation of this function.
phungductung	0:e87aa4c49e95	2297
phungductung	0:e87aa4c49e95	2298	*/
phungductung	0:e87aa4c49e95	2299	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
phungductung	0:e87aa4c49e95	2300	{
phungductung	0:e87aa4c49e95	2301	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
phungductung	0:e87aa4c49e95	2302
phungductung	0:e87aa4c49e95	2303	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
phungductung	0:e87aa4c49e95	2304	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
phungductung	0:e87aa4c49e95	2305	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
phungductung	0:e87aa4c49e95	2306	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
phungductung	0:e87aa4c49e95	2307	SysTick_CTRL_TICKINT_Msk \|
phungductung	0:e87aa4c49e95	2308	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
phungductung	0:e87aa4c49e95	2309	return (0UL); /* Function successful */
phungductung	0:e87aa4c49e95	2310	}
phungductung	0:e87aa4c49e95	2311
phungductung	0:e87aa4c49e95	2312	#endif
phungductung	0:e87aa4c49e95	2313
phungductung	0:e87aa4c49e95	2314	/@} end of CMSIS_Core_SysTickFunctions /
phungductung	0:e87aa4c49e95	2315
phungductung	0:e87aa4c49e95	2316
phungductung	0:e87aa4c49e95	2317
phungductung	0:e87aa4c49e95	2318	/* ##################################### Debug In/Output function ########################################### */
phungductung	0:e87aa4c49e95	2319	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	2320	\defgroup CMSIS_core_DebugFunctions ITM Functions
phungductung	0:e87aa4c49e95	2321	\brief Functions that access the ITM debug interface.
phungductung	0:e87aa4c49e95	2322	@{
phungductung	0:e87aa4c49e95	2323	*/
phungductung	0:e87aa4c49e95	2324
phungductung	0:e87aa4c49e95	2325	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
phungductung	0:e87aa4c49e95	2326	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
phungductung	0:e87aa4c49e95	2327
phungductung	0:e87aa4c49e95	2328
phungductung	0:e87aa4c49e95	2329	/** \brief ITM Send Character
phungductung	0:e87aa4c49e95	2330
phungductung	0:e87aa4c49e95	2331	The function transmits a character via the ITM channel 0, and
phungductung	0:e87aa4c49e95	2332	\li Just returns when no debugger is connected that has booked the output.
phungductung	0:e87aa4c49e95	2333	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
phungductung	0:e87aa4c49e95	2334
phungductung	0:e87aa4c49e95	2335	\param [in] ch Character to transmit.
phungductung	0:e87aa4c49e95	2336
phungductung	0:e87aa4c49e95	2337	\returns Character to transmit.
phungductung	0:e87aa4c49e95	2338	*/
phungductung	0:e87aa4c49e95	2339	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
phungductung	0:e87aa4c49e95	2340	{
phungductung	0:e87aa4c49e95	2341	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
phungductung	0:e87aa4c49e95	2342	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
phungductung	0:e87aa4c49e95	2343	{
phungductung	0:e87aa4c49e95	2344	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
phungductung	0:e87aa4c49e95	2345	ITM->PORT[0].u8 = (uint8_t)ch;
phungductung	0:e87aa4c49e95	2346	}
phungductung	0:e87aa4c49e95	2347	return (ch);
phungductung	0:e87aa4c49e95	2348	}
phungductung	0:e87aa4c49e95	2349
phungductung	0:e87aa4c49e95	2350
phungductung	0:e87aa4c49e95	2351	/** \brief ITM Receive Character
phungductung	0:e87aa4c49e95	2352
phungductung	0:e87aa4c49e95	2353	The function inputs a character via the external variable \ref ITM_RxBuffer.
phungductung	0:e87aa4c49e95	2354
phungductung	0:e87aa4c49e95	2355	\return Received character.
phungductung	0:e87aa4c49e95	2356	\return -1 No character pending.
phungductung	0:e87aa4c49e95	2357	*/
phungductung	0:e87aa4c49e95	2358	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
phungductung	0:e87aa4c49e95	2359	int32_t ch = -1; /* no character available */
phungductung	0:e87aa4c49e95	2360
phungductung	0:e87aa4c49e95	2361	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
phungductung	0:e87aa4c49e95	2362	ch = ITM_RxBuffer;
phungductung	0:e87aa4c49e95	2363	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
phungductung	0:e87aa4c49e95	2364	}
phungductung	0:e87aa4c49e95	2365
phungductung	0:e87aa4c49e95	2366	return (ch);
phungductung	0:e87aa4c49e95	2367	}
phungductung	0:e87aa4c49e95	2368
phungductung	0:e87aa4c49e95	2369
phungductung	0:e87aa4c49e95	2370	/** \brief ITM Check Character
phungductung	0:e87aa4c49e95	2371
phungductung	0:e87aa4c49e95	2372	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
phungductung	0:e87aa4c49e95	2373
phungductung	0:e87aa4c49e95	2374	\return 0 No character available.
phungductung	0:e87aa4c49e95	2375	\return 1 Character available.
phungductung	0:e87aa4c49e95	2376	*/
phungductung	0:e87aa4c49e95	2377	__STATIC_INLINE int32_t ITM_CheckChar (void) {
phungductung	0:e87aa4c49e95	2378
phungductung	0:e87aa4c49e95	2379	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
phungductung	0:e87aa4c49e95	2380	return (0); /* no character available */
phungductung	0:e87aa4c49e95	2381	} else {
phungductung	0:e87aa4c49e95	2382	return (1); /* character available */
phungductung	0:e87aa4c49e95	2383	}
phungductung	0:e87aa4c49e95	2384	}
phungductung	0:e87aa4c49e95	2385
phungductung	0:e87aa4c49e95	2386	/@} end of CMSIS_core_DebugFunctions /
phungductung	0:e87aa4c49e95	2387
phungductung	0:e87aa4c49e95	2388
phungductung	0:e87aa4c49e95	2389
phungductung	0:e87aa4c49e95	2390
phungductung	0:e87aa4c49e95	2391	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	2392	}
phungductung	0:e87aa4c49e95	2393	#endif
phungductung	0:e87aa4c49e95	2394
phungductung	0:e87aa4c49e95	2395	#endif /* __CORE_CM7_H_DEPENDANT */
phungductung	0:e87aa4c49e95	2396
phungductung	0:e87aa4c49e95	2397	#endif /* __CMSIS_GENERIC */

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	04 Jun 2019
Imports:	8
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/core_cm7.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning