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targets/cmsis/core_cm4.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

libray

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User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/************************************************************************//
phungductung	0:e87aa4c49e95	2	* @file core_cm4.h
phungductung	0:e87aa4c49e95	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
phungductung	0:e87aa4c49e95	4	* @version V4.10
phungductung	0:e87aa4c49e95	5	* @date 18. March 2015
phungductung	0:e87aa4c49e95	6	*
phungductung	0:e87aa4c49e95	7	* @note
phungductung	0:e87aa4c49e95	8	*
phungductung	0:e87aa4c49e95	9	******************************************************************************/
phungductung	0:e87aa4c49e95	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
phungductung	0:e87aa4c49e95	11
phungductung	0:e87aa4c49e95	12	All rights reserved.
phungductung	0:e87aa4c49e95	13	Redistribution and use in source and binary forms, with or without
phungductung	0:e87aa4c49e95	14	modification, are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	15	- Redistributions of source code must retain the above copyright
phungductung	0:e87aa4c49e95	16	notice, this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	17	- Redistributions in binary form must reproduce the above copyright
phungductung	0:e87aa4c49e95	18	notice, this list of conditions and the following disclaimer in the
phungductung	0:e87aa4c49e95	19	documentation and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	20	- Neither the name of ARM nor the names of its contributors may be used
phungductung	0:e87aa4c49e95	21	to endorse or promote products derived from this software without
phungductung	0:e87aa4c49e95	22	specific prior written permission.
phungductung	0:e87aa4c49e95	23	*
phungductung	0:e87aa4c49e95	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
phungductung	0:e87aa4c49e95	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
phungductung	0:e87aa4c49e95	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
phungductung	0:e87aa4c49e95	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
phungductung	0:e87aa4c49e95	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
phungductung	0:e87aa4c49e95	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
phungductung	0:e87aa4c49e95	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
phungductung	0:e87aa4c49e95	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
phungductung	0:e87aa4c49e95	34	POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	35	---------------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	36
phungductung	0:e87aa4c49e95	37
phungductung	0:e87aa4c49e95	38	#if defined ( __ICCARM__ )
phungductung	0:e87aa4c49e95	39	#pragma system_include /* treat file as system include file for MISRA check */
phungductung	0:e87aa4c49e95	40	#endif
phungductung	0:e87aa4c49e95	41
phungductung	0:e87aa4c49e95	42	#ifndef __CORE_CM4_H_GENERIC
phungductung	0:e87aa4c49e95	43	#define __CORE_CM4_H_GENERIC
phungductung	0:e87aa4c49e95	44
phungductung	0:e87aa4c49e95	45	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	46	extern "C" {
phungductung	0:e87aa4c49e95	47	#endif
phungductung	0:e87aa4c49e95	48
phungductung	0:e87aa4c49e95	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
phungductung	0:e87aa4c49e95	50	CMSIS violates the following MISRA-C:2004 rules:
phungductung	0:e87aa4c49e95	51
phungductung	0:e87aa4c49e95	52	\li Required Rule 8.5, object/function definition in header file.<br>
phungductung	0:e87aa4c49e95	53	Function definitions in header files are used to allow 'inlining'.
phungductung	0:e87aa4c49e95	54
phungductung	0:e87aa4c49e95	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
phungductung	0:e87aa4c49e95	56	Unions are used for effective representation of core registers.
phungductung	0:e87aa4c49e95	57
phungductung	0:e87aa4c49e95	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
phungductung	0:e87aa4c49e95	59	Function-like macros are used to allow more efficient code.
phungductung	0:e87aa4c49e95	60	*/
phungductung	0:e87aa4c49e95	61
phungductung	0:e87aa4c49e95	62
phungductung	0:e87aa4c49e95	63	/*******************************************************************************
phungductung	0:e87aa4c49e95	64	* CMSIS definitions
phungductung	0:e87aa4c49e95	65	******************************************************************************/
phungductung	0:e87aa4c49e95	66	/** \ingroup Cortex_M4
phungductung	0:e87aa4c49e95	67	@{
phungductung	0:e87aa4c49e95	68	*/
phungductung	0:e87aa4c49e95	69
phungductung	0:e87aa4c49e95	70	/* CMSIS CM4 definitions */
phungductung	0:e87aa4c49e95	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
phungductung	0:e87aa4c49e95	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
phungductung	0:e87aa4c49e95	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
phungductung	0:e87aa4c49e95	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
phungductung	0:e87aa4c49e95	75
phungductung	0:e87aa4c49e95	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
phungductung	0:e87aa4c49e95	77
phungductung	0:e87aa4c49e95	78
phungductung	0:e87aa4c49e95	79	#if defined ( __CC_ARM )
phungductung	0:e87aa4c49e95	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
phungductung	0:e87aa4c49e95	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
phungductung	0:e87aa4c49e95	82	#define __STATIC_INLINE static __inline
phungductung	0:e87aa4c49e95	83
phungductung	0:e87aa4c49e95	84	#elif defined ( __GNUC__ )
phungductung	0:e87aa4c49e95	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
phungductung	0:e87aa4c49e95	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
phungductung	0:e87aa4c49e95	87	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	88
phungductung	0:e87aa4c49e95	89	#elif defined ( __ICCARM__ )
phungductung	0:e87aa4c49e95	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
phungductung	0:e87aa4c49e95	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
phungductung	0:e87aa4c49e95	92	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	93
phungductung	0:e87aa4c49e95	94	#elif defined ( __TMS470__ )
phungductung	0:e87aa4c49e95	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
phungductung	0:e87aa4c49e95	96	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	97
phungductung	0:e87aa4c49e95	98	#elif defined ( __TASKING__ )
phungductung	0:e87aa4c49e95	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
phungductung	0:e87aa4c49e95	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
phungductung	0:e87aa4c49e95	101	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	102
phungductung	0:e87aa4c49e95	103	#elif defined ( __CSMC__ )
phungductung	0:e87aa4c49e95	104	#define __packed
phungductung	0:e87aa4c49e95	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
phungductung	0:e87aa4c49e95	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
phungductung	0:e87aa4c49e95	107	#define __STATIC_INLINE static inline
phungductung	0:e87aa4c49e95	108
phungductung	0:e87aa4c49e95	109	#endif
phungductung	0:e87aa4c49e95	110
phungductung	0:e87aa4c49e95	111	/** __FPU_USED indicates whether an FPU is used or not.
phungductung	0:e87aa4c49e95	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
phungductung	0:e87aa4c49e95	113	*/
phungductung	0:e87aa4c49e95	114	#if defined ( __CC_ARM )
phungductung	0:e87aa4c49e95	115	#if defined __TARGET_FPU_VFP
phungductung	0:e87aa4c49e95	116	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	117	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	118	#else
phungductung	0:e87aa4c49e95	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	120	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	121	#endif
phungductung	0:e87aa4c49e95	122	#else
phungductung	0:e87aa4c49e95	123	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	124	#endif
phungductung	0:e87aa4c49e95	125
phungductung	0:e87aa4c49e95	126	#elif defined ( __GNUC__ )
phungductung	0:e87aa4c49e95	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
phungductung	0:e87aa4c49e95	128	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	129	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	130	#else
phungductung	0:e87aa4c49e95	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	132	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	133	#endif
phungductung	0:e87aa4c49e95	134	#else
phungductung	0:e87aa4c49e95	135	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	136	#endif
phungductung	0:e87aa4c49e95	137
phungductung	0:e87aa4c49e95	138	#elif defined ( __ICCARM__ )
phungductung	0:e87aa4c49e95	139	#if defined __ARMVFP__
phungductung	0:e87aa4c49e95	140	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	141	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	142	#else
phungductung	0:e87aa4c49e95	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	144	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	145	#endif
phungductung	0:e87aa4c49e95	146	#else
phungductung	0:e87aa4c49e95	147	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	148	#endif
phungductung	0:e87aa4c49e95	149
phungductung	0:e87aa4c49e95	150	#elif defined ( __TMS470__ )
phungductung	0:e87aa4c49e95	151	#if defined __TI_VFP_SUPPORT__
phungductung	0:e87aa4c49e95	152	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	153	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	154	#else
phungductung	0:e87aa4c49e95	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	156	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	157	#endif
phungductung	0:e87aa4c49e95	158	#else
phungductung	0:e87aa4c49e95	159	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	160	#endif
phungductung	0:e87aa4c49e95	161
phungductung	0:e87aa4c49e95	162	#elif defined ( __TASKING__ )
phungductung	0:e87aa4c49e95	163	#if defined __FPU_VFP__
phungductung	0:e87aa4c49e95	164	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	165	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	166	#else
phungductung	0:e87aa4c49e95	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	168	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	169	#endif
phungductung	0:e87aa4c49e95	170	#else
phungductung	0:e87aa4c49e95	171	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	172	#endif
phungductung	0:e87aa4c49e95	173
phungductung	0:e87aa4c49e95	174	#elif defined ( __CSMC__ ) /* Cosmic */
phungductung	0:e87aa4c49e95	175	#if ( __CSMC__ & 0x400) // FPU present for parser
phungductung	0:e87aa4c49e95	176	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	177	#define __FPU_USED 1
phungductung	0:e87aa4c49e95	178	#else
phungductung	0:e87aa4c49e95	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung	0:e87aa4c49e95	180	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	181	#endif
phungductung	0:e87aa4c49e95	182	#else
phungductung	0:e87aa4c49e95	183	#define __FPU_USED 0
phungductung	0:e87aa4c49e95	184	#endif
phungductung	0:e87aa4c49e95	185	#endif
phungductung	0:e87aa4c49e95	186
phungductung	0:e87aa4c49e95	187	#include <stdint.h> /* standard types definitions */
phungductung	0:e87aa4c49e95	188	#include <core_cmInstr.h> /* Core Instruction Access */
phungductung	0:e87aa4c49e95	189	#include <core_cmFunc.h> /* Core Function Access */
phungductung	0:e87aa4c49e95	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
phungductung	0:e87aa4c49e95	191
phungductung	0:e87aa4c49e95	192	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	193	}
phungductung	0:e87aa4c49e95	194	#endif
phungductung	0:e87aa4c49e95	195
phungductung	0:e87aa4c49e95	196	#endif /* __CORE_CM4_H_GENERIC */
phungductung	0:e87aa4c49e95	197
phungductung	0:e87aa4c49e95	198	#ifndef __CMSIS_GENERIC
phungductung	0:e87aa4c49e95	199
phungductung	0:e87aa4c49e95	200	#ifndef __CORE_CM4_H_DEPENDANT
phungductung	0:e87aa4c49e95	201	#define __CORE_CM4_H_DEPENDANT
phungductung	0:e87aa4c49e95	202
phungductung	0:e87aa4c49e95	203	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	204	extern "C" {
phungductung	0:e87aa4c49e95	205	#endif
phungductung	0:e87aa4c49e95	206
phungductung	0:e87aa4c49e95	207	/* check device defines and use defaults */
phungductung	0:e87aa4c49e95	208	#if defined __CHECK_DEVICE_DEFINES
phungductung	0:e87aa4c49e95	209	#ifndef __CM4_REV
phungductung	0:e87aa4c49e95	210	#define __CM4_REV 0x0000
phungductung	0:e87aa4c49e95	211	#warning "__CM4_REV not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	212	#endif
phungductung	0:e87aa4c49e95	213
phungductung	0:e87aa4c49e95	214	#ifndef __FPU_PRESENT
phungductung	0:e87aa4c49e95	215	#define __FPU_PRESENT 0
phungductung	0:e87aa4c49e95	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	217	#endif
phungductung	0:e87aa4c49e95	218
phungductung	0:e87aa4c49e95	219	#ifndef __MPU_PRESENT
phungductung	0:e87aa4c49e95	220	#define __MPU_PRESENT 0
phungductung	0:e87aa4c49e95	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	222	#endif
phungductung	0:e87aa4c49e95	223
phungductung	0:e87aa4c49e95	224	#ifndef __NVIC_PRIO_BITS
phungductung	0:e87aa4c49e95	225	#define __NVIC_PRIO_BITS 4
phungductung	0:e87aa4c49e95	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	227	#endif
phungductung	0:e87aa4c49e95	228
phungductung	0:e87aa4c49e95	229	#ifndef __Vendor_SysTickConfig
phungductung	0:e87aa4c49e95	230	#define __Vendor_SysTickConfig 0
phungductung	0:e87aa4c49e95	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
phungductung	0:e87aa4c49e95	232	#endif
phungductung	0:e87aa4c49e95	233	#endif
phungductung	0:e87aa4c49e95	234
phungductung	0:e87aa4c49e95	235	/* IO definitions (access restrictions to peripheral registers) */
phungductung	0:e87aa4c49e95	236	/**
phungductung	0:e87aa4c49e95	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
phungductung	0:e87aa4c49e95	238
phungductung	0:e87aa4c49e95	239	<strong>IO Type Qualifiers</strong> are used
phungductung	0:e87aa4c49e95	240	\li to specify the access to peripheral variables.
phungductung	0:e87aa4c49e95	241	\li for automatic generation of peripheral register debug information.
phungductung	0:e87aa4c49e95	242	*/
phungductung	0:e87aa4c49e95	243	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	244	#define __I volatile /!< Defines 'read only' permissions /
phungductung	0:e87aa4c49e95	245	#else
phungductung	0:e87aa4c49e95	246	#define __I volatile const /!< Defines 'read only' permissions /
phungductung	0:e87aa4c49e95	247	#endif
phungductung	0:e87aa4c49e95	248	#define __O volatile /!< Defines 'write only' permissions /
phungductung	0:e87aa4c49e95	249	#define __IO volatile /!< Defines 'read / write' permissions /
phungductung	0:e87aa4c49e95	250
phungductung	0:e87aa4c49e95	251	/@} end of group Cortex_M4 /
phungductung	0:e87aa4c49e95	252
phungductung	0:e87aa4c49e95	253
phungductung	0:e87aa4c49e95	254
phungductung	0:e87aa4c49e95	255	/*******************************************************************************
phungductung	0:e87aa4c49e95	256	* Register Abstraction
phungductung	0:e87aa4c49e95	257	Core Register contain:
phungductung	0:e87aa4c49e95	258	- Core Register
phungductung	0:e87aa4c49e95	259	- Core NVIC Register
phungductung	0:e87aa4c49e95	260	- Core SCB Register
phungductung	0:e87aa4c49e95	261	- Core SysTick Register
phungductung	0:e87aa4c49e95	262	- Core Debug Register
phungductung	0:e87aa4c49e95	263	- Core MPU Register
phungductung	0:e87aa4c49e95	264	- Core FPU Register
phungductung	0:e87aa4c49e95	265	******************************************************************************/
phungductung	0:e87aa4c49e95	266	/** \defgroup CMSIS_core_register Defines and Type Definitions
phungductung	0:e87aa4c49e95	267	\brief Type definitions and defines for Cortex-M processor based devices.
phungductung	0:e87aa4c49e95	268	*/
phungductung	0:e87aa4c49e95	269
phungductung	0:e87aa4c49e95	270	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	271	\defgroup CMSIS_CORE Status and Control Registers
phungductung	0:e87aa4c49e95	272	\brief Core Register type definitions.
phungductung	0:e87aa4c49e95	273	@{
phungductung	0:e87aa4c49e95	274	*/
phungductung	0:e87aa4c49e95	275
phungductung	0:e87aa4c49e95	276	/** \brief Union type to access the Application Program Status Register (APSR).
phungductung	0:e87aa4c49e95	277	*/
phungductung	0:e87aa4c49e95	278	typedef union
phungductung	0:e87aa4c49e95	279	{
phungductung	0:e87aa4c49e95	280	struct
phungductung	0:e87aa4c49e95	281	{
phungductung	0:e87aa4c49e95	282	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
phungductung	0:e87aa4c49e95	283	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
phungductung	0:e87aa4c49e95	284	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
phungductung	0:e87aa4c49e95	285	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
phungductung	0:e87aa4c49e95	286	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
phungductung	0:e87aa4c49e95	287	uint32_t C:1; /!< bit: 29 Carry condition code flag /
phungductung	0:e87aa4c49e95	288	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
phungductung	0:e87aa4c49e95	289	uint32_t N:1; /!< bit: 31 Negative condition code flag /
phungductung	0:e87aa4c49e95	290	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	291	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	292	} APSR_Type;
phungductung	0:e87aa4c49e95	293
phungductung	0:e87aa4c49e95	294	/* APSR Register Definitions */
phungductung	0:e87aa4c49e95	295	#define APSR_N_Pos 31 /!< APSR: N Position /
phungductung	0:e87aa4c49e95	296	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
phungductung	0:e87aa4c49e95	297
phungductung	0:e87aa4c49e95	298	#define APSR_Z_Pos 30 /!< APSR: Z Position /
phungductung	0:e87aa4c49e95	299	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
phungductung	0:e87aa4c49e95	300
phungductung	0:e87aa4c49e95	301	#define APSR_C_Pos 29 /!< APSR: C Position /
phungductung	0:e87aa4c49e95	302	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
phungductung	0:e87aa4c49e95	303
phungductung	0:e87aa4c49e95	304	#define APSR_V_Pos 28 /!< APSR: V Position /
phungductung	0:e87aa4c49e95	305	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
phungductung	0:e87aa4c49e95	306
phungductung	0:e87aa4c49e95	307	#define APSR_Q_Pos 27 /!< APSR: Q Position /
phungductung	0:e87aa4c49e95	308	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
phungductung	0:e87aa4c49e95	309
phungductung	0:e87aa4c49e95	310	#define APSR_GE_Pos 16 /!< APSR: GE Position /
phungductung	0:e87aa4c49e95	311	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
phungductung	0:e87aa4c49e95	312
phungductung	0:e87aa4c49e95	313
phungductung	0:e87aa4c49e95	314	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
phungductung	0:e87aa4c49e95	315	*/
phungductung	0:e87aa4c49e95	316	typedef union
phungductung	0:e87aa4c49e95	317	{
phungductung	0:e87aa4c49e95	318	struct
phungductung	0:e87aa4c49e95	319	{
phungductung	0:e87aa4c49e95	320	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
phungductung	0:e87aa4c49e95	321	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
phungductung	0:e87aa4c49e95	322	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	323	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	324	} IPSR_Type;
phungductung	0:e87aa4c49e95	325
phungductung	0:e87aa4c49e95	326	/* IPSR Register Definitions */
phungductung	0:e87aa4c49e95	327	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
phungductung	0:e87aa4c49e95	328	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
phungductung	0:e87aa4c49e95	329
phungductung	0:e87aa4c49e95	330
phungductung	0:e87aa4c49e95	331	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
phungductung	0:e87aa4c49e95	332	*/
phungductung	0:e87aa4c49e95	333	typedef union
phungductung	0:e87aa4c49e95	334	{
phungductung	0:e87aa4c49e95	335	struct
phungductung	0:e87aa4c49e95	336	{
phungductung	0:e87aa4c49e95	337	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
phungductung	0:e87aa4c49e95	338	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
phungductung	0:e87aa4c49e95	339	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
phungductung	0:e87aa4c49e95	340	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
phungductung	0:e87aa4c49e95	341	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
phungductung	0:e87aa4c49e95	342	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
phungductung	0:e87aa4c49e95	343	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
phungductung	0:e87aa4c49e95	344	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
phungductung	0:e87aa4c49e95	345	uint32_t C:1; /!< bit: 29 Carry condition code flag /
phungductung	0:e87aa4c49e95	346	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
phungductung	0:e87aa4c49e95	347	uint32_t N:1; /!< bit: 31 Negative condition code flag /
phungductung	0:e87aa4c49e95	348	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	349	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	350	} xPSR_Type;
phungductung	0:e87aa4c49e95	351
phungductung	0:e87aa4c49e95	352	/* xPSR Register Definitions */
phungductung	0:e87aa4c49e95	353	#define xPSR_N_Pos 31 /!< xPSR: N Position /
phungductung	0:e87aa4c49e95	354	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
phungductung	0:e87aa4c49e95	355
phungductung	0:e87aa4c49e95	356	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
phungductung	0:e87aa4c49e95	357	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
phungductung	0:e87aa4c49e95	358
phungductung	0:e87aa4c49e95	359	#define xPSR_C_Pos 29 /!< xPSR: C Position /
phungductung	0:e87aa4c49e95	360	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
phungductung	0:e87aa4c49e95	361
phungductung	0:e87aa4c49e95	362	#define xPSR_V_Pos 28 /!< xPSR: V Position /
phungductung	0:e87aa4c49e95	363	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
phungductung	0:e87aa4c49e95	364
phungductung	0:e87aa4c49e95	365	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
phungductung	0:e87aa4c49e95	366	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
phungductung	0:e87aa4c49e95	367
phungductung	0:e87aa4c49e95	368	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
phungductung	0:e87aa4c49e95	369	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
phungductung	0:e87aa4c49e95	370
phungductung	0:e87aa4c49e95	371	#define xPSR_T_Pos 24 /!< xPSR: T Position /
phungductung	0:e87aa4c49e95	372	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
phungductung	0:e87aa4c49e95	373
phungductung	0:e87aa4c49e95	374	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
phungductung	0:e87aa4c49e95	375	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
phungductung	0:e87aa4c49e95	376
phungductung	0:e87aa4c49e95	377	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
phungductung	0:e87aa4c49e95	378	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
phungductung	0:e87aa4c49e95	379
phungductung	0:e87aa4c49e95	380
phungductung	0:e87aa4c49e95	381	/** \brief Union type to access the Control Registers (CONTROL).
phungductung	0:e87aa4c49e95	382	*/
phungductung	0:e87aa4c49e95	383	typedef union
phungductung	0:e87aa4c49e95	384	{
phungductung	0:e87aa4c49e95	385	struct
phungductung	0:e87aa4c49e95	386	{
phungductung	0:e87aa4c49e95	387	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
phungductung	0:e87aa4c49e95	388	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
phungductung	0:e87aa4c49e95	389	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
phungductung	0:e87aa4c49e95	390	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
phungductung	0:e87aa4c49e95	391	} b; /!< Structure used for bit access /
phungductung	0:e87aa4c49e95	392	uint32_t w; /!< Type used for word access /
phungductung	0:e87aa4c49e95	393	} CONTROL_Type;
phungductung	0:e87aa4c49e95	394
phungductung	0:e87aa4c49e95	395	/* CONTROL Register Definitions */
phungductung	0:e87aa4c49e95	396	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
phungductung	0:e87aa4c49e95	397	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
phungductung	0:e87aa4c49e95	398
phungductung	0:e87aa4c49e95	399	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
phungductung	0:e87aa4c49e95	400	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
phungductung	0:e87aa4c49e95	401
phungductung	0:e87aa4c49e95	402	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
phungductung	0:e87aa4c49e95	403	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
phungductung	0:e87aa4c49e95	404
phungductung	0:e87aa4c49e95	405	/@} end of group CMSIS_CORE /
phungductung	0:e87aa4c49e95	406
phungductung	0:e87aa4c49e95	407
phungductung	0:e87aa4c49e95	408	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	409	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
phungductung	0:e87aa4c49e95	410	\brief Type definitions for the NVIC Registers
phungductung	0:e87aa4c49e95	411	@{
phungductung	0:e87aa4c49e95	412	*/
phungductung	0:e87aa4c49e95	413
phungductung	0:e87aa4c49e95	414	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
phungductung	0:e87aa4c49e95	415	*/
phungductung	0:e87aa4c49e95	416	typedef struct
phungductung	0:e87aa4c49e95	417	{
phungductung	0:e87aa4c49e95	418	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
phungductung	0:e87aa4c49e95	419	uint32_t RESERVED0[24];
phungductung	0:e87aa4c49e95	420	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
phungductung	0:e87aa4c49e95	421	uint32_t RSERVED1[24];
phungductung	0:e87aa4c49e95	422	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
phungductung	0:e87aa4c49e95	423	uint32_t RESERVED2[24];
phungductung	0:e87aa4c49e95	424	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
phungductung	0:e87aa4c49e95	425	uint32_t RESERVED3[24];
phungductung	0:e87aa4c49e95	426	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
phungductung	0:e87aa4c49e95	427	uint32_t RESERVED4[56];
phungductung	0:e87aa4c49e95	428	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
phungductung	0:e87aa4c49e95	429	uint32_t RESERVED5[644];
phungductung	0:e87aa4c49e95	430	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
phungductung	0:e87aa4c49e95	431	} NVIC_Type;
phungductung	0:e87aa4c49e95	432
phungductung	0:e87aa4c49e95	433	/* Software Triggered Interrupt Register Definitions */
phungductung	0:e87aa4c49e95	434	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
phungductung	0:e87aa4c49e95	435	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
phungductung	0:e87aa4c49e95	436
phungductung	0:e87aa4c49e95	437	/@} end of group CMSIS_NVIC /
phungductung	0:e87aa4c49e95	438
phungductung	0:e87aa4c49e95	439
phungductung	0:e87aa4c49e95	440	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	441	\defgroup CMSIS_SCB System Control Block (SCB)
phungductung	0:e87aa4c49e95	442	\brief Type definitions for the System Control Block Registers
phungductung	0:e87aa4c49e95	443	@{
phungductung	0:e87aa4c49e95	444	*/
phungductung	0:e87aa4c49e95	445
phungductung	0:e87aa4c49e95	446	/** \brief Structure type to access the System Control Block (SCB).
phungductung	0:e87aa4c49e95	447	*/
phungductung	0:e87aa4c49e95	448	typedef struct
phungductung	0:e87aa4c49e95	449	{
phungductung	0:e87aa4c49e95	450	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
phungductung	0:e87aa4c49e95	451	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
phungductung	0:e87aa4c49e95	452	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
phungductung	0:e87aa4c49e95	453	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
phungductung	0:e87aa4c49e95	454	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
phungductung	0:e87aa4c49e95	455	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
phungductung	0:e87aa4c49e95	456	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
phungductung	0:e87aa4c49e95	457	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
phungductung	0:e87aa4c49e95	458	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
phungductung	0:e87aa4c49e95	459	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
phungductung	0:e87aa4c49e95	460	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
phungductung	0:e87aa4c49e95	461	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
phungductung	0:e87aa4c49e95	462	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
phungductung	0:e87aa4c49e95	463	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
phungductung	0:e87aa4c49e95	464	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
phungductung	0:e87aa4c49e95	465	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
phungductung	0:e87aa4c49e95	466	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
phungductung	0:e87aa4c49e95	467	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
phungductung	0:e87aa4c49e95	468	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
phungductung	0:e87aa4c49e95	469	uint32_t RESERVED0[5];
phungductung	0:e87aa4c49e95	470	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
phungductung	0:e87aa4c49e95	471	} SCB_Type;
phungductung	0:e87aa4c49e95	472
phungductung	0:e87aa4c49e95	473	/* SCB CPUID Register Definitions */
phungductung	0:e87aa4c49e95	474	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
phungductung	0:e87aa4c49e95	475	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
phungductung	0:e87aa4c49e95	476
phungductung	0:e87aa4c49e95	477	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
phungductung	0:e87aa4c49e95	478	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
phungductung	0:e87aa4c49e95	479
phungductung	0:e87aa4c49e95	480	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
phungductung	0:e87aa4c49e95	481	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
phungductung	0:e87aa4c49e95	482
phungductung	0:e87aa4c49e95	483	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
phungductung	0:e87aa4c49e95	484	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
phungductung	0:e87aa4c49e95	485
phungductung	0:e87aa4c49e95	486	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
phungductung	0:e87aa4c49e95	487	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
phungductung	0:e87aa4c49e95	488
phungductung	0:e87aa4c49e95	489	/* SCB Interrupt Control State Register Definitions */
phungductung	0:e87aa4c49e95	490	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
phungductung	0:e87aa4c49e95	491	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
phungductung	0:e87aa4c49e95	492
phungductung	0:e87aa4c49e95	493	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
phungductung	0:e87aa4c49e95	494	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
phungductung	0:e87aa4c49e95	495
phungductung	0:e87aa4c49e95	496	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
phungductung	0:e87aa4c49e95	497	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
phungductung	0:e87aa4c49e95	498
phungductung	0:e87aa4c49e95	499	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
phungductung	0:e87aa4c49e95	500	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
phungductung	0:e87aa4c49e95	501
phungductung	0:e87aa4c49e95	502	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
phungductung	0:e87aa4c49e95	503	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
phungductung	0:e87aa4c49e95	504
phungductung	0:e87aa4c49e95	505	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
phungductung	0:e87aa4c49e95	506	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
phungductung	0:e87aa4c49e95	507
phungductung	0:e87aa4c49e95	508	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
phungductung	0:e87aa4c49e95	509	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
phungductung	0:e87aa4c49e95	510
phungductung	0:e87aa4c49e95	511	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
phungductung	0:e87aa4c49e95	512	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
phungductung	0:e87aa4c49e95	513
phungductung	0:e87aa4c49e95	514	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
phungductung	0:e87aa4c49e95	515	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
phungductung	0:e87aa4c49e95	516
phungductung	0:e87aa4c49e95	517	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
phungductung	0:e87aa4c49e95	518	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
phungductung	0:e87aa4c49e95	519
phungductung	0:e87aa4c49e95	520	/* SCB Vector Table Offset Register Definitions */
phungductung	0:e87aa4c49e95	521	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
phungductung	0:e87aa4c49e95	522	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
phungductung	0:e87aa4c49e95	523
phungductung	0:e87aa4c49e95	524	/* SCB Application Interrupt and Reset Control Register Definitions */
phungductung	0:e87aa4c49e95	525	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
phungductung	0:e87aa4c49e95	526	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
phungductung	0:e87aa4c49e95	527
phungductung	0:e87aa4c49e95	528	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
phungductung	0:e87aa4c49e95	529	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
phungductung	0:e87aa4c49e95	530
phungductung	0:e87aa4c49e95	531	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
phungductung	0:e87aa4c49e95	532	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
phungductung	0:e87aa4c49e95	533
phungductung	0:e87aa4c49e95	534	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
phungductung	0:e87aa4c49e95	535	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
phungductung	0:e87aa4c49e95	536
phungductung	0:e87aa4c49e95	537	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
phungductung	0:e87aa4c49e95	538	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
phungductung	0:e87aa4c49e95	539
phungductung	0:e87aa4c49e95	540	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
phungductung	0:e87aa4c49e95	541	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
phungductung	0:e87aa4c49e95	542
phungductung	0:e87aa4c49e95	543	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
phungductung	0:e87aa4c49e95	544	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
phungductung	0:e87aa4c49e95	545
phungductung	0:e87aa4c49e95	546	/* SCB System Control Register Definitions */
phungductung	0:e87aa4c49e95	547	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
phungductung	0:e87aa4c49e95	548	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
phungductung	0:e87aa4c49e95	549
phungductung	0:e87aa4c49e95	550	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
phungductung	0:e87aa4c49e95	551	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
phungductung	0:e87aa4c49e95	552
phungductung	0:e87aa4c49e95	553	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
phungductung	0:e87aa4c49e95	554	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
phungductung	0:e87aa4c49e95	555
phungductung	0:e87aa4c49e95	556	/* SCB Configuration Control Register Definitions */
phungductung	0:e87aa4c49e95	557	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
phungductung	0:e87aa4c49e95	558	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
phungductung	0:e87aa4c49e95	559
phungductung	0:e87aa4c49e95	560	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
phungductung	0:e87aa4c49e95	561	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
phungductung	0:e87aa4c49e95	562
phungductung	0:e87aa4c49e95	563	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
phungductung	0:e87aa4c49e95	564	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
phungductung	0:e87aa4c49e95	565
phungductung	0:e87aa4c49e95	566	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
phungductung	0:e87aa4c49e95	567	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
phungductung	0:e87aa4c49e95	568
phungductung	0:e87aa4c49e95	569	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
phungductung	0:e87aa4c49e95	570	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
phungductung	0:e87aa4c49e95	571
phungductung	0:e87aa4c49e95	572	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
phungductung	0:e87aa4c49e95	573	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
phungductung	0:e87aa4c49e95	574
phungductung	0:e87aa4c49e95	575	/* SCB System Handler Control and State Register Definitions */
phungductung	0:e87aa4c49e95	576	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
phungductung	0:e87aa4c49e95	577	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
phungductung	0:e87aa4c49e95	578
phungductung	0:e87aa4c49e95	579	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
phungductung	0:e87aa4c49e95	580	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
phungductung	0:e87aa4c49e95	581
phungductung	0:e87aa4c49e95	582	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
phungductung	0:e87aa4c49e95	583	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
phungductung	0:e87aa4c49e95	584
phungductung	0:e87aa4c49e95	585	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
phungductung	0:e87aa4c49e95	586	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
phungductung	0:e87aa4c49e95	587
phungductung	0:e87aa4c49e95	588	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
phungductung	0:e87aa4c49e95	589	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
phungductung	0:e87aa4c49e95	590
phungductung	0:e87aa4c49e95	591	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
phungductung	0:e87aa4c49e95	592	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
phungductung	0:e87aa4c49e95	593
phungductung	0:e87aa4c49e95	594	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
phungductung	0:e87aa4c49e95	595	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
phungductung	0:e87aa4c49e95	596
phungductung	0:e87aa4c49e95	597	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
phungductung	0:e87aa4c49e95	598	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
phungductung	0:e87aa4c49e95	599
phungductung	0:e87aa4c49e95	600	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
phungductung	0:e87aa4c49e95	601	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
phungductung	0:e87aa4c49e95	602
phungductung	0:e87aa4c49e95	603	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
phungductung	0:e87aa4c49e95	604	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
phungductung	0:e87aa4c49e95	605
phungductung	0:e87aa4c49e95	606	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
phungductung	0:e87aa4c49e95	607	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
phungductung	0:e87aa4c49e95	608
phungductung	0:e87aa4c49e95	609	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
phungductung	0:e87aa4c49e95	610	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
phungductung	0:e87aa4c49e95	611
phungductung	0:e87aa4c49e95	612	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
phungductung	0:e87aa4c49e95	613	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
phungductung	0:e87aa4c49e95	614
phungductung	0:e87aa4c49e95	615	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
phungductung	0:e87aa4c49e95	616	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
phungductung	0:e87aa4c49e95	617
phungductung	0:e87aa4c49e95	618	/* SCB Configurable Fault Status Registers Definitions */
phungductung	0:e87aa4c49e95	619	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
phungductung	0:e87aa4c49e95	620	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
phungductung	0:e87aa4c49e95	621
phungductung	0:e87aa4c49e95	622	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
phungductung	0:e87aa4c49e95	623	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
phungductung	0:e87aa4c49e95	624
phungductung	0:e87aa4c49e95	625	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
phungductung	0:e87aa4c49e95	626	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
phungductung	0:e87aa4c49e95	627
phungductung	0:e87aa4c49e95	628	/* SCB Hard Fault Status Registers Definitions */
phungductung	0:e87aa4c49e95	629	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
phungductung	0:e87aa4c49e95	630	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
phungductung	0:e87aa4c49e95	631
phungductung	0:e87aa4c49e95	632	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
phungductung	0:e87aa4c49e95	633	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
phungductung	0:e87aa4c49e95	634
phungductung	0:e87aa4c49e95	635	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
phungductung	0:e87aa4c49e95	636	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
phungductung	0:e87aa4c49e95	637
phungductung	0:e87aa4c49e95	638	/* SCB Debug Fault Status Register Definitions */
phungductung	0:e87aa4c49e95	639	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
phungductung	0:e87aa4c49e95	640	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
phungductung	0:e87aa4c49e95	641
phungductung	0:e87aa4c49e95	642	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
phungductung	0:e87aa4c49e95	643	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
phungductung	0:e87aa4c49e95	644
phungductung	0:e87aa4c49e95	645	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
phungductung	0:e87aa4c49e95	646	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
phungductung	0:e87aa4c49e95	647
phungductung	0:e87aa4c49e95	648	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
phungductung	0:e87aa4c49e95	649	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
phungductung	0:e87aa4c49e95	650
phungductung	0:e87aa4c49e95	651	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
phungductung	0:e87aa4c49e95	652	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
phungductung	0:e87aa4c49e95	653
phungductung	0:e87aa4c49e95	654	/@} end of group CMSIS_SCB /
phungductung	0:e87aa4c49e95	655
phungductung	0:e87aa4c49e95	656
phungductung	0:e87aa4c49e95	657	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	658	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
phungductung	0:e87aa4c49e95	659	\brief Type definitions for the System Control and ID Register not in the SCB
phungductung	0:e87aa4c49e95	660	@{
phungductung	0:e87aa4c49e95	661	*/
phungductung	0:e87aa4c49e95	662
phungductung	0:e87aa4c49e95	663	/** \brief Structure type to access the System Control and ID Register not in the SCB.
phungductung	0:e87aa4c49e95	664	*/
phungductung	0:e87aa4c49e95	665	typedef struct
phungductung	0:e87aa4c49e95	666	{
phungductung	0:e87aa4c49e95	667	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	668	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
phungductung	0:e87aa4c49e95	669	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
phungductung	0:e87aa4c49e95	670	} SCnSCB_Type;
phungductung	0:e87aa4c49e95	671
phungductung	0:e87aa4c49e95	672	/* Interrupt Controller Type Register Definitions */
phungductung	0:e87aa4c49e95	673	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
phungductung	0:e87aa4c49e95	674	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
phungductung	0:e87aa4c49e95	675
phungductung	0:e87aa4c49e95	676	/* Auxiliary Control Register Definitions */
phungductung	0:e87aa4c49e95	677	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
phungductung	0:e87aa4c49e95	678	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
phungductung	0:e87aa4c49e95	679
phungductung	0:e87aa4c49e95	680	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
phungductung	0:e87aa4c49e95	681	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
phungductung	0:e87aa4c49e95	682
phungductung	0:e87aa4c49e95	683	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
phungductung	0:e87aa4c49e95	684	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
phungductung	0:e87aa4c49e95	685
phungductung	0:e87aa4c49e95	686	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
phungductung	0:e87aa4c49e95	687	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
phungductung	0:e87aa4c49e95	688
phungductung	0:e87aa4c49e95	689	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
phungductung	0:e87aa4c49e95	690	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
phungductung	0:e87aa4c49e95	691
phungductung	0:e87aa4c49e95	692	/@} end of group CMSIS_SCnotSCB /
phungductung	0:e87aa4c49e95	693
phungductung	0:e87aa4c49e95	694
phungductung	0:e87aa4c49e95	695	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	696	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
phungductung	0:e87aa4c49e95	697	\brief Type definitions for the System Timer Registers.
phungductung	0:e87aa4c49e95	698	@{
phungductung	0:e87aa4c49e95	699	*/
phungductung	0:e87aa4c49e95	700
phungductung	0:e87aa4c49e95	701	/** \brief Structure type to access the System Timer (SysTick).
phungductung	0:e87aa4c49e95	702	*/
phungductung	0:e87aa4c49e95	703	typedef struct
phungductung	0:e87aa4c49e95	704	{
phungductung	0:e87aa4c49e95	705	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
phungductung	0:e87aa4c49e95	706	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
phungductung	0:e87aa4c49e95	707	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
phungductung	0:e87aa4c49e95	708	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
phungductung	0:e87aa4c49e95	709	} SysTick_Type;
phungductung	0:e87aa4c49e95	710
phungductung	0:e87aa4c49e95	711	/* SysTick Control / Status Register Definitions */
phungductung	0:e87aa4c49e95	712	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
phungductung	0:e87aa4c49e95	713	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
phungductung	0:e87aa4c49e95	714
phungductung	0:e87aa4c49e95	715	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
phungductung	0:e87aa4c49e95	716	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
phungductung	0:e87aa4c49e95	717
phungductung	0:e87aa4c49e95	718	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
phungductung	0:e87aa4c49e95	719	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
phungductung	0:e87aa4c49e95	720
phungductung	0:e87aa4c49e95	721	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
phungductung	0:e87aa4c49e95	722	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
phungductung	0:e87aa4c49e95	723
phungductung	0:e87aa4c49e95	724	/* SysTick Reload Register Definitions */
phungductung	0:e87aa4c49e95	725	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
phungductung	0:e87aa4c49e95	726	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
phungductung	0:e87aa4c49e95	727
phungductung	0:e87aa4c49e95	728	/* SysTick Current Register Definitions */
phungductung	0:e87aa4c49e95	729	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
phungductung	0:e87aa4c49e95	730	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
phungductung	0:e87aa4c49e95	731
phungductung	0:e87aa4c49e95	732	/* SysTick Calibration Register Definitions */
phungductung	0:e87aa4c49e95	733	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
phungductung	0:e87aa4c49e95	734	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
phungductung	0:e87aa4c49e95	735
phungductung	0:e87aa4c49e95	736	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
phungductung	0:e87aa4c49e95	737	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
phungductung	0:e87aa4c49e95	738
phungductung	0:e87aa4c49e95	739	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
phungductung	0:e87aa4c49e95	740	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
phungductung	0:e87aa4c49e95	741
phungductung	0:e87aa4c49e95	742	/@} end of group CMSIS_SysTick /
phungductung	0:e87aa4c49e95	743
phungductung	0:e87aa4c49e95	744
phungductung	0:e87aa4c49e95	745	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	746	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
phungductung	0:e87aa4c49e95	747	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
phungductung	0:e87aa4c49e95	748	@{
phungductung	0:e87aa4c49e95	749	*/
phungductung	0:e87aa4c49e95	750
phungductung	0:e87aa4c49e95	751	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
phungductung	0:e87aa4c49e95	752	*/
phungductung	0:e87aa4c49e95	753	typedef struct
phungductung	0:e87aa4c49e95	754	{
phungductung	0:e87aa4c49e95	755	__O union
phungductung	0:e87aa4c49e95	756	{
phungductung	0:e87aa4c49e95	757	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
phungductung	0:e87aa4c49e95	758	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
phungductung	0:e87aa4c49e95	759	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
phungductung	0:e87aa4c49e95	760	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
phungductung	0:e87aa4c49e95	761	uint32_t RESERVED0[864];
phungductung	0:e87aa4c49e95	762	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
phungductung	0:e87aa4c49e95	763	uint32_t RESERVED1[15];
phungductung	0:e87aa4c49e95	764	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
phungductung	0:e87aa4c49e95	765	uint32_t RESERVED2[15];
phungductung	0:e87aa4c49e95	766	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
phungductung	0:e87aa4c49e95	767	uint32_t RESERVED3[29];
phungductung	0:e87aa4c49e95	768	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
phungductung	0:e87aa4c49e95	769	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
phungductung	0:e87aa4c49e95	770	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
phungductung	0:e87aa4c49e95	771	uint32_t RESERVED4[43];
phungductung	0:e87aa4c49e95	772	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
phungductung	0:e87aa4c49e95	773	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
phungductung	0:e87aa4c49e95	774	uint32_t RESERVED5[6];
phungductung	0:e87aa4c49e95	775	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
phungductung	0:e87aa4c49e95	776	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
phungductung	0:e87aa4c49e95	777	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
phungductung	0:e87aa4c49e95	778	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
phungductung	0:e87aa4c49e95	779	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
phungductung	0:e87aa4c49e95	780	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
phungductung	0:e87aa4c49e95	781	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
phungductung	0:e87aa4c49e95	782	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
phungductung	0:e87aa4c49e95	783	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
phungductung	0:e87aa4c49e95	784	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
phungductung	0:e87aa4c49e95	785	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
phungductung	0:e87aa4c49e95	786	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
phungductung	0:e87aa4c49e95	787	} ITM_Type;
phungductung	0:e87aa4c49e95	788
phungductung	0:e87aa4c49e95	789	/* ITM Trace Privilege Register Definitions */
phungductung	0:e87aa4c49e95	790	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
phungductung	0:e87aa4c49e95	791	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
phungductung	0:e87aa4c49e95	792
phungductung	0:e87aa4c49e95	793	/* ITM Trace Control Register Definitions */
phungductung	0:e87aa4c49e95	794	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
phungductung	0:e87aa4c49e95	795	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
phungductung	0:e87aa4c49e95	796
phungductung	0:e87aa4c49e95	797	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
phungductung	0:e87aa4c49e95	798	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
phungductung	0:e87aa4c49e95	799
phungductung	0:e87aa4c49e95	800	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
phungductung	0:e87aa4c49e95	801	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
phungductung	0:e87aa4c49e95	802
phungductung	0:e87aa4c49e95	803	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
phungductung	0:e87aa4c49e95	804	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
phungductung	0:e87aa4c49e95	805
phungductung	0:e87aa4c49e95	806	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
phungductung	0:e87aa4c49e95	807	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
phungductung	0:e87aa4c49e95	808
phungductung	0:e87aa4c49e95	809	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
phungductung	0:e87aa4c49e95	810	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
phungductung	0:e87aa4c49e95	811
phungductung	0:e87aa4c49e95	812	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
phungductung	0:e87aa4c49e95	813	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
phungductung	0:e87aa4c49e95	814
phungductung	0:e87aa4c49e95	815	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
phungductung	0:e87aa4c49e95	816	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
phungductung	0:e87aa4c49e95	817
phungductung	0:e87aa4c49e95	818	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
phungductung	0:e87aa4c49e95	819	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
phungductung	0:e87aa4c49e95	820
phungductung	0:e87aa4c49e95	821	/* ITM Integration Write Register Definitions */
phungductung	0:e87aa4c49e95	822	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
phungductung	0:e87aa4c49e95	823	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
phungductung	0:e87aa4c49e95	824
phungductung	0:e87aa4c49e95	825	/* ITM Integration Read Register Definitions */
phungductung	0:e87aa4c49e95	826	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
phungductung	0:e87aa4c49e95	827	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
phungductung	0:e87aa4c49e95	828
phungductung	0:e87aa4c49e95	829	/* ITM Integration Mode Control Register Definitions */
phungductung	0:e87aa4c49e95	830	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
phungductung	0:e87aa4c49e95	831	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
phungductung	0:e87aa4c49e95	832
phungductung	0:e87aa4c49e95	833	/* ITM Lock Status Register Definitions */
phungductung	0:e87aa4c49e95	834	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
phungductung	0:e87aa4c49e95	835	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
phungductung	0:e87aa4c49e95	836
phungductung	0:e87aa4c49e95	837	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
phungductung	0:e87aa4c49e95	838	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
phungductung	0:e87aa4c49e95	839
phungductung	0:e87aa4c49e95	840	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
phungductung	0:e87aa4c49e95	841	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
phungductung	0:e87aa4c49e95	842
phungductung	0:e87aa4c49e95	843	/@}/ /* end of group CMSIS_ITM */
phungductung	0:e87aa4c49e95	844
phungductung	0:e87aa4c49e95	845
phungductung	0:e87aa4c49e95	846	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	847	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
phungductung	0:e87aa4c49e95	848	\brief Type definitions for the Data Watchpoint and Trace (DWT)
phungductung	0:e87aa4c49e95	849	@{
phungductung	0:e87aa4c49e95	850	*/
phungductung	0:e87aa4c49e95	851
phungductung	0:e87aa4c49e95	852	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
phungductung	0:e87aa4c49e95	853	*/
phungductung	0:e87aa4c49e95	854	typedef struct
phungductung	0:e87aa4c49e95	855	{
phungductung	0:e87aa4c49e95	856	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
phungductung	0:e87aa4c49e95	857	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
phungductung	0:e87aa4c49e95	858	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
phungductung	0:e87aa4c49e95	859	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
phungductung	0:e87aa4c49e95	860	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
phungductung	0:e87aa4c49e95	861	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
phungductung	0:e87aa4c49e95	862	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
phungductung	0:e87aa4c49e95	863	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
phungductung	0:e87aa4c49e95	864	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
phungductung	0:e87aa4c49e95	865	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
phungductung	0:e87aa4c49e95	866	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
phungductung	0:e87aa4c49e95	867	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	868	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
phungductung	0:e87aa4c49e95	869	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
phungductung	0:e87aa4c49e95	870	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
phungductung	0:e87aa4c49e95	871	uint32_t RESERVED1[1];
phungductung	0:e87aa4c49e95	872	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
phungductung	0:e87aa4c49e95	873	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
phungductung	0:e87aa4c49e95	874	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
phungductung	0:e87aa4c49e95	875	uint32_t RESERVED2[1];
phungductung	0:e87aa4c49e95	876	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
phungductung	0:e87aa4c49e95	877	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
phungductung	0:e87aa4c49e95	878	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
phungductung	0:e87aa4c49e95	879	} DWT_Type;
phungductung	0:e87aa4c49e95	880
phungductung	0:e87aa4c49e95	881	/* DWT Control Register Definitions */
phungductung	0:e87aa4c49e95	882	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
phungductung	0:e87aa4c49e95	883	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
phungductung	0:e87aa4c49e95	884
phungductung	0:e87aa4c49e95	885	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
phungductung	0:e87aa4c49e95	886	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
phungductung	0:e87aa4c49e95	887
phungductung	0:e87aa4c49e95	888	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
phungductung	0:e87aa4c49e95	889	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
phungductung	0:e87aa4c49e95	890
phungductung	0:e87aa4c49e95	891	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
phungductung	0:e87aa4c49e95	892	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
phungductung	0:e87aa4c49e95	893
phungductung	0:e87aa4c49e95	894	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
phungductung	0:e87aa4c49e95	895	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
phungductung	0:e87aa4c49e95	896
phungductung	0:e87aa4c49e95	897	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
phungductung	0:e87aa4c49e95	898	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
phungductung	0:e87aa4c49e95	899
phungductung	0:e87aa4c49e95	900	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
phungductung	0:e87aa4c49e95	901	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
phungductung	0:e87aa4c49e95	902
phungductung	0:e87aa4c49e95	903	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
phungductung	0:e87aa4c49e95	904	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
phungductung	0:e87aa4c49e95	905
phungductung	0:e87aa4c49e95	906	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
phungductung	0:e87aa4c49e95	907	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
phungductung	0:e87aa4c49e95	908
phungductung	0:e87aa4c49e95	909	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
phungductung	0:e87aa4c49e95	910	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
phungductung	0:e87aa4c49e95	911
phungductung	0:e87aa4c49e95	912	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
phungductung	0:e87aa4c49e95	913	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
phungductung	0:e87aa4c49e95	914
phungductung	0:e87aa4c49e95	915	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
phungductung	0:e87aa4c49e95	916	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
phungductung	0:e87aa4c49e95	917
phungductung	0:e87aa4c49e95	918	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
phungductung	0:e87aa4c49e95	919	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
phungductung	0:e87aa4c49e95	920
phungductung	0:e87aa4c49e95	921	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
phungductung	0:e87aa4c49e95	922	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
phungductung	0:e87aa4c49e95	923
phungductung	0:e87aa4c49e95	924	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
phungductung	0:e87aa4c49e95	925	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
phungductung	0:e87aa4c49e95	926
phungductung	0:e87aa4c49e95	927	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
phungductung	0:e87aa4c49e95	928	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
phungductung	0:e87aa4c49e95	929
phungductung	0:e87aa4c49e95	930	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
phungductung	0:e87aa4c49e95	931	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
phungductung	0:e87aa4c49e95	932
phungductung	0:e87aa4c49e95	933	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
phungductung	0:e87aa4c49e95	934	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
phungductung	0:e87aa4c49e95	935
phungductung	0:e87aa4c49e95	936	/* DWT CPI Count Register Definitions */
phungductung	0:e87aa4c49e95	937	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
phungductung	0:e87aa4c49e95	938	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
phungductung	0:e87aa4c49e95	939
phungductung	0:e87aa4c49e95	940	/* DWT Exception Overhead Count Register Definitions */
phungductung	0:e87aa4c49e95	941	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
phungductung	0:e87aa4c49e95	942	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
phungductung	0:e87aa4c49e95	943
phungductung	0:e87aa4c49e95	944	/* DWT Sleep Count Register Definitions */
phungductung	0:e87aa4c49e95	945	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
phungductung	0:e87aa4c49e95	946	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
phungductung	0:e87aa4c49e95	947
phungductung	0:e87aa4c49e95	948	/* DWT LSU Count Register Definitions */
phungductung	0:e87aa4c49e95	949	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
phungductung	0:e87aa4c49e95	950	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
phungductung	0:e87aa4c49e95	951
phungductung	0:e87aa4c49e95	952	/* DWT Folded-instruction Count Register Definitions */
phungductung	0:e87aa4c49e95	953	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
phungductung	0:e87aa4c49e95	954	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
phungductung	0:e87aa4c49e95	955
phungductung	0:e87aa4c49e95	956	/* DWT Comparator Mask Register Definitions */
phungductung	0:e87aa4c49e95	957	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
phungductung	0:e87aa4c49e95	958	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
phungductung	0:e87aa4c49e95	959
phungductung	0:e87aa4c49e95	960	/* DWT Comparator Function Register Definitions */
phungductung	0:e87aa4c49e95	961	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
phungductung	0:e87aa4c49e95	962	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
phungductung	0:e87aa4c49e95	963
phungductung	0:e87aa4c49e95	964	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
phungductung	0:e87aa4c49e95	965	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
phungductung	0:e87aa4c49e95	966
phungductung	0:e87aa4c49e95	967	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
phungductung	0:e87aa4c49e95	968	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
phungductung	0:e87aa4c49e95	969
phungductung	0:e87aa4c49e95	970	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
phungductung	0:e87aa4c49e95	971	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
phungductung	0:e87aa4c49e95	972
phungductung	0:e87aa4c49e95	973	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
phungductung	0:e87aa4c49e95	974	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
phungductung	0:e87aa4c49e95	975
phungductung	0:e87aa4c49e95	976	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
phungductung	0:e87aa4c49e95	977	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
phungductung	0:e87aa4c49e95	978
phungductung	0:e87aa4c49e95	979	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
phungductung	0:e87aa4c49e95	980	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
phungductung	0:e87aa4c49e95	981
phungductung	0:e87aa4c49e95	982	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
phungductung	0:e87aa4c49e95	983	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
phungductung	0:e87aa4c49e95	984
phungductung	0:e87aa4c49e95	985	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
phungductung	0:e87aa4c49e95	986	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
phungductung	0:e87aa4c49e95	987
phungductung	0:e87aa4c49e95	988	/@}/ /* end of group CMSIS_DWT */
phungductung	0:e87aa4c49e95	989
phungductung	0:e87aa4c49e95	990
phungductung	0:e87aa4c49e95	991	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	992	\defgroup CMSIS_TPI Trace Port Interface (TPI)
phungductung	0:e87aa4c49e95	993	\brief Type definitions for the Trace Port Interface (TPI)
phungductung	0:e87aa4c49e95	994	@{
phungductung	0:e87aa4c49e95	995	*/
phungductung	0:e87aa4c49e95	996
phungductung	0:e87aa4c49e95	997	/** \brief Structure type to access the Trace Port Interface Register (TPI).
phungductung	0:e87aa4c49e95	998	*/
phungductung	0:e87aa4c49e95	999	typedef struct
phungductung	0:e87aa4c49e95	1000	{
phungductung	0:e87aa4c49e95	1001	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
phungductung	0:e87aa4c49e95	1002	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
phungductung	0:e87aa4c49e95	1003	uint32_t RESERVED0[2];
phungductung	0:e87aa4c49e95	1004	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
phungductung	0:e87aa4c49e95	1005	uint32_t RESERVED1[55];
phungductung	0:e87aa4c49e95	1006	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
phungductung	0:e87aa4c49e95	1007	uint32_t RESERVED2[131];
phungductung	0:e87aa4c49e95	1008	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
phungductung	0:e87aa4c49e95	1009	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
phungductung	0:e87aa4c49e95	1010	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
phungductung	0:e87aa4c49e95	1011	uint32_t RESERVED3[759];
phungductung	0:e87aa4c49e95	1012	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
phungductung	0:e87aa4c49e95	1013	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
phungductung	0:e87aa4c49e95	1014	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
phungductung	0:e87aa4c49e95	1015	uint32_t RESERVED4[1];
phungductung	0:e87aa4c49e95	1016	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
phungductung	0:e87aa4c49e95	1017	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
phungductung	0:e87aa4c49e95	1018	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
phungductung	0:e87aa4c49e95	1019	uint32_t RESERVED5[39];
phungductung	0:e87aa4c49e95	1020	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
phungductung	0:e87aa4c49e95	1021	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
phungductung	0:e87aa4c49e95	1022	uint32_t RESERVED7[8];
phungductung	0:e87aa4c49e95	1023	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
phungductung	0:e87aa4c49e95	1024	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
phungductung	0:e87aa4c49e95	1025	} TPI_Type;
phungductung	0:e87aa4c49e95	1026
phungductung	0:e87aa4c49e95	1027	/* TPI Asynchronous Clock Prescaler Register Definitions */
phungductung	0:e87aa4c49e95	1028	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
phungductung	0:e87aa4c49e95	1029	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
phungductung	0:e87aa4c49e95	1030
phungductung	0:e87aa4c49e95	1031	/* TPI Selected Pin Protocol Register Definitions */
phungductung	0:e87aa4c49e95	1032	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
phungductung	0:e87aa4c49e95	1033	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
phungductung	0:e87aa4c49e95	1034
phungductung	0:e87aa4c49e95	1035	/* TPI Formatter and Flush Status Register Definitions */
phungductung	0:e87aa4c49e95	1036	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
phungductung	0:e87aa4c49e95	1037	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
phungductung	0:e87aa4c49e95	1038
phungductung	0:e87aa4c49e95	1039	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
phungductung	0:e87aa4c49e95	1040	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
phungductung	0:e87aa4c49e95	1041
phungductung	0:e87aa4c49e95	1042	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
phungductung	0:e87aa4c49e95	1043	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
phungductung	0:e87aa4c49e95	1044
phungductung	0:e87aa4c49e95	1045	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
phungductung	0:e87aa4c49e95	1046	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
phungductung	0:e87aa4c49e95	1047
phungductung	0:e87aa4c49e95	1048	/* TPI Formatter and Flush Control Register Definitions */
phungductung	0:e87aa4c49e95	1049	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
phungductung	0:e87aa4c49e95	1050	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
phungductung	0:e87aa4c49e95	1051
phungductung	0:e87aa4c49e95	1052	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
phungductung	0:e87aa4c49e95	1053	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
phungductung	0:e87aa4c49e95	1054
phungductung	0:e87aa4c49e95	1055	/* TPI TRIGGER Register Definitions */
phungductung	0:e87aa4c49e95	1056	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
phungductung	0:e87aa4c49e95	1057	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
phungductung	0:e87aa4c49e95	1058
phungductung	0:e87aa4c49e95	1059	/* TPI Integration ETM Data Register Definitions (FIFO0) */
phungductung	0:e87aa4c49e95	1060	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
phungductung	0:e87aa4c49e95	1061	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1062
phungductung	0:e87aa4c49e95	1063	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
phungductung	0:e87aa4c49e95	1064	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
phungductung	0:e87aa4c49e95	1065
phungductung	0:e87aa4c49e95	1066	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
phungductung	0:e87aa4c49e95	1067	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1068
phungductung	0:e87aa4c49e95	1069	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
phungductung	0:e87aa4c49e95	1070	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
phungductung	0:e87aa4c49e95	1071
phungductung	0:e87aa4c49e95	1072	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
phungductung	0:e87aa4c49e95	1073	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
phungductung	0:e87aa4c49e95	1074
phungductung	0:e87aa4c49e95	1075	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
phungductung	0:e87aa4c49e95	1076	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
phungductung	0:e87aa4c49e95	1077
phungductung	0:e87aa4c49e95	1078	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
phungductung	0:e87aa4c49e95	1079	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
phungductung	0:e87aa4c49e95	1080
phungductung	0:e87aa4c49e95	1081	/* TPI ITATBCTR2 Register Definitions */
phungductung	0:e87aa4c49e95	1082	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
phungductung	0:e87aa4c49e95	1083	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
phungductung	0:e87aa4c49e95	1084
phungductung	0:e87aa4c49e95	1085	/* TPI Integration ITM Data Register Definitions (FIFO1) */
phungductung	0:e87aa4c49e95	1086	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
phungductung	0:e87aa4c49e95	1087	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1088
phungductung	0:e87aa4c49e95	1089	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
phungductung	0:e87aa4c49e95	1090	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
phungductung	0:e87aa4c49e95	1091
phungductung	0:e87aa4c49e95	1092	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
phungductung	0:e87aa4c49e95	1093	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
phungductung	0:e87aa4c49e95	1094
phungductung	0:e87aa4c49e95	1095	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
phungductung	0:e87aa4c49e95	1096	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
phungductung	0:e87aa4c49e95	1097
phungductung	0:e87aa4c49e95	1098	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
phungductung	0:e87aa4c49e95	1099	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
phungductung	0:e87aa4c49e95	1100
phungductung	0:e87aa4c49e95	1101	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
phungductung	0:e87aa4c49e95	1102	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
phungductung	0:e87aa4c49e95	1103
phungductung	0:e87aa4c49e95	1104	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
phungductung	0:e87aa4c49e95	1105	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
phungductung	0:e87aa4c49e95	1106
phungductung	0:e87aa4c49e95	1107	/* TPI ITATBCTR0 Register Definitions */
phungductung	0:e87aa4c49e95	1108	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
phungductung	0:e87aa4c49e95	1109	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
phungductung	0:e87aa4c49e95	1110
phungductung	0:e87aa4c49e95	1111	/* TPI Integration Mode Control Register Definitions */
phungductung	0:e87aa4c49e95	1112	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
phungductung	0:e87aa4c49e95	1113	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
phungductung	0:e87aa4c49e95	1114
phungductung	0:e87aa4c49e95	1115	/* TPI DEVID Register Definitions */
phungductung	0:e87aa4c49e95	1116	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
phungductung	0:e87aa4c49e95	1117	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
phungductung	0:e87aa4c49e95	1118
phungductung	0:e87aa4c49e95	1119	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
phungductung	0:e87aa4c49e95	1120	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
phungductung	0:e87aa4c49e95	1121
phungductung	0:e87aa4c49e95	1122	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
phungductung	0:e87aa4c49e95	1123	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
phungductung	0:e87aa4c49e95	1124
phungductung	0:e87aa4c49e95	1125	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
phungductung	0:e87aa4c49e95	1126	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
phungductung	0:e87aa4c49e95	1127
phungductung	0:e87aa4c49e95	1128	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
phungductung	0:e87aa4c49e95	1129	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
phungductung	0:e87aa4c49e95	1130
phungductung	0:e87aa4c49e95	1131	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
phungductung	0:e87aa4c49e95	1132	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
phungductung	0:e87aa4c49e95	1133
phungductung	0:e87aa4c49e95	1134	/* TPI DEVTYPE Register Definitions */
phungductung	0:e87aa4c49e95	1135	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
phungductung	0:e87aa4c49e95	1136	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
phungductung	0:e87aa4c49e95	1137
phungductung	0:e87aa4c49e95	1138	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
phungductung	0:e87aa4c49e95	1139	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
phungductung	0:e87aa4c49e95	1140
phungductung	0:e87aa4c49e95	1141	/@}/ /* end of group CMSIS_TPI */
phungductung	0:e87aa4c49e95	1142
phungductung	0:e87aa4c49e95	1143
phungductung	0:e87aa4c49e95	1144	#if (__MPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1145	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1146	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
phungductung	0:e87aa4c49e95	1147	\brief Type definitions for the Memory Protection Unit (MPU)
phungductung	0:e87aa4c49e95	1148	@{
phungductung	0:e87aa4c49e95	1149	*/
phungductung	0:e87aa4c49e95	1150
phungductung	0:e87aa4c49e95	1151	/** \brief Structure type to access the Memory Protection Unit (MPU).
phungductung	0:e87aa4c49e95	1152	*/
phungductung	0:e87aa4c49e95	1153	typedef struct
phungductung	0:e87aa4c49e95	1154	{
phungductung	0:e87aa4c49e95	1155	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
phungductung	0:e87aa4c49e95	1156	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
phungductung	0:e87aa4c49e95	1157	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
phungductung	0:e87aa4c49e95	1158	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
phungductung	0:e87aa4c49e95	1159	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1160	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
phungductung	0:e87aa4c49e95	1161	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1162	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
phungductung	0:e87aa4c49e95	1163	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1164	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
phungductung	0:e87aa4c49e95	1165	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
phungductung	0:e87aa4c49e95	1166	} MPU_Type;
phungductung	0:e87aa4c49e95	1167
phungductung	0:e87aa4c49e95	1168	/* MPU Type Register */
phungductung	0:e87aa4c49e95	1169	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
phungductung	0:e87aa4c49e95	1170	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
phungductung	0:e87aa4c49e95	1171
phungductung	0:e87aa4c49e95	1172	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
phungductung	0:e87aa4c49e95	1173	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
phungductung	0:e87aa4c49e95	1174
phungductung	0:e87aa4c49e95	1175	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
phungductung	0:e87aa4c49e95	1176	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
phungductung	0:e87aa4c49e95	1177
phungductung	0:e87aa4c49e95	1178	/* MPU Control Register */
phungductung	0:e87aa4c49e95	1179	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
phungductung	0:e87aa4c49e95	1180	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
phungductung	0:e87aa4c49e95	1181
phungductung	0:e87aa4c49e95	1182	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
phungductung	0:e87aa4c49e95	1183	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
phungductung	0:e87aa4c49e95	1184
phungductung	0:e87aa4c49e95	1185	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
phungductung	0:e87aa4c49e95	1186	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
phungductung	0:e87aa4c49e95	1187
phungductung	0:e87aa4c49e95	1188	/* MPU Region Number Register */
phungductung	0:e87aa4c49e95	1189	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
phungductung	0:e87aa4c49e95	1190	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
phungductung	0:e87aa4c49e95	1191
phungductung	0:e87aa4c49e95	1192	/* MPU Region Base Address Register */
phungductung	0:e87aa4c49e95	1193	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
phungductung	0:e87aa4c49e95	1194	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
phungductung	0:e87aa4c49e95	1195
phungductung	0:e87aa4c49e95	1196	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
phungductung	0:e87aa4c49e95	1197	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
phungductung	0:e87aa4c49e95	1198
phungductung	0:e87aa4c49e95	1199	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
phungductung	0:e87aa4c49e95	1200	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
phungductung	0:e87aa4c49e95	1201
phungductung	0:e87aa4c49e95	1202	/* MPU Region Attribute and Size Register */
phungductung	0:e87aa4c49e95	1203	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
phungductung	0:e87aa4c49e95	1204	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
phungductung	0:e87aa4c49e95	1205
phungductung	0:e87aa4c49e95	1206	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
phungductung	0:e87aa4c49e95	1207	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
phungductung	0:e87aa4c49e95	1208
phungductung	0:e87aa4c49e95	1209	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
phungductung	0:e87aa4c49e95	1210	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
phungductung	0:e87aa4c49e95	1211
phungductung	0:e87aa4c49e95	1212	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
phungductung	0:e87aa4c49e95	1213	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
phungductung	0:e87aa4c49e95	1214
phungductung	0:e87aa4c49e95	1215	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
phungductung	0:e87aa4c49e95	1216	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
phungductung	0:e87aa4c49e95	1217
phungductung	0:e87aa4c49e95	1218	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
phungductung	0:e87aa4c49e95	1219	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
phungductung	0:e87aa4c49e95	1220
phungductung	0:e87aa4c49e95	1221	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
phungductung	0:e87aa4c49e95	1222	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
phungductung	0:e87aa4c49e95	1223
phungductung	0:e87aa4c49e95	1224	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
phungductung	0:e87aa4c49e95	1225	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
phungductung	0:e87aa4c49e95	1226
phungductung	0:e87aa4c49e95	1227	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
phungductung	0:e87aa4c49e95	1228	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
phungductung	0:e87aa4c49e95	1229
phungductung	0:e87aa4c49e95	1230	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
phungductung	0:e87aa4c49e95	1231	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
phungductung	0:e87aa4c49e95	1232
phungductung	0:e87aa4c49e95	1233	/@} end of group CMSIS_MPU /
phungductung	0:e87aa4c49e95	1234	#endif
phungductung	0:e87aa4c49e95	1235
phungductung	0:e87aa4c49e95	1236
phungductung	0:e87aa4c49e95	1237	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1238	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1239	\defgroup CMSIS_FPU Floating Point Unit (FPU)
phungductung	0:e87aa4c49e95	1240	\brief Type definitions for the Floating Point Unit (FPU)
phungductung	0:e87aa4c49e95	1241	@{
phungductung	0:e87aa4c49e95	1242	*/
phungductung	0:e87aa4c49e95	1243
phungductung	0:e87aa4c49e95	1244	/** \brief Structure type to access the Floating Point Unit (FPU).
phungductung	0:e87aa4c49e95	1245	*/
phungductung	0:e87aa4c49e95	1246	typedef struct
phungductung	0:e87aa4c49e95	1247	{
phungductung	0:e87aa4c49e95	1248	uint32_t RESERVED0[1];
phungductung	0:e87aa4c49e95	1249	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
phungductung	0:e87aa4c49e95	1250	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
phungductung	0:e87aa4c49e95	1251	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
phungductung	0:e87aa4c49e95	1252	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
phungductung	0:e87aa4c49e95	1253	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
phungductung	0:e87aa4c49e95	1254	} FPU_Type;
phungductung	0:e87aa4c49e95	1255
phungductung	0:e87aa4c49e95	1256	/* Floating-Point Context Control Register */
phungductung	0:e87aa4c49e95	1257	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
phungductung	0:e87aa4c49e95	1258	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
phungductung	0:e87aa4c49e95	1259
phungductung	0:e87aa4c49e95	1260	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
phungductung	0:e87aa4c49e95	1261	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
phungductung	0:e87aa4c49e95	1262
phungductung	0:e87aa4c49e95	1263	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
phungductung	0:e87aa4c49e95	1264	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
phungductung	0:e87aa4c49e95	1265
phungductung	0:e87aa4c49e95	1266	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
phungductung	0:e87aa4c49e95	1267	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
phungductung	0:e87aa4c49e95	1268
phungductung	0:e87aa4c49e95	1269	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
phungductung	0:e87aa4c49e95	1270	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
phungductung	0:e87aa4c49e95	1271
phungductung	0:e87aa4c49e95	1272	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
phungductung	0:e87aa4c49e95	1273	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
phungductung	0:e87aa4c49e95	1274
phungductung	0:e87aa4c49e95	1275	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
phungductung	0:e87aa4c49e95	1276	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
phungductung	0:e87aa4c49e95	1277
phungductung	0:e87aa4c49e95	1278	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
phungductung	0:e87aa4c49e95	1279	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
phungductung	0:e87aa4c49e95	1280
phungductung	0:e87aa4c49e95	1281	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
phungductung	0:e87aa4c49e95	1282	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
phungductung	0:e87aa4c49e95	1283
phungductung	0:e87aa4c49e95	1284	/* Floating-Point Context Address Register */
phungductung	0:e87aa4c49e95	1285	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
phungductung	0:e87aa4c49e95	1286	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
phungductung	0:e87aa4c49e95	1287
phungductung	0:e87aa4c49e95	1288	/* Floating-Point Default Status Control Register */
phungductung	0:e87aa4c49e95	1289	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
phungductung	0:e87aa4c49e95	1290	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
phungductung	0:e87aa4c49e95	1291
phungductung	0:e87aa4c49e95	1292	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
phungductung	0:e87aa4c49e95	1293	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
phungductung	0:e87aa4c49e95	1294
phungductung	0:e87aa4c49e95	1295	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
phungductung	0:e87aa4c49e95	1296	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
phungductung	0:e87aa4c49e95	1297
phungductung	0:e87aa4c49e95	1298	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
phungductung	0:e87aa4c49e95	1299	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
phungductung	0:e87aa4c49e95	1300
phungductung	0:e87aa4c49e95	1301	/* Media and FP Feature Register 0 */
phungductung	0:e87aa4c49e95	1302	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
phungductung	0:e87aa4c49e95	1303	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
phungductung	0:e87aa4c49e95	1304
phungductung	0:e87aa4c49e95	1305	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
phungductung	0:e87aa4c49e95	1306	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
phungductung	0:e87aa4c49e95	1307
phungductung	0:e87aa4c49e95	1308	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
phungductung	0:e87aa4c49e95	1309	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
phungductung	0:e87aa4c49e95	1310
phungductung	0:e87aa4c49e95	1311	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
phungductung	0:e87aa4c49e95	1312	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
phungductung	0:e87aa4c49e95	1313
phungductung	0:e87aa4c49e95	1314	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
phungductung	0:e87aa4c49e95	1315	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
phungductung	0:e87aa4c49e95	1316
phungductung	0:e87aa4c49e95	1317	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
phungductung	0:e87aa4c49e95	1318	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
phungductung	0:e87aa4c49e95	1319
phungductung	0:e87aa4c49e95	1320	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
phungductung	0:e87aa4c49e95	1321	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
phungductung	0:e87aa4c49e95	1322
phungductung	0:e87aa4c49e95	1323	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
phungductung	0:e87aa4c49e95	1324	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
phungductung	0:e87aa4c49e95	1325
phungductung	0:e87aa4c49e95	1326	/* Media and FP Feature Register 1 */
phungductung	0:e87aa4c49e95	1327	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
phungductung	0:e87aa4c49e95	1328	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
phungductung	0:e87aa4c49e95	1329
phungductung	0:e87aa4c49e95	1330	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
phungductung	0:e87aa4c49e95	1331	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
phungductung	0:e87aa4c49e95	1332
phungductung	0:e87aa4c49e95	1333	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
phungductung	0:e87aa4c49e95	1334	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
phungductung	0:e87aa4c49e95	1335
phungductung	0:e87aa4c49e95	1336	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
phungductung	0:e87aa4c49e95	1337	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
phungductung	0:e87aa4c49e95	1338
phungductung	0:e87aa4c49e95	1339	/@} end of group CMSIS_FPU /
phungductung	0:e87aa4c49e95	1340	#endif
phungductung	0:e87aa4c49e95	1341
phungductung	0:e87aa4c49e95	1342
phungductung	0:e87aa4c49e95	1343	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1344	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
phungductung	0:e87aa4c49e95	1345	\brief Type definitions for the Core Debug Registers
phungductung	0:e87aa4c49e95	1346	@{
phungductung	0:e87aa4c49e95	1347	*/
phungductung	0:e87aa4c49e95	1348
phungductung	0:e87aa4c49e95	1349	/** \brief Structure type to access the Core Debug Register (CoreDebug).
phungductung	0:e87aa4c49e95	1350	*/
phungductung	0:e87aa4c49e95	1351	typedef struct
phungductung	0:e87aa4c49e95	1352	{
phungductung	0:e87aa4c49e95	1353	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
phungductung	0:e87aa4c49e95	1354	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
phungductung	0:e87aa4c49e95	1355	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
phungductung	0:e87aa4c49e95	1356	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
phungductung	0:e87aa4c49e95	1357	} CoreDebug_Type;
phungductung	0:e87aa4c49e95	1358
phungductung	0:e87aa4c49e95	1359	/* Debug Halting Control and Status Register */
phungductung	0:e87aa4c49e95	1360	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
phungductung	0:e87aa4c49e95	1361	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
phungductung	0:e87aa4c49e95	1362
phungductung	0:e87aa4c49e95	1363	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
phungductung	0:e87aa4c49e95	1364	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
phungductung	0:e87aa4c49e95	1365
phungductung	0:e87aa4c49e95	1366	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
phungductung	0:e87aa4c49e95	1367	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
phungductung	0:e87aa4c49e95	1368
phungductung	0:e87aa4c49e95	1369	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
phungductung	0:e87aa4c49e95	1370	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
phungductung	0:e87aa4c49e95	1371
phungductung	0:e87aa4c49e95	1372	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
phungductung	0:e87aa4c49e95	1373	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
phungductung	0:e87aa4c49e95	1374
phungductung	0:e87aa4c49e95	1375	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
phungductung	0:e87aa4c49e95	1376	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
phungductung	0:e87aa4c49e95	1377
phungductung	0:e87aa4c49e95	1378	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
phungductung	0:e87aa4c49e95	1379	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
phungductung	0:e87aa4c49e95	1380
phungductung	0:e87aa4c49e95	1381	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
phungductung	0:e87aa4c49e95	1382	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
phungductung	0:e87aa4c49e95	1383
phungductung	0:e87aa4c49e95	1384	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
phungductung	0:e87aa4c49e95	1385	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
phungductung	0:e87aa4c49e95	1386
phungductung	0:e87aa4c49e95	1387	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
phungductung	0:e87aa4c49e95	1388	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
phungductung	0:e87aa4c49e95	1389
phungductung	0:e87aa4c49e95	1390	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
phungductung	0:e87aa4c49e95	1391	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
phungductung	0:e87aa4c49e95	1392
phungductung	0:e87aa4c49e95	1393	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
phungductung	0:e87aa4c49e95	1394	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
phungductung	0:e87aa4c49e95	1395
phungductung	0:e87aa4c49e95	1396	/* Debug Core Register Selector Register */
phungductung	0:e87aa4c49e95	1397	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
phungductung	0:e87aa4c49e95	1398	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
phungductung	0:e87aa4c49e95	1399
phungductung	0:e87aa4c49e95	1400	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
phungductung	0:e87aa4c49e95	1401	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
phungductung	0:e87aa4c49e95	1402
phungductung	0:e87aa4c49e95	1403	/* Debug Exception and Monitor Control Register */
phungductung	0:e87aa4c49e95	1404	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
phungductung	0:e87aa4c49e95	1405	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
phungductung	0:e87aa4c49e95	1406
phungductung	0:e87aa4c49e95	1407	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
phungductung	0:e87aa4c49e95	1408	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
phungductung	0:e87aa4c49e95	1409
phungductung	0:e87aa4c49e95	1410	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
phungductung	0:e87aa4c49e95	1411	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
phungductung	0:e87aa4c49e95	1412
phungductung	0:e87aa4c49e95	1413	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
phungductung	0:e87aa4c49e95	1414	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
phungductung	0:e87aa4c49e95	1415
phungductung	0:e87aa4c49e95	1416	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
phungductung	0:e87aa4c49e95	1417	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
phungductung	0:e87aa4c49e95	1418
phungductung	0:e87aa4c49e95	1419	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
phungductung	0:e87aa4c49e95	1420	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
phungductung	0:e87aa4c49e95	1421
phungductung	0:e87aa4c49e95	1422	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
phungductung	0:e87aa4c49e95	1423	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
phungductung	0:e87aa4c49e95	1424
phungductung	0:e87aa4c49e95	1425	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
phungductung	0:e87aa4c49e95	1426	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
phungductung	0:e87aa4c49e95	1427
phungductung	0:e87aa4c49e95	1428	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
phungductung	0:e87aa4c49e95	1429	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
phungductung	0:e87aa4c49e95	1430
phungductung	0:e87aa4c49e95	1431	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
phungductung	0:e87aa4c49e95	1432	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
phungductung	0:e87aa4c49e95	1433
phungductung	0:e87aa4c49e95	1434	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
phungductung	0:e87aa4c49e95	1435	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
phungductung	0:e87aa4c49e95	1436
phungductung	0:e87aa4c49e95	1437	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
phungductung	0:e87aa4c49e95	1438	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
phungductung	0:e87aa4c49e95	1439
phungductung	0:e87aa4c49e95	1440	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
phungductung	0:e87aa4c49e95	1441	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
phungductung	0:e87aa4c49e95	1442
phungductung	0:e87aa4c49e95	1443	/@} end of group CMSIS_CoreDebug /
phungductung	0:e87aa4c49e95	1444
phungductung	0:e87aa4c49e95	1445
phungductung	0:e87aa4c49e95	1446	/** \ingroup CMSIS_core_register
phungductung	0:e87aa4c49e95	1447	\defgroup CMSIS_core_base Core Definitions
phungductung	0:e87aa4c49e95	1448	\brief Definitions for base addresses, unions, and structures.
phungductung	0:e87aa4c49e95	1449	@{
phungductung	0:e87aa4c49e95	1450	*/
phungductung	0:e87aa4c49e95	1451
phungductung	0:e87aa4c49e95	1452	/* Memory mapping of Cortex-M4 Hardware */
phungductung	0:e87aa4c49e95	1453	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
phungductung	0:e87aa4c49e95	1454	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
phungductung	0:e87aa4c49e95	1455	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
phungductung	0:e87aa4c49e95	1456	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
phungductung	0:e87aa4c49e95	1457	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
phungductung	0:e87aa4c49e95	1458	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
phungductung	0:e87aa4c49e95	1459	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
phungductung	0:e87aa4c49e95	1460	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
phungductung	0:e87aa4c49e95	1461
phungductung	0:e87aa4c49e95	1462	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
phungductung	0:e87aa4c49e95	1463	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
phungductung	0:e87aa4c49e95	1464	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
phungductung	0:e87aa4c49e95	1465	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
phungductung	0:e87aa4c49e95	1466	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
phungductung	0:e87aa4c49e95	1467	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
phungductung	0:e87aa4c49e95	1468	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
phungductung	0:e87aa4c49e95	1469	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
phungductung	0:e87aa4c49e95	1470
phungductung	0:e87aa4c49e95	1471	#if (__MPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1472	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
phungductung	0:e87aa4c49e95	1473	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
phungductung	0:e87aa4c49e95	1474	#endif
phungductung	0:e87aa4c49e95	1475
phungductung	0:e87aa4c49e95	1476	#if (__FPU_PRESENT == 1)
phungductung	0:e87aa4c49e95	1477	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
phungductung	0:e87aa4c49e95	1478	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
phungductung	0:e87aa4c49e95	1479	#endif
phungductung	0:e87aa4c49e95	1480
phungductung	0:e87aa4c49e95	1481	/@} /
phungductung	0:e87aa4c49e95	1482
phungductung	0:e87aa4c49e95	1483
phungductung	0:e87aa4c49e95	1484
phungductung	0:e87aa4c49e95	1485	/*******************************************************************************
phungductung	0:e87aa4c49e95	1486	* Hardware Abstraction Layer
phungductung	0:e87aa4c49e95	1487	Core Function Interface contains:
phungductung	0:e87aa4c49e95	1488	- Core NVIC Functions
phungductung	0:e87aa4c49e95	1489	- Core SysTick Functions
phungductung	0:e87aa4c49e95	1490	- Core Debug Functions
phungductung	0:e87aa4c49e95	1491	- Core Register Access Functions
phungductung	0:e87aa4c49e95	1492	******************************************************************************/
phungductung	0:e87aa4c49e95	1493	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
phungductung	0:e87aa4c49e95	1494	*/
phungductung	0:e87aa4c49e95	1495
phungductung	0:e87aa4c49e95	1496
phungductung	0:e87aa4c49e95	1497
phungductung	0:e87aa4c49e95	1498	/* ########################## NVIC functions #################################### */
phungductung	0:e87aa4c49e95	1499	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	1500	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
phungductung	0:e87aa4c49e95	1501	\brief Functions that manage interrupts and exceptions via the NVIC.
phungductung	0:e87aa4c49e95	1502	@{
phungductung	0:e87aa4c49e95	1503	*/
phungductung	0:e87aa4c49e95	1504
phungductung	0:e87aa4c49e95	1505	/** \brief Set Priority Grouping
phungductung	0:e87aa4c49e95	1506
phungductung	0:e87aa4c49e95	1507	The function sets the priority grouping field using the required unlock sequence.
phungductung	0:e87aa4c49e95	1508	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
phungductung	0:e87aa4c49e95	1509	Only values from 0..7 are used.
phungductung	0:e87aa4c49e95	1510	In case of a conflict between priority grouping and available
phungductung	0:e87aa4c49e95	1511	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
phungductung	0:e87aa4c49e95	1512
phungductung	0:e87aa4c49e95	1513	\param [in] PriorityGroup Priority grouping field.
phungductung	0:e87aa4c49e95	1514	*/
phungductung	0:e87aa4c49e95	1515	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
phungductung	0:e87aa4c49e95	1516	{
phungductung	0:e87aa4c49e95	1517	uint32_t reg_value;
phungductung	0:e87aa4c49e95	1518	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung	0:e87aa4c49e95	1519
phungductung	0:e87aa4c49e95	1520	reg_value = SCB->AIRCR; /* read old register configuration */
phungductung	0:e87aa4c49e95	1521	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
phungductung	0:e87aa4c49e95	1522	reg_value = (reg_value \|
phungductung	0:e87aa4c49e95	1523	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
phungductung	0:e87aa4c49e95	1524	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
phungductung	0:e87aa4c49e95	1525	SCB->AIRCR = reg_value;
phungductung	0:e87aa4c49e95	1526	}
phungductung	0:e87aa4c49e95	1527
phungductung	0:e87aa4c49e95	1528
phungductung	0:e87aa4c49e95	1529	/** \brief Get Priority Grouping
phungductung	0:e87aa4c49e95	1530
phungductung	0:e87aa4c49e95	1531	The function reads the priority grouping field from the NVIC Interrupt Controller.
phungductung	0:e87aa4c49e95	1532
phungductung	0:e87aa4c49e95	1533	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
phungductung	0:e87aa4c49e95	1534	*/
phungductung	0:e87aa4c49e95	1535	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
phungductung	0:e87aa4c49e95	1536	{
phungductung	0:e87aa4c49e95	1537	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
phungductung	0:e87aa4c49e95	1538	}
phungductung	0:e87aa4c49e95	1539
phungductung	0:e87aa4c49e95	1540
phungductung	0:e87aa4c49e95	1541	/** \brief Enable External Interrupt
phungductung	0:e87aa4c49e95	1542
phungductung	0:e87aa4c49e95	1543	The function enables a device-specific interrupt in the NVIC interrupt controller.
phungductung	0:e87aa4c49e95	1544
phungductung	0:e87aa4c49e95	1545	\param [in] IRQn External interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1546	*/
phungductung	0:e87aa4c49e95	1547	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1548	{
phungductung	0:e87aa4c49e95	1549	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1550	}
phungductung	0:e87aa4c49e95	1551
phungductung	0:e87aa4c49e95	1552
phungductung	0:e87aa4c49e95	1553	/** \brief Disable External Interrupt
phungductung	0:e87aa4c49e95	1554
phungductung	0:e87aa4c49e95	1555	The function disables a device-specific interrupt in the NVIC interrupt controller.
phungductung	0:e87aa4c49e95	1556
phungductung	0:e87aa4c49e95	1557	\param [in] IRQn External interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1558	*/
phungductung	0:e87aa4c49e95	1559	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1560	{
phungductung	0:e87aa4c49e95	1561	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1562	}
phungductung	0:e87aa4c49e95	1563
phungductung	0:e87aa4c49e95	1564
phungductung	0:e87aa4c49e95	1565	/** \brief Get Pending Interrupt
phungductung	0:e87aa4c49e95	1566
phungductung	0:e87aa4c49e95	1567	The function reads the pending register in the NVIC and returns the pending bit
phungductung	0:e87aa4c49e95	1568	for the specified interrupt.
phungductung	0:e87aa4c49e95	1569
phungductung	0:e87aa4c49e95	1570	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1571
phungductung	0:e87aa4c49e95	1572	\return 0 Interrupt status is not pending.
phungductung	0:e87aa4c49e95	1573	\return 1 Interrupt status is pending.
phungductung	0:e87aa4c49e95	1574	*/
phungductung	0:e87aa4c49e95	1575	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1576	{
phungductung	0:e87aa4c49e95	1577	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung	0:e87aa4c49e95	1578	}
phungductung	0:e87aa4c49e95	1579
phungductung	0:e87aa4c49e95	1580
phungductung	0:e87aa4c49e95	1581	/** \brief Set Pending Interrupt
phungductung	0:e87aa4c49e95	1582
phungductung	0:e87aa4c49e95	1583	The function sets the pending bit of an external interrupt.
phungductung	0:e87aa4c49e95	1584
phungductung	0:e87aa4c49e95	1585	\param [in] IRQn Interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1586	*/
phungductung	0:e87aa4c49e95	1587	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1588	{
phungductung	0:e87aa4c49e95	1589	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1590	}
phungductung	0:e87aa4c49e95	1591
phungductung	0:e87aa4c49e95	1592
phungductung	0:e87aa4c49e95	1593	/** \brief Clear Pending Interrupt
phungductung	0:e87aa4c49e95	1594
phungductung	0:e87aa4c49e95	1595	The function clears the pending bit of an external interrupt.
phungductung	0:e87aa4c49e95	1596
phungductung	0:e87aa4c49e95	1597	\param [in] IRQn External interrupt number. Value cannot be negative.
phungductung	0:e87aa4c49e95	1598	*/
phungductung	0:e87aa4c49e95	1599	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1600	{
phungductung	0:e87aa4c49e95	1601	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung	0:e87aa4c49e95	1602	}
phungductung	0:e87aa4c49e95	1603
phungductung	0:e87aa4c49e95	1604
phungductung	0:e87aa4c49e95	1605	/** \brief Get Active Interrupt
phungductung	0:e87aa4c49e95	1606
phungductung	0:e87aa4c49e95	1607	The function reads the active register in NVIC and returns the active bit.
phungductung	0:e87aa4c49e95	1608
phungductung	0:e87aa4c49e95	1609	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1610
phungductung	0:e87aa4c49e95	1611	\return 0 Interrupt status is not active.
phungductung	0:e87aa4c49e95	1612	\return 1 Interrupt status is active.
phungductung	0:e87aa4c49e95	1613	*/
phungductung	0:e87aa4c49e95	1614	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1615	{
phungductung	0:e87aa4c49e95	1616	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung	0:e87aa4c49e95	1617	}
phungductung	0:e87aa4c49e95	1618
phungductung	0:e87aa4c49e95	1619
phungductung	0:e87aa4c49e95	1620	/** \brief Set Interrupt Priority
phungductung	0:e87aa4c49e95	1621
phungductung	0:e87aa4c49e95	1622	The function sets the priority of an interrupt.
phungductung	0:e87aa4c49e95	1623
phungductung	0:e87aa4c49e95	1624	\note The priority cannot be set for every core interrupt.
phungductung	0:e87aa4c49e95	1625
phungductung	0:e87aa4c49e95	1626	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1627	\param [in] priority Priority to set.
phungductung	0:e87aa4c49e95	1628	*/
phungductung	0:e87aa4c49e95	1629	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
phungductung	0:e87aa4c49e95	1630	{
phungductung	0:e87aa4c49e95	1631	if((int32_t)IRQn < 0) {
phungductung	0:e87aa4c49e95	1632	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
phungductung	0:e87aa4c49e95	1633	}
phungductung	0:e87aa4c49e95	1634	else {
phungductung	0:e87aa4c49e95	1635	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
phungductung	0:e87aa4c49e95	1636	}
phungductung	0:e87aa4c49e95	1637	}
phungductung	0:e87aa4c49e95	1638
phungductung	0:e87aa4c49e95	1639
phungductung	0:e87aa4c49e95	1640	/** \brief Get Interrupt Priority
phungductung	0:e87aa4c49e95	1641
phungductung	0:e87aa4c49e95	1642	The function reads the priority of an interrupt. The interrupt
phungductung	0:e87aa4c49e95	1643	number can be positive to specify an external (device specific)
phungductung	0:e87aa4c49e95	1644	interrupt, or negative to specify an internal (core) interrupt.
phungductung	0:e87aa4c49e95	1645
phungductung	0:e87aa4c49e95	1646
phungductung	0:e87aa4c49e95	1647	\param [in] IRQn Interrupt number.
phungductung	0:e87aa4c49e95	1648	\return Interrupt Priority. Value is aligned automatically to the implemented
phungductung	0:e87aa4c49e95	1649	priority bits of the microcontroller.
phungductung	0:e87aa4c49e95	1650	*/
phungductung	0:e87aa4c49e95	1651	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
phungductung	0:e87aa4c49e95	1652	{
phungductung	0:e87aa4c49e95	1653
phungductung	0:e87aa4c49e95	1654	if((int32_t)IRQn < 0) {
phungductung	0:e87aa4c49e95	1655	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
phungductung	0:e87aa4c49e95	1656	}
phungductung	0:e87aa4c49e95	1657	else {
phungductung	0:e87aa4c49e95	1658	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
phungductung	0:e87aa4c49e95	1659	}
phungductung	0:e87aa4c49e95	1660	}
phungductung	0:e87aa4c49e95	1661
phungductung	0:e87aa4c49e95	1662
phungductung	0:e87aa4c49e95	1663	/** \brief Encode Priority
phungductung	0:e87aa4c49e95	1664
phungductung	0:e87aa4c49e95	1665	The function encodes the priority for an interrupt with the given priority group,
phungductung	0:e87aa4c49e95	1666	preemptive priority value, and subpriority value.
phungductung	0:e87aa4c49e95	1667	In case of a conflict between priority grouping and available
phungductung	0:e87aa4c49e95	1668	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
phungductung	0:e87aa4c49e95	1669
phungductung	0:e87aa4c49e95	1670	\param [in] PriorityGroup Used priority group.
phungductung	0:e87aa4c49e95	1671	\param [in] PreemptPriority Preemptive priority value (starting from 0).
phungductung	0:e87aa4c49e95	1672	\param [in] SubPriority Subpriority value (starting from 0).
phungductung	0:e87aa4c49e95	1673	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
phungductung	0:e87aa4c49e95	1674	*/
phungductung	0:e87aa4c49e95	1675	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
phungductung	0:e87aa4c49e95	1676	{
phungductung	0:e87aa4c49e95	1677	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung	0:e87aa4c49e95	1678	uint32_t PreemptPriorityBits;
phungductung	0:e87aa4c49e95	1679	uint32_t SubPriorityBits;
phungductung	0:e87aa4c49e95	1680
phungductung	0:e87aa4c49e95	1681	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
phungductung	0:e87aa4c49e95	1682	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
phungductung	0:e87aa4c49e95	1683
phungductung	0:e87aa4c49e95	1684	return (
phungductung	0:e87aa4c49e95	1685	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
phungductung	0:e87aa4c49e95	1686	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
phungductung	0:e87aa4c49e95	1687	);
phungductung	0:e87aa4c49e95	1688	}
phungductung	0:e87aa4c49e95	1689
phungductung	0:e87aa4c49e95	1690
phungductung	0:e87aa4c49e95	1691	/** \brief Decode Priority
phungductung	0:e87aa4c49e95	1692
phungductung	0:e87aa4c49e95	1693	The function decodes an interrupt priority value with a given priority group to
phungductung	0:e87aa4c49e95	1694	preemptive priority value and subpriority value.
phungductung	0:e87aa4c49e95	1695	In case of a conflict between priority grouping and available
phungductung	0:e87aa4c49e95	1696	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
phungductung	0:e87aa4c49e95	1697
phungductung	0:e87aa4c49e95	1698	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
phungductung	0:e87aa4c49e95	1699	\param [in] PriorityGroup Used priority group.
phungductung	0:e87aa4c49e95	1700	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
phungductung	0:e87aa4c49e95	1701	\param [out] pSubPriority Subpriority value (starting from 0).
phungductung	0:e87aa4c49e95	1702	*/
phungductung	0:e87aa4c49e95	1703	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
phungductung	0:e87aa4c49e95	1704	{
phungductung	0:e87aa4c49e95	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung	0:e87aa4c49e95	1706	uint32_t PreemptPriorityBits;
phungductung	0:e87aa4c49e95	1707	uint32_t SubPriorityBits;
phungductung	0:e87aa4c49e95	1708
phungductung	0:e87aa4c49e95	1709	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
phungductung	0:e87aa4c49e95	1710	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
phungductung	0:e87aa4c49e95	1711
phungductung	0:e87aa4c49e95	1712	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
phungductung	0:e87aa4c49e95	1713	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
phungductung	0:e87aa4c49e95	1714	}
phungductung	0:e87aa4c49e95	1715
phungductung	0:e87aa4c49e95	1716
phungductung	0:e87aa4c49e95	1717	/** \brief System Reset
phungductung	0:e87aa4c49e95	1718
phungductung	0:e87aa4c49e95	1719	The function initiates a system reset request to reset the MCU.
phungductung	0:e87aa4c49e95	1720	*/
phungductung	0:e87aa4c49e95	1721	__STATIC_INLINE void NVIC_SystemReset(void)
phungductung	0:e87aa4c49e95	1722	{
phungductung	0:e87aa4c49e95	1723	__DSB(); /* Ensure all outstanding memory accesses included
phungductung	0:e87aa4c49e95	1724	buffered write are completed before reset */
phungductung	0:e87aa4c49e95	1725	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
phungductung	0:e87aa4c49e95	1726	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
phungductung	0:e87aa4c49e95	1727	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
phungductung	0:e87aa4c49e95	1728	__DSB(); /* Ensure completion of memory access */
phungductung	0:e87aa4c49e95	1729	while(1) { __NOP(); } /* wait until reset */
phungductung	0:e87aa4c49e95	1730	}
phungductung	0:e87aa4c49e95	1731
phungductung	0:e87aa4c49e95	1732	/@} end of CMSIS_Core_NVICFunctions /
phungductung	0:e87aa4c49e95	1733
phungductung	0:e87aa4c49e95	1734
phungductung	0:e87aa4c49e95	1735
phungductung	0:e87aa4c49e95	1736	/* ################################## SysTick function ############################################ */
phungductung	0:e87aa4c49e95	1737	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	1738	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
phungductung	0:e87aa4c49e95	1739	\brief Functions that configure the System.
phungductung	0:e87aa4c49e95	1740	@{
phungductung	0:e87aa4c49e95	1741	*/
phungductung	0:e87aa4c49e95	1742
phungductung	0:e87aa4c49e95	1743	#if (__Vendor_SysTickConfig == 0)
phungductung	0:e87aa4c49e95	1744
phungductung	0:e87aa4c49e95	1745	/** \brief System Tick Configuration
phungductung	0:e87aa4c49e95	1746
phungductung	0:e87aa4c49e95	1747	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
phungductung	0:e87aa4c49e95	1748	Counter is in free running mode to generate periodic interrupts.
phungductung	0:e87aa4c49e95	1749
phungductung	0:e87aa4c49e95	1750	\param [in] ticks Number of ticks between two interrupts.
phungductung	0:e87aa4c49e95	1751
phungductung	0:e87aa4c49e95	1752	\return 0 Function succeeded.
phungductung	0:e87aa4c49e95	1753	\return 1 Function failed.
phungductung	0:e87aa4c49e95	1754
phungductung	0:e87aa4c49e95	1755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
phungductung	0:e87aa4c49e95	1756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
phungductung	0:e87aa4c49e95	1757	must contain a vendor-specific implementation of this function.
phungductung	0:e87aa4c49e95	1758
phungductung	0:e87aa4c49e95	1759	*/
phungductung	0:e87aa4c49e95	1760	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
phungductung	0:e87aa4c49e95	1761	{
phungductung	0:e87aa4c49e95	1762	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
phungductung	0:e87aa4c49e95	1763
phungductung	0:e87aa4c49e95	1764	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
phungductung	0:e87aa4c49e95	1765	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
phungductung	0:e87aa4c49e95	1766	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
phungductung	0:e87aa4c49e95	1767	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
phungductung	0:e87aa4c49e95	1768	SysTick_CTRL_TICKINT_Msk \|
phungductung	0:e87aa4c49e95	1769	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
phungductung	0:e87aa4c49e95	1770	return (0UL); /* Function successful */
phungductung	0:e87aa4c49e95	1771	}
phungductung	0:e87aa4c49e95	1772
phungductung	0:e87aa4c49e95	1773	#endif
phungductung	0:e87aa4c49e95	1774
phungductung	0:e87aa4c49e95	1775	/@} end of CMSIS_Core_SysTickFunctions /
phungductung	0:e87aa4c49e95	1776
phungductung	0:e87aa4c49e95	1777
phungductung	0:e87aa4c49e95	1778
phungductung	0:e87aa4c49e95	1779	/* ##################################### Debug In/Output function ########################################### */
phungductung	0:e87aa4c49e95	1780	/** \ingroup CMSIS_Core_FunctionInterface
phungductung	0:e87aa4c49e95	1781	\defgroup CMSIS_core_DebugFunctions ITM Functions
phungductung	0:e87aa4c49e95	1782	\brief Functions that access the ITM debug interface.
phungductung	0:e87aa4c49e95	1783	@{
phungductung	0:e87aa4c49e95	1784	*/
phungductung	0:e87aa4c49e95	1785
phungductung	0:e87aa4c49e95	1786	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
phungductung	0:e87aa4c49e95	1787	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
phungductung	0:e87aa4c49e95	1788
phungductung	0:e87aa4c49e95	1789
phungductung	0:e87aa4c49e95	1790	/** \brief ITM Send Character
phungductung	0:e87aa4c49e95	1791
phungductung	0:e87aa4c49e95	1792	The function transmits a character via the ITM channel 0, and
phungductung	0:e87aa4c49e95	1793	\li Just returns when no debugger is connected that has booked the output.
phungductung	0:e87aa4c49e95	1794	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
phungductung	0:e87aa4c49e95	1795
phungductung	0:e87aa4c49e95	1796	\param [in] ch Character to transmit.
phungductung	0:e87aa4c49e95	1797
phungductung	0:e87aa4c49e95	1798	\returns Character to transmit.
phungductung	0:e87aa4c49e95	1799	*/
phungductung	0:e87aa4c49e95	1800	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
phungductung	0:e87aa4c49e95	1801	{
phungductung	0:e87aa4c49e95	1802	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
phungductung	0:e87aa4c49e95	1803	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
phungductung	0:e87aa4c49e95	1804	{
phungductung	0:e87aa4c49e95	1805	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
phungductung	0:e87aa4c49e95	1806	ITM->PORT[0].u8 = (uint8_t)ch;
phungductung	0:e87aa4c49e95	1807	}
phungductung	0:e87aa4c49e95	1808	return (ch);
phungductung	0:e87aa4c49e95	1809	}
phungductung	0:e87aa4c49e95	1810
phungductung	0:e87aa4c49e95	1811
phungductung	0:e87aa4c49e95	1812	/** \brief ITM Receive Character
phungductung	0:e87aa4c49e95	1813
phungductung	0:e87aa4c49e95	1814	The function inputs a character via the external variable \ref ITM_RxBuffer.
phungductung	0:e87aa4c49e95	1815
phungductung	0:e87aa4c49e95	1816	\return Received character.
phungductung	0:e87aa4c49e95	1817	\return -1 No character pending.
phungductung	0:e87aa4c49e95	1818	*/
phungductung	0:e87aa4c49e95	1819	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
phungductung	0:e87aa4c49e95	1820	int32_t ch = -1; /* no character available */
phungductung	0:e87aa4c49e95	1821
phungductung	0:e87aa4c49e95	1822	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
phungductung	0:e87aa4c49e95	1823	ch = ITM_RxBuffer;
phungductung	0:e87aa4c49e95	1824	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
phungductung	0:e87aa4c49e95	1825	}
phungductung	0:e87aa4c49e95	1826
phungductung	0:e87aa4c49e95	1827	return (ch);
phungductung	0:e87aa4c49e95	1828	}
phungductung	0:e87aa4c49e95	1829
phungductung	0:e87aa4c49e95	1830
phungductung	0:e87aa4c49e95	1831	/** \brief ITM Check Character
phungductung	0:e87aa4c49e95	1832
phungductung	0:e87aa4c49e95	1833	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
phungductung	0:e87aa4c49e95	1834
phungductung	0:e87aa4c49e95	1835	\return 0 No character available.
phungductung	0:e87aa4c49e95	1836	\return 1 Character available.
phungductung	0:e87aa4c49e95	1837	*/
phungductung	0:e87aa4c49e95	1838	__STATIC_INLINE int32_t ITM_CheckChar (void) {
phungductung	0:e87aa4c49e95	1839
phungductung	0:e87aa4c49e95	1840	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
phungductung	0:e87aa4c49e95	1841	return (0); /* no character available */
phungductung	0:e87aa4c49e95	1842	} else {
phungductung	0:e87aa4c49e95	1843	return (1); /* character available */
phungductung	0:e87aa4c49e95	1844	}
phungductung	0:e87aa4c49e95	1845	}
phungductung	0:e87aa4c49e95	1846
phungductung	0:e87aa4c49e95	1847	/@} end of CMSIS_core_DebugFunctions /
phungductung	0:e87aa4c49e95	1848
phungductung	0:e87aa4c49e95	1849
phungductung	0:e87aa4c49e95	1850
phungductung	0:e87aa4c49e95	1851
phungductung	0:e87aa4c49e95	1852	#ifdef __cplusplus
phungductung	0:e87aa4c49e95	1853	}
phungductung	0:e87aa4c49e95	1854	#endif
phungductung	0:e87aa4c49e95	1855
phungductung	0:e87aa4c49e95	1856	#endif /* __CORE_CM4_H_DEPENDANT */
phungductung	0:e87aa4c49e95	1857
phungductung	0:e87aa4c49e95	1858	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	04 Jun 2019
Imports:	8
Forks:	0
Commits:	1
Dependents:	1
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targets/cmsis/core_cm4.h@0:e87aa4c49e95, 2019-06-04 (annotated)

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