PHung Tung / SRC_STM32F7

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targets/cmsis/core_caFunc.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

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phungductung 0:e87aa4c49e95 1 /**************************************************************************//**
phungductung 0:e87aa4c49e95 2 * @file core_caFunc.h
phungductung 0:e87aa4c49e95 3 * @brief CMSIS Cortex-A Core Function Access Header File
phungductung 0:e87aa4c49e95 4 * @version V3.10
phungductung 0:e87aa4c49e95 5 * @date 30 Oct 2013
phungductung 0:e87aa4c49e95 6 *
phungductung 0:e87aa4c49e95 7 * @note
phungductung 0:e87aa4c49e95 8 *
phungductung 0:e87aa4c49e95 9 ******************************************************************************/
phungductung 0:e87aa4c49e95 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
phungductung 0:e87aa4c49e95 11
phungductung 0:e87aa4c49e95 12 All rights reserved.
phungductung 0:e87aa4c49e95 13 Redistribution and use in source and binary forms, with or without
phungductung 0:e87aa4c49e95 14 modification, are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 15 - Redistributions of source code must retain the above copyright
phungductung 0:e87aa4c49e95 16 notice, this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 17 - Redistributions in binary form must reproduce the above copyright
phungductung 0:e87aa4c49e95 18 notice, this list of conditions and the following disclaimer in the
phungductung 0:e87aa4c49e95 19 documentation and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 20 - Neither the name of ARM nor the names of its contributors may be used
phungductung 0:e87aa4c49e95 21 to endorse or promote products derived from this software without
phungductung 0:e87aa4c49e95 22 specific prior written permission.
phungductung 0:e87aa4c49e95 23 *
phungductung 0:e87aa4c49e95 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
phungductung 0:e87aa4c49e95 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
phungductung 0:e87aa4c49e95 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
phungductung 0:e87aa4c49e95 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
phungductung 0:e87aa4c49e95 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
phungductung 0:e87aa4c49e95 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
phungductung 0:e87aa4c49e95 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
phungductung 0:e87aa4c49e95 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
phungductung 0:e87aa4c49e95 34 POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 35 ---------------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 36
phungductung 0:e87aa4c49e95 37
phungductung 0:e87aa4c49e95 38 #ifndef __CORE_CAFUNC_H__
phungductung 0:e87aa4c49e95 39 #define __CORE_CAFUNC_H__
phungductung 0:e87aa4c49e95 40
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 /* ########################### Core Function Access ########################### */
phungductung 0:e87aa4c49e95 43 /** \ingroup CMSIS_Core_FunctionInterface
phungductung 0:e87aa4c49e95 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
phungductung 0:e87aa4c49e95 45 @{
phungductung 0:e87aa4c49e95 46 */
phungductung 0:e87aa4c49e95 47
phungductung 0:e87aa4c49e95 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
phungductung 0:e87aa4c49e95 49 /* ARM armcc specific functions */
phungductung 0:e87aa4c49e95 50
phungductung 0:e87aa4c49e95 51 #if (__ARMCC_VERSION < 400677)
phungductung 0:e87aa4c49e95 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
phungductung 0:e87aa4c49e95 53 #endif
phungductung 0:e87aa4c49e95 54
phungductung 0:e87aa4c49e95 55 #define MODE_USR 0x10
phungductung 0:e87aa4c49e95 56 #define MODE_FIQ 0x11
phungductung 0:e87aa4c49e95 57 #define MODE_IRQ 0x12
phungductung 0:e87aa4c49e95 58 #define MODE_SVC 0x13
phungductung 0:e87aa4c49e95 59 #define MODE_MON 0x16
phungductung 0:e87aa4c49e95 60 #define MODE_ABT 0x17
phungductung 0:e87aa4c49e95 61 #define MODE_HYP 0x1A
phungductung 0:e87aa4c49e95 62 #define MODE_UND 0x1B
phungductung 0:e87aa4c49e95 63 #define MODE_SYS 0x1F
phungductung 0:e87aa4c49e95 64
phungductung 0:e87aa4c49e95 65 /** \brief Get APSR Register
phungductung 0:e87aa4c49e95 66
phungductung 0:e87aa4c49e95 67 This function returns the content of the APSR Register.
phungductung 0:e87aa4c49e95 68
phungductung 0:e87aa4c49e95 69 \return APSR Register value
phungductung 0:e87aa4c49e95 70 */
phungductung 0:e87aa4c49e95 71 __STATIC_INLINE uint32_t __get_APSR(void)
phungductung 0:e87aa4c49e95 72 {
phungductung 0:e87aa4c49e95 73 register uint32_t __regAPSR __ASM("apsr");
phungductung 0:e87aa4c49e95 74 return(__regAPSR);
phungductung 0:e87aa4c49e95 75 }
phungductung 0:e87aa4c49e95 76
phungductung 0:e87aa4c49e95 77
phungductung 0:e87aa4c49e95 78 /** \brief Get CPSR Register
phungductung 0:e87aa4c49e95 79
phungductung 0:e87aa4c49e95 80 This function returns the content of the CPSR Register.
phungductung 0:e87aa4c49e95 81
phungductung 0:e87aa4c49e95 82 \return CPSR Register value
phungductung 0:e87aa4c49e95 83 */
phungductung 0:e87aa4c49e95 84 __STATIC_INLINE uint32_t __get_CPSR(void)
phungductung 0:e87aa4c49e95 85 {
phungductung 0:e87aa4c49e95 86 register uint32_t __regCPSR __ASM("cpsr");
phungductung 0:e87aa4c49e95 87 return(__regCPSR);
phungductung 0:e87aa4c49e95 88 }
phungductung 0:e87aa4c49e95 89
phungductung 0:e87aa4c49e95 90 /** \brief Set Stack Pointer
phungductung 0:e87aa4c49e95 91
phungductung 0:e87aa4c49e95 92 This function assigns the given value to the current stack pointer.
phungductung 0:e87aa4c49e95 93
phungductung 0:e87aa4c49e95 94 \param [in] topOfStack Stack Pointer value to set
phungductung 0:e87aa4c49e95 95 */
phungductung 0:e87aa4c49e95 96 register uint32_t __regSP __ASM("sp");
phungductung 0:e87aa4c49e95 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
phungductung 0:e87aa4c49e95 98 {
phungductung 0:e87aa4c49e95 99 __regSP = topOfStack;
phungductung 0:e87aa4c49e95 100 }
phungductung 0:e87aa4c49e95 101
phungductung 0:e87aa4c49e95 102
phungductung 0:e87aa4c49e95 103 /** \brief Get link register
phungductung 0:e87aa4c49e95 104
phungductung 0:e87aa4c49e95 105 This function returns the value of the link register
phungductung 0:e87aa4c49e95 106
phungductung 0:e87aa4c49e95 107 \return Value of link register
phungductung 0:e87aa4c49e95 108 */
phungductung 0:e87aa4c49e95 109 register uint32_t __reglr __ASM("lr");
phungductung 0:e87aa4c49e95 110 __STATIC_INLINE uint32_t __get_LR(void)
phungductung 0:e87aa4c49e95 111 {
phungductung 0:e87aa4c49e95 112 return(__reglr);
phungductung 0:e87aa4c49e95 113 }
phungductung 0:e87aa4c49e95 114
phungductung 0:e87aa4c49e95 115 /** \brief Set link register
phungductung 0:e87aa4c49e95 116
phungductung 0:e87aa4c49e95 117 This function sets the value of the link register
phungductung 0:e87aa4c49e95 118
phungductung 0:e87aa4c49e95 119 \param [in] lr LR value to set
phungductung 0:e87aa4c49e95 120 */
phungductung 0:e87aa4c49e95 121 __STATIC_INLINE void __set_LR(uint32_t lr)
phungductung 0:e87aa4c49e95 122 {
phungductung 0:e87aa4c49e95 123 __reglr = lr;
phungductung 0:e87aa4c49e95 124 }
phungductung 0:e87aa4c49e95 125
phungductung 0:e87aa4c49e95 126 /** \brief Set Process Stack Pointer
phungductung 0:e87aa4c49e95 127
phungductung 0:e87aa4c49e95 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
phungductung 0:e87aa4c49e95 129
phungductung 0:e87aa4c49e95 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
phungductung 0:e87aa4c49e95 131 */
phungductung 0:e87aa4c49e95 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
phungductung 0:e87aa4c49e95 133 {
phungductung 0:e87aa4c49e95 134 ARM
phungductung 0:e87aa4c49e95 135 PRESERVE8
phungductung 0:e87aa4c49e95 136
phungductung 0:e87aa4c49e95 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
phungductung 0:e87aa4c49e95 138 MRS R1, CPSR
phungductung 0:e87aa4c49e95 139 CPS #MODE_SYS ;no effect in USR mode
phungductung 0:e87aa4c49e95 140 MOV SP, R0
phungductung 0:e87aa4c49e95 141 MSR CPSR_c, R1 ;no effect in USR mode
phungductung 0:e87aa4c49e95 142 ISB
phungductung 0:e87aa4c49e95 143 BX LR
phungductung 0:e87aa4c49e95 144
phungductung 0:e87aa4c49e95 145 }
phungductung 0:e87aa4c49e95 146
phungductung 0:e87aa4c49e95 147 /** \brief Set User Mode
phungductung 0:e87aa4c49e95 148
phungductung 0:e87aa4c49e95 149 This function changes the processor state to User Mode
phungductung 0:e87aa4c49e95 150 */
phungductung 0:e87aa4c49e95 151 __STATIC_ASM void __set_CPS_USR(void)
phungductung 0:e87aa4c49e95 152 {
phungductung 0:e87aa4c49e95 153 ARM
phungductung 0:e87aa4c49e95 154
phungductung 0:e87aa4c49e95 155 CPS #MODE_USR
phungductung 0:e87aa4c49e95 156 BX LR
phungductung 0:e87aa4c49e95 157 }
phungductung 0:e87aa4c49e95 158
phungductung 0:e87aa4c49e95 159
phungductung 0:e87aa4c49e95 160 /** \brief Enable FIQ
phungductung 0:e87aa4c49e95 161
phungductung 0:e87aa4c49e95 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
phungductung 0:e87aa4c49e95 163 Can only be executed in Privileged modes.
phungductung 0:e87aa4c49e95 164 */
phungductung 0:e87aa4c49e95 165 #define __enable_fault_irq __enable_fiq
phungductung 0:e87aa4c49e95 166
phungductung 0:e87aa4c49e95 167
phungductung 0:e87aa4c49e95 168 /** \brief Disable FIQ
phungductung 0:e87aa4c49e95 169
phungductung 0:e87aa4c49e95 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
phungductung 0:e87aa4c49e95 171 Can only be executed in Privileged modes.
phungductung 0:e87aa4c49e95 172 */
phungductung 0:e87aa4c49e95 173 #define __disable_fault_irq __disable_fiq
phungductung 0:e87aa4c49e95 174
phungductung 0:e87aa4c49e95 175
phungductung 0:e87aa4c49e95 176 /** \brief Get FPSCR
phungductung 0:e87aa4c49e95 177
phungductung 0:e87aa4c49e95 178 This function returns the current value of the Floating Point Status/Control register.
phungductung 0:e87aa4c49e95 179
phungductung 0:e87aa4c49e95 180 \return Floating Point Status/Control register value
phungductung 0:e87aa4c49e95 181 */
phungductung 0:e87aa4c49e95 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
phungductung 0:e87aa4c49e95 183 {
phungductung 0:e87aa4c49e95 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
phungductung 0:e87aa4c49e95 185 register uint32_t __regfpscr __ASM("fpscr");
phungductung 0:e87aa4c49e95 186 return(__regfpscr);
phungductung 0:e87aa4c49e95 187 #else
phungductung 0:e87aa4c49e95 188 return(0);
phungductung 0:e87aa4c49e95 189 #endif
phungductung 0:e87aa4c49e95 190 }
phungductung 0:e87aa4c49e95 191
phungductung 0:e87aa4c49e95 192
phungductung 0:e87aa4c49e95 193 /** \brief Set FPSCR
phungductung 0:e87aa4c49e95 194
phungductung 0:e87aa4c49e95 195 This function assigns the given value to the Floating Point Status/Control register.
phungductung 0:e87aa4c49e95 196
phungductung 0:e87aa4c49e95 197 \param [in] fpscr Floating Point Status/Control value to set
phungductung 0:e87aa4c49e95 198 */
phungductung 0:e87aa4c49e95 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
phungductung 0:e87aa4c49e95 200 {
phungductung 0:e87aa4c49e95 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
phungductung 0:e87aa4c49e95 202 register uint32_t __regfpscr __ASM("fpscr");
phungductung 0:e87aa4c49e95 203 __regfpscr = (fpscr);
phungductung 0:e87aa4c49e95 204 #endif
phungductung 0:e87aa4c49e95 205 }
phungductung 0:e87aa4c49e95 206
phungductung 0:e87aa4c49e95 207 /** \brief Get FPEXC
phungductung 0:e87aa4c49e95 208
phungductung 0:e87aa4c49e95 209 This function returns the current value of the Floating Point Exception Control register.
phungductung 0:e87aa4c49e95 210
phungductung 0:e87aa4c49e95 211 \return Floating Point Exception Control register value
phungductung 0:e87aa4c49e95 212 */
phungductung 0:e87aa4c49e95 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
phungductung 0:e87aa4c49e95 214 {
phungductung 0:e87aa4c49e95 215 #if (__FPU_PRESENT == 1)
phungductung 0:e87aa4c49e95 216 register uint32_t __regfpexc __ASM("fpexc");
phungductung 0:e87aa4c49e95 217 return(__regfpexc);
phungductung 0:e87aa4c49e95 218 #else
phungductung 0:e87aa4c49e95 219 return(0);
phungductung 0:e87aa4c49e95 220 #endif
phungductung 0:e87aa4c49e95 221 }
phungductung 0:e87aa4c49e95 222
phungductung 0:e87aa4c49e95 223
phungductung 0:e87aa4c49e95 224 /** \brief Set FPEXC
phungductung 0:e87aa4c49e95 225
phungductung 0:e87aa4c49e95 226 This function assigns the given value to the Floating Point Exception Control register.
phungductung 0:e87aa4c49e95 227
phungductung 0:e87aa4c49e95 228 \param [in] fpscr Floating Point Exception Control value to set
phungductung 0:e87aa4c49e95 229 */
phungductung 0:e87aa4c49e95 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
phungductung 0:e87aa4c49e95 231 {
phungductung 0:e87aa4c49e95 232 #if (__FPU_PRESENT == 1)
phungductung 0:e87aa4c49e95 233 register uint32_t __regfpexc __ASM("fpexc");
phungductung 0:e87aa4c49e95 234 __regfpexc = (fpexc);
phungductung 0:e87aa4c49e95 235 #endif
phungductung 0:e87aa4c49e95 236 }
phungductung 0:e87aa4c49e95 237
phungductung 0:e87aa4c49e95 238 /** \brief Get CPACR
phungductung 0:e87aa4c49e95 239
phungductung 0:e87aa4c49e95 240 This function returns the current value of the Coprocessor Access Control register.
phungductung 0:e87aa4c49e95 241
phungductung 0:e87aa4c49e95 242 \return Coprocessor Access Control register value
phungductung 0:e87aa4c49e95 243 */
phungductung 0:e87aa4c49e95 244 __STATIC_INLINE uint32_t __get_CPACR(void)
phungductung 0:e87aa4c49e95 245 {
phungductung 0:e87aa4c49e95 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
phungductung 0:e87aa4c49e95 247 return __regCPACR;
phungductung 0:e87aa4c49e95 248 }
phungductung 0:e87aa4c49e95 249
phungductung 0:e87aa4c49e95 250 /** \brief Set CPACR
phungductung 0:e87aa4c49e95 251
phungductung 0:e87aa4c49e95 252 This function assigns the given value to the Coprocessor Access Control register.
phungductung 0:e87aa4c49e95 253
phungductung 0:e87aa4c49e95 254 \param [in] cpacr Coprocessor Acccess Control value to set
phungductung 0:e87aa4c49e95 255 */
phungductung 0:e87aa4c49e95 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
phungductung 0:e87aa4c49e95 257 {
phungductung 0:e87aa4c49e95 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
phungductung 0:e87aa4c49e95 259 __regCPACR = cpacr;
phungductung 0:e87aa4c49e95 260 __ISB();
phungductung 0:e87aa4c49e95 261 }
phungductung 0:e87aa4c49e95 262
phungductung 0:e87aa4c49e95 263 /** \brief Get CBAR
phungductung 0:e87aa4c49e95 264
phungductung 0:e87aa4c49e95 265 This function returns the value of the Configuration Base Address register.
phungductung 0:e87aa4c49e95 266
phungductung 0:e87aa4c49e95 267 \return Configuration Base Address register value
phungductung 0:e87aa4c49e95 268 */
phungductung 0:e87aa4c49e95 269 __STATIC_INLINE uint32_t __get_CBAR() {
phungductung 0:e87aa4c49e95 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
phungductung 0:e87aa4c49e95 271 return(__regCBAR);
phungductung 0:e87aa4c49e95 272 }
phungductung 0:e87aa4c49e95 273
phungductung 0:e87aa4c49e95 274 /** \brief Get TTBR0
phungductung 0:e87aa4c49e95 275
phungductung 0:e87aa4c49e95 276 This function returns the value of the Translation Table Base Register 0.
phungductung 0:e87aa4c49e95 277
phungductung 0:e87aa4c49e95 278 \return Translation Table Base Register 0 value
phungductung 0:e87aa4c49e95 279 */
phungductung 0:e87aa4c49e95 280 __STATIC_INLINE uint32_t __get_TTBR0() {
phungductung 0:e87aa4c49e95 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
phungductung 0:e87aa4c49e95 282 return(__regTTBR0);
phungductung 0:e87aa4c49e95 283 }
phungductung 0:e87aa4c49e95 284
phungductung 0:e87aa4c49e95 285 /** \brief Set TTBR0
phungductung 0:e87aa4c49e95 286
phungductung 0:e87aa4c49e95 287 This function assigns the given value to the Translation Table Base Register 0.
phungductung 0:e87aa4c49e95 288
phungductung 0:e87aa4c49e95 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
phungductung 0:e87aa4c49e95 290 */
phungductung 0:e87aa4c49e95 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
phungductung 0:e87aa4c49e95 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
phungductung 0:e87aa4c49e95 293 __regTTBR0 = ttbr0;
phungductung 0:e87aa4c49e95 294 __ISB();
phungductung 0:e87aa4c49e95 295 }
phungductung 0:e87aa4c49e95 296
phungductung 0:e87aa4c49e95 297 /** \brief Get DACR
phungductung 0:e87aa4c49e95 298
phungductung 0:e87aa4c49e95 299 This function returns the value of the Domain Access Control Register.
phungductung 0:e87aa4c49e95 300
phungductung 0:e87aa4c49e95 301 \return Domain Access Control Register value
phungductung 0:e87aa4c49e95 302 */
phungductung 0:e87aa4c49e95 303 __STATIC_INLINE uint32_t __get_DACR() {
phungductung 0:e87aa4c49e95 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
phungductung 0:e87aa4c49e95 305 return(__regDACR);
phungductung 0:e87aa4c49e95 306 }
phungductung 0:e87aa4c49e95 307
phungductung 0:e87aa4c49e95 308 /** \brief Set DACR
phungductung 0:e87aa4c49e95 309
phungductung 0:e87aa4c49e95 310 This function assigns the given value to the Domain Access Control Register.
phungductung 0:e87aa4c49e95 311
phungductung 0:e87aa4c49e95 312 \param [in] dacr Domain Access Control Register value to set
phungductung 0:e87aa4c49e95 313 */
phungductung 0:e87aa4c49e95 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
phungductung 0:e87aa4c49e95 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
phungductung 0:e87aa4c49e95 316 __regDACR = dacr;
phungductung 0:e87aa4c49e95 317 __ISB();
phungductung 0:e87aa4c49e95 318 }
phungductung 0:e87aa4c49e95 319
phungductung 0:e87aa4c49e95 320 /******************************** Cache and BTAC enable ****************************************************/
phungductung 0:e87aa4c49e95 321
phungductung 0:e87aa4c49e95 322 /** \brief Set SCTLR
phungductung 0:e87aa4c49e95 323
phungductung 0:e87aa4c49e95 324 This function assigns the given value to the System Control Register.
phungductung 0:e87aa4c49e95 325
phungductung 0:e87aa4c49e95 326 \param [in] sctlr System Control Register value to set
phungductung 0:e87aa4c49e95 327 */
phungductung 0:e87aa4c49e95 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
phungductung 0:e87aa4c49e95 329 {
phungductung 0:e87aa4c49e95 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
phungductung 0:e87aa4c49e95 331 __regSCTLR = sctlr;
phungductung 0:e87aa4c49e95 332 }
phungductung 0:e87aa4c49e95 333
phungductung 0:e87aa4c49e95 334 /** \brief Get SCTLR
phungductung 0:e87aa4c49e95 335
phungductung 0:e87aa4c49e95 336 This function returns the value of the System Control Register.
phungductung 0:e87aa4c49e95 337
phungductung 0:e87aa4c49e95 338 \return System Control Register value
phungductung 0:e87aa4c49e95 339 */
phungductung 0:e87aa4c49e95 340 __STATIC_INLINE uint32_t __get_SCTLR() {
phungductung 0:e87aa4c49e95 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
phungductung 0:e87aa4c49e95 342 return(__regSCTLR);
phungductung 0:e87aa4c49e95 343 }
phungductung 0:e87aa4c49e95 344
phungductung 0:e87aa4c49e95 345 /** \brief Enable Caches
phungductung 0:e87aa4c49e95 346
phungductung 0:e87aa4c49e95 347 Enable Caches
phungductung 0:e87aa4c49e95 348 */
phungductung 0:e87aa4c49e95 349 __STATIC_INLINE void __enable_caches(void) {
phungductung 0:e87aa4c49e95 350 // Set I bit 12 to enable I Cache
phungductung 0:e87aa4c49e95 351 // Set C bit 2 to enable D Cache
phungductung 0:e87aa4c49e95 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
phungductung 0:e87aa4c49e95 353 }
phungductung 0:e87aa4c49e95 354
phungductung 0:e87aa4c49e95 355 /** \brief Disable Caches
phungductung 0:e87aa4c49e95 356
phungductung 0:e87aa4c49e95 357 Disable Caches
phungductung 0:e87aa4c49e95 358 */
phungductung 0:e87aa4c49e95 359 __STATIC_INLINE void __disable_caches(void) {
phungductung 0:e87aa4c49e95 360 // Clear I bit 12 to disable I Cache
phungductung 0:e87aa4c49e95 361 // Clear C bit 2 to disable D Cache
phungductung 0:e87aa4c49e95 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
phungductung 0:e87aa4c49e95 363 __ISB();
phungductung 0:e87aa4c49e95 364 }
phungductung 0:e87aa4c49e95 365
phungductung 0:e87aa4c49e95 366 /** \brief Enable BTAC
phungductung 0:e87aa4c49e95 367
phungductung 0:e87aa4c49e95 368 Enable BTAC
phungductung 0:e87aa4c49e95 369 */
phungductung 0:e87aa4c49e95 370 __STATIC_INLINE void __enable_btac(void) {
phungductung 0:e87aa4c49e95 371 // Set Z bit 11 to enable branch prediction
phungductung 0:e87aa4c49e95 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
phungductung 0:e87aa4c49e95 373 __ISB();
phungductung 0:e87aa4c49e95 374 }
phungductung 0:e87aa4c49e95 375
phungductung 0:e87aa4c49e95 376 /** \brief Disable BTAC
phungductung 0:e87aa4c49e95 377
phungductung 0:e87aa4c49e95 378 Disable BTAC
phungductung 0:e87aa4c49e95 379 */
phungductung 0:e87aa4c49e95 380 __STATIC_INLINE void __disable_btac(void) {
phungductung 0:e87aa4c49e95 381 // Clear Z bit 11 to disable branch prediction
phungductung 0:e87aa4c49e95 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
phungductung 0:e87aa4c49e95 383 }
phungductung 0:e87aa4c49e95 384
phungductung 0:e87aa4c49e95 385
phungductung 0:e87aa4c49e95 386 /** \brief Enable MMU
phungductung 0:e87aa4c49e95 387
phungductung 0:e87aa4c49e95 388 Enable MMU
phungductung 0:e87aa4c49e95 389 */
phungductung 0:e87aa4c49e95 390 __STATIC_INLINE void __enable_mmu(void) {
phungductung 0:e87aa4c49e95 391 // Set M bit 0 to enable the MMU
phungductung 0:e87aa4c49e95 392 // Set AFE bit to enable simplified access permissions model
phungductung 0:e87aa4c49e95 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
phungductung 0:e87aa4c49e95 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
phungductung 0:e87aa4c49e95 395 __ISB();
phungductung 0:e87aa4c49e95 396 }
phungductung 0:e87aa4c49e95 397
phungductung 0:e87aa4c49e95 398 /** \brief Disable MMU
phungductung 0:e87aa4c49e95 399
phungductung 0:e87aa4c49e95 400 Disable MMU
phungductung 0:e87aa4c49e95 401 */
phungductung 0:e87aa4c49e95 402 __STATIC_INLINE void __disable_mmu(void) {
phungductung 0:e87aa4c49e95 403 // Clear M bit 0 to disable the MMU
phungductung 0:e87aa4c49e95 404 __set_SCTLR( __get_SCTLR() & ~1);
phungductung 0:e87aa4c49e95 405 __ISB();
phungductung 0:e87aa4c49e95 406 }
phungductung 0:e87aa4c49e95 407
phungductung 0:e87aa4c49e95 408 /******************************** TLB maintenance operations ************************************************/
phungductung 0:e87aa4c49e95 409 /** \brief Invalidate the whole tlb
phungductung 0:e87aa4c49e95 410
phungductung 0:e87aa4c49e95 411 TLBIALL. Invalidate the whole tlb
phungductung 0:e87aa4c49e95 412 */
phungductung 0:e87aa4c49e95 413
phungductung 0:e87aa4c49e95 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
phungductung 0:e87aa4c49e95 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
phungductung 0:e87aa4c49e95 416 __TLBIALL = 0;
phungductung 0:e87aa4c49e95 417 __DSB();
phungductung 0:e87aa4c49e95 418 __ISB();
phungductung 0:e87aa4c49e95 419 }
phungductung 0:e87aa4c49e95 420
phungductung 0:e87aa4c49e95 421 /******************************** BTB maintenance operations ************************************************/
phungductung 0:e87aa4c49e95 422 /** \brief Invalidate entire branch predictor array
phungductung 0:e87aa4c49e95 423
phungductung 0:e87aa4c49e95 424 BPIALL. Branch Predictor Invalidate All.
phungductung 0:e87aa4c49e95 425 */
phungductung 0:e87aa4c49e95 426
phungductung 0:e87aa4c49e95 427 __STATIC_INLINE void __v7_inv_btac(void) {
phungductung 0:e87aa4c49e95 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
phungductung 0:e87aa4c49e95 429 __BPIALL = 0;
phungductung 0:e87aa4c49e95 430 __DSB(); //ensure completion of the invalidation
phungductung 0:e87aa4c49e95 431 __ISB(); //ensure instruction fetch path sees new state
phungductung 0:e87aa4c49e95 432 }
phungductung 0:e87aa4c49e95 433
phungductung 0:e87aa4c49e95 434
phungductung 0:e87aa4c49e95 435 /******************************** L1 cache operations ******************************************************/
phungductung 0:e87aa4c49e95 436
phungductung 0:e87aa4c49e95 437 /** \brief Invalidate the whole I$
phungductung 0:e87aa4c49e95 438
phungductung 0:e87aa4c49e95 439 ICIALLU. Instruction Cache Invalidate All to PoU
phungductung 0:e87aa4c49e95 440 */
phungductung 0:e87aa4c49e95 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
phungductung 0:e87aa4c49e95 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
phungductung 0:e87aa4c49e95 443 __ICIALLU = 0;
phungductung 0:e87aa4c49e95 444 __DSB(); //ensure completion of the invalidation
phungductung 0:e87aa4c49e95 445 __ISB(); //ensure instruction fetch path sees new I cache state
phungductung 0:e87aa4c49e95 446 }
phungductung 0:e87aa4c49e95 447
phungductung 0:e87aa4c49e95 448 /** \brief Clean D$ by MVA
phungductung 0:e87aa4c49e95 449
phungductung 0:e87aa4c49e95 450 DCCMVAC. Data cache clean by MVA to PoC
phungductung 0:e87aa4c49e95 451 */
phungductung 0:e87aa4c49e95 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
phungductung 0:e87aa4c49e95 454 __DCCMVAC = (uint32_t)va;
phungductung 0:e87aa4c49e95 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
phungductung 0:e87aa4c49e95 456 }
phungductung 0:e87aa4c49e95 457
phungductung 0:e87aa4c49e95 458 /** \brief Invalidate D$ by MVA
phungductung 0:e87aa4c49e95 459
phungductung 0:e87aa4c49e95 460 DCIMVAC. Data cache invalidate by MVA to PoC
phungductung 0:e87aa4c49e95 461 */
phungductung 0:e87aa4c49e95 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
phungductung 0:e87aa4c49e95 464 __DCIMVAC = (uint32_t)va;
phungductung 0:e87aa4c49e95 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
phungductung 0:e87aa4c49e95 466 }
phungductung 0:e87aa4c49e95 467
phungductung 0:e87aa4c49e95 468 /** \brief Clean and Invalidate D$ by MVA
phungductung 0:e87aa4c49e95 469
phungductung 0:e87aa4c49e95 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
phungductung 0:e87aa4c49e95 471 */
phungductung 0:e87aa4c49e95 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
phungductung 0:e87aa4c49e95 474 __DCCIMVAC = (uint32_t)va;
phungductung 0:e87aa4c49e95 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
phungductung 0:e87aa4c49e95 476 }
phungductung 0:e87aa4c49e95 477
phungductung 0:e87aa4c49e95 478 /** \brief Clean and Invalidate the entire data or unified cache
phungductung 0:e87aa4c49e95 479
phungductung 0:e87aa4c49e95 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
phungductung 0:e87aa4c49e95 481 */
phungductung 0:e87aa4c49e95 482 #pragma push
phungductung 0:e87aa4c49e95 483 #pragma arm
phungductung 0:e87aa4c49e95 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
phungductung 0:e87aa4c49e95 485 ARM
phungductung 0:e87aa4c49e95 486
phungductung 0:e87aa4c49e95 487 PUSH {R4-R11}
phungductung 0:e87aa4c49e95 488
phungductung 0:e87aa4c49e95 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
phungductung 0:e87aa4c49e95 490 ANDS R3, R6, #0x07000000 // Extract coherency level
phungductung 0:e87aa4c49e95 491 MOV R3, R3, LSR #23 // Total cache levels << 1
phungductung 0:e87aa4c49e95 492 BEQ Finished // If 0, no need to clean
phungductung 0:e87aa4c49e95 493
phungductung 0:e87aa4c49e95 494 MOV R10, #0 // R10 holds current cache level << 1
phungductung 0:e87aa4c49e95 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
phungductung 0:e87aa4c49e95 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
phungductung 0:e87aa4c49e95 497 AND R1, R1, #7 // Isolate those lower 3 bits
phungductung 0:e87aa4c49e95 498 CMP R1, #2
phungductung 0:e87aa4c49e95 499 BLT Skip // No cache or only instruction cache at this level
phungductung 0:e87aa4c49e95 500
phungductung 0:e87aa4c49e95 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
phungductung 0:e87aa4c49e95 502 ISB // ISB to sync the change to the CacheSizeID reg
phungductung 0:e87aa4c49e95 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
phungductung 0:e87aa4c49e95 504 AND R2, R1, #7 // Extract the line length field
phungductung 0:e87aa4c49e95 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
phungductung 0:e87aa4c49e95 506 LDR R4, =0x3FF
phungductung 0:e87aa4c49e95 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
phungductung 0:e87aa4c49e95 508 CLZ R5, R4 // R5 is the bit position of the way size increment
phungductung 0:e87aa4c49e95 509 LDR R7, =0x7FFF
phungductung 0:e87aa4c49e95 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
phungductung 0:e87aa4c49e95 511
phungductung 0:e87aa4c49e95 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
phungductung 0:e87aa4c49e95 513
phungductung 0:e87aa4c49e95 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
phungductung 0:e87aa4c49e95 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
phungductung 0:e87aa4c49e95 516 CMP R0, #0
phungductung 0:e87aa4c49e95 517 BNE Dccsw
phungductung 0:e87aa4c49e95 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
phungductung 0:e87aa4c49e95 519 B cont
phungductung 0:e87aa4c49e95 520 Dccsw CMP R0, #1
phungductung 0:e87aa4c49e95 521 BNE Dccisw
phungductung 0:e87aa4c49e95 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
phungductung 0:e87aa4c49e95 523 B cont
phungductung 0:e87aa4c49e95 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
phungductung 0:e87aa4c49e95 525 cont SUBS R9, R9, #1 // Decrement the Way number
phungductung 0:e87aa4c49e95 526 BGE Loop3
phungductung 0:e87aa4c49e95 527 SUBS R7, R7, #1 // Decrement the Set number
phungductung 0:e87aa4c49e95 528 BGE Loop2
phungductung 0:e87aa4c49e95 529 Skip ADD R10, R10, #2 // Increment the cache number
phungductung 0:e87aa4c49e95 530 CMP R3, R10
phungductung 0:e87aa4c49e95 531 BGT Loop1
phungductung 0:e87aa4c49e95 532
phungductung 0:e87aa4c49e95 533 Finished
phungductung 0:e87aa4c49e95 534 DSB
phungductung 0:e87aa4c49e95 535 POP {R4-R11}
phungductung 0:e87aa4c49e95 536 BX lr
phungductung 0:e87aa4c49e95 537
phungductung 0:e87aa4c49e95 538 }
phungductung 0:e87aa4c49e95 539 #pragma pop
phungductung 0:e87aa4c49e95 540
phungductung 0:e87aa4c49e95 541
phungductung 0:e87aa4c49e95 542 /** \brief Invalidate the whole D$
phungductung 0:e87aa4c49e95 543
phungductung 0:e87aa4c49e95 544 DCISW. Invalidate by Set/Way
phungductung 0:e87aa4c49e95 545 */
phungductung 0:e87aa4c49e95 546
phungductung 0:e87aa4c49e95 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
phungductung 0:e87aa4c49e95 548 __v7_all_cache(0);
phungductung 0:e87aa4c49e95 549 }
phungductung 0:e87aa4c49e95 550
phungductung 0:e87aa4c49e95 551 /** \brief Clean the whole D$
phungductung 0:e87aa4c49e95 552
phungductung 0:e87aa4c49e95 553 DCCSW. Clean by Set/Way
phungductung 0:e87aa4c49e95 554 */
phungductung 0:e87aa4c49e95 555
phungductung 0:e87aa4c49e95 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
phungductung 0:e87aa4c49e95 557 __v7_all_cache(1);
phungductung 0:e87aa4c49e95 558 }
phungductung 0:e87aa4c49e95 559
phungductung 0:e87aa4c49e95 560 /** \brief Clean and invalidate the whole D$
phungductung 0:e87aa4c49e95 561
phungductung 0:e87aa4c49e95 562 DCCISW. Clean and Invalidate by Set/Way
phungductung 0:e87aa4c49e95 563 */
phungductung 0:e87aa4c49e95 564
phungductung 0:e87aa4c49e95 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
phungductung 0:e87aa4c49e95 566 __v7_all_cache(2);
phungductung 0:e87aa4c49e95 567 }
phungductung 0:e87aa4c49e95 568
phungductung 0:e87aa4c49e95 569 #include "core_ca_mmu.h"
phungductung 0:e87aa4c49e95 570
phungductung 0:e87aa4c49e95 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
phungductung 0:e87aa4c49e95 572
phungductung 0:e87aa4c49e95 573 #define __inline inline
phungductung 0:e87aa4c49e95 574
phungductung 0:e87aa4c49e95 575 inline static uint32_t __disable_irq_iar() {
phungductung 0:e87aa4c49e95 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
phungductung 0:e87aa4c49e95 577 __disable_irq();
phungductung 0:e87aa4c49e95 578 return irq_dis;
phungductung 0:e87aa4c49e95 579 }
phungductung 0:e87aa4c49e95 580
phungductung 0:e87aa4c49e95 581 #define MODE_USR 0x10
phungductung 0:e87aa4c49e95 582 #define MODE_FIQ 0x11
phungductung 0:e87aa4c49e95 583 #define MODE_IRQ 0x12
phungductung 0:e87aa4c49e95 584 #define MODE_SVC 0x13
phungductung 0:e87aa4c49e95 585 #define MODE_MON 0x16
phungductung 0:e87aa4c49e95 586 #define MODE_ABT 0x17
phungductung 0:e87aa4c49e95 587 #define MODE_HYP 0x1A
phungductung 0:e87aa4c49e95 588 #define MODE_UND 0x1B
phungductung 0:e87aa4c49e95 589 #define MODE_SYS 0x1F
phungductung 0:e87aa4c49e95 590
phungductung 0:e87aa4c49e95 591 /** \brief Set Process Stack Pointer
phungductung 0:e87aa4c49e95 592
phungductung 0:e87aa4c49e95 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
phungductung 0:e87aa4c49e95 594
phungductung 0:e87aa4c49e95 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
phungductung 0:e87aa4c49e95 596 */
phungductung 0:e87aa4c49e95 597 // from rt_CMSIS.c
phungductung 0:e87aa4c49e95 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
phungductung 0:e87aa4c49e95 599 __asm(
phungductung 0:e87aa4c49e95 600 " ARM\n"
phungductung 0:e87aa4c49e95 601 // " PRESERVE8\n"
phungductung 0:e87aa4c49e95 602
phungductung 0:e87aa4c49e95 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
phungductung 0:e87aa4c49e95 604 " MRS R1, CPSR \n"
phungductung 0:e87aa4c49e95 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
phungductung 0:e87aa4c49e95 606 " MOV SP, R0 \n"
phungductung 0:e87aa4c49e95 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
phungductung 0:e87aa4c49e95 608 " ISB \n"
phungductung 0:e87aa4c49e95 609 " BX LR \n");
phungductung 0:e87aa4c49e95 610 }
phungductung 0:e87aa4c49e95 611
phungductung 0:e87aa4c49e95 612 /** \brief Set User Mode
phungductung 0:e87aa4c49e95 613
phungductung 0:e87aa4c49e95 614 This function changes the processor state to User Mode
phungductung 0:e87aa4c49e95 615 */
phungductung 0:e87aa4c49e95 616 // from rt_CMSIS.c
phungductung 0:e87aa4c49e95 617 __arm static inline void __set_CPS_USR(void) {
phungductung 0:e87aa4c49e95 618 __asm(
phungductung 0:e87aa4c49e95 619 " ARM \n"
phungductung 0:e87aa4c49e95 620
phungductung 0:e87aa4c49e95 621 " CPS #0x10 \n" // MODE_USR
phungductung 0:e87aa4c49e95 622 " BX LR\n");
phungductung 0:e87aa4c49e95 623 }
phungductung 0:e87aa4c49e95 624
phungductung 0:e87aa4c49e95 625 /** \brief Set TTBR0
phungductung 0:e87aa4c49e95 626
phungductung 0:e87aa4c49e95 627 This function assigns the given value to the Translation Table Base Register 0.
phungductung 0:e87aa4c49e95 628
phungductung 0:e87aa4c49e95 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
phungductung 0:e87aa4c49e95 630 */
phungductung 0:e87aa4c49e95 631 // from mmu_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
phungductung 0:e87aa4c49e95 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
phungductung 0:e87aa4c49e95 634 __ISB();
phungductung 0:e87aa4c49e95 635 }
phungductung 0:e87aa4c49e95 636
phungductung 0:e87aa4c49e95 637 /** \brief Set DACR
phungductung 0:e87aa4c49e95 638
phungductung 0:e87aa4c49e95 639 This function assigns the given value to the Domain Access Control Register.
phungductung 0:e87aa4c49e95 640
phungductung 0:e87aa4c49e95 641 \param [in] dacr Domain Access Control Register value to set
phungductung 0:e87aa4c49e95 642 */
phungductung 0:e87aa4c49e95 643 // from mmu_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
phungductung 0:e87aa4c49e95 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
phungductung 0:e87aa4c49e95 646 __ISB();
phungductung 0:e87aa4c49e95 647 }
phungductung 0:e87aa4c49e95 648
phungductung 0:e87aa4c49e95 649
phungductung 0:e87aa4c49e95 650 /******************************** Cache and BTAC enable ****************************************************/
phungductung 0:e87aa4c49e95 651 /** \brief Set SCTLR
phungductung 0:e87aa4c49e95 652
phungductung 0:e87aa4c49e95 653 This function assigns the given value to the System Control Register.
phungductung 0:e87aa4c49e95 654
phungductung 0:e87aa4c49e95 655 \param [in] sctlr System Control Register value to set
phungductung 0:e87aa4c49e95 656 */
phungductung 0:e87aa4c49e95 657 // from __enable_mmu()
phungductung 0:e87aa4c49e95 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
phungductung 0:e87aa4c49e95 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
phungductung 0:e87aa4c49e95 660 }
phungductung 0:e87aa4c49e95 661
phungductung 0:e87aa4c49e95 662 /** \brief Get SCTLR
phungductung 0:e87aa4c49e95 663
phungductung 0:e87aa4c49e95 664 This function returns the value of the System Control Register.
phungductung 0:e87aa4c49e95 665
phungductung 0:e87aa4c49e95 666 \return System Control Register value
phungductung 0:e87aa4c49e95 667 */
phungductung 0:e87aa4c49e95 668 // from __enable_mmu()
phungductung 0:e87aa4c49e95 669 __STATIC_INLINE uint32_t __get_SCTLR() {
phungductung 0:e87aa4c49e95 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
phungductung 0:e87aa4c49e95 671 return __regSCTLR;
phungductung 0:e87aa4c49e95 672 }
phungductung 0:e87aa4c49e95 673
phungductung 0:e87aa4c49e95 674 /** \brief Enable Caches
phungductung 0:e87aa4c49e95 675
phungductung 0:e87aa4c49e95 676 Enable Caches
phungductung 0:e87aa4c49e95 677 */
phungductung 0:e87aa4c49e95 678 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 679 __STATIC_INLINE void __enable_caches(void) {
phungductung 0:e87aa4c49e95 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
phungductung 0:e87aa4c49e95 681 }
phungductung 0:e87aa4c49e95 682
phungductung 0:e87aa4c49e95 683 /** \brief Enable BTAC
phungductung 0:e87aa4c49e95 684
phungductung 0:e87aa4c49e95 685 Enable BTAC
phungductung 0:e87aa4c49e95 686 */
phungductung 0:e87aa4c49e95 687 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 688 __STATIC_INLINE void __enable_btac(void) {
phungductung 0:e87aa4c49e95 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
phungductung 0:e87aa4c49e95 690 __ISB();
phungductung 0:e87aa4c49e95 691 }
phungductung 0:e87aa4c49e95 692
phungductung 0:e87aa4c49e95 693 /** \brief Enable MMU
phungductung 0:e87aa4c49e95 694
phungductung 0:e87aa4c49e95 695 Enable MMU
phungductung 0:e87aa4c49e95 696 */
phungductung 0:e87aa4c49e95 697 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 698 __STATIC_INLINE void __enable_mmu(void) {
phungductung 0:e87aa4c49e95 699 // Set M bit 0 to enable the MMU
phungductung 0:e87aa4c49e95 700 // Set AFE bit to enable simplified access permissions model
phungductung 0:e87aa4c49e95 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
phungductung 0:e87aa4c49e95 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
phungductung 0:e87aa4c49e95 703 __ISB();
phungductung 0:e87aa4c49e95 704 }
phungductung 0:e87aa4c49e95 705
phungductung 0:e87aa4c49e95 706 /******************************** TLB maintenance operations ************************************************/
phungductung 0:e87aa4c49e95 707 /** \brief Invalidate the whole tlb
phungductung 0:e87aa4c49e95 708
phungductung 0:e87aa4c49e95 709 TLBIALL. Invalidate the whole tlb
phungductung 0:e87aa4c49e95 710 */
phungductung 0:e87aa4c49e95 711 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
phungductung 0:e87aa4c49e95 713 uint32_t val = 0;
phungductung 0:e87aa4c49e95 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
phungductung 0:e87aa4c49e95 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
phungductung 0:e87aa4c49e95 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
phungductung 0:e87aa4c49e95 717 __DSB();
phungductung 0:e87aa4c49e95 718 __ISB();
phungductung 0:e87aa4c49e95 719 }
phungductung 0:e87aa4c49e95 720
phungductung 0:e87aa4c49e95 721 /******************************** BTB maintenance operations ************************************************/
phungductung 0:e87aa4c49e95 722 /** \brief Invalidate entire branch predictor array
phungductung 0:e87aa4c49e95 723
phungductung 0:e87aa4c49e95 724 BPIALL. Branch Predictor Invalidate All.
phungductung 0:e87aa4c49e95 725 */
phungductung 0:e87aa4c49e95 726 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 727 __STATIC_INLINE void __v7_inv_btac(void) {
phungductung 0:e87aa4c49e95 728 uint32_t val = 0;
phungductung 0:e87aa4c49e95 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
phungductung 0:e87aa4c49e95 730 __DSB(); //ensure completion of the invalidation
phungductung 0:e87aa4c49e95 731 __ISB(); //ensure instruction fetch path sees new state
phungductung 0:e87aa4c49e95 732 }
phungductung 0:e87aa4c49e95 733
phungductung 0:e87aa4c49e95 734
phungductung 0:e87aa4c49e95 735 /******************************** L1 cache operations ******************************************************/
phungductung 0:e87aa4c49e95 736
phungductung 0:e87aa4c49e95 737 /** \brief Invalidate the whole I$
phungductung 0:e87aa4c49e95 738
phungductung 0:e87aa4c49e95 739 ICIALLU. Instruction Cache Invalidate All to PoU
phungductung 0:e87aa4c49e95 740 */
phungductung 0:e87aa4c49e95 741 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
phungductung 0:e87aa4c49e95 743 uint32_t val = 0;
phungductung 0:e87aa4c49e95 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
phungductung 0:e87aa4c49e95 745 __DSB(); //ensure completion of the invalidation
phungductung 0:e87aa4c49e95 746 __ISB(); //ensure instruction fetch path sees new I cache state
phungductung 0:e87aa4c49e95 747 }
phungductung 0:e87aa4c49e95 748
phungductung 0:e87aa4c49e95 749 // from __v7_inv_dcache_all()
phungductung 0:e87aa4c49e95 750 __arm static inline void __v7_all_cache(uint32_t op) {
phungductung 0:e87aa4c49e95 751 __asm(
phungductung 0:e87aa4c49e95 752 " ARM \n"
phungductung 0:e87aa4c49e95 753
phungductung 0:e87aa4c49e95 754 " PUSH {R4-R11} \n"
phungductung 0:e87aa4c49e95 755
phungductung 0:e87aa4c49e95 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
phungductung 0:e87aa4c49e95 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
phungductung 0:e87aa4c49e95 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
phungductung 0:e87aa4c49e95 759 " BEQ Finished\n" // If 0, no need to clean
phungductung 0:e87aa4c49e95 760
phungductung 0:e87aa4c49e95 761 " MOV R10, #0\n" // R10 holds current cache level << 1
phungductung 0:e87aa4c49e95 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
phungductung 0:e87aa4c49e95 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
phungductung 0:e87aa4c49e95 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
phungductung 0:e87aa4c49e95 765 " CMP R1, #2 \n"
phungductung 0:e87aa4c49e95 766 " BLT Skip \n" // No cache or only instruction cache at this level
phungductung 0:e87aa4c49e95 767
phungductung 0:e87aa4c49e95 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
phungductung 0:e87aa4c49e95 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
phungductung 0:e87aa4c49e95 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
phungductung 0:e87aa4c49e95 771 " AND R2, R1, #7 \n" // Extract the line length field
phungductung 0:e87aa4c49e95 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
phungductung 0:e87aa4c49e95 773 " movw R4, #0x3FF \n"
phungductung 0:e87aa4c49e95 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
phungductung 0:e87aa4c49e95 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
phungductung 0:e87aa4c49e95 776 " movw R7, #0x7FFF \n"
phungductung 0:e87aa4c49e95 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
phungductung 0:e87aa4c49e95 778
phungductung 0:e87aa4c49e95 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
phungductung 0:e87aa4c49e95 780
phungductung 0:e87aa4c49e95 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
phungductung 0:e87aa4c49e95 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
phungductung 0:e87aa4c49e95 783 " CMP R0, #0 \n"
phungductung 0:e87aa4c49e95 784 " BNE Dccsw \n"
phungductung 0:e87aa4c49e95 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
phungductung 0:e87aa4c49e95 786 " B cont \n"
phungductung 0:e87aa4c49e95 787 "Dccsw: CMP R0, #1 \n"
phungductung 0:e87aa4c49e95 788 " BNE Dccisw \n"
phungductung 0:e87aa4c49e95 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
phungductung 0:e87aa4c49e95 790 " B cont \n"
phungductung 0:e87aa4c49e95 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
phungductung 0:e87aa4c49e95 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
phungductung 0:e87aa4c49e95 793 " BGE Loop3 \n"
phungductung 0:e87aa4c49e95 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
phungductung 0:e87aa4c49e95 795 " BGE Loop2 \n"
phungductung 0:e87aa4c49e95 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
phungductung 0:e87aa4c49e95 797 " CMP R3, R10 \n"
phungductung 0:e87aa4c49e95 798 " BGT Loop1 \n"
phungductung 0:e87aa4c49e95 799
phungductung 0:e87aa4c49e95 800 "Finished: \n"
phungductung 0:e87aa4c49e95 801 " DSB \n"
phungductung 0:e87aa4c49e95 802 " POP {R4-R11} \n"
phungductung 0:e87aa4c49e95 803 " BX lr \n" );
phungductung 0:e87aa4c49e95 804 }
phungductung 0:e87aa4c49e95 805
phungductung 0:e87aa4c49e95 806 /** \brief Invalidate the whole D$
phungductung 0:e87aa4c49e95 807
phungductung 0:e87aa4c49e95 808 DCISW. Invalidate by Set/Way
phungductung 0:e87aa4c49e95 809 */
phungductung 0:e87aa4c49e95 810 // from system_Renesas_RZ_A1.c
phungductung 0:e87aa4c49e95 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
phungductung 0:e87aa4c49e95 812 __v7_all_cache(0);
phungductung 0:e87aa4c49e95 813 }
phungductung 0:e87aa4c49e95 814 /** \brief Clean and Invalidate D$ by MVA
phungductung 0:e87aa4c49e95 815
phungductung 0:e87aa4c49e95 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
phungductung 0:e87aa4c49e95 817 */
phungductung 0:e87aa4c49e95 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
phungductung 0:e87aa4c49e95 820 __DMB();
phungductung 0:e87aa4c49e95 821 }
phungductung 0:e87aa4c49e95 822
phungductung 0:e87aa4c49e95 823 #include "core_ca_mmu.h"
phungductung 0:e87aa4c49e95 824
phungductung 0:e87aa4c49e95 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
phungductung 0:e87aa4c49e95 826 /* GNU gcc specific functions */
phungductung 0:e87aa4c49e95 827
phungductung 0:e87aa4c49e95 828 #define MODE_USR 0x10
phungductung 0:e87aa4c49e95 829 #define MODE_FIQ 0x11
phungductung 0:e87aa4c49e95 830 #define MODE_IRQ 0x12
phungductung 0:e87aa4c49e95 831 #define MODE_SVC 0x13
phungductung 0:e87aa4c49e95 832 #define MODE_MON 0x16
phungductung 0:e87aa4c49e95 833 #define MODE_ABT 0x17
phungductung 0:e87aa4c49e95 834 #define MODE_HYP 0x1A
phungductung 0:e87aa4c49e95 835 #define MODE_UND 0x1B
phungductung 0:e87aa4c49e95 836 #define MODE_SYS 0x1F
phungductung 0:e87aa4c49e95 837
phungductung 0:e87aa4c49e95 838
phungductung 0:e87aa4c49e95 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
phungductung 0:e87aa4c49e95 840 {
phungductung 0:e87aa4c49e95 841 __ASM volatile ("cpsie i");
phungductung 0:e87aa4c49e95 842 }
phungductung 0:e87aa4c49e95 843
phungductung 0:e87aa4c49e95 844 /** \brief Disable IRQ Interrupts
phungductung 0:e87aa4c49e95 845
phungductung 0:e87aa4c49e95 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
phungductung 0:e87aa4c49e95 847 Can only be executed in Privileged modes.
phungductung 0:e87aa4c49e95 848 */
phungductung 0:e87aa4c49e95 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
phungductung 0:e87aa4c49e95 850 {
phungductung 0:e87aa4c49e95 851 uint32_t result;
phungductung 0:e87aa4c49e95 852
phungductung 0:e87aa4c49e95 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
phungductung 0:e87aa4c49e95 854 __ASM volatile ("cpsid i");
phungductung 0:e87aa4c49e95 855 return(result & 0x80);
phungductung 0:e87aa4c49e95 856 }
phungductung 0:e87aa4c49e95 857
phungductung 0:e87aa4c49e95 858
phungductung 0:e87aa4c49e95 859 /** \brief Get APSR Register
phungductung 0:e87aa4c49e95 860
phungductung 0:e87aa4c49e95 861 This function returns the content of the APSR Register.
phungductung 0:e87aa4c49e95 862
phungductung 0:e87aa4c49e95 863 \return APSR Register value
phungductung 0:e87aa4c49e95 864 */
phungductung 0:e87aa4c49e95 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
phungductung 0:e87aa4c49e95 866 {
phungductung 0:e87aa4c49e95 867 #if 1
phungductung 0:e87aa4c49e95 868 register uint32_t __regAPSR;
phungductung 0:e87aa4c49e95 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
phungductung 0:e87aa4c49e95 870 #else
phungductung 0:e87aa4c49e95 871 register uint32_t __regAPSR __ASM("apsr");
phungductung 0:e87aa4c49e95 872 #endif
phungductung 0:e87aa4c49e95 873 return(__regAPSR);
phungductung 0:e87aa4c49e95 874 }
phungductung 0:e87aa4c49e95 875
phungductung 0:e87aa4c49e95 876
phungductung 0:e87aa4c49e95 877 /** \brief Get CPSR Register
phungductung 0:e87aa4c49e95 878
phungductung 0:e87aa4c49e95 879 This function returns the content of the CPSR Register.
phungductung 0:e87aa4c49e95 880
phungductung 0:e87aa4c49e95 881 \return CPSR Register value
phungductung 0:e87aa4c49e95 882 */
phungductung 0:e87aa4c49e95 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
phungductung 0:e87aa4c49e95 884 {
phungductung 0:e87aa4c49e95 885 #if 1
phungductung 0:e87aa4c49e95 886 register uint32_t __regCPSR;
phungductung 0:e87aa4c49e95 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
phungductung 0:e87aa4c49e95 888 #else
phungductung 0:e87aa4c49e95 889 register uint32_t __regCPSR __ASM("cpsr");
phungductung 0:e87aa4c49e95 890 #endif
phungductung 0:e87aa4c49e95 891 return(__regCPSR);
phungductung 0:e87aa4c49e95 892 }
phungductung 0:e87aa4c49e95 893
phungductung 0:e87aa4c49e95 894 #if 0
phungductung 0:e87aa4c49e95 895 /** \brief Set Stack Pointer
phungductung 0:e87aa4c49e95 896
phungductung 0:e87aa4c49e95 897 This function assigns the given value to the current stack pointer.
phungductung 0:e87aa4c49e95 898
phungductung 0:e87aa4c49e95 899 \param [in] topOfStack Stack Pointer value to set
phungductung 0:e87aa4c49e95 900 */
phungductung 0:e87aa4c49e95 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
phungductung 0:e87aa4c49e95 902 {
phungductung 0:e87aa4c49e95 903 register uint32_t __regSP __ASM("sp");
phungductung 0:e87aa4c49e95 904 __regSP = topOfStack;
phungductung 0:e87aa4c49e95 905 }
phungductung 0:e87aa4c49e95 906 #endif
phungductung 0:e87aa4c49e95 907
phungductung 0:e87aa4c49e95 908 /** \brief Get link register
phungductung 0:e87aa4c49e95 909
phungductung 0:e87aa4c49e95 910 This function returns the value of the link register
phungductung 0:e87aa4c49e95 911
phungductung 0:e87aa4c49e95 912 \return Value of link register
phungductung 0:e87aa4c49e95 913 */
phungductung 0:e87aa4c49e95 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
phungductung 0:e87aa4c49e95 915 {
phungductung 0:e87aa4c49e95 916 register uint32_t __reglr __ASM("lr");
phungductung 0:e87aa4c49e95 917 return(__reglr);
phungductung 0:e87aa4c49e95 918 }
phungductung 0:e87aa4c49e95 919
phungductung 0:e87aa4c49e95 920 #if 0
phungductung 0:e87aa4c49e95 921 /** \brief Set link register
phungductung 0:e87aa4c49e95 922
phungductung 0:e87aa4c49e95 923 This function sets the value of the link register
phungductung 0:e87aa4c49e95 924
phungductung 0:e87aa4c49e95 925 \param [in] lr LR value to set
phungductung 0:e87aa4c49e95 926 */
phungductung 0:e87aa4c49e95 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
phungductung 0:e87aa4c49e95 928 {
phungductung 0:e87aa4c49e95 929 register uint32_t __reglr __ASM("lr");
phungductung 0:e87aa4c49e95 930 __reglr = lr;
phungductung 0:e87aa4c49e95 931 }
phungductung 0:e87aa4c49e95 932 #endif
phungductung 0:e87aa4c49e95 933
phungductung 0:e87aa4c49e95 934 /** \brief Set Process Stack Pointer
phungductung 0:e87aa4c49e95 935
phungductung 0:e87aa4c49e95 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
phungductung 0:e87aa4c49e95 937
phungductung 0:e87aa4c49e95 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
phungductung 0:e87aa4c49e95 939 */
phungductung 0:e87aa4c49e95 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
phungductung 0:e87aa4c49e95 941 {
phungductung 0:e87aa4c49e95 942 __asm__ volatile (
phungductung 0:e87aa4c49e95 943 ".ARM;"
phungductung 0:e87aa4c49e95 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
phungductung 0:e87aa4c49e95 945
phungductung 0:e87aa4c49e95 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
phungductung 0:e87aa4c49e95 947 "MRS R1, CPSR;"
phungductung 0:e87aa4c49e95 948 "CPS %0;" /* ;no effect in USR mode */
phungductung 0:e87aa4c49e95 949 "MOV SP, R0;"
phungductung 0:e87aa4c49e95 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
phungductung 0:e87aa4c49e95 951 "ISB;"
phungductung 0:e87aa4c49e95 952 //"BX LR;"
phungductung 0:e87aa4c49e95 953 :
phungductung 0:e87aa4c49e95 954 : "i"(MODE_SYS)
phungductung 0:e87aa4c49e95 955 : "r0", "r1");
phungductung 0:e87aa4c49e95 956 return;
phungductung 0:e87aa4c49e95 957 }
phungductung 0:e87aa4c49e95 958
phungductung 0:e87aa4c49e95 959 /** \brief Set User Mode
phungductung 0:e87aa4c49e95 960
phungductung 0:e87aa4c49e95 961 This function changes the processor state to User Mode
phungductung 0:e87aa4c49e95 962 */
phungductung 0:e87aa4c49e95 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
phungductung 0:e87aa4c49e95 964 {
phungductung 0:e87aa4c49e95 965 __asm__ volatile (
phungductung 0:e87aa4c49e95 966 ".ARM;"
phungductung 0:e87aa4c49e95 967
phungductung 0:e87aa4c49e95 968 "CPS %0;"
phungductung 0:e87aa4c49e95 969 //"BX LR;"
phungductung 0:e87aa4c49e95 970 :
phungductung 0:e87aa4c49e95 971 : "i"(MODE_USR)
phungductung 0:e87aa4c49e95 972 : );
phungductung 0:e87aa4c49e95 973 return;
phungductung 0:e87aa4c49e95 974 }
phungductung 0:e87aa4c49e95 975
phungductung 0:e87aa4c49e95 976
phungductung 0:e87aa4c49e95 977 /** \brief Enable FIQ
phungductung 0:e87aa4c49e95 978
phungductung 0:e87aa4c49e95 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
phungductung 0:e87aa4c49e95 980 Can only be executed in Privileged modes.
phungductung 0:e87aa4c49e95 981 */
phungductung 0:e87aa4c49e95 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
phungductung 0:e87aa4c49e95 983
phungductung 0:e87aa4c49e95 984
phungductung 0:e87aa4c49e95 985 /** \brief Disable FIQ
phungductung 0:e87aa4c49e95 986
phungductung 0:e87aa4c49e95 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
phungductung 0:e87aa4c49e95 988 Can only be executed in Privileged modes.
phungductung 0:e87aa4c49e95 989 */
phungductung 0:e87aa4c49e95 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
phungductung 0:e87aa4c49e95 991
phungductung 0:e87aa4c49e95 992
phungductung 0:e87aa4c49e95 993 /** \brief Get FPSCR
phungductung 0:e87aa4c49e95 994
phungductung 0:e87aa4c49e95 995 This function returns the current value of the Floating Point Status/Control register.
phungductung 0:e87aa4c49e95 996
phungductung 0:e87aa4c49e95 997 \return Floating Point Status/Control register value
phungductung 0:e87aa4c49e95 998 */
phungductung 0:e87aa4c49e95 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
phungductung 0:e87aa4c49e95 1000 {
phungductung 0:e87aa4c49e95 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
phungductung 0:e87aa4c49e95 1002 #if 1
phungductung 0:e87aa4c49e95 1003 uint32_t result;
phungductung 0:e87aa4c49e95 1004
phungductung 0:e87aa4c49e95 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
phungductung 0:e87aa4c49e95 1006 return (result);
phungductung 0:e87aa4c49e95 1007 #else
phungductung 0:e87aa4c49e95 1008 register uint32_t __regfpscr __ASM("fpscr");
phungductung 0:e87aa4c49e95 1009 return(__regfpscr);
phungductung 0:e87aa4c49e95 1010 #endif
phungductung 0:e87aa4c49e95 1011 #else
phungductung 0:e87aa4c49e95 1012 return(0);
phungductung 0:e87aa4c49e95 1013 #endif
phungductung 0:e87aa4c49e95 1014 }
phungductung 0:e87aa4c49e95 1015
phungductung 0:e87aa4c49e95 1016
phungductung 0:e87aa4c49e95 1017 /** \brief Set FPSCR
phungductung 0:e87aa4c49e95 1018
phungductung 0:e87aa4c49e95 1019 This function assigns the given value to the Floating Point Status/Control register.
phungductung 0:e87aa4c49e95 1020
phungductung 0:e87aa4c49e95 1021 \param [in] fpscr Floating Point Status/Control value to set
phungductung 0:e87aa4c49e95 1022 */
phungductung 0:e87aa4c49e95 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
phungductung 0:e87aa4c49e95 1024 {
phungductung 0:e87aa4c49e95 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
phungductung 0:e87aa4c49e95 1026 #if 1
phungductung 0:e87aa4c49e95 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
phungductung 0:e87aa4c49e95 1028 #else
phungductung 0:e87aa4c49e95 1029 register uint32_t __regfpscr __ASM("fpscr");
phungductung 0:e87aa4c49e95 1030 __regfpscr = (fpscr);
phungductung 0:e87aa4c49e95 1031 #endif
phungductung 0:e87aa4c49e95 1032 #endif
phungductung 0:e87aa4c49e95 1033 }
phungductung 0:e87aa4c49e95 1034
phungductung 0:e87aa4c49e95 1035 /** \brief Get FPEXC
phungductung 0:e87aa4c49e95 1036
phungductung 0:e87aa4c49e95 1037 This function returns the current value of the Floating Point Exception Control register.
phungductung 0:e87aa4c49e95 1038
phungductung 0:e87aa4c49e95 1039 \return Floating Point Exception Control register value
phungductung 0:e87aa4c49e95 1040 */
phungductung 0:e87aa4c49e95 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
phungductung 0:e87aa4c49e95 1042 {
phungductung 0:e87aa4c49e95 1043 #if (__FPU_PRESENT == 1)
phungductung 0:e87aa4c49e95 1044 #if 1
phungductung 0:e87aa4c49e95 1045 uint32_t result;
phungductung 0:e87aa4c49e95 1046
phungductung 0:e87aa4c49e95 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
phungductung 0:e87aa4c49e95 1048 return (result);
phungductung 0:e87aa4c49e95 1049 #else
phungductung 0:e87aa4c49e95 1050 register uint32_t __regfpexc __ASM("fpexc");
phungductung 0:e87aa4c49e95 1051 return(__regfpexc);
phungductung 0:e87aa4c49e95 1052 #endif
phungductung 0:e87aa4c49e95 1053 #else
phungductung 0:e87aa4c49e95 1054 return(0);
phungductung 0:e87aa4c49e95 1055 #endif
phungductung 0:e87aa4c49e95 1056 }
phungductung 0:e87aa4c49e95 1057
phungductung 0:e87aa4c49e95 1058
phungductung 0:e87aa4c49e95 1059 /** \brief Set FPEXC
phungductung 0:e87aa4c49e95 1060
phungductung 0:e87aa4c49e95 1061 This function assigns the given value to the Floating Point Exception Control register.
phungductung 0:e87aa4c49e95 1062
phungductung 0:e87aa4c49e95 1063 \param [in] fpscr Floating Point Exception Control value to set
phungductung 0:e87aa4c49e95 1064 */
phungductung 0:e87aa4c49e95 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
phungductung 0:e87aa4c49e95 1066 {
phungductung 0:e87aa4c49e95 1067 #if (__FPU_PRESENT == 1)
phungductung 0:e87aa4c49e95 1068 #if 1
phungductung 0:e87aa4c49e95 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
phungductung 0:e87aa4c49e95 1070 #else
phungductung 0:e87aa4c49e95 1071 register uint32_t __regfpexc __ASM("fpexc");
phungductung 0:e87aa4c49e95 1072 __regfpexc = (fpexc);
phungductung 0:e87aa4c49e95 1073 #endif
phungductung 0:e87aa4c49e95 1074 #endif
phungductung 0:e87aa4c49e95 1075 }
phungductung 0:e87aa4c49e95 1076
phungductung 0:e87aa4c49e95 1077 /** \brief Get CPACR
phungductung 0:e87aa4c49e95 1078
phungductung 0:e87aa4c49e95 1079 This function returns the current value of the Coprocessor Access Control register.
phungductung 0:e87aa4c49e95 1080
phungductung 0:e87aa4c49e95 1081 \return Coprocessor Access Control register value
phungductung 0:e87aa4c49e95 1082 */
phungductung 0:e87aa4c49e95 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
phungductung 0:e87aa4c49e95 1084 {
phungductung 0:e87aa4c49e95 1085 #if 1
phungductung 0:e87aa4c49e95 1086 register uint32_t __regCPACR;
phungductung 0:e87aa4c49e95 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
phungductung 0:e87aa4c49e95 1088 #else
phungductung 0:e87aa4c49e95 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
phungductung 0:e87aa4c49e95 1090 #endif
phungductung 0:e87aa4c49e95 1091 return __regCPACR;
phungductung 0:e87aa4c49e95 1092 }
phungductung 0:e87aa4c49e95 1093
phungductung 0:e87aa4c49e95 1094 /** \brief Set CPACR
phungductung 0:e87aa4c49e95 1095
phungductung 0:e87aa4c49e95 1096 This function assigns the given value to the Coprocessor Access Control register.
phungductung 0:e87aa4c49e95 1097
phungductung 0:e87aa4c49e95 1098 \param [in] cpacr Coprocessor Acccess Control value to set
phungductung 0:e87aa4c49e95 1099 */
phungductung 0:e87aa4c49e95 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
phungductung 0:e87aa4c49e95 1101 {
phungductung 0:e87aa4c49e95 1102 #if 1
phungductung 0:e87aa4c49e95 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
phungductung 0:e87aa4c49e95 1104 #else
phungductung 0:e87aa4c49e95 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
phungductung 0:e87aa4c49e95 1106 __regCPACR = cpacr;
phungductung 0:e87aa4c49e95 1107 #endif
phungductung 0:e87aa4c49e95 1108 __ISB();
phungductung 0:e87aa4c49e95 1109 }
phungductung 0:e87aa4c49e95 1110
phungductung 0:e87aa4c49e95 1111 /** \brief Get CBAR
phungductung 0:e87aa4c49e95 1112
phungductung 0:e87aa4c49e95 1113 This function returns the value of the Configuration Base Address register.
phungductung 0:e87aa4c49e95 1114
phungductung 0:e87aa4c49e95 1115 \return Configuration Base Address register value
phungductung 0:e87aa4c49e95 1116 */
phungductung 0:e87aa4c49e95 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
phungductung 0:e87aa4c49e95 1118 #if 1
phungductung 0:e87aa4c49e95 1119 register uint32_t __regCBAR;
phungductung 0:e87aa4c49e95 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
phungductung 0:e87aa4c49e95 1121 #else
phungductung 0:e87aa4c49e95 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
phungductung 0:e87aa4c49e95 1123 #endif
phungductung 0:e87aa4c49e95 1124 return(__regCBAR);
phungductung 0:e87aa4c49e95 1125 }
phungductung 0:e87aa4c49e95 1126
phungductung 0:e87aa4c49e95 1127 /** \brief Get TTBR0
phungductung 0:e87aa4c49e95 1128
phungductung 0:e87aa4c49e95 1129 This function returns the value of the Translation Table Base Register 0.
phungductung 0:e87aa4c49e95 1130
phungductung 0:e87aa4c49e95 1131 \return Translation Table Base Register 0 value
phungductung 0:e87aa4c49e95 1132 */
phungductung 0:e87aa4c49e95 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
phungductung 0:e87aa4c49e95 1134 #if 1
phungductung 0:e87aa4c49e95 1135 register uint32_t __regTTBR0;
phungductung 0:e87aa4c49e95 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
phungductung 0:e87aa4c49e95 1137 #else
phungductung 0:e87aa4c49e95 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
phungductung 0:e87aa4c49e95 1139 #endif
phungductung 0:e87aa4c49e95 1140 return(__regTTBR0);
phungductung 0:e87aa4c49e95 1141 }
phungductung 0:e87aa4c49e95 1142
phungductung 0:e87aa4c49e95 1143 /** \brief Set TTBR0
phungductung 0:e87aa4c49e95 1144
phungductung 0:e87aa4c49e95 1145 This function assigns the given value to the Translation Table Base Register 0.
phungductung 0:e87aa4c49e95 1146
phungductung 0:e87aa4c49e95 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
phungductung 0:e87aa4c49e95 1148 */
phungductung 0:e87aa4c49e95 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
phungductung 0:e87aa4c49e95 1150 #if 1
phungductung 0:e87aa4c49e95 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
phungductung 0:e87aa4c49e95 1152 #else
phungductung 0:e87aa4c49e95 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
phungductung 0:e87aa4c49e95 1154 __regTTBR0 = ttbr0;
phungductung 0:e87aa4c49e95 1155 #endif
phungductung 0:e87aa4c49e95 1156 __ISB();
phungductung 0:e87aa4c49e95 1157 }
phungductung 0:e87aa4c49e95 1158
phungductung 0:e87aa4c49e95 1159 /** \brief Get DACR
phungductung 0:e87aa4c49e95 1160
phungductung 0:e87aa4c49e95 1161 This function returns the value of the Domain Access Control Register.
phungductung 0:e87aa4c49e95 1162
phungductung 0:e87aa4c49e95 1163 \return Domain Access Control Register value
phungductung 0:e87aa4c49e95 1164 */
phungductung 0:e87aa4c49e95 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
phungductung 0:e87aa4c49e95 1166 #if 1
phungductung 0:e87aa4c49e95 1167 register uint32_t __regDACR;
phungductung 0:e87aa4c49e95 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
phungductung 0:e87aa4c49e95 1169 #else
phungductung 0:e87aa4c49e95 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
phungductung 0:e87aa4c49e95 1171 #endif
phungductung 0:e87aa4c49e95 1172 return(__regDACR);
phungductung 0:e87aa4c49e95 1173 }
phungductung 0:e87aa4c49e95 1174
phungductung 0:e87aa4c49e95 1175 /** \brief Set DACR
phungductung 0:e87aa4c49e95 1176
phungductung 0:e87aa4c49e95 1177 This function assigns the given value to the Domain Access Control Register.
phungductung 0:e87aa4c49e95 1178
phungductung 0:e87aa4c49e95 1179 \param [in] dacr Domain Access Control Register value to set
phungductung 0:e87aa4c49e95 1180 */
phungductung 0:e87aa4c49e95 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
phungductung 0:e87aa4c49e95 1182 #if 1
phungductung 0:e87aa4c49e95 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
phungductung 0:e87aa4c49e95 1184 #else
phungductung 0:e87aa4c49e95 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
phungductung 0:e87aa4c49e95 1186 __regDACR = dacr;
phungductung 0:e87aa4c49e95 1187 #endif
phungductung 0:e87aa4c49e95 1188 __ISB();
phungductung 0:e87aa4c49e95 1189 }
phungductung 0:e87aa4c49e95 1190
phungductung 0:e87aa4c49e95 1191 /******************************** Cache and BTAC enable ****************************************************/
phungductung 0:e87aa4c49e95 1192
phungductung 0:e87aa4c49e95 1193 /** \brief Set SCTLR
phungductung 0:e87aa4c49e95 1194
phungductung 0:e87aa4c49e95 1195 This function assigns the given value to the System Control Register.
phungductung 0:e87aa4c49e95 1196
phungductung 0:e87aa4c49e95 1197 \param [in] sctlr System Control Register value to set
phungductung 0:e87aa4c49e95 1198 */
phungductung 0:e87aa4c49e95 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
phungductung 0:e87aa4c49e95 1200 {
phungductung 0:e87aa4c49e95 1201 #if 1
phungductung 0:e87aa4c49e95 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
phungductung 0:e87aa4c49e95 1203 #else
phungductung 0:e87aa4c49e95 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
phungductung 0:e87aa4c49e95 1205 __regSCTLR = sctlr;
phungductung 0:e87aa4c49e95 1206 #endif
phungductung 0:e87aa4c49e95 1207 }
phungductung 0:e87aa4c49e95 1208
phungductung 0:e87aa4c49e95 1209 /** \brief Get SCTLR
phungductung 0:e87aa4c49e95 1210
phungductung 0:e87aa4c49e95 1211 This function returns the value of the System Control Register.
phungductung 0:e87aa4c49e95 1212
phungductung 0:e87aa4c49e95 1213 \return System Control Register value
phungductung 0:e87aa4c49e95 1214 */
phungductung 0:e87aa4c49e95 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
phungductung 0:e87aa4c49e95 1216 #if 1
phungductung 0:e87aa4c49e95 1217 register uint32_t __regSCTLR;
phungductung 0:e87aa4c49e95 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
phungductung 0:e87aa4c49e95 1219 #else
phungductung 0:e87aa4c49e95 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
phungductung 0:e87aa4c49e95 1221 #endif
phungductung 0:e87aa4c49e95 1222 return(__regSCTLR);
phungductung 0:e87aa4c49e95 1223 }
phungductung 0:e87aa4c49e95 1224
phungductung 0:e87aa4c49e95 1225 /** \brief Enable Caches
phungductung 0:e87aa4c49e95 1226
phungductung 0:e87aa4c49e95 1227 Enable Caches
phungductung 0:e87aa4c49e95 1228 */
phungductung 0:e87aa4c49e95 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
phungductung 0:e87aa4c49e95 1230 // Set I bit 12 to enable I Cache
phungductung 0:e87aa4c49e95 1231 // Set C bit 2 to enable D Cache
phungductung 0:e87aa4c49e95 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
phungductung 0:e87aa4c49e95 1233 }
phungductung 0:e87aa4c49e95 1234
phungductung 0:e87aa4c49e95 1235 /** \brief Disable Caches
phungductung 0:e87aa4c49e95 1236
phungductung 0:e87aa4c49e95 1237 Disable Caches
phungductung 0:e87aa4c49e95 1238 */
phungductung 0:e87aa4c49e95 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
phungductung 0:e87aa4c49e95 1240 // Clear I bit 12 to disable I Cache
phungductung 0:e87aa4c49e95 1241 // Clear C bit 2 to disable D Cache
phungductung 0:e87aa4c49e95 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
phungductung 0:e87aa4c49e95 1243 __ISB();
phungductung 0:e87aa4c49e95 1244 }
phungductung 0:e87aa4c49e95 1245
phungductung 0:e87aa4c49e95 1246 /** \brief Enable BTAC
phungductung 0:e87aa4c49e95 1247
phungductung 0:e87aa4c49e95 1248 Enable BTAC
phungductung 0:e87aa4c49e95 1249 */
phungductung 0:e87aa4c49e95 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
phungductung 0:e87aa4c49e95 1251 // Set Z bit 11 to enable branch prediction
phungductung 0:e87aa4c49e95 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
phungductung 0:e87aa4c49e95 1253 __ISB();
phungductung 0:e87aa4c49e95 1254 }
phungductung 0:e87aa4c49e95 1255
phungductung 0:e87aa4c49e95 1256 /** \brief Disable BTAC
phungductung 0:e87aa4c49e95 1257
phungductung 0:e87aa4c49e95 1258 Disable BTAC
phungductung 0:e87aa4c49e95 1259 */
phungductung 0:e87aa4c49e95 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
phungductung 0:e87aa4c49e95 1261 // Clear Z bit 11 to disable branch prediction
phungductung 0:e87aa4c49e95 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
phungductung 0:e87aa4c49e95 1263 }
phungductung 0:e87aa4c49e95 1264
phungductung 0:e87aa4c49e95 1265
phungductung 0:e87aa4c49e95 1266 /** \brief Enable MMU
phungductung 0:e87aa4c49e95 1267
phungductung 0:e87aa4c49e95 1268 Enable MMU
phungductung 0:e87aa4c49e95 1269 */
phungductung 0:e87aa4c49e95 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
phungductung 0:e87aa4c49e95 1271 // Set M bit 0 to enable the MMU
phungductung 0:e87aa4c49e95 1272 // Set AFE bit to enable simplified access permissions model
phungductung 0:e87aa4c49e95 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
phungductung 0:e87aa4c49e95 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
phungductung 0:e87aa4c49e95 1275 __ISB();
phungductung 0:e87aa4c49e95 1276 }
phungductung 0:e87aa4c49e95 1277
phungductung 0:e87aa4c49e95 1278 /** \brief Disable MMU
phungductung 0:e87aa4c49e95 1279
phungductung 0:e87aa4c49e95 1280 Disable MMU
phungductung 0:e87aa4c49e95 1281 */
phungductung 0:e87aa4c49e95 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
phungductung 0:e87aa4c49e95 1283 // Clear M bit 0 to disable the MMU
phungductung 0:e87aa4c49e95 1284 __set_SCTLR( __get_SCTLR() & ~1);
phungductung 0:e87aa4c49e95 1285 __ISB();
phungductung 0:e87aa4c49e95 1286 }
phungductung 0:e87aa4c49e95 1287
phungductung 0:e87aa4c49e95 1288 /******************************** TLB maintenance operations ************************************************/
phungductung 0:e87aa4c49e95 1289 /** \brief Invalidate the whole tlb
phungductung 0:e87aa4c49e95 1290
phungductung 0:e87aa4c49e95 1291 TLBIALL. Invalidate the whole tlb
phungductung 0:e87aa4c49e95 1292 */
phungductung 0:e87aa4c49e95 1293
phungductung 0:e87aa4c49e95 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
phungductung 0:e87aa4c49e95 1295 #if 1
phungductung 0:e87aa4c49e95 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
phungductung 0:e87aa4c49e95 1297 #else
phungductung 0:e87aa4c49e95 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
phungductung 0:e87aa4c49e95 1299 __TLBIALL = 0;
phungductung 0:e87aa4c49e95 1300 #endif
phungductung 0:e87aa4c49e95 1301 __DSB();
phungductung 0:e87aa4c49e95 1302 __ISB();
phungductung 0:e87aa4c49e95 1303 }
phungductung 0:e87aa4c49e95 1304
phungductung 0:e87aa4c49e95 1305 /******************************** BTB maintenance operations ************************************************/
phungductung 0:e87aa4c49e95 1306 /** \brief Invalidate entire branch predictor array
phungductung 0:e87aa4c49e95 1307
phungductung 0:e87aa4c49e95 1308 BPIALL. Branch Predictor Invalidate All.
phungductung 0:e87aa4c49e95 1309 */
phungductung 0:e87aa4c49e95 1310
phungductung 0:e87aa4c49e95 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
phungductung 0:e87aa4c49e95 1312 #if 1
phungductung 0:e87aa4c49e95 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
phungductung 0:e87aa4c49e95 1314 #else
phungductung 0:e87aa4c49e95 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
phungductung 0:e87aa4c49e95 1316 __BPIALL = 0;
phungductung 0:e87aa4c49e95 1317 #endif
phungductung 0:e87aa4c49e95 1318 __DSB(); //ensure completion of the invalidation
phungductung 0:e87aa4c49e95 1319 __ISB(); //ensure instruction fetch path sees new state
phungductung 0:e87aa4c49e95 1320 }
phungductung 0:e87aa4c49e95 1321
phungductung 0:e87aa4c49e95 1322
phungductung 0:e87aa4c49e95 1323 /******************************** L1 cache operations ******************************************************/
phungductung 0:e87aa4c49e95 1324
phungductung 0:e87aa4c49e95 1325 /** \brief Invalidate the whole I$
phungductung 0:e87aa4c49e95 1326
phungductung 0:e87aa4c49e95 1327 ICIALLU. Instruction Cache Invalidate All to PoU
phungductung 0:e87aa4c49e95 1328 */
phungductung 0:e87aa4c49e95 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
phungductung 0:e87aa4c49e95 1330 #if 1
phungductung 0:e87aa4c49e95 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
phungductung 0:e87aa4c49e95 1332 #else
phungductung 0:e87aa4c49e95 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
phungductung 0:e87aa4c49e95 1334 __ICIALLU = 0;
phungductung 0:e87aa4c49e95 1335 #endif
phungductung 0:e87aa4c49e95 1336 __DSB(); //ensure completion of the invalidation
phungductung 0:e87aa4c49e95 1337 __ISB(); //ensure instruction fetch path sees new I cache state
phungductung 0:e87aa4c49e95 1338 }
phungductung 0:e87aa4c49e95 1339
phungductung 0:e87aa4c49e95 1340 /** \brief Clean D$ by MVA
phungductung 0:e87aa4c49e95 1341
phungductung 0:e87aa4c49e95 1342 DCCMVAC. Data cache clean by MVA to PoC
phungductung 0:e87aa4c49e95 1343 */
phungductung 0:e87aa4c49e95 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 1345 #if 1
phungductung 0:e87aa4c49e95 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
phungductung 0:e87aa4c49e95 1347 #else
phungductung 0:e87aa4c49e95 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
phungductung 0:e87aa4c49e95 1349 __DCCMVAC = (uint32_t)va;
phungductung 0:e87aa4c49e95 1350 #endif
phungductung 0:e87aa4c49e95 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
phungductung 0:e87aa4c49e95 1352 }
phungductung 0:e87aa4c49e95 1353
phungductung 0:e87aa4c49e95 1354 /** \brief Invalidate D$ by MVA
phungductung 0:e87aa4c49e95 1355
phungductung 0:e87aa4c49e95 1356 DCIMVAC. Data cache invalidate by MVA to PoC
phungductung 0:e87aa4c49e95 1357 */
phungductung 0:e87aa4c49e95 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 1359 #if 1
phungductung 0:e87aa4c49e95 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
phungductung 0:e87aa4c49e95 1361 #else
phungductung 0:e87aa4c49e95 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
phungductung 0:e87aa4c49e95 1363 __DCIMVAC = (uint32_t)va;
phungductung 0:e87aa4c49e95 1364 #endif
phungductung 0:e87aa4c49e95 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
phungductung 0:e87aa4c49e95 1366 }
phungductung 0:e87aa4c49e95 1367
phungductung 0:e87aa4c49e95 1368 /** \brief Clean and Invalidate D$ by MVA
phungductung 0:e87aa4c49e95 1369
phungductung 0:e87aa4c49e95 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
phungductung 0:e87aa4c49e95 1371 */
phungductung 0:e87aa4c49e95 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
phungductung 0:e87aa4c49e95 1373 #if 1
phungductung 0:e87aa4c49e95 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
phungductung 0:e87aa4c49e95 1375 #else
phungductung 0:e87aa4c49e95 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
phungductung 0:e87aa4c49e95 1377 __DCCIMVAC = (uint32_t)va;
phungductung 0:e87aa4c49e95 1378 #endif
phungductung 0:e87aa4c49e95 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
phungductung 0:e87aa4c49e95 1380 }
phungductung 0:e87aa4c49e95 1381
phungductung 0:e87aa4c49e95 1382 /** \brief Clean and Invalidate the entire data or unified cache
phungductung 0:e87aa4c49e95 1383
phungductung 0:e87aa4c49e95 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
phungductung 0:e87aa4c49e95 1385 */
phungductung 0:e87aa4c49e95 1386 extern void __v7_all_cache(uint32_t op);
phungductung 0:e87aa4c49e95 1387
phungductung 0:e87aa4c49e95 1388
phungductung 0:e87aa4c49e95 1389 /** \brief Invalidate the whole D$
phungductung 0:e87aa4c49e95 1390
phungductung 0:e87aa4c49e95 1391 DCISW. Invalidate by Set/Way
phungductung 0:e87aa4c49e95 1392 */
phungductung 0:e87aa4c49e95 1393
phungductung 0:e87aa4c49e95 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
phungductung 0:e87aa4c49e95 1395 __v7_all_cache(0);
phungductung 0:e87aa4c49e95 1396 }
phungductung 0:e87aa4c49e95 1397
phungductung 0:e87aa4c49e95 1398 /** \brief Clean the whole D$
phungductung 0:e87aa4c49e95 1399
phungductung 0:e87aa4c49e95 1400 DCCSW. Clean by Set/Way
phungductung 0:e87aa4c49e95 1401 */
phungductung 0:e87aa4c49e95 1402
phungductung 0:e87aa4c49e95 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
phungductung 0:e87aa4c49e95 1404 __v7_all_cache(1);
phungductung 0:e87aa4c49e95 1405 }
phungductung 0:e87aa4c49e95 1406
phungductung 0:e87aa4c49e95 1407 /** \brief Clean and invalidate the whole D$
phungductung 0:e87aa4c49e95 1408
phungductung 0:e87aa4c49e95 1409 DCCISW. Clean and Invalidate by Set/Way
phungductung 0:e87aa4c49e95 1410 */
phungductung 0:e87aa4c49e95 1411
phungductung 0:e87aa4c49e95 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
phungductung 0:e87aa4c49e95 1413 __v7_all_cache(2);
phungductung 0:e87aa4c49e95 1414 }
phungductung 0:e87aa4c49e95 1415
phungductung 0:e87aa4c49e95 1416 #include "core_ca_mmu.h"
phungductung 0:e87aa4c49e95 1417
phungductung 0:e87aa4c49e95 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
phungductung 0:e87aa4c49e95 1419
phungductung 0:e87aa4c49e95 1420 #error TASKING Compiler support not implemented for Cortex-A
phungductung 0:e87aa4c49e95 1421
phungductung 0:e87aa4c49e95 1422 #endif
phungductung 0:e87aa4c49e95 1423
phungductung 0:e87aa4c49e95 1424 /*@} end of CMSIS_Core_RegAccFunctions */
phungductung 0:e87aa4c49e95 1425
phungductung 0:e87aa4c49e95 1426
phungductung 0:e87aa4c49e95 1427 #endif /* __CORE_CAFUNC_H__ */