PHung Tung / SRC_STM32F7

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

Who changed what in which revision?

UserRevisionLine numberNew contents of line
phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_ll_sdmmc.c
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief SDMMC Low Layer HAL module driver.
phungductung 0:e87aa4c49e95 8 *
phungductung 0:e87aa4c49e95 9 * This file provides firmware functions to manage the following
phungductung 0:e87aa4c49e95 10 * functionalities of the SDMMC peripheral:
phungductung 0:e87aa4c49e95 11 * + Initialization/de-initialization functions
phungductung 0:e87aa4c49e95 12 * + I/O operation functions
phungductung 0:e87aa4c49e95 13 * + Peripheral Control functions
phungductung 0:e87aa4c49e95 14 * + Peripheral State functions
phungductung 0:e87aa4c49e95 15 *
phungductung 0:e87aa4c49e95 16 @verbatim
phungductung 0:e87aa4c49e95 17 ==============================================================================
phungductung 0:e87aa4c49e95 18 ##### SDMMC peripheral features #####
phungductung 0:e87aa4c49e95 19 ==============================================================================
phungductung 0:e87aa4c49e95 20 [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
phungductung 0:e87aa4c49e95 21 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
phungductung 0:e87aa4c49e95 22 devices.
phungductung 0:e87aa4c49e95 23
phungductung 0:e87aa4c49e95 24 [..] The SDMMC features include the following:
phungductung 0:e87aa4c49e95 25 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
phungductung 0:e87aa4c49e95 26 for three different databus modes: 1-bit (default), 4-bit and 8-bit
phungductung 0:e87aa4c49e95 27 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
phungductung 0:e87aa4c49e95 28 (+) Full compliance with SD Memory Card Specifications Version 2.0
phungductung 0:e87aa4c49e95 29 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
phungductung 0:e87aa4c49e95 30 different data bus modes: 1-bit (default) and 4-bit
phungductung 0:e87aa4c49e95 31 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
phungductung 0:e87aa4c49e95 32 Rev1.1)
phungductung 0:e87aa4c49e95 33 (+) Data transfer up to 48 MHz for the 8 bit mode
phungductung 0:e87aa4c49e95 34 (+) Data and command output enable signals to control external bidirectional drivers.
phungductung 0:e87aa4c49e95 35
phungductung 0:e87aa4c49e95 36
phungductung 0:e87aa4c49e95 37 ##### How to use this driver #####
phungductung 0:e87aa4c49e95 38 ==============================================================================
phungductung 0:e87aa4c49e95 39 [..]
phungductung 0:e87aa4c49e95 40 This driver is a considered as a driver of service for external devices drivers
phungductung 0:e87aa4c49e95 41 that interfaces with the SDMMC peripheral.
phungductung 0:e87aa4c49e95 42 According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
phungductung 0:e87aa4c49e95 43 is used in the device's driver to perform SDMMC operations and functionalities.
phungductung 0:e87aa4c49e95 44
phungductung 0:e87aa4c49e95 45 This driver is almost transparent for the final user, it is only used to implement other
phungductung 0:e87aa4c49e95 46 functionalities of the external device.
phungductung 0:e87aa4c49e95 47
phungductung 0:e87aa4c49e95 48 [..]
phungductung 0:e87aa4c49e95 49 (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL
phungductung 0:e87aa4c49e95 50 (PLL48CLK). Before start working with SDMMC peripheral make sure that the
phungductung 0:e87aa4c49e95 51 PLL is well configured.
phungductung 0:e87aa4c49e95 52 The SDMMC peripheral uses two clock signals:
phungductung 0:e87aa4c49e95 53 (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
phungductung 0:e87aa4c49e95 54 (++) APB2 bus clock (PCLK2)
phungductung 0:e87aa4c49e95 55
phungductung 0:e87aa4c49e95 56 -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
phungductung 0:e87aa4c49e95 57 Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
phungductung 0:e87aa4c49e95 58
phungductung 0:e87aa4c49e95 59 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
phungductung 0:e87aa4c49e95 60 peripheral.
phungductung 0:e87aa4c49e95 61
phungductung 0:e87aa4c49e95 62 (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
phungductung 0:e87aa4c49e95 63 function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
phungductung 0:e87aa4c49e95 64
phungductung 0:e87aa4c49e95 65 (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
phungductung 0:e87aa4c49e95 66
phungductung 0:e87aa4c49e95 67 (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
phungductung 0:e87aa4c49e95 68 and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
phungductung 0:e87aa4c49e95 69
phungductung 0:e87aa4c49e95 70 (+) When using the DMA mode
phungductung 0:e87aa4c49e95 71 (++) Configure the DMA in the MSP layer of the external device
phungductung 0:e87aa4c49e95 72 (++) Active the needed channel Request
phungductung 0:e87aa4c49e95 73 (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
phungductung 0:e87aa4c49e95 74 __SDMMC_DMA_DISABLE().
phungductung 0:e87aa4c49e95 75
phungductung 0:e87aa4c49e95 76 (+) To control the CPSM (Command Path State Machine) and send
phungductung 0:e87aa4c49e95 77 commands to the card use the SDMMC_SendCommand(SDMMCx),
phungductung 0:e87aa4c49e95 78 SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
phungductung 0:e87aa4c49e95 79 to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
phungductung 0:e87aa4c49e95 80 to the selected command to be sent.
phungductung 0:e87aa4c49e95 81 The parameters that should be filled are:
phungductung 0:e87aa4c49e95 82 (++) Command Argument
phungductung 0:e87aa4c49e95 83 (++) Command Index
phungductung 0:e87aa4c49e95 84 (++) Command Response type
phungductung 0:e87aa4c49e95 85 (++) Command Wait
phungductung 0:e87aa4c49e95 86 (++) CPSM Status (Enable or Disable).
phungductung 0:e87aa4c49e95 87
phungductung 0:e87aa4c49e95 88 -@@- To check if the command is well received, read the SDMMC_CMDRESP
phungductung 0:e87aa4c49e95 89 register using the SDMMC_GetCommandResponse().
phungductung 0:e87aa4c49e95 90 The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
phungductung 0:e87aa4c49e95 91 SDMMC_GetResponse() function.
phungductung 0:e87aa4c49e95 92
phungductung 0:e87aa4c49e95 93 (+) To control the DPSM (Data Path State Machine) and send/receive
phungductung 0:e87aa4c49e95 94 data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
phungductung 0:e87aa4c49e95 95 SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions.
phungductung 0:e87aa4c49e95 96
phungductung 0:e87aa4c49e95 97 *** Read Operations ***
phungductung 0:e87aa4c49e95 98 =======================
phungductung 0:e87aa4c49e95 99 [..]
phungductung 0:e87aa4c49e95 100 (#) First, user has to fill the data structure (pointer to
phungductung 0:e87aa4c49e95 101 SDMMC_DataInitTypeDef) according to the selected data type to be received.
phungductung 0:e87aa4c49e95 102 The parameters that should be filled are:
phungductung 0:e87aa4c49e95 103 (++) Data TimeOut
phungductung 0:e87aa4c49e95 104 (++) Data Length
phungductung 0:e87aa4c49e95 105 (++) Data Block size
phungductung 0:e87aa4c49e95 106 (++) Data Transfer direction: should be from card (To SDMMC)
phungductung 0:e87aa4c49e95 107 (++) Data Transfer mode
phungductung 0:e87aa4c49e95 108 (++) DPSM Status (Enable or Disable)
phungductung 0:e87aa4c49e95 109
phungductung 0:e87aa4c49e95 110 (#) Configure the SDMMC resources to receive the data from the card
phungductung 0:e87aa4c49e95 111 according to selected transfer mode (Refer to Step 8, 9 and 10).
phungductung 0:e87aa4c49e95 112
phungductung 0:e87aa4c49e95 113 (#) Send the selected Read command (refer to step 11).
phungductung 0:e87aa4c49e95 114
phungductung 0:e87aa4c49e95 115 (#) Use the SDMMC flags/interrupts to check the transfer status.
phungductung 0:e87aa4c49e95 116
phungductung 0:e87aa4c49e95 117 *** Write Operations ***
phungductung 0:e87aa4c49e95 118 ========================
phungductung 0:e87aa4c49e95 119 [..]
phungductung 0:e87aa4c49e95 120 (#) First, user has to fill the data structure (pointer to
phungductung 0:e87aa4c49e95 121 SDMMC_DataInitTypeDef) according to the selected data type to be received.
phungductung 0:e87aa4c49e95 122 The parameters that should be filled are:
phungductung 0:e87aa4c49e95 123 (++) Data TimeOut
phungductung 0:e87aa4c49e95 124 (++) Data Length
phungductung 0:e87aa4c49e95 125 (++) Data Block size
phungductung 0:e87aa4c49e95 126 (++) Data Transfer direction: should be to card (To CARD)
phungductung 0:e87aa4c49e95 127 (++) Data Transfer mode
phungductung 0:e87aa4c49e95 128 (++) DPSM Status (Enable or Disable)
phungductung 0:e87aa4c49e95 129
phungductung 0:e87aa4c49e95 130 (#) Configure the SDMMC resources to send the data to the card according to
phungductung 0:e87aa4c49e95 131 selected transfer mode.
phungductung 0:e87aa4c49e95 132
phungductung 0:e87aa4c49e95 133 (#) Send the selected Write command.
phungductung 0:e87aa4c49e95 134
phungductung 0:e87aa4c49e95 135 (#) Use the SDMMC flags/interrupts to check the transfer status.
phungductung 0:e87aa4c49e95 136
phungductung 0:e87aa4c49e95 137 @endverbatim
phungductung 0:e87aa4c49e95 138 ******************************************************************************
phungductung 0:e87aa4c49e95 139 * @attention
phungductung 0:e87aa4c49e95 140 *
phungductung 0:e87aa4c49e95 141 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 142 *
phungductung 0:e87aa4c49e95 143 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 144 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 145 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 146 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 147 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 148 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 149 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 150 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 151 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 152 * without specific prior written permission.
phungductung 0:e87aa4c49e95 153 *
phungductung 0:e87aa4c49e95 154 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 155 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 156 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 157 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 158 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 159 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 160 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 161 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 162 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 163 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 164 *
phungductung 0:e87aa4c49e95 165 ******************************************************************************
phungductung 0:e87aa4c49e95 166 */
phungductung 0:e87aa4c49e95 167
phungductung 0:e87aa4c49e95 168 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 169 #include "stm32f7xx_hal.h"
phungductung 0:e87aa4c49e95 170
phungductung 0:e87aa4c49e95 171 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 172 * @{
phungductung 0:e87aa4c49e95 173 */
phungductung 0:e87aa4c49e95 174
phungductung 0:e87aa4c49e95 175 /** @defgroup SDMMC_LL SDMMC Low Layer
phungductung 0:e87aa4c49e95 176 * @brief Low layer module for SD
phungductung 0:e87aa4c49e95 177 * @{
phungductung 0:e87aa4c49e95 178 */
phungductung 0:e87aa4c49e95 179
phungductung 0:e87aa4c49e95 180 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
phungductung 0:e87aa4c49e95 181
phungductung 0:e87aa4c49e95 182 /* Private typedef -----------------------------------------------------------*/
phungductung 0:e87aa4c49e95 183 /* Private define ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 184 /* Private macro -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 185 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 186 /* Private function prototypes -----------------------------------------------*/
phungductung 0:e87aa4c49e95 187 /* Exported functions --------------------------------------------------------*/
phungductung 0:e87aa4c49e95 188
phungductung 0:e87aa4c49e95 189 /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
phungductung 0:e87aa4c49e95 190 * @{
phungductung 0:e87aa4c49e95 191 */
phungductung 0:e87aa4c49e95 192
phungductung 0:e87aa4c49e95 193 /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
phungductung 0:e87aa4c49e95 194 * @brief Initialization and Configuration functions
phungductung 0:e87aa4c49e95 195 *
phungductung 0:e87aa4c49e95 196 @verbatim
phungductung 0:e87aa4c49e95 197 ===============================================================================
phungductung 0:e87aa4c49e95 198 ##### Initialization/de-initialization functions #####
phungductung 0:e87aa4c49e95 199 ===============================================================================
phungductung 0:e87aa4c49e95 200 [..] This section provides functions allowing to:
phungductung 0:e87aa4c49e95 201
phungductung 0:e87aa4c49e95 202 @endverbatim
phungductung 0:e87aa4c49e95 203 * @{
phungductung 0:e87aa4c49e95 204 */
phungductung 0:e87aa4c49e95 205
phungductung 0:e87aa4c49e95 206 /**
phungductung 0:e87aa4c49e95 207 * @brief Initializes the SDMMC according to the specified
phungductung 0:e87aa4c49e95 208 * parameters in the SDMMC_InitTypeDef and create the associated handle.
phungductung 0:e87aa4c49e95 209 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 210 * @param Init: SDMMC initialization structure
phungductung 0:e87aa4c49e95 211 * @retval HAL status
phungductung 0:e87aa4c49e95 212 */
phungductung 0:e87aa4c49e95 213 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
phungductung 0:e87aa4c49e95 214 {
phungductung 0:e87aa4c49e95 215 uint32_t tmpreg = 0;
phungductung 0:e87aa4c49e95 216
phungductung 0:e87aa4c49e95 217 /* Check the parameters */
phungductung 0:e87aa4c49e95 218 assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
phungductung 0:e87aa4c49e95 219 assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
phungductung 0:e87aa4c49e95 220 assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
phungductung 0:e87aa4c49e95 221 assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
phungductung 0:e87aa4c49e95 222 assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
phungductung 0:e87aa4c49e95 223 assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
phungductung 0:e87aa4c49e95 224 assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
phungductung 0:e87aa4c49e95 225
phungductung 0:e87aa4c49e95 226 /* Set SDMMC configuration parameters */
phungductung 0:e87aa4c49e95 227 tmpreg |= (Init.ClockEdge |\
phungductung 0:e87aa4c49e95 228 Init.ClockBypass |\
phungductung 0:e87aa4c49e95 229 Init.ClockPowerSave |\
phungductung 0:e87aa4c49e95 230 Init.BusWide |\
phungductung 0:e87aa4c49e95 231 Init.HardwareFlowControl |\
phungductung 0:e87aa4c49e95 232 Init.ClockDiv
phungductung 0:e87aa4c49e95 233 );
phungductung 0:e87aa4c49e95 234
phungductung 0:e87aa4c49e95 235 /* Write to SDMMC CLKCR */
phungductung 0:e87aa4c49e95 236 MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
phungductung 0:e87aa4c49e95 237
phungductung 0:e87aa4c49e95 238 return HAL_OK;
phungductung 0:e87aa4c49e95 239 }
phungductung 0:e87aa4c49e95 240
phungductung 0:e87aa4c49e95 241
phungductung 0:e87aa4c49e95 242
phungductung 0:e87aa4c49e95 243 /**
phungductung 0:e87aa4c49e95 244 * @}
phungductung 0:e87aa4c49e95 245 */
phungductung 0:e87aa4c49e95 246
phungductung 0:e87aa4c49e95 247 /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
phungductung 0:e87aa4c49e95 248 * @brief Data transfers functions
phungductung 0:e87aa4c49e95 249 *
phungductung 0:e87aa4c49e95 250 @verbatim
phungductung 0:e87aa4c49e95 251 ===============================================================================
phungductung 0:e87aa4c49e95 252 ##### I/O operation functions #####
phungductung 0:e87aa4c49e95 253 ===============================================================================
phungductung 0:e87aa4c49e95 254 [..]
phungductung 0:e87aa4c49e95 255 This subsection provides a set of functions allowing to manage the SDMMC data
phungductung 0:e87aa4c49e95 256 transfers.
phungductung 0:e87aa4c49e95 257
phungductung 0:e87aa4c49e95 258 @endverbatim
phungductung 0:e87aa4c49e95 259 * @{
phungductung 0:e87aa4c49e95 260 */
phungductung 0:e87aa4c49e95 261
phungductung 0:e87aa4c49e95 262 /**
phungductung 0:e87aa4c49e95 263 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
phungductung 0:e87aa4c49e95 264 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 265 * @retval HAL status
phungductung 0:e87aa4c49e95 266 */
phungductung 0:e87aa4c49e95 267 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 268 {
phungductung 0:e87aa4c49e95 269 /* Read data from Rx FIFO */
phungductung 0:e87aa4c49e95 270 return (SDMMCx->FIFO);
phungductung 0:e87aa4c49e95 271 }
phungductung 0:e87aa4c49e95 272
phungductung 0:e87aa4c49e95 273 /**
phungductung 0:e87aa4c49e95 274 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
phungductung 0:e87aa4c49e95 275 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 276 * @param pWriteData: pointer to data to write
phungductung 0:e87aa4c49e95 277 * @retval HAL status
phungductung 0:e87aa4c49e95 278 */
phungductung 0:e87aa4c49e95 279 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
phungductung 0:e87aa4c49e95 280 {
phungductung 0:e87aa4c49e95 281 /* Write data to FIFO */
phungductung 0:e87aa4c49e95 282 SDMMCx->FIFO = *pWriteData;
phungductung 0:e87aa4c49e95 283
phungductung 0:e87aa4c49e95 284 return HAL_OK;
phungductung 0:e87aa4c49e95 285 }
phungductung 0:e87aa4c49e95 286
phungductung 0:e87aa4c49e95 287 /**
phungductung 0:e87aa4c49e95 288 * @}
phungductung 0:e87aa4c49e95 289 */
phungductung 0:e87aa4c49e95 290
phungductung 0:e87aa4c49e95 291 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
phungductung 0:e87aa4c49e95 292 * @brief management functions
phungductung 0:e87aa4c49e95 293 *
phungductung 0:e87aa4c49e95 294 @verbatim
phungductung 0:e87aa4c49e95 295 ===============================================================================
phungductung 0:e87aa4c49e95 296 ##### Peripheral Control functions #####
phungductung 0:e87aa4c49e95 297 ===============================================================================
phungductung 0:e87aa4c49e95 298 [..]
phungductung 0:e87aa4c49e95 299 This subsection provides a set of functions allowing to control the SDMMC data
phungductung 0:e87aa4c49e95 300 transfers.
phungductung 0:e87aa4c49e95 301
phungductung 0:e87aa4c49e95 302 @endverbatim
phungductung 0:e87aa4c49e95 303 * @{
phungductung 0:e87aa4c49e95 304 */
phungductung 0:e87aa4c49e95 305
phungductung 0:e87aa4c49e95 306 /**
phungductung 0:e87aa4c49e95 307 * @brief Set SDMMC Power state to ON.
phungductung 0:e87aa4c49e95 308 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 309 * @retval HAL status
phungductung 0:e87aa4c49e95 310 */
phungductung 0:e87aa4c49e95 311 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 312 {
phungductung 0:e87aa4c49e95 313 /* Set power state to ON */
phungductung 0:e87aa4c49e95 314 SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
phungductung 0:e87aa4c49e95 315
phungductung 0:e87aa4c49e95 316 return HAL_OK;
phungductung 0:e87aa4c49e95 317 }
phungductung 0:e87aa4c49e95 318
phungductung 0:e87aa4c49e95 319 /**
phungductung 0:e87aa4c49e95 320 * @brief Set SDMMC Power state to OFF.
phungductung 0:e87aa4c49e95 321 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 322 * @retval HAL status
phungductung 0:e87aa4c49e95 323 */
phungductung 0:e87aa4c49e95 324 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 325 {
phungductung 0:e87aa4c49e95 326 /* Set power state to OFF */
phungductung 0:e87aa4c49e95 327 SDMMCx->POWER = (uint32_t)0x00000000;
phungductung 0:e87aa4c49e95 328
phungductung 0:e87aa4c49e95 329 return HAL_OK;
phungductung 0:e87aa4c49e95 330 }
phungductung 0:e87aa4c49e95 331
phungductung 0:e87aa4c49e95 332 /**
phungductung 0:e87aa4c49e95 333 * @brief Get SDMMC Power state.
phungductung 0:e87aa4c49e95 334 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 335 * @retval Power status of the controller. The returned value can be one of the
phungductung 0:e87aa4c49e95 336 * following values:
phungductung 0:e87aa4c49e95 337 * - 0x00: Power OFF
phungductung 0:e87aa4c49e95 338 * - 0x02: Power UP
phungductung 0:e87aa4c49e95 339 * - 0x03: Power ON
phungductung 0:e87aa4c49e95 340 */
phungductung 0:e87aa4c49e95 341 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 342 {
phungductung 0:e87aa4c49e95 343 return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
phungductung 0:e87aa4c49e95 344 }
phungductung 0:e87aa4c49e95 345
phungductung 0:e87aa4c49e95 346 /**
phungductung 0:e87aa4c49e95 347 * @brief Configure the SDMMC command path according to the specified parameters in
phungductung 0:e87aa4c49e95 348 * SDMMC_CmdInitTypeDef structure and send the command
phungductung 0:e87aa4c49e95 349 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 350 * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
phungductung 0:e87aa4c49e95 351 * the configuration information for the SDMMC command
phungductung 0:e87aa4c49e95 352 * @retval HAL status
phungductung 0:e87aa4c49e95 353 */
phungductung 0:e87aa4c49e95 354 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
phungductung 0:e87aa4c49e95 355 {
phungductung 0:e87aa4c49e95 356 uint32_t tmpreg = 0;
phungductung 0:e87aa4c49e95 357
phungductung 0:e87aa4c49e95 358 /* Check the parameters */
phungductung 0:e87aa4c49e95 359 assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
phungductung 0:e87aa4c49e95 360 assert_param(IS_SDMMC_RESPONSE(Command->Response));
phungductung 0:e87aa4c49e95 361 assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
phungductung 0:e87aa4c49e95 362 assert_param(IS_SDMMC_CPSM(Command->CPSM));
phungductung 0:e87aa4c49e95 363
phungductung 0:e87aa4c49e95 364 /* Set the SDMMC Argument value */
phungductung 0:e87aa4c49e95 365 SDMMCx->ARG = Command->Argument;
phungductung 0:e87aa4c49e95 366
phungductung 0:e87aa4c49e95 367 /* Set SDMMC command parameters */
phungductung 0:e87aa4c49e95 368 tmpreg |= (uint32_t)(Command->CmdIndex |\
phungductung 0:e87aa4c49e95 369 Command->Response |\
phungductung 0:e87aa4c49e95 370 Command->WaitForInterrupt |\
phungductung 0:e87aa4c49e95 371 Command->CPSM);
phungductung 0:e87aa4c49e95 372
phungductung 0:e87aa4c49e95 373 /* Write to SDMMC CMD register */
phungductung 0:e87aa4c49e95 374 MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
phungductung 0:e87aa4c49e95 375
phungductung 0:e87aa4c49e95 376 return HAL_OK;
phungductung 0:e87aa4c49e95 377 }
phungductung 0:e87aa4c49e95 378
phungductung 0:e87aa4c49e95 379 /**
phungductung 0:e87aa4c49e95 380 * @brief Return the command index of last command for which response received
phungductung 0:e87aa4c49e95 381 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 382 * @retval Command index of the last command response received
phungductung 0:e87aa4c49e95 383 */
phungductung 0:e87aa4c49e95 384 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 385 {
phungductung 0:e87aa4c49e95 386 return (uint8_t)(SDMMCx->RESPCMD);
phungductung 0:e87aa4c49e95 387 }
phungductung 0:e87aa4c49e95 388
phungductung 0:e87aa4c49e95 389
phungductung 0:e87aa4c49e95 390 /**
phungductung 0:e87aa4c49e95 391 * @brief Return the response received from the card for the last command
phungductung 0:e87aa4c49e95 392 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 393 * @param Response: Specifies the SDMMC response register.
phungductung 0:e87aa4c49e95 394 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 395 * @arg SDMMC_RESP1: Response Register 1
phungductung 0:e87aa4c49e95 396 * @arg SDMMC_RESP2: Response Register 2
phungductung 0:e87aa4c49e95 397 * @arg SDMMC_RESP3: Response Register 3
phungductung 0:e87aa4c49e95 398 * @arg SDMMC_RESP4: Response Register 4
phungductung 0:e87aa4c49e95 399 * @retval The Corresponding response register value
phungductung 0:e87aa4c49e95 400 */
phungductung 0:e87aa4c49e95 401 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
phungductung 0:e87aa4c49e95 402 {
phungductung 0:e87aa4c49e95 403 __IO uint32_t tmp = 0;
phungductung 0:e87aa4c49e95 404
phungductung 0:e87aa4c49e95 405 /* Check the parameters */
phungductung 0:e87aa4c49e95 406 assert_param(IS_SDMMC_RESP(Response));
phungductung 0:e87aa4c49e95 407
phungductung 0:e87aa4c49e95 408 /* Get the response */
phungductung 0:e87aa4c49e95 409 tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
phungductung 0:e87aa4c49e95 410
phungductung 0:e87aa4c49e95 411 return (*(__IO uint32_t *) tmp);
phungductung 0:e87aa4c49e95 412 }
phungductung 0:e87aa4c49e95 413
phungductung 0:e87aa4c49e95 414 /**
phungductung 0:e87aa4c49e95 415 * @brief Configure the SDMMC data path according to the specified
phungductung 0:e87aa4c49e95 416 * parameters in the SDMMC_DataInitTypeDef.
phungductung 0:e87aa4c49e95 417 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 418 * @param Data : pointer to a SDMMC_DataInitTypeDef structure
phungductung 0:e87aa4c49e95 419 * that contains the configuration information for the SDMMC data.
phungductung 0:e87aa4c49e95 420 * @retval HAL status
phungductung 0:e87aa4c49e95 421 */
phungductung 0:e87aa4c49e95 422 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
phungductung 0:e87aa4c49e95 423 {
phungductung 0:e87aa4c49e95 424 uint32_t tmpreg = 0;
phungductung 0:e87aa4c49e95 425
phungductung 0:e87aa4c49e95 426 /* Check the parameters */
phungductung 0:e87aa4c49e95 427 assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
phungductung 0:e87aa4c49e95 428 assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
phungductung 0:e87aa4c49e95 429 assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
phungductung 0:e87aa4c49e95 430 assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
phungductung 0:e87aa4c49e95 431 assert_param(IS_SDMMC_DPSM(Data->DPSM));
phungductung 0:e87aa4c49e95 432
phungductung 0:e87aa4c49e95 433 /* Set the SDMMC Data TimeOut value */
phungductung 0:e87aa4c49e95 434 SDMMCx->DTIMER = Data->DataTimeOut;
phungductung 0:e87aa4c49e95 435
phungductung 0:e87aa4c49e95 436 /* Set the SDMMC DataLength value */
phungductung 0:e87aa4c49e95 437 SDMMCx->DLEN = Data->DataLength;
phungductung 0:e87aa4c49e95 438
phungductung 0:e87aa4c49e95 439 /* Set the SDMMC data configuration parameters */
phungductung 0:e87aa4c49e95 440 tmpreg |= (uint32_t)(Data->DataBlockSize |\
phungductung 0:e87aa4c49e95 441 Data->TransferDir |\
phungductung 0:e87aa4c49e95 442 Data->TransferMode |\
phungductung 0:e87aa4c49e95 443 Data->DPSM);
phungductung 0:e87aa4c49e95 444
phungductung 0:e87aa4c49e95 445 /* Write to SDMMC DCTRL */
phungductung 0:e87aa4c49e95 446 MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
phungductung 0:e87aa4c49e95 447
phungductung 0:e87aa4c49e95 448 return HAL_OK;
phungductung 0:e87aa4c49e95 449
phungductung 0:e87aa4c49e95 450 }
phungductung 0:e87aa4c49e95 451
phungductung 0:e87aa4c49e95 452 /**
phungductung 0:e87aa4c49e95 453 * @brief Returns number of remaining data bytes to be transferred.
phungductung 0:e87aa4c49e95 454 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 455 * @retval Number of remaining data bytes to be transferred
phungductung 0:e87aa4c49e95 456 */
phungductung 0:e87aa4c49e95 457 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 458 {
phungductung 0:e87aa4c49e95 459 return (SDMMCx->DCOUNT);
phungductung 0:e87aa4c49e95 460 }
phungductung 0:e87aa4c49e95 461
phungductung 0:e87aa4c49e95 462 /**
phungductung 0:e87aa4c49e95 463 * @brief Get the FIFO data
phungductung 0:e87aa4c49e95 464 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 465 * @retval Data received
phungductung 0:e87aa4c49e95 466 */
phungductung 0:e87aa4c49e95 467 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
phungductung 0:e87aa4c49e95 468 {
phungductung 0:e87aa4c49e95 469 return (SDMMCx->FIFO);
phungductung 0:e87aa4c49e95 470 }
phungductung 0:e87aa4c49e95 471
phungductung 0:e87aa4c49e95 472
phungductung 0:e87aa4c49e95 473 /**
phungductung 0:e87aa4c49e95 474 * @brief Sets one of the two options of inserting read wait interval.
phungductung 0:e87aa4c49e95 475 * @param SDMMCx: Pointer to SDMMC register base
phungductung 0:e87aa4c49e95 476 * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
phungductung 0:e87aa4c49e95 477 * This parameter can be:
phungductung 0:e87aa4c49e95 478 * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
phungductung 0:e87aa4c49e95 479 * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
phungductung 0:e87aa4c49e95 480 * @retval None
phungductung 0:e87aa4c49e95 481 */
phungductung 0:e87aa4c49e95 482 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
phungductung 0:e87aa4c49e95 483 {
phungductung 0:e87aa4c49e95 484 /* Check the parameters */
phungductung 0:e87aa4c49e95 485 assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
phungductung 0:e87aa4c49e95 486
phungductung 0:e87aa4c49e95 487 /* Set SDMMC read wait mode */
phungductung 0:e87aa4c49e95 488 MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
phungductung 0:e87aa4c49e95 489
phungductung 0:e87aa4c49e95 490 return HAL_OK;
phungductung 0:e87aa4c49e95 491 }
phungductung 0:e87aa4c49e95 492
phungductung 0:e87aa4c49e95 493 /**
phungductung 0:e87aa4c49e95 494 * @}
phungductung 0:e87aa4c49e95 495 */
phungductung 0:e87aa4c49e95 496
phungductung 0:e87aa4c49e95 497 /**
phungductung 0:e87aa4c49e95 498 * @}
phungductung 0:e87aa4c49e95 499 */
phungductung 0:e87aa4c49e95 500
phungductung 0:e87aa4c49e95 501 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
phungductung 0:e87aa4c49e95 502 /**
phungductung 0:e87aa4c49e95 503 * @}
phungductung 0:e87aa4c49e95 504 */
phungductung 0:e87aa4c49e95 505
phungductung 0:e87aa4c49e95 506 /**
phungductung 0:e87aa4c49e95 507 * @}
phungductung 0:e87aa4c49e95 508 */
phungductung 0:e87aa4c49e95 509
phungductung 0:e87aa4c49e95 510 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/