PHung Tung / SRC_STM32F7

SPKT

Dependents:   WAV

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

Who changed what in which revision?

UserRevisionLine numberNew contents of line
phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_hal_sram.c
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief SRAM HAL module driver.
phungductung 0:e87aa4c49e95 8 * This file provides a generic firmware to drive SRAM memories
phungductung 0:e87aa4c49e95 9 * mounted as external device.
phungductung 0:e87aa4c49e95 10 *
phungductung 0:e87aa4c49e95 11 @verbatim
phungductung 0:e87aa4c49e95 12 ==============================================================================
phungductung 0:e87aa4c49e95 13 ##### How to use this driver #####
phungductung 0:e87aa4c49e95 14 ==============================================================================
phungductung 0:e87aa4c49e95 15 [..]
phungductung 0:e87aa4c49e95 16 This driver is a generic layered driver which contains a set of APIs used to
phungductung 0:e87aa4c49e95 17 control SRAM memories. It uses the FMC layer functions to interface
phungductung 0:e87aa4c49e95 18 with SRAM devices.
phungductung 0:e87aa4c49e95 19 The following sequence should be followed to configure the FMC to interface
phungductung 0:e87aa4c49e95 20 with SRAM/PSRAM memories:
phungductung 0:e87aa4c49e95 21
phungductung 0:e87aa4c49e95 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
phungductung 0:e87aa4c49e95 23 SRAM_HandleTypeDef hsram; and:
phungductung 0:e87aa4c49e95 24
phungductung 0:e87aa4c49e95 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
phungductung 0:e87aa4c49e95 26 values of the structure member.
phungductung 0:e87aa4c49e95 27
phungductung 0:e87aa4c49e95 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
phungductung 0:e87aa4c49e95 29 base register instance for NOR or SRAM device
phungductung 0:e87aa4c49e95 30
phungductung 0:e87aa4c49e95 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
phungductung 0:e87aa4c49e95 32 base register instance for NOR or SRAM extended mode
phungductung 0:e87aa4c49e95 33
phungductung 0:e87aa4c49e95 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
phungductung 0:e87aa4c49e95 35 mode timings; for example:
phungductung 0:e87aa4c49e95 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
phungductung 0:e87aa4c49e95 37 and fill its fields with the allowed values of the structure member.
phungductung 0:e87aa4c49e95 38
phungductung 0:e87aa4c49e95 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
phungductung 0:e87aa4c49e95 40 performs the following sequence:
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
phungductung 0:e87aa4c49e95 43 (##) Control register configuration using the FMC NORSRAM interface function
phungductung 0:e87aa4c49e95 44 FMC_NORSRAM_Init()
phungductung 0:e87aa4c49e95 45 (##) Timing register configuration using the FMC NORSRAM interface function
phungductung 0:e87aa4c49e95 46 FMC_NORSRAM_Timing_Init()
phungductung 0:e87aa4c49e95 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
phungductung 0:e87aa4c49e95 48 FMC_NORSRAM_Extended_Timing_Init()
phungductung 0:e87aa4c49e95 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
phungductung 0:e87aa4c49e95 50
phungductung 0:e87aa4c49e95 51 (#) At this stage you can perform read/write accesses from/to the memory connected
phungductung 0:e87aa4c49e95 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
phungductung 0:e87aa4c49e95 53 following APIs:
phungductung 0:e87aa4c49e95 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
phungductung 0:e87aa4c49e95 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
phungductung 0:e87aa4c49e95 56
phungductung 0:e87aa4c49e95 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
phungductung 0:e87aa4c49e95 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
phungductung 0:e87aa4c49e95 59
phungductung 0:e87aa4c49e95 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
phungductung 0:e87aa4c49e95 61 HAL_SRAM_GetState()
phungductung 0:e87aa4c49e95 62
phungductung 0:e87aa4c49e95 63 @endverbatim
phungductung 0:e87aa4c49e95 64 ******************************************************************************
phungductung 0:e87aa4c49e95 65 * @attention
phungductung 0:e87aa4c49e95 66 *
phungductung 0:e87aa4c49e95 67 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 68 *
phungductung 0:e87aa4c49e95 69 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 70 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 71 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 72 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 74 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 75 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 77 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 78 * without specific prior written permission.
phungductung 0:e87aa4c49e95 79 *
phungductung 0:e87aa4c49e95 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 90 *
phungductung 0:e87aa4c49e95 91 ******************************************************************************
phungductung 0:e87aa4c49e95 92 */
phungductung 0:e87aa4c49e95 93
phungductung 0:e87aa4c49e95 94 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 95 #include "stm32f7xx_hal.h"
phungductung 0:e87aa4c49e95 96
phungductung 0:e87aa4c49e95 97 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 98 * @{
phungductung 0:e87aa4c49e95 99 */
phungductung 0:e87aa4c49e95 100
phungductung 0:e87aa4c49e95 101 /** @defgroup SRAM SRAM
phungductung 0:e87aa4c49e95 102 * @brief SRAM driver modules
phungductung 0:e87aa4c49e95 103 * @{
phungductung 0:e87aa4c49e95 104 */
phungductung 0:e87aa4c49e95 105 #ifdef HAL_SRAM_MODULE_ENABLED
phungductung 0:e87aa4c49e95 106 /* Private typedef -----------------------------------------------------------*/
phungductung 0:e87aa4c49e95 107 /* Private define ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 108 /* Private macro -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 109 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 110 /* Private function prototypes -----------------------------------------------*/
phungductung 0:e87aa4c49e95 111 /* Exported functions --------------------------------------------------------*/
phungductung 0:e87aa4c49e95 112
phungductung 0:e87aa4c49e95 113 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
phungductung 0:e87aa4c49e95 114 * @{
phungductung 0:e87aa4c49e95 115 */
phungductung 0:e87aa4c49e95 116
phungductung 0:e87aa4c49e95 117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung 0:e87aa4c49e95 118 * @brief Initialization and Configuration functions.
phungductung 0:e87aa4c49e95 119 *
phungductung 0:e87aa4c49e95 120 @verbatim
phungductung 0:e87aa4c49e95 121 ==============================================================================
phungductung 0:e87aa4c49e95 122 ##### SRAM Initialization and de_initialization functions #####
phungductung 0:e87aa4c49e95 123 ==============================================================================
phungductung 0:e87aa4c49e95 124 [..] This section provides functions allowing to initialize/de-initialize
phungductung 0:e87aa4c49e95 125 the SRAM memory
phungductung 0:e87aa4c49e95 126
phungductung 0:e87aa4c49e95 127 @endverbatim
phungductung 0:e87aa4c49e95 128 * @{
phungductung 0:e87aa4c49e95 129 */
phungductung 0:e87aa4c49e95 130
phungductung 0:e87aa4c49e95 131 /**
phungductung 0:e87aa4c49e95 132 * @brief Performs the SRAM device initialization sequence
phungductung 0:e87aa4c49e95 133 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 134 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 135 * @param Timing: Pointer to SRAM control timing structure
phungductung 0:e87aa4c49e95 136 * @param ExtTiming: Pointer to SRAM extended mode timing structure
phungductung 0:e87aa4c49e95 137 * @retval HAL status
phungductung 0:e87aa4c49e95 138 */
phungductung 0:e87aa4c49e95 139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
phungductung 0:e87aa4c49e95 140 {
phungductung 0:e87aa4c49e95 141 /* Check the SRAM handle parameter */
phungductung 0:e87aa4c49e95 142 if(hsram == NULL)
phungductung 0:e87aa4c49e95 143 {
phungductung 0:e87aa4c49e95 144 return HAL_ERROR;
phungductung 0:e87aa4c49e95 145 }
phungductung 0:e87aa4c49e95 146
phungductung 0:e87aa4c49e95 147 if(hsram->State == HAL_SRAM_STATE_RESET)
phungductung 0:e87aa4c49e95 148 {
phungductung 0:e87aa4c49e95 149 /* Allocate lock resource and initialize it */
phungductung 0:e87aa4c49e95 150 hsram->Lock = HAL_UNLOCKED;
phungductung 0:e87aa4c49e95 151 /* Initialize the low level hardware (MSP) */
phungductung 0:e87aa4c49e95 152 HAL_SRAM_MspInit(hsram);
phungductung 0:e87aa4c49e95 153 }
phungductung 0:e87aa4c49e95 154
phungductung 0:e87aa4c49e95 155 /* Initialize SRAM control Interface */
phungductung 0:e87aa4c49e95 156 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
phungductung 0:e87aa4c49e95 157
phungductung 0:e87aa4c49e95 158 /* Initialize SRAM timing Interface */
phungductung 0:e87aa4c49e95 159 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
phungductung 0:e87aa4c49e95 160
phungductung 0:e87aa4c49e95 161 /* Initialize SRAM extended mode timing Interface */
phungductung 0:e87aa4c49e95 162 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
phungductung 0:e87aa4c49e95 163
phungductung 0:e87aa4c49e95 164 /* Enable the NORSRAM device */
phungductung 0:e87aa4c49e95 165 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
phungductung 0:e87aa4c49e95 166
phungductung 0:e87aa4c49e95 167 return HAL_OK;
phungductung 0:e87aa4c49e95 168 }
phungductung 0:e87aa4c49e95 169
phungductung 0:e87aa4c49e95 170 /**
phungductung 0:e87aa4c49e95 171 * @brief Performs the SRAM device De-initialization sequence.
phungductung 0:e87aa4c49e95 172 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 173 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 174 * @retval HAL status
phungductung 0:e87aa4c49e95 175 */
phungductung 0:e87aa4c49e95 176 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
phungductung 0:e87aa4c49e95 177 {
phungductung 0:e87aa4c49e95 178 /* De-Initialize the low level hardware (MSP) */
phungductung 0:e87aa4c49e95 179 HAL_SRAM_MspDeInit(hsram);
phungductung 0:e87aa4c49e95 180
phungductung 0:e87aa4c49e95 181 /* Configure the SRAM registers with their reset values */
phungductung 0:e87aa4c49e95 182 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
phungductung 0:e87aa4c49e95 183
phungductung 0:e87aa4c49e95 184 hsram->State = HAL_SRAM_STATE_RESET;
phungductung 0:e87aa4c49e95 185
phungductung 0:e87aa4c49e95 186 /* Release Lock */
phungductung 0:e87aa4c49e95 187 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 188
phungductung 0:e87aa4c49e95 189 return HAL_OK;
phungductung 0:e87aa4c49e95 190 }
phungductung 0:e87aa4c49e95 191
phungductung 0:e87aa4c49e95 192 /**
phungductung 0:e87aa4c49e95 193 * @brief SRAM MSP Init.
phungductung 0:e87aa4c49e95 194 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 195 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 196 * @retval None
phungductung 0:e87aa4c49e95 197 */
phungductung 0:e87aa4c49e95 198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
phungductung 0:e87aa4c49e95 199 {
phungductung 0:e87aa4c49e95 200 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 201 UNUSED(hsram);
phungductung 0:e87aa4c49e95 202
phungductung 0:e87aa4c49e95 203 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 204 the HAL_SRAM_MspInit could be implemented in the user file
phungductung 0:e87aa4c49e95 205 */
phungductung 0:e87aa4c49e95 206 }
phungductung 0:e87aa4c49e95 207
phungductung 0:e87aa4c49e95 208 /**
phungductung 0:e87aa4c49e95 209 * @brief SRAM MSP DeInit.
phungductung 0:e87aa4c49e95 210 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 211 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 212 * @retval None
phungductung 0:e87aa4c49e95 213 */
phungductung 0:e87aa4c49e95 214 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
phungductung 0:e87aa4c49e95 215 {
phungductung 0:e87aa4c49e95 216 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 217 UNUSED(hsram);
phungductung 0:e87aa4c49e95 218
phungductung 0:e87aa4c49e95 219 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 220 the HAL_SRAM_MspDeInit could be implemented in the user file
phungductung 0:e87aa4c49e95 221 */
phungductung 0:e87aa4c49e95 222 }
phungductung 0:e87aa4c49e95 223
phungductung 0:e87aa4c49e95 224 /**
phungductung 0:e87aa4c49e95 225 * @brief DMA transfer complete callback.
phungductung 0:e87aa4c49e95 226 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 227 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 228 * @retval None
phungductung 0:e87aa4c49e95 229 */
phungductung 0:e87aa4c49e95 230 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 231 {
phungductung 0:e87aa4c49e95 232 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 233 UNUSED(hdma);
phungductung 0:e87aa4c49e95 234
phungductung 0:e87aa4c49e95 235 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 236 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
phungductung 0:e87aa4c49e95 237 */
phungductung 0:e87aa4c49e95 238 }
phungductung 0:e87aa4c49e95 239
phungductung 0:e87aa4c49e95 240 /**
phungductung 0:e87aa4c49e95 241 * @brief DMA transfer complete error callback.
phungductung 0:e87aa4c49e95 242 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 243 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 244 * @retval None
phungductung 0:e87aa4c49e95 245 */
phungductung 0:e87aa4c49e95 246 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 247 {
phungductung 0:e87aa4c49e95 248 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 249 UNUSED(hdma);
phungductung 0:e87aa4c49e95 250
phungductung 0:e87aa4c49e95 251 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 252 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
phungductung 0:e87aa4c49e95 253 */
phungductung 0:e87aa4c49e95 254 }
phungductung 0:e87aa4c49e95 255
phungductung 0:e87aa4c49e95 256 /**
phungductung 0:e87aa4c49e95 257 * @}
phungductung 0:e87aa4c49e95 258 */
phungductung 0:e87aa4c49e95 259
phungductung 0:e87aa4c49e95 260 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
phungductung 0:e87aa4c49e95 261 * @brief Input Output and memory control functions
phungductung 0:e87aa4c49e95 262 *
phungductung 0:e87aa4c49e95 263 @verbatim
phungductung 0:e87aa4c49e95 264 ==============================================================================
phungductung 0:e87aa4c49e95 265 ##### SRAM Input and Output functions #####
phungductung 0:e87aa4c49e95 266 ==============================================================================
phungductung 0:e87aa4c49e95 267 [..]
phungductung 0:e87aa4c49e95 268 This section provides functions allowing to use and control the SRAM memory
phungductung 0:e87aa4c49e95 269
phungductung 0:e87aa4c49e95 270 @endverbatim
phungductung 0:e87aa4c49e95 271 * @{
phungductung 0:e87aa4c49e95 272 */
phungductung 0:e87aa4c49e95 273
phungductung 0:e87aa4c49e95 274 /**
phungductung 0:e87aa4c49e95 275 * @brief Reads 8-bit buffer from SRAM memory.
phungductung 0:e87aa4c49e95 276 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 277 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 278 * @param pAddress: Pointer to read start address
phungductung 0:e87aa4c49e95 279 * @param pDstBuffer: Pointer to destination buffer
phungductung 0:e87aa4c49e95 280 * @param BufferSize: Size of the buffer to read from memory
phungductung 0:e87aa4c49e95 281 * @retval HAL status
phungductung 0:e87aa4c49e95 282 */
phungductung 0:e87aa4c49e95 283 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 284 {
phungductung 0:e87aa4c49e95 285 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
phungductung 0:e87aa4c49e95 286
phungductung 0:e87aa4c49e95 287 /* Process Locked */
phungductung 0:e87aa4c49e95 288 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 289
phungductung 0:e87aa4c49e95 290 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 291 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 292
phungductung 0:e87aa4c49e95 293 /* Read data from memory */
phungductung 0:e87aa4c49e95 294 for(; BufferSize != 0; BufferSize--)
phungductung 0:e87aa4c49e95 295 {
phungductung 0:e87aa4c49e95 296 *pDstBuffer = *(__IO uint8_t *)psramaddress;
phungductung 0:e87aa4c49e95 297 pDstBuffer++;
phungductung 0:e87aa4c49e95 298 psramaddress++;
phungductung 0:e87aa4c49e95 299 }
phungductung 0:e87aa4c49e95 300
phungductung 0:e87aa4c49e95 301 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 302 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 303
phungductung 0:e87aa4c49e95 304 /* Process unlocked */
phungductung 0:e87aa4c49e95 305 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 306
phungductung 0:e87aa4c49e95 307 return HAL_OK;
phungductung 0:e87aa4c49e95 308 }
phungductung 0:e87aa4c49e95 309
phungductung 0:e87aa4c49e95 310 /**
phungductung 0:e87aa4c49e95 311 * @brief Writes 8-bit buffer to SRAM memory.
phungductung 0:e87aa4c49e95 312 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 313 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 314 * @param pAddress: Pointer to write start address
phungductung 0:e87aa4c49e95 315 * @param pSrcBuffer: Pointer to source buffer to write
phungductung 0:e87aa4c49e95 316 * @param BufferSize: Size of the buffer to write to memory
phungductung 0:e87aa4c49e95 317 * @retval HAL status
phungductung 0:e87aa4c49e95 318 */
phungductung 0:e87aa4c49e95 319 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 320 {
phungductung 0:e87aa4c49e95 321 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
phungductung 0:e87aa4c49e95 322
phungductung 0:e87aa4c49e95 323 /* Check the SRAM controller state */
phungductung 0:e87aa4c49e95 324 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
phungductung 0:e87aa4c49e95 325 {
phungductung 0:e87aa4c49e95 326 return HAL_ERROR;
phungductung 0:e87aa4c49e95 327 }
phungductung 0:e87aa4c49e95 328
phungductung 0:e87aa4c49e95 329 /* Process Locked */
phungductung 0:e87aa4c49e95 330 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 331
phungductung 0:e87aa4c49e95 332 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 333 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 334
phungductung 0:e87aa4c49e95 335 /* Write data to memory */
phungductung 0:e87aa4c49e95 336 for(; BufferSize != 0; BufferSize--)
phungductung 0:e87aa4c49e95 337 {
phungductung 0:e87aa4c49e95 338 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
phungductung 0:e87aa4c49e95 339 pSrcBuffer++;
phungductung 0:e87aa4c49e95 340 psramaddress++;
phungductung 0:e87aa4c49e95 341 }
phungductung 0:e87aa4c49e95 342
phungductung 0:e87aa4c49e95 343 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 344 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 345
phungductung 0:e87aa4c49e95 346 /* Process unlocked */
phungductung 0:e87aa4c49e95 347 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 348
phungductung 0:e87aa4c49e95 349 return HAL_OK;
phungductung 0:e87aa4c49e95 350 }
phungductung 0:e87aa4c49e95 351
phungductung 0:e87aa4c49e95 352 /**
phungductung 0:e87aa4c49e95 353 * @brief Reads 16-bit buffer from SRAM memory.
phungductung 0:e87aa4c49e95 354 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 355 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 356 * @param pAddress: Pointer to read start address
phungductung 0:e87aa4c49e95 357 * @param pDstBuffer: Pointer to destination buffer
phungductung 0:e87aa4c49e95 358 * @param BufferSize: Size of the buffer to read from memory
phungductung 0:e87aa4c49e95 359 * @retval HAL status
phungductung 0:e87aa4c49e95 360 */
phungductung 0:e87aa4c49e95 361 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 362 {
phungductung 0:e87aa4c49e95 363 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
phungductung 0:e87aa4c49e95 364
phungductung 0:e87aa4c49e95 365 /* Process Locked */
phungductung 0:e87aa4c49e95 366 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 367
phungductung 0:e87aa4c49e95 368 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 369 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 370
phungductung 0:e87aa4c49e95 371 /* Read data from memory */
phungductung 0:e87aa4c49e95 372 for(; BufferSize != 0; BufferSize--)
phungductung 0:e87aa4c49e95 373 {
phungductung 0:e87aa4c49e95 374 *pDstBuffer = *(__IO uint16_t *)psramaddress;
phungductung 0:e87aa4c49e95 375 pDstBuffer++;
phungductung 0:e87aa4c49e95 376 psramaddress++;
phungductung 0:e87aa4c49e95 377 }
phungductung 0:e87aa4c49e95 378
phungductung 0:e87aa4c49e95 379 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 380 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 381
phungductung 0:e87aa4c49e95 382 /* Process unlocked */
phungductung 0:e87aa4c49e95 383 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 384
phungductung 0:e87aa4c49e95 385 return HAL_OK;
phungductung 0:e87aa4c49e95 386 }
phungductung 0:e87aa4c49e95 387
phungductung 0:e87aa4c49e95 388 /**
phungductung 0:e87aa4c49e95 389 * @brief Writes 16-bit buffer to SRAM memory.
phungductung 0:e87aa4c49e95 390 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 391 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 392 * @param pAddress: Pointer to write start address
phungductung 0:e87aa4c49e95 393 * @param pSrcBuffer: Pointer to source buffer to write
phungductung 0:e87aa4c49e95 394 * @param BufferSize: Size of the buffer to write to memory
phungductung 0:e87aa4c49e95 395 * @retval HAL status
phungductung 0:e87aa4c49e95 396 */
phungductung 0:e87aa4c49e95 397 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 398 {
phungductung 0:e87aa4c49e95 399 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
phungductung 0:e87aa4c49e95 400
phungductung 0:e87aa4c49e95 401 /* Check the SRAM controller state */
phungductung 0:e87aa4c49e95 402 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
phungductung 0:e87aa4c49e95 403 {
phungductung 0:e87aa4c49e95 404 return HAL_ERROR;
phungductung 0:e87aa4c49e95 405 }
phungductung 0:e87aa4c49e95 406
phungductung 0:e87aa4c49e95 407 /* Process Locked */
phungductung 0:e87aa4c49e95 408 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 409
phungductung 0:e87aa4c49e95 410 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 411 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 412
phungductung 0:e87aa4c49e95 413 /* Write data to memory */
phungductung 0:e87aa4c49e95 414 for(; BufferSize != 0; BufferSize--)
phungductung 0:e87aa4c49e95 415 {
phungductung 0:e87aa4c49e95 416 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
phungductung 0:e87aa4c49e95 417 pSrcBuffer++;
phungductung 0:e87aa4c49e95 418 psramaddress++;
phungductung 0:e87aa4c49e95 419 }
phungductung 0:e87aa4c49e95 420
phungductung 0:e87aa4c49e95 421 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 422 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 423
phungductung 0:e87aa4c49e95 424 /* Process unlocked */
phungductung 0:e87aa4c49e95 425 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 426
phungductung 0:e87aa4c49e95 427 return HAL_OK;
phungductung 0:e87aa4c49e95 428 }
phungductung 0:e87aa4c49e95 429
phungductung 0:e87aa4c49e95 430 /**
phungductung 0:e87aa4c49e95 431 * @brief Reads 32-bit buffer from SRAM memory.
phungductung 0:e87aa4c49e95 432 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 433 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 434 * @param pAddress: Pointer to read start address
phungductung 0:e87aa4c49e95 435 * @param pDstBuffer: Pointer to destination buffer
phungductung 0:e87aa4c49e95 436 * @param BufferSize: Size of the buffer to read from memory
phungductung 0:e87aa4c49e95 437 * @retval HAL status
phungductung 0:e87aa4c49e95 438 */
phungductung 0:e87aa4c49e95 439 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 440 {
phungductung 0:e87aa4c49e95 441 /* Process Locked */
phungductung 0:e87aa4c49e95 442 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 443
phungductung 0:e87aa4c49e95 444 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 445 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 446
phungductung 0:e87aa4c49e95 447 /* Read data from memory */
phungductung 0:e87aa4c49e95 448 for(; BufferSize != 0; BufferSize--)
phungductung 0:e87aa4c49e95 449 {
phungductung 0:e87aa4c49e95 450 *pDstBuffer = *(__IO uint32_t *)pAddress;
phungductung 0:e87aa4c49e95 451 pDstBuffer++;
phungductung 0:e87aa4c49e95 452 pAddress++;
phungductung 0:e87aa4c49e95 453 }
phungductung 0:e87aa4c49e95 454
phungductung 0:e87aa4c49e95 455 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 456 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 457
phungductung 0:e87aa4c49e95 458 /* Process unlocked */
phungductung 0:e87aa4c49e95 459 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 460
phungductung 0:e87aa4c49e95 461 return HAL_OK;
phungductung 0:e87aa4c49e95 462 }
phungductung 0:e87aa4c49e95 463
phungductung 0:e87aa4c49e95 464 /**
phungductung 0:e87aa4c49e95 465 * @brief Writes 32-bit buffer to SRAM memory.
phungductung 0:e87aa4c49e95 466 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 467 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 468 * @param pAddress: Pointer to write start address
phungductung 0:e87aa4c49e95 469 * @param pSrcBuffer: Pointer to source buffer to write
phungductung 0:e87aa4c49e95 470 * @param BufferSize: Size of the buffer to write to memory
phungductung 0:e87aa4c49e95 471 * @retval HAL status
phungductung 0:e87aa4c49e95 472 */
phungductung 0:e87aa4c49e95 473 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 474 {
phungductung 0:e87aa4c49e95 475 /* Check the SRAM controller state */
phungductung 0:e87aa4c49e95 476 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
phungductung 0:e87aa4c49e95 477 {
phungductung 0:e87aa4c49e95 478 return HAL_ERROR;
phungductung 0:e87aa4c49e95 479 }
phungductung 0:e87aa4c49e95 480
phungductung 0:e87aa4c49e95 481 /* Process Locked */
phungductung 0:e87aa4c49e95 482 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 483
phungductung 0:e87aa4c49e95 484 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 485 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 486
phungductung 0:e87aa4c49e95 487 /* Write data to memory */
phungductung 0:e87aa4c49e95 488 for(; BufferSize != 0; BufferSize--)
phungductung 0:e87aa4c49e95 489 {
phungductung 0:e87aa4c49e95 490 *(__IO uint32_t *)pAddress = *pSrcBuffer;
phungductung 0:e87aa4c49e95 491 pSrcBuffer++;
phungductung 0:e87aa4c49e95 492 pAddress++;
phungductung 0:e87aa4c49e95 493 }
phungductung 0:e87aa4c49e95 494
phungductung 0:e87aa4c49e95 495 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 496 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 497
phungductung 0:e87aa4c49e95 498 /* Process unlocked */
phungductung 0:e87aa4c49e95 499 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 500
phungductung 0:e87aa4c49e95 501 return HAL_OK;
phungductung 0:e87aa4c49e95 502 }
phungductung 0:e87aa4c49e95 503
phungductung 0:e87aa4c49e95 504 /**
phungductung 0:e87aa4c49e95 505 * @brief Reads a Words data from the SRAM memory using DMA transfer.
phungductung 0:e87aa4c49e95 506 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 507 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 508 * @param pAddress: Pointer to read start address
phungductung 0:e87aa4c49e95 509 * @param pDstBuffer: Pointer to destination buffer
phungductung 0:e87aa4c49e95 510 * @param BufferSize: Size of the buffer to read from memory
phungductung 0:e87aa4c49e95 511 * @retval HAL status
phungductung 0:e87aa4c49e95 512 */
phungductung 0:e87aa4c49e95 513 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 514 {
phungductung 0:e87aa4c49e95 515 /* Process Locked */
phungductung 0:e87aa4c49e95 516 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 517
phungductung 0:e87aa4c49e95 518 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 519 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 520
phungductung 0:e87aa4c49e95 521 /* Configure DMA user callbacks */
phungductung 0:e87aa4c49e95 522 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
phungductung 0:e87aa4c49e95 523 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
phungductung 0:e87aa4c49e95 524
phungductung 0:e87aa4c49e95 525 /* Enable the DMA Stream */
phungductung 0:e87aa4c49e95 526 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
phungductung 0:e87aa4c49e95 527
phungductung 0:e87aa4c49e95 528 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 529 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 530
phungductung 0:e87aa4c49e95 531 /* Process unlocked */
phungductung 0:e87aa4c49e95 532 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 533
phungductung 0:e87aa4c49e95 534 return HAL_OK;
phungductung 0:e87aa4c49e95 535 }
phungductung 0:e87aa4c49e95 536
phungductung 0:e87aa4c49e95 537 /**
phungductung 0:e87aa4c49e95 538 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
phungductung 0:e87aa4c49e95 539 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 540 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 541 * @param pAddress: Pointer to write start address
phungductung 0:e87aa4c49e95 542 * @param pSrcBuffer: Pointer to source buffer to write
phungductung 0:e87aa4c49e95 543 * @param BufferSize: Size of the buffer to write to memory
phungductung 0:e87aa4c49e95 544 * @retval HAL status
phungductung 0:e87aa4c49e95 545 */
phungductung 0:e87aa4c49e95 546 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
phungductung 0:e87aa4c49e95 547 {
phungductung 0:e87aa4c49e95 548 /* Check the SRAM controller state */
phungductung 0:e87aa4c49e95 549 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
phungductung 0:e87aa4c49e95 550 {
phungductung 0:e87aa4c49e95 551 return HAL_ERROR;
phungductung 0:e87aa4c49e95 552 }
phungductung 0:e87aa4c49e95 553
phungductung 0:e87aa4c49e95 554 /* Process Locked */
phungductung 0:e87aa4c49e95 555 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 556
phungductung 0:e87aa4c49e95 557 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 558 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 559
phungductung 0:e87aa4c49e95 560 /* Configure DMA user callbacks */
phungductung 0:e87aa4c49e95 561 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
phungductung 0:e87aa4c49e95 562 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
phungductung 0:e87aa4c49e95 563
phungductung 0:e87aa4c49e95 564 /* Enable the DMA Stream */
phungductung 0:e87aa4c49e95 565 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
phungductung 0:e87aa4c49e95 566
phungductung 0:e87aa4c49e95 567 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 568 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 569
phungductung 0:e87aa4c49e95 570 /* Process unlocked */
phungductung 0:e87aa4c49e95 571 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 572
phungductung 0:e87aa4c49e95 573 return HAL_OK;
phungductung 0:e87aa4c49e95 574 }
phungductung 0:e87aa4c49e95 575
phungductung 0:e87aa4c49e95 576 /**
phungductung 0:e87aa4c49e95 577 * @}
phungductung 0:e87aa4c49e95 578 */
phungductung 0:e87aa4c49e95 579
phungductung 0:e87aa4c49e95 580 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
phungductung 0:e87aa4c49e95 581 * @brief Control functions
phungductung 0:e87aa4c49e95 582 *
phungductung 0:e87aa4c49e95 583 @verbatim
phungductung 0:e87aa4c49e95 584 ==============================================================================
phungductung 0:e87aa4c49e95 585 ##### SRAM Control functions #####
phungductung 0:e87aa4c49e95 586 ==============================================================================
phungductung 0:e87aa4c49e95 587 [..]
phungductung 0:e87aa4c49e95 588 This subsection provides a set of functions allowing to control dynamically
phungductung 0:e87aa4c49e95 589 the SRAM interface.
phungductung 0:e87aa4c49e95 590
phungductung 0:e87aa4c49e95 591 @endverbatim
phungductung 0:e87aa4c49e95 592 * @{
phungductung 0:e87aa4c49e95 593 */
phungductung 0:e87aa4c49e95 594
phungductung 0:e87aa4c49e95 595 /**
phungductung 0:e87aa4c49e95 596 * @brief Enables dynamically SRAM write operation.
phungductung 0:e87aa4c49e95 597 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 598 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 599 * @retval HAL status
phungductung 0:e87aa4c49e95 600 */
phungductung 0:e87aa4c49e95 601 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
phungductung 0:e87aa4c49e95 602 {
phungductung 0:e87aa4c49e95 603 /* Process Locked */
phungductung 0:e87aa4c49e95 604 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 605
phungductung 0:e87aa4c49e95 606 /* Enable write operation */
phungductung 0:e87aa4c49e95 607 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
phungductung 0:e87aa4c49e95 608
phungductung 0:e87aa4c49e95 609 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 610 hsram->State = HAL_SRAM_STATE_READY;
phungductung 0:e87aa4c49e95 611
phungductung 0:e87aa4c49e95 612 /* Process unlocked */
phungductung 0:e87aa4c49e95 613 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 614
phungductung 0:e87aa4c49e95 615 return HAL_OK;
phungductung 0:e87aa4c49e95 616 }
phungductung 0:e87aa4c49e95 617
phungductung 0:e87aa4c49e95 618 /**
phungductung 0:e87aa4c49e95 619 * @brief Disables dynamically SRAM write operation.
phungductung 0:e87aa4c49e95 620 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 621 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 622 * @retval HAL status
phungductung 0:e87aa4c49e95 623 */
phungductung 0:e87aa4c49e95 624 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
phungductung 0:e87aa4c49e95 625 {
phungductung 0:e87aa4c49e95 626 /* Process Locked */
phungductung 0:e87aa4c49e95 627 __HAL_LOCK(hsram);
phungductung 0:e87aa4c49e95 628
phungductung 0:e87aa4c49e95 629 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 630 hsram->State = HAL_SRAM_STATE_BUSY;
phungductung 0:e87aa4c49e95 631
phungductung 0:e87aa4c49e95 632 /* Disable write operation */
phungductung 0:e87aa4c49e95 633 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
phungductung 0:e87aa4c49e95 634
phungductung 0:e87aa4c49e95 635 /* Update the SRAM controller state */
phungductung 0:e87aa4c49e95 636 hsram->State = HAL_SRAM_STATE_PROTECTED;
phungductung 0:e87aa4c49e95 637
phungductung 0:e87aa4c49e95 638 /* Process unlocked */
phungductung 0:e87aa4c49e95 639 __HAL_UNLOCK(hsram);
phungductung 0:e87aa4c49e95 640
phungductung 0:e87aa4c49e95 641 return HAL_OK;
phungductung 0:e87aa4c49e95 642 }
phungductung 0:e87aa4c49e95 643
phungductung 0:e87aa4c49e95 644 /**
phungductung 0:e87aa4c49e95 645 * @}
phungductung 0:e87aa4c49e95 646 */
phungductung 0:e87aa4c49e95 647
phungductung 0:e87aa4c49e95 648 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
phungductung 0:e87aa4c49e95 649 * @brief Peripheral State functions
phungductung 0:e87aa4c49e95 650 *
phungductung 0:e87aa4c49e95 651 @verbatim
phungductung 0:e87aa4c49e95 652 ==============================================================================
phungductung 0:e87aa4c49e95 653 ##### SRAM State functions #####
phungductung 0:e87aa4c49e95 654 ==============================================================================
phungductung 0:e87aa4c49e95 655 [..]
phungductung 0:e87aa4c49e95 656 This subsection permits to get in run-time the status of the SRAM controller
phungductung 0:e87aa4c49e95 657 and the data flow.
phungductung 0:e87aa4c49e95 658
phungductung 0:e87aa4c49e95 659 @endverbatim
phungductung 0:e87aa4c49e95 660 * @{
phungductung 0:e87aa4c49e95 661 */
phungductung 0:e87aa4c49e95 662
phungductung 0:e87aa4c49e95 663 /**
phungductung 0:e87aa4c49e95 664 * @brief Returns the SRAM controller state
phungductung 0:e87aa4c49e95 665 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 666 * the configuration information for SRAM module.
phungductung 0:e87aa4c49e95 667 * @retval HAL state
phungductung 0:e87aa4c49e95 668 */
phungductung 0:e87aa4c49e95 669 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
phungductung 0:e87aa4c49e95 670 {
phungductung 0:e87aa4c49e95 671 return hsram->State;
phungductung 0:e87aa4c49e95 672 }
phungductung 0:e87aa4c49e95 673
phungductung 0:e87aa4c49e95 674 /**
phungductung 0:e87aa4c49e95 675 * @}
phungductung 0:e87aa4c49e95 676 */
phungductung 0:e87aa4c49e95 677
phungductung 0:e87aa4c49e95 678 /**
phungductung 0:e87aa4c49e95 679 * @}
phungductung 0:e87aa4c49e95 680 */
phungductung 0:e87aa4c49e95 681 #endif /* HAL_SRAM_MODULE_ENABLED */
phungductung 0:e87aa4c49e95 682 /**
phungductung 0:e87aa4c49e95 683 * @}
phungductung 0:e87aa4c49e95 684 */
phungductung 0:e87aa4c49e95 685
phungductung 0:e87aa4c49e95 686 /**
phungductung 0:e87aa4c49e95 687 * @}
phungductung 0:e87aa4c49e95 688 */
phungductung 0:e87aa4c49e95 689
phungductung 0:e87aa4c49e95 690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/