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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

libray

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User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/**
phungductung	0:e87aa4c49e95	2	******************************************************************************
phungductung	0:e87aa4c49e95	3	* @file stm32f7xx_hal_spi.c
phungductung	0:e87aa4c49e95	4	* @author MCD Application Team
phungductung	0:e87aa4c49e95	5	* @version V1.0.4
phungductung	0:e87aa4c49e95	6	* @date 09-December-2015
phungductung	0:e87aa4c49e95	7	* @brief SPI HAL module driver.
phungductung	0:e87aa4c49e95	8	* This file provides firmware functions to manage the following
phungductung	0:e87aa4c49e95	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
phungductung	0:e87aa4c49e95	10	* + Initialization and de-initialization functions
phungductung	0:e87aa4c49e95	11	* + IO operation functions
phungductung	0:e87aa4c49e95	12	* + Peripheral Control functions
phungductung	0:e87aa4c49e95	13	* + Peripheral State functions
phungductung	0:e87aa4c49e95	14	@verbatim
phungductung	0:e87aa4c49e95	15	==============================================================================
phungductung	0:e87aa4c49e95	16	##### How to use this driver #####
phungductung	0:e87aa4c49e95	17	==============================================================================
phungductung	0:e87aa4c49e95	18	[..]
phungductung	0:e87aa4c49e95	19	The SPI HAL driver can be used as follows:
phungductung	0:e87aa4c49e95	20
phungductung	0:e87aa4c49e95	21	(#) Declare a SPI_HandleTypeDef handle structure, for example:
phungductung	0:e87aa4c49e95	22	SPI_HandleTypeDef hspi;
phungductung	0:e87aa4c49e95	23
phungductung	0:e87aa4c49e95	24	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
phungductung	0:e87aa4c49e95	25	(##) Enable the SPIx interface clock
phungductung	0:e87aa4c49e95	26	(##) SPI pins configuration
phungductung	0:e87aa4c49e95	27	(+++) Enable the clock for the SPI GPIOs
phungductung	0:e87aa4c49e95	28	(+++) Configure these SPI pins as alternate function push-pull
phungductung	0:e87aa4c49e95	29	(##) NVIC configuration if you need to use interrupt process
phungductung	0:e87aa4c49e95	30	(+++) Configure the SPIx interrupt priority
phungductung	0:e87aa4c49e95	31	(+++) Enable the NVIC SPI IRQ handle
phungductung	0:e87aa4c49e95	32	(##) DMA Configuration if you need to use DMA process
phungductung	0:e87aa4c49e95	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
phungductung	0:e87aa4c49e95	34	(+++) Enable the DMAx clock
phungductung	0:e87aa4c49e95	35	(+++) Configure the DMA handle parameters
phungductung	0:e87aa4c49e95	36	(+++) Configure the DMA Tx or Rx channel
phungductung	0:e87aa4c49e95	37	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
phungductung	0:e87aa4c49e95	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
phungductung	0:e87aa4c49e95	39
phungductung	0:e87aa4c49e95	40	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
phungductung	0:e87aa4c49e95	41	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
phungductung	0:e87aa4c49e95	42
phungductung	0:e87aa4c49e95	43	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
phungductung	0:e87aa4c49e95	44	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
phungductung	0:e87aa4c49e95	45	by calling the customised HAL_SPI_MspInit() API.
phungductung	0:e87aa4c49e95	46	[..]
phungductung	0:e87aa4c49e95	47	Circular mode restriction:
phungductung	0:e87aa4c49e95	48	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
phungductung	0:e87aa4c49e95	49	(##) Master 2Lines RxOnly
phungductung	0:e87aa4c49e95	50	(##) Master 1Line Rx
phungductung	0:e87aa4c49e95	51	(#) The CRC feature is not managed when the DMA circular mode is enabled
phungductung	0:e87aa4c49e95	52	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
phungductung	0:e87aa4c49e95	53	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
phungductung	0:e87aa4c49e95	54
phungductung	0:e87aa4c49e95	55	@endverbatim
phungductung	0:e87aa4c49e95	56	******************************************************************************
phungductung	0:e87aa4c49e95	57	* @attention
phungductung	0:e87aa4c49e95	58	*
phungductung	0:e87aa4c49e95	59	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung	0:e87aa4c49e95	60	*
phungductung	0:e87aa4c49e95	61	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:e87aa4c49e95	62	* are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	63	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:e87aa4c49e95	64	* this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	65	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:e87aa4c49e95	66	* this list of conditions and the following disclaimer in the documentation
phungductung	0:e87aa4c49e95	67	* and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	68	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:e87aa4c49e95	69	* may be used to endorse or promote products derived from this software
phungductung	0:e87aa4c49e95	70	* without specific prior written permission.
phungductung	0:e87aa4c49e95	71	*
phungductung	0:e87aa4c49e95	72	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	73	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	74	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:e87aa4c49e95	75	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:e87aa4c49e95	76	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:e87aa4c49e95	77	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:e87aa4c49e95	78	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:e87aa4c49e95	79	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:e87aa4c49e95	80	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:e87aa4c49e95	81	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	82	*
phungductung	0:e87aa4c49e95	83	******************************************************************************
phungductung	0:e87aa4c49e95	84	*/
phungductung	0:e87aa4c49e95	85
phungductung	0:e87aa4c49e95	86	/* Includes ------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	87	#include "stm32f7xx_hal.h"
phungductung	0:e87aa4c49e95	88
phungductung	0:e87aa4c49e95	89	/** @addtogroup STM32F7xx_HAL_Driver
phungductung	0:e87aa4c49e95	90	* @{
phungductung	0:e87aa4c49e95	91	*/
phungductung	0:e87aa4c49e95	92
phungductung	0:e87aa4c49e95	93	/** @defgroup SPI SPI
phungductung	0:e87aa4c49e95	94	* @brief SPI HAL module driver
phungductung	0:e87aa4c49e95	95	* @{
phungductung	0:e87aa4c49e95	96	*/
phungductung	0:e87aa4c49e95	97	#ifdef HAL_SPI_MODULE_ENABLED
phungductung	0:e87aa4c49e95	98
phungductung	0:e87aa4c49e95	99	/* Private typedef -----------------------------------------------------------*/
phungductung	0:e87aa4c49e95	100	/* Private defines -----------------------------------------------------------*/
phungductung	0:e87aa4c49e95	101	/** @defgroup SPI_Private_Constants SPI Private Constants
phungductung	0:e87aa4c49e95	102	* @{
phungductung	0:e87aa4c49e95	103	*/
phungductung	0:e87aa4c49e95	104	#define SPI_DEFAULT_TIMEOUT 50
phungductung	0:e87aa4c49e95	105	/**
phungductung	0:e87aa4c49e95	106	* @}
phungductung	0:e87aa4c49e95	107	*/
phungductung	0:e87aa4c49e95	108
phungductung	0:e87aa4c49e95	109	/* Private macro -------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	110	/* Private variables ---------------------------------------------------------*/
phungductung	0:e87aa4c49e95	111	/* Private function prototypes -----------------------------------------------*/
phungductung	0:e87aa4c49e95	112	/** @addtogroup SPI_Private_Functions
phungductung	0:e87aa4c49e95	113	* @{
phungductung	0:e87aa4c49e95	114	*/
phungductung	0:e87aa4c49e95	115	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	116	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	117	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	118	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	119	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	120	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	121	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	122	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
phungductung	0:e87aa4c49e95	123	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
phungductung	0:e87aa4c49e95	124	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	125	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	126	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	127	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	128	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	129	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	130	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	131	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	132	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	133	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	134	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	135	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	136	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	137	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	138	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
phungductung	0:e87aa4c49e95	139	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
phungductung	0:e87aa4c49e95	140	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
phungductung	0:e87aa4c49e95	141	/**
phungductung	0:e87aa4c49e95	142	* @}
phungductung	0:e87aa4c49e95	143	*/
phungductung	0:e87aa4c49e95	144
phungductung	0:e87aa4c49e95	145	/* Exported functions ---------------------------------------------------------*/
phungductung	0:e87aa4c49e95	146
phungductung	0:e87aa4c49e95	147	/** @defgroup SPI_Exported_Functions SPI Exported Functions
phungductung	0:e87aa4c49e95	148	* @{
phungductung	0:e87aa4c49e95	149	*/
phungductung	0:e87aa4c49e95	150
phungductung	0:e87aa4c49e95	151	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung	0:e87aa4c49e95	152	* @brief Initialization and Configuration functions
phungductung	0:e87aa4c49e95	153	*
phungductung	0:e87aa4c49e95	154	@verbatim
phungductung	0:e87aa4c49e95	155	===============================================================================
phungductung	0:e87aa4c49e95	156	##### Initialization and de-initialization functions #####
phungductung	0:e87aa4c49e95	157	===============================================================================
phungductung	0:e87aa4c49e95	158	[..] This subsection provides a set of functions allowing to initialize and
phungductung	0:e87aa4c49e95	159	de-initialize the SPIx peripheral:
phungductung	0:e87aa4c49e95	160
phungductung	0:e87aa4c49e95	161	(+) User must implement HAL_SPI_MspInit() function in which he configures
phungductung	0:e87aa4c49e95	162	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
phungductung	0:e87aa4c49e95	163
phungductung	0:e87aa4c49e95	164	(+) Call the function HAL_SPI_Init() to configure the selected device with
phungductung	0:e87aa4c49e95	165	the selected configuration:
phungductung	0:e87aa4c49e95	166	(++) Mode
phungductung	0:e87aa4c49e95	167	(++) Direction
phungductung	0:e87aa4c49e95	168	(++) Data Size
phungductung	0:e87aa4c49e95	169	(++) Clock Polarity and Phase
phungductung	0:e87aa4c49e95	170	(++) NSS Management
phungductung	0:e87aa4c49e95	171	(++) BaudRate Prescaler
phungductung	0:e87aa4c49e95	172	(++) FirstBit
phungductung	0:e87aa4c49e95	173	(++) TIMode
phungductung	0:e87aa4c49e95	174	(++) CRC Calculation
phungductung	0:e87aa4c49e95	175	(++) CRC Polynomial if CRC enabled
phungductung	0:e87aa4c49e95	176	(++) CRC Length, used only with Data8 and Data16
phungductung	0:e87aa4c49e95	177	(++) FIFO reception threshold
phungductung	0:e87aa4c49e95	178
phungductung	0:e87aa4c49e95	179	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
phungductung	0:e87aa4c49e95	180	of the selected SPIx peripheral.
phungductung	0:e87aa4c49e95	181
phungductung	0:e87aa4c49e95	182	@endverbatim
phungductung	0:e87aa4c49e95	183	* @{
phungductung	0:e87aa4c49e95	184	*/
phungductung	0:e87aa4c49e95	185
phungductung	0:e87aa4c49e95	186	/**
phungductung	0:e87aa4c49e95	187	* @brief Initializes the SPI according to the specified parameters
phungductung	0:e87aa4c49e95	188	* in the SPI_InitTypeDef and create the associated handle.
phungductung	0:e87aa4c49e95	189	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	190	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	191	* @retval HAL status
phungductung	0:e87aa4c49e95	192	*/
phungductung	0:e87aa4c49e95	193	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	194	{
phungductung	0:e87aa4c49e95	195	uint32_t frxth;
phungductung	0:e87aa4c49e95	196
phungductung	0:e87aa4c49e95	197	/* Check the SPI handle allocation */
phungductung	0:e87aa4c49e95	198	if(hspi == NULL)
phungductung	0:e87aa4c49e95	199	{
phungductung	0:e87aa4c49e95	200	return HAL_ERROR;
phungductung	0:e87aa4c49e95	201	}
phungductung	0:e87aa4c49e95	202
phungductung	0:e87aa4c49e95	203	/* Check the parameters */
phungductung	0:e87aa4c49e95	204	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
phungductung	0:e87aa4c49e95	205	assert_param(IS_SPI_MODE(hspi->Init.Mode));
phungductung	0:e87aa4c49e95	206	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	207	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
phungductung	0:e87aa4c49e95	208	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
phungductung	0:e87aa4c49e95	209	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
phungductung	0:e87aa4c49e95	210	assert_param(IS_SPI_NSS(hspi->Init.NSS));
phungductung	0:e87aa4c49e95	211	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
phungductung	0:e87aa4c49e95	212	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
phungductung	0:e87aa4c49e95	213	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
phungductung	0:e87aa4c49e95	214	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
phungductung	0:e87aa4c49e95	215	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
phungductung	0:e87aa4c49e95	216	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
phungductung	0:e87aa4c49e95	217	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
phungductung	0:e87aa4c49e95	218
phungductung	0:e87aa4c49e95	219	if(hspi->State == HAL_SPI_STATE_RESET)
phungductung	0:e87aa4c49e95	220	{
phungductung	0:e87aa4c49e95	221	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	222	hspi->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	223
phungductung	0:e87aa4c49e95	224	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
phungductung	0:e87aa4c49e95	225	HAL_SPI_MspInit(hspi);
phungductung	0:e87aa4c49e95	226	}
phungductung	0:e87aa4c49e95	227
phungductung	0:e87aa4c49e95	228	hspi->State = HAL_SPI_STATE_BUSY;
phungductung	0:e87aa4c49e95	229
phungductung	0:e87aa4c49e95	230	/* Disable the selected SPI peripheral */
phungductung	0:e87aa4c49e95	231	__HAL_SPI_DISABLE(hspi);
phungductung	0:e87aa4c49e95	232
phungductung	0:e87aa4c49e95	233	/* Align by default the rs fifo threshold on the data size */
phungductung	0:e87aa4c49e95	234	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	235	{
phungductung	0:e87aa4c49e95	236	frxth = SPI_RXFIFO_THRESHOLD_HF;
phungductung	0:e87aa4c49e95	237	}
phungductung	0:e87aa4c49e95	238	else
phungductung	0:e87aa4c49e95	239	{
phungductung	0:e87aa4c49e95	240	frxth = SPI_RXFIFO_THRESHOLD_QF;
phungductung	0:e87aa4c49e95	241	}
phungductung	0:e87aa4c49e95	242
phungductung	0:e87aa4c49e95	243	/* CRC calculation is valid only for 16Bit and 8 Bit */
phungductung	0:e87aa4c49e95	244	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
phungductung	0:e87aa4c49e95	245	{
phungductung	0:e87aa4c49e95	246	/* CRC must be disabled */
phungductung	0:e87aa4c49e95	247	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
phungductung	0:e87aa4c49e95	248	}
phungductung	0:e87aa4c49e95	249
phungductung	0:e87aa4c49e95	250	/* Align the CRC Length on the data size */
phungductung	0:e87aa4c49e95	251	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
phungductung	0:e87aa4c49e95	252	{
phungductung	0:e87aa4c49e95	253	/* CRC Length aligned on the data size : value set by default */
phungductung	0:e87aa4c49e95	254	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	255	{
phungductung	0:e87aa4c49e95	256	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
phungductung	0:e87aa4c49e95	257	}
phungductung	0:e87aa4c49e95	258	else
phungductung	0:e87aa4c49e95	259	{
phungductung	0:e87aa4c49e95	260	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
phungductung	0:e87aa4c49e95	261	}
phungductung	0:e87aa4c49e95	262	}
phungductung	0:e87aa4c49e95	263
phungductung	0:e87aa4c49e95	264	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
phungductung	0:e87aa4c49e95	265	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
phungductung	0:e87aa4c49e95	266	Communication speed, First bit, CRC calculation state, CRC Length */
phungductung	0:e87aa4c49e95	267	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
phungductung	0:e87aa4c49e95	268	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
phungductung	0:e87aa4c49e95	269	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
phungductung	0:e87aa4c49e95	270
phungductung	0:e87aa4c49e95	271	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
phungductung	0:e87aa4c49e95	272	{
phungductung	0:e87aa4c49e95	273	hspi->Instance->CR1\|= SPI_CR1_CRCL;
phungductung	0:e87aa4c49e95	274	}
phungductung	0:e87aa4c49e95	275
phungductung	0:e87aa4c49e95	276	/* Configure : NSS management */
phungductung	0:e87aa4c49e95	277	/* Configure : Rx Fifo Threshold */
phungductung	0:e87aa4c49e95	278	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
phungductung	0:e87aa4c49e95	279	hspi->Init.DataSize ) \| frxth;
phungductung	0:e87aa4c49e95	280
phungductung	0:e87aa4c49e95	281	/---------------------------- SPIx CRCPOLY Configuration --------------------/
phungductung	0:e87aa4c49e95	282	/* Configure : CRC Polynomial */
phungductung	0:e87aa4c49e95	283	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
phungductung	0:e87aa4c49e95	284
phungductung	0:e87aa4c49e95	285	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	286	hspi->State= HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	287
phungductung	0:e87aa4c49e95	288	return HAL_OK;
phungductung	0:e87aa4c49e95	289	}
phungductung	0:e87aa4c49e95	290
phungductung	0:e87aa4c49e95	291	/**
phungductung	0:e87aa4c49e95	292	* @brief DeInitializes the SPI peripheral
phungductung	0:e87aa4c49e95	293	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	294	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	295	* @retval HAL status
phungductung	0:e87aa4c49e95	296	*/
phungductung	0:e87aa4c49e95	297	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	298	{
phungductung	0:e87aa4c49e95	299	/* Check the SPI handle allocation */
phungductung	0:e87aa4c49e95	300	if(hspi == NULL)
phungductung	0:e87aa4c49e95	301	{
phungductung	0:e87aa4c49e95	302	return HAL_ERROR;
phungductung	0:e87aa4c49e95	303	}
phungductung	0:e87aa4c49e95	304
phungductung	0:e87aa4c49e95	305	/* Check the parameters */
phungductung	0:e87aa4c49e95	306	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
phungductung	0:e87aa4c49e95	307
phungductung	0:e87aa4c49e95	308	hspi->State = HAL_SPI_STATE_BUSY;
phungductung	0:e87aa4c49e95	309
phungductung	0:e87aa4c49e95	310	/* check flag before the SPI disable */
phungductung	0:e87aa4c49e95	311	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
phungductung	0:e87aa4c49e95	312	SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
phungductung	0:e87aa4c49e95	313	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
phungductung	0:e87aa4c49e95	314
phungductung	0:e87aa4c49e95	315	/* Disable the SPI Peripheral Clock */
phungductung	0:e87aa4c49e95	316	__HAL_SPI_DISABLE(hspi);
phungductung	0:e87aa4c49e95	317
phungductung	0:e87aa4c49e95	318	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
phungductung	0:e87aa4c49e95	319	HAL_SPI_MspDeInit(hspi);
phungductung	0:e87aa4c49e95	320
phungductung	0:e87aa4c49e95	321	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	322	hspi->State = HAL_SPI_STATE_RESET;
phungductung	0:e87aa4c49e95	323
phungductung	0:e87aa4c49e95	324	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	325
phungductung	0:e87aa4c49e95	326	return HAL_OK;
phungductung	0:e87aa4c49e95	327	}
phungductung	0:e87aa4c49e95	328
phungductung	0:e87aa4c49e95	329	/**
phungductung	0:e87aa4c49e95	330	* @brief SPI MSP Init
phungductung	0:e87aa4c49e95	331	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	332	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	333	* @retval None
phungductung	0:e87aa4c49e95	334	*/
phungductung	0:e87aa4c49e95	335	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	336	{
phungductung	0:e87aa4c49e95	337	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	338	UNUSED(hspi);
phungductung	0:e87aa4c49e95	339
phungductung	0:e87aa4c49e95	340	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	341	the HAL_SPI_MspInit should be implemented in the user file
phungductung	0:e87aa4c49e95	342	*/
phungductung	0:e87aa4c49e95	343	}
phungductung	0:e87aa4c49e95	344
phungductung	0:e87aa4c49e95	345	/**
phungductung	0:e87aa4c49e95	346	* @brief SPI MSP DeInit
phungductung	0:e87aa4c49e95	347	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	348	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	349	* @retval None
phungductung	0:e87aa4c49e95	350	*/
phungductung	0:e87aa4c49e95	351	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	352	{
phungductung	0:e87aa4c49e95	353	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	354	UNUSED(hspi);
phungductung	0:e87aa4c49e95	355
phungductung	0:e87aa4c49e95	356	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	357	the HAL_SPI_MspDeInit should be implemented in the user file
phungductung	0:e87aa4c49e95	358	*/
phungductung	0:e87aa4c49e95	359	}
phungductung	0:e87aa4c49e95	360
phungductung	0:e87aa4c49e95	361	/**
phungductung	0:e87aa4c49e95	362	* @}
phungductung	0:e87aa4c49e95	363	*/
phungductung	0:e87aa4c49e95	364
phungductung	0:e87aa4c49e95	365	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
phungductung	0:e87aa4c49e95	366	* @brief Data transfers functions
phungductung	0:e87aa4c49e95	367	*
phungductung	0:e87aa4c49e95	368	@verbatim
phungductung	0:e87aa4c49e95	369	==============================================================================
phungductung	0:e87aa4c49e95	370	##### IO operation functions #####
phungductung	0:e87aa4c49e95	371	===============================================================================
phungductung	0:e87aa4c49e95	372	This subsection provides a set of functions allowing to manage the SPI
phungductung	0:e87aa4c49e95	373	data transfers.
phungductung	0:e87aa4c49e95	374
phungductung	0:e87aa4c49e95	375	[..] The SPI supports master and slave mode :
phungductung	0:e87aa4c49e95	376
phungductung	0:e87aa4c49e95	377	(#) There are two modes of transfer:
phungductung	0:e87aa4c49e95	378	(++) Blocking mode: The communication is performed in polling mode.
phungductung	0:e87aa4c49e95	379	The HAL status of all data processing is returned by the same function
phungductung	0:e87aa4c49e95	380	after finishing transfer.
phungductung	0:e87aa4c49e95	381	(++) No-Blocking mode: The communication is performed using Interrupts
phungductung	0:e87aa4c49e95	382	or DMA, These APIs return the HAL status.
phungductung	0:e87aa4c49e95	383	The end of the data processing will be indicated through the
phungductung	0:e87aa4c49e95	384	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
phungductung	0:e87aa4c49e95	385	using DMA mode.
phungductung	0:e87aa4c49e95	386	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
phungductung	0:e87aa4c49e95	387	will be executed respectively at the end of the transmit or Receive process
phungductung	0:e87aa4c49e95	388	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
phungductung	0:e87aa4c49e95	389
phungductung	0:e87aa4c49e95	390	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
phungductung	0:e87aa4c49e95	391	exist for 1Line (simplex) and 2Lines (full duplex) modes.
phungductung	0:e87aa4c49e95	392
phungductung	0:e87aa4c49e95	393	@endverbatim
phungductung	0:e87aa4c49e95	394	* @{
phungductung	0:e87aa4c49e95	395	*/
phungductung	0:e87aa4c49e95	396
phungductung	0:e87aa4c49e95	397	/**
phungductung	0:e87aa4c49e95	398	* @brief Transmit an amount of data in blocking mode
phungductung	0:e87aa4c49e95	399	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	400	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	401	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	402	* @param Size: amount of data to be sent
phungductung	0:e87aa4c49e95	403	* @param Timeout: Timeout duration
phungductung	0:e87aa4c49e95	404	* @retval HAL status
phungductung	0:e87aa4c49e95	405	*/
phungductung	0:e87aa4c49e95	406	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
phungductung	0:e87aa4c49e95	407	{
phungductung	0:e87aa4c49e95	408	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	409
phungductung	0:e87aa4c49e95	410	/* Process Locked */
phungductung	0:e87aa4c49e95	411	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	412
phungductung	0:e87aa4c49e95	413	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	414	{
phungductung	0:e87aa4c49e95	415	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	416	/* Process Unlocked */
phungductung	0:e87aa4c49e95	417	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	418	return HAL_BUSY;
phungductung	0:e87aa4c49e95	419	}
phungductung	0:e87aa4c49e95	420
phungductung	0:e87aa4c49e95	421	if((pData == NULL ) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	422	{
phungductung	0:e87aa4c49e95	423	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	424	/* Process Unlocked */
phungductung	0:e87aa4c49e95	425	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	426	return HAL_ERROR;
phungductung	0:e87aa4c49e95	427	}
phungductung	0:e87aa4c49e95	428
phungductung	0:e87aa4c49e95	429	/* Set the transaction information */
phungductung	0:e87aa4c49e95	430	hspi->State = HAL_SPI_STATE_BUSY_TX;
phungductung	0:e87aa4c49e95	431	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	432	hspi->pTxBuffPtr = pData;
phungductung	0:e87aa4c49e95	433	hspi->TxXferSize = Size;
phungductung	0:e87aa4c49e95	434	hspi->TxXferCount = Size;
phungductung	0:e87aa4c49e95	435	hspi->pRxBuffPtr = (uint8_t *)NULL;
phungductung	0:e87aa4c49e95	436	hspi->RxXferSize = 0;
phungductung	0:e87aa4c49e95	437	hspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	438
phungductung	0:e87aa4c49e95	439	/* Configure communication direction : 1Line */
phungductung	0:e87aa4c49e95	440	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:e87aa4c49e95	441	{
phungductung	0:e87aa4c49e95	442	SPI_1LINE_TX(hspi);
phungductung	0:e87aa4c49e95	443	}
phungductung	0:e87aa4c49e95	444
phungductung	0:e87aa4c49e95	445	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	446	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	447	{
phungductung	0:e87aa4c49e95	448	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	449	}
phungductung	0:e87aa4c49e95	450
phungductung	0:e87aa4c49e95	451	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	452	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	453	{
phungductung	0:e87aa4c49e95	454	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	455	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	456	}
phungductung	0:e87aa4c49e95	457
phungductung	0:e87aa4c49e95	458	/* Transmit data in 16 Bit mode */
phungductung	0:e87aa4c49e95	459	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	460	{
phungductung	0:e87aa4c49e95	461	/* Transmit data in 16 Bit mode */
phungductung	0:e87aa4c49e95	462	while (hspi->TxXferCount > 0)
phungductung	0:e87aa4c49e95	463	{
phungductung	0:e87aa4c49e95	464	/* Wait until TXE flag is set to send data */
phungductung	0:e87aa4c49e95	465	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	466	{
phungductung	0:e87aa4c49e95	467	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	468	/* Process Unlocked */
phungductung	0:e87aa4c49e95	469	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	470	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	471	}
phungductung	0:e87aa4c49e95	472	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	473	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	474	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	475	}
phungductung	0:e87aa4c49e95	476	}
phungductung	0:e87aa4c49e95	477	/* Transmit data in 8 Bit mode */
phungductung	0:e87aa4c49e95	478	else
phungductung	0:e87aa4c49e95	479	{
phungductung	0:e87aa4c49e95	480	while (hspi->TxXferCount > 0)
phungductung	0:e87aa4c49e95	481	{
phungductung	0:e87aa4c49e95	482	if(hspi->TxXferCount != 0x1)
phungductung	0:e87aa4c49e95	483	{
phungductung	0:e87aa4c49e95	484	/* Wait until TXE flag is set to send data */
phungductung	0:e87aa4c49e95	485	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	486	{
phungductung	0:e87aa4c49e95	487	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	488	/* Process Unlocked */
phungductung	0:e87aa4c49e95	489	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	490	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	491	}
phungductung	0:e87aa4c49e95	492	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	493	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	494	hspi->TxXferCount -= 2;
phungductung	0:e87aa4c49e95	495	}
phungductung	0:e87aa4c49e95	496	else
phungductung	0:e87aa4c49e95	497	{
phungductung	0:e87aa4c49e95	498	/* Wait until TXE flag is set to send data */
phungductung	0:e87aa4c49e95	499	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	500	{
phungductung	0:e87aa4c49e95	501	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	502	}
phungductung	0:e87aa4c49e95	503	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
phungductung	0:e87aa4c49e95	504	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	505	}
phungductung	0:e87aa4c49e95	506	}
phungductung	0:e87aa4c49e95	507	}
phungductung	0:e87aa4c49e95	508
phungductung	0:e87aa4c49e95	509	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	510	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	511	{
phungductung	0:e87aa4c49e95	512	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	513	}
phungductung	0:e87aa4c49e95	514
phungductung	0:e87aa4c49e95	515	/* Check the end of the transaction */
phungductung	0:e87aa4c49e95	516	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	517	{
phungductung	0:e87aa4c49e95	518	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	519	}
phungductung	0:e87aa4c49e95	520
phungductung	0:e87aa4c49e95	521	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
phungductung	0:e87aa4c49e95	522	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
phungductung	0:e87aa4c49e95	523	{
phungductung	0:e87aa4c49e95	524	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:e87aa4c49e95	525	}
phungductung	0:e87aa4c49e95	526
phungductung	0:e87aa4c49e95	527	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	528
phungductung	0:e87aa4c49e95	529	/* Process Unlocked */
phungductung	0:e87aa4c49e95	530	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	531
phungductung	0:e87aa4c49e95	532	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	533	{
phungductung	0:e87aa4c49e95	534	return HAL_ERROR;
phungductung	0:e87aa4c49e95	535	}
phungductung	0:e87aa4c49e95	536	else
phungductung	0:e87aa4c49e95	537	{
phungductung	0:e87aa4c49e95	538	return HAL_OK;
phungductung	0:e87aa4c49e95	539	}
phungductung	0:e87aa4c49e95	540	}
phungductung	0:e87aa4c49e95	541
phungductung	0:e87aa4c49e95	542	/**
phungductung	0:e87aa4c49e95	543	* @brief Receive an amount of data in blocking mode
phungductung	0:e87aa4c49e95	544	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	545	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	546	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	547	* @param Size: amount of data to be received
phungductung	0:e87aa4c49e95	548	* @param Timeout: Timeout duration
phungductung	0:e87aa4c49e95	549	* @retval HAL status
phungductung	0:e87aa4c49e95	550	*/
phungductung	0:e87aa4c49e95	551	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
phungductung	0:e87aa4c49e95	552	{
phungductung	0:e87aa4c49e95	553	__IO uint16_t tmpreg;
phungductung	0:e87aa4c49e95	554
phungductung	0:e87aa4c49e95	555	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	556	{
phungductung	0:e87aa4c49e95	557	return HAL_BUSY;
phungductung	0:e87aa4c49e95	558	}
phungductung	0:e87aa4c49e95	559
phungductung	0:e87aa4c49e95	560	if((pData == NULL ) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	561	{
phungductung	0:e87aa4c49e95	562	return HAL_ERROR;
phungductung	0:e87aa4c49e95	563	}
phungductung	0:e87aa4c49e95	564
phungductung	0:e87aa4c49e95	565	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
phungductung	0:e87aa4c49e95	566	{
phungductung	0:e87aa4c49e95	567	/* the receive process is not supported in 2Lines direction master mode */
phungductung	0:e87aa4c49e95	568	/* in this case we call the transmitReceive process */
phungductung	0:e87aa4c49e95	569	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
phungductung	0:e87aa4c49e95	570	}
phungductung	0:e87aa4c49e95	571
phungductung	0:e87aa4c49e95	572	/* Process Locked */
phungductung	0:e87aa4c49e95	573	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	574
phungductung	0:e87aa4c49e95	575	hspi->State = HAL_SPI_STATE_BUSY_RX;
phungductung	0:e87aa4c49e95	576	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	577	hspi->pRxBuffPtr = pData;
phungductung	0:e87aa4c49e95	578	hspi->RxXferSize = Size;
phungductung	0:e87aa4c49e95	579	hspi->RxXferCount = Size;
phungductung	0:e87aa4c49e95	580	hspi->pTxBuffPtr = (uint8_t *)NULL;
phungductung	0:e87aa4c49e95	581	hspi->TxXferSize = 0;
phungductung	0:e87aa4c49e95	582	hspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	583
phungductung	0:e87aa4c49e95	584	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	585	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	586	{
phungductung	0:e87aa4c49e95	587	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	588	/* this is done to handle the CRCNEXT before the latest data */
phungductung	0:e87aa4c49e95	589	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	590	}
phungductung	0:e87aa4c49e95	591
phungductung	0:e87aa4c49e95	592	/* Set the Rx Fido threshold */
phungductung	0:e87aa4c49e95	593	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	594	{
phungductung	0:e87aa4c49e95	595	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:e87aa4c49e95	596	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	597	}
phungductung	0:e87aa4c49e95	598	else
phungductung	0:e87aa4c49e95	599	{
phungductung	0:e87aa4c49e95	600	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:e87aa4c49e95	601	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	602	}
phungductung	0:e87aa4c49e95	603
phungductung	0:e87aa4c49e95	604	/* Configure communication direction 1Line and enabled SPI if needed */
phungductung	0:e87aa4c49e95	605	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:e87aa4c49e95	606	{
phungductung	0:e87aa4c49e95	607	SPI_1LINE_RX(hspi);
phungductung	0:e87aa4c49e95	608	}
phungductung	0:e87aa4c49e95	609
phungductung	0:e87aa4c49e95	610	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	611	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	612	{
phungductung	0:e87aa4c49e95	613	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	614	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	615	}
phungductung	0:e87aa4c49e95	616
phungductung	0:e87aa4c49e95	617	/* Receive data in 8 Bit mode */
phungductung	0:e87aa4c49e95	618	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	619	{
phungductung	0:e87aa4c49e95	620	while(hspi->RxXferCount > 1)
phungductung	0:e87aa4c49e95	621	{
phungductung	0:e87aa4c49e95	622	/* Wait until the RXNE flag */
phungductung	0:e87aa4c49e95	623	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	624	{
phungductung	0:e87aa4c49e95	625	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	626	}
phungductung	0:e87aa4c49e95	627	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	628	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	629	}
phungductung	0:e87aa4c49e95	630	}
phungductung	0:e87aa4c49e95	631	else /* Receive data in 16 Bit mode */
phungductung	0:e87aa4c49e95	632	{
phungductung	0:e87aa4c49e95	633	while(hspi->RxXferCount > 1 )
phungductung	0:e87aa4c49e95	634	{
phungductung	0:e87aa4c49e95	635	/* Wait until RXNE flag is reset to read data */
phungductung	0:e87aa4c49e95	636	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	637	{
phungductung	0:e87aa4c49e95	638	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	639	}
phungductung	0:e87aa4c49e95	640	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	641	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	642	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	643	}
phungductung	0:e87aa4c49e95	644	}
phungductung	0:e87aa4c49e95	645
phungductung	0:e87aa4c49e95	646	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	647	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	648	{
phungductung	0:e87aa4c49e95	649	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	650	}
phungductung	0:e87aa4c49e95	651
phungductung	0:e87aa4c49e95	652	/* Wait until RXNE flag is set */
phungductung	0:e87aa4c49e95	653	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	654	{
phungductung	0:e87aa4c49e95	655	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	656	}
phungductung	0:e87aa4c49e95	657
phungductung	0:e87aa4c49e95	658	/* Receive last data in 16 Bit mode */
phungductung	0:e87aa4c49e95	659	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	660	{
phungductung	0:e87aa4c49e95	661	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	662	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	663	}
phungductung	0:e87aa4c49e95	664	/* Receive last data in 8 Bit mode */
phungductung	0:e87aa4c49e95	665	else
phungductung	0:e87aa4c49e95	666	{
phungductung	0:e87aa4c49e95	667	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	668	}
phungductung	0:e87aa4c49e95	669	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	670
phungductung	0:e87aa4c49e95	671	/* Read CRC from DR to close CRC calculation process */
phungductung	0:e87aa4c49e95	672	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	673	{
phungductung	0:e87aa4c49e95	674	/* Wait until TXE flag */
phungductung	0:e87aa4c49e95	675	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	676	{
phungductung	0:e87aa4c49e95	677	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	678	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	679	}
phungductung	0:e87aa4c49e95	680	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	681	{
phungductung	0:e87aa4c49e95	682	tmpreg = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	683	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	684	}
phungductung	0:e87aa4c49e95	685	else
phungductung	0:e87aa4c49e95	686	{
phungductung	0:e87aa4c49e95	687	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	688	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	689
phungductung	0:e87aa4c49e95	690	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
phungductung	0:e87aa4c49e95	691	{
phungductung	0:e87aa4c49e95	692	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	693	{
phungductung	0:e87aa4c49e95	694	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	695	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
phungductung	0:e87aa4c49e95	696	}
phungductung	0:e87aa4c49e95	697	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	698	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	699	}
phungductung	0:e87aa4c49e95	700	}
phungductung	0:e87aa4c49e95	701	}
phungductung	0:e87aa4c49e95	702
phungductung	0:e87aa4c49e95	703	/* Check the end of the transaction */
phungductung	0:e87aa4c49e95	704	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	705	{
phungductung	0:e87aa4c49e95	706	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	707	}
phungductung	0:e87aa4c49e95	708
phungductung	0:e87aa4c49e95	709	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	710
phungductung	0:e87aa4c49e95	711	/* Check if CRC error occurred */
phungductung	0:e87aa4c49e95	712	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:e87aa4c49e95	713	{
phungductung	0:e87aa4c49e95	714	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	715	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:e87aa4c49e95	716
phungductung	0:e87aa4c49e95	717	/* Process Unlocked */
phungductung	0:e87aa4c49e95	718	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	719	return HAL_ERROR;
phungductung	0:e87aa4c49e95	720	}
phungductung	0:e87aa4c49e95	721
phungductung	0:e87aa4c49e95	722	/* Process Unlocked */
phungductung	0:e87aa4c49e95	723	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	724
phungductung	0:e87aa4c49e95	725	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	726	{
phungductung	0:e87aa4c49e95	727	return HAL_ERROR;
phungductung	0:e87aa4c49e95	728	}
phungductung	0:e87aa4c49e95	729	else
phungductung	0:e87aa4c49e95	730	{
phungductung	0:e87aa4c49e95	731	return HAL_OK;
phungductung	0:e87aa4c49e95	732	}
phungductung	0:e87aa4c49e95	733	}
phungductung	0:e87aa4c49e95	734
phungductung	0:e87aa4c49e95	735	/**
phungductung	0:e87aa4c49e95	736	* @brief Transmit and Receive an amount of data in blocking mode
phungductung	0:e87aa4c49e95	737	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	738	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	739	* @param pTxData: pointer to transmission data buffer
phungductung	0:e87aa4c49e95	740	* @param pRxData: pointer to reception data buffer
phungductung	0:e87aa4c49e95	741	* @param Size: amount of data to be sent and received
phungductung	0:e87aa4c49e95	742	* @param Timeout: Timeout duration
phungductung	0:e87aa4c49e95	743	* @retval HAL status
phungductung	0:e87aa4c49e95	744	*/
phungductung	0:e87aa4c49e95	745	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
phungductung	0:e87aa4c49e95	746	{
phungductung	0:e87aa4c49e95	747	__IO uint16_t tmpreg = 0;
phungductung	0:e87aa4c49e95	748	uint32_t tickstart = HAL_GetTick();
phungductung	0:e87aa4c49e95	749
phungductung	0:e87aa4c49e95	750	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	751
phungductung	0:e87aa4c49e95	752	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	753	{
phungductung	0:e87aa4c49e95	754	return HAL_BUSY;
phungductung	0:e87aa4c49e95	755	}
phungductung	0:e87aa4c49e95	756
phungductung	0:e87aa4c49e95	757	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	758	{
phungductung	0:e87aa4c49e95	759	return HAL_ERROR;
phungductung	0:e87aa4c49e95	760	}
phungductung	0:e87aa4c49e95	761
phungductung	0:e87aa4c49e95	762
phungductung	0:e87aa4c49e95	763	/* Process Locked */
phungductung	0:e87aa4c49e95	764	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	765
phungductung	0:e87aa4c49e95	766	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
phungductung	0:e87aa4c49e95	767	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	768	hspi->pRxBuffPtr = pRxData;
phungductung	0:e87aa4c49e95	769	hspi->RxXferCount = Size;
phungductung	0:e87aa4c49e95	770	hspi->RxXferSize = Size;
phungductung	0:e87aa4c49e95	771	hspi->pTxBuffPtr = pTxData;
phungductung	0:e87aa4c49e95	772	hspi->TxXferCount = Size;
phungductung	0:e87aa4c49e95	773	hspi->TxXferSize = Size;
phungductung	0:e87aa4c49e95	774
phungductung	0:e87aa4c49e95	775	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	776	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	777	{
phungductung	0:e87aa4c49e95	778	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	779	}
phungductung	0:e87aa4c49e95	780
phungductung	0:e87aa4c49e95	781	/* Set the Rx Fido threshold */
phungductung	0:e87aa4c49e95	782	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
phungductung	0:e87aa4c49e95	783	{
phungductung	0:e87aa4c49e95	784	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:e87aa4c49e95	785	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	786	}
phungductung	0:e87aa4c49e95	787	else
phungductung	0:e87aa4c49e95	788	{
phungductung	0:e87aa4c49e95	789	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:e87aa4c49e95	790	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	791	}
phungductung	0:e87aa4c49e95	792
phungductung	0:e87aa4c49e95	793	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	794	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	795	{
phungductung	0:e87aa4c49e95	796	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	797	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	798	}
phungductung	0:e87aa4c49e95	799
phungductung	0:e87aa4c49e95	800	/* Transmit and Receive data in 16 Bit mode */
phungductung	0:e87aa4c49e95	801	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	802	{
phungductung	0:e87aa4c49e95	803	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
phungductung	0:e87aa4c49e95	804	{
phungductung	0:e87aa4c49e95	805	/* Check TXE flag */
phungductung	0:e87aa4c49e95	806	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
phungductung	0:e87aa4c49e95	807	{
phungductung	0:e87aa4c49e95	808	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	809	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	810	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	811
phungductung	0:e87aa4c49e95	812	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	813	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:e87aa4c49e95	814	{
phungductung	0:e87aa4c49e95	815	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
phungductung	0:e87aa4c49e95	816	}
phungductung	0:e87aa4c49e95	817	}
phungductung	0:e87aa4c49e95	818
phungductung	0:e87aa4c49e95	819	/* Check RXNE flag */
phungductung	0:e87aa4c49e95	820	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
phungductung	0:e87aa4c49e95	821	{
phungductung	0:e87aa4c49e95	822	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	823	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	824	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	825	}
phungductung	0:e87aa4c49e95	826	if(Timeout != HAL_MAX_DELAY)
phungductung	0:e87aa4c49e95	827	{
phungductung	0:e87aa4c49e95	828	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
phungductung	0:e87aa4c49e95	829	{
phungductung	0:e87aa4c49e95	830	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	831	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	832	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	833	}
phungductung	0:e87aa4c49e95	834	}
phungductung	0:e87aa4c49e95	835	}
phungductung	0:e87aa4c49e95	836	}
phungductung	0:e87aa4c49e95	837	/* Transmit and Receive data in 8 Bit mode */
phungductung	0:e87aa4c49e95	838	else
phungductung	0:e87aa4c49e95	839	{
phungductung	0:e87aa4c49e95	840	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
phungductung	0:e87aa4c49e95	841	{
phungductung	0:e87aa4c49e95	842	/* check TXE flag */
phungductung	0:e87aa4c49e95	843	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
phungductung	0:e87aa4c49e95	844	{
phungductung	0:e87aa4c49e95	845	if(hspi->TxXferCount > 1)
phungductung	0:e87aa4c49e95	846	{
phungductung	0:e87aa4c49e95	847	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	848	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	849	hspi->TxXferCount -= 2;
phungductung	0:e87aa4c49e95	850	}
phungductung	0:e87aa4c49e95	851	else
phungductung	0:e87aa4c49e95	852	{
phungductung	0:e87aa4c49e95	853	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
phungductung	0:e87aa4c49e95	854	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	855	}
phungductung	0:e87aa4c49e95	856
phungductung	0:e87aa4c49e95	857	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	858	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:e87aa4c49e95	859	{
phungductung	0:e87aa4c49e95	860	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
phungductung	0:e87aa4c49e95	861	}
phungductung	0:e87aa4c49e95	862	}
phungductung	0:e87aa4c49e95	863
phungductung	0:e87aa4c49e95	864	/* Wait until RXNE flag is reset */
phungductung	0:e87aa4c49e95	865	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
phungductung	0:e87aa4c49e95	866	{
phungductung	0:e87aa4c49e95	867	if(hspi->RxXferCount > 1)
phungductung	0:e87aa4c49e95	868	{
phungductung	0:e87aa4c49e95	869	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	870	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	871	hspi->RxXferCount -= 2;
phungductung	0:e87aa4c49e95	872	if(hspi->RxXferCount <= 1)
phungductung	0:e87aa4c49e95	873	{
phungductung	0:e87aa4c49e95	874	/* set fiforxthreshold before to switch on 8 bit data size */
phungductung	0:e87aa4c49e95	875	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	876	}
phungductung	0:e87aa4c49e95	877	}
phungductung	0:e87aa4c49e95	878	else
phungductung	0:e87aa4c49e95	879	{
phungductung	0:e87aa4c49e95	880	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	881	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	882	}
phungductung	0:e87aa4c49e95	883	}
phungductung	0:e87aa4c49e95	884	if(Timeout != HAL_MAX_DELAY)
phungductung	0:e87aa4c49e95	885	{
phungductung	0:e87aa4c49e95	886	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
phungductung	0:e87aa4c49e95	887	{
phungductung	0:e87aa4c49e95	888	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	889	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	890	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	891	}
phungductung	0:e87aa4c49e95	892	}
phungductung	0:e87aa4c49e95	893	}
phungductung	0:e87aa4c49e95	894	}
phungductung	0:e87aa4c49e95	895
phungductung	0:e87aa4c49e95	896	/* Read CRC from DR to close CRC calculation process */
phungductung	0:e87aa4c49e95	897	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	898	{
phungductung	0:e87aa4c49e95	899	/* Wait until TXE flag */
phungductung	0:e87aa4c49e95	900	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	901	{
phungductung	0:e87aa4c49e95	902	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	903	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	904	}
phungductung	0:e87aa4c49e95	905
phungductung	0:e87aa4c49e95	906	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
phungductung	0:e87aa4c49e95	907	{
phungductung	0:e87aa4c49e95	908	tmpreg = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	909	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	910	}
phungductung	0:e87aa4c49e95	911	else
phungductung	0:e87aa4c49e95	912	{
phungductung	0:e87aa4c49e95	913	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	914	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	915
phungductung	0:e87aa4c49e95	916	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
phungductung	0:e87aa4c49e95	917	{
phungductung	0:e87aa4c49e95	918	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	919	{
phungductung	0:e87aa4c49e95	920	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	921	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	922	}
phungductung	0:e87aa4c49e95	923	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	924	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	925	}
phungductung	0:e87aa4c49e95	926	}
phungductung	0:e87aa4c49e95	927	}
phungductung	0:e87aa4c49e95	928
phungductung	0:e87aa4c49e95	929	/* Check the end of the transaction */
phungductung	0:e87aa4c49e95	930	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	931	{
phungductung	0:e87aa4c49e95	932	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	933	}
phungductung	0:e87aa4c49e95	934
phungductung	0:e87aa4c49e95	935	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	936
phungductung	0:e87aa4c49e95	937	/* Check if CRC error occurred */
phungductung	0:e87aa4c49e95	938	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:e87aa4c49e95	939	{
phungductung	0:e87aa4c49e95	940	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	941	/* Clear CRC Flag */
phungductung	0:e87aa4c49e95	942	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:e87aa4c49e95	943
phungductung	0:e87aa4c49e95	944	/* Process Unlocked */
phungductung	0:e87aa4c49e95	945	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	946
phungductung	0:e87aa4c49e95	947	return HAL_ERROR;
phungductung	0:e87aa4c49e95	948	}
phungductung	0:e87aa4c49e95	949
phungductung	0:e87aa4c49e95	950	/* Process Unlocked */
phungductung	0:e87aa4c49e95	951	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	952
phungductung	0:e87aa4c49e95	953	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	954	{
phungductung	0:e87aa4c49e95	955	return HAL_ERROR;
phungductung	0:e87aa4c49e95	956	}
phungductung	0:e87aa4c49e95	957	else
phungductung	0:e87aa4c49e95	958	{
phungductung	0:e87aa4c49e95	959	return HAL_OK;
phungductung	0:e87aa4c49e95	960	}
phungductung	0:e87aa4c49e95	961	}
phungductung	0:e87aa4c49e95	962
phungductung	0:e87aa4c49e95	963	/**
phungductung	0:e87aa4c49e95	964	* @brief Transmit an amount of data in no-blocking mode with Interrupt
phungductung	0:e87aa4c49e95	965	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	966	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	967	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	968	* @param Size: amount of data to be sent
phungductung	0:e87aa4c49e95	969	* @retval HAL status
phungductung	0:e87aa4c49e95	970	*/
phungductung	0:e87aa4c49e95	971	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:e87aa4c49e95	972	{
phungductung	0:e87aa4c49e95	973	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	974
phungductung	0:e87aa4c49e95	975	if(hspi->State == HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	976	{
phungductung	0:e87aa4c49e95	977	if((pData == NULL) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	978	{
phungductung	0:e87aa4c49e95	979	return HAL_ERROR;
phungductung	0:e87aa4c49e95	980	}
phungductung	0:e87aa4c49e95	981
phungductung	0:e87aa4c49e95	982	/* Process Locked */
phungductung	0:e87aa4c49e95	983	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	984
phungductung	0:e87aa4c49e95	985	hspi->State = HAL_SPI_STATE_BUSY_TX;
phungductung	0:e87aa4c49e95	986	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	987	hspi->pTxBuffPtr = pData;
phungductung	0:e87aa4c49e95	988	hspi->TxXferSize = Size;
phungductung	0:e87aa4c49e95	989	hspi->TxXferCount = Size;
phungductung	0:e87aa4c49e95	990	hspi->pRxBuffPtr = NULL;
phungductung	0:e87aa4c49e95	991	hspi->RxXferSize = 0;
phungductung	0:e87aa4c49e95	992	hspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	993
phungductung	0:e87aa4c49e95	994	/* Set the function for IT treatement */
phungductung	0:e87aa4c49e95	995	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
phungductung	0:e87aa4c49e95	996	{
phungductung	0:e87aa4c49e95	997	hspi->RxISR = NULL;
phungductung	0:e87aa4c49e95	998	hspi->TxISR = SPI_TxISR_16BIT;
phungductung	0:e87aa4c49e95	999	}
phungductung	0:e87aa4c49e95	1000	else
phungductung	0:e87aa4c49e95	1001	{
phungductung	0:e87aa4c49e95	1002	hspi->RxISR = NULL;
phungductung	0:e87aa4c49e95	1003	hspi->TxISR = SPI_TxISR_8BIT;
phungductung	0:e87aa4c49e95	1004	}
phungductung	0:e87aa4c49e95	1005
phungductung	0:e87aa4c49e95	1006	/* Configure communication direction : 1Line */
phungductung	0:e87aa4c49e95	1007	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:e87aa4c49e95	1008	{
phungductung	0:e87aa4c49e95	1009	SPI_1LINE_TX(hspi);
phungductung	0:e87aa4c49e95	1010	}
phungductung	0:e87aa4c49e95	1011
phungductung	0:e87aa4c49e95	1012	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	1013	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1014	{
phungductung	0:e87aa4c49e95	1015	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	1016	}
phungductung	0:e87aa4c49e95	1017
phungductung	0:e87aa4c49e95	1018	/* Enable TXE and ERR interrupt */
phungductung	0:e87aa4c49e95	1019	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
phungductung	0:e87aa4c49e95	1020
phungductung	0:e87aa4c49e95	1021	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1022	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1023
phungductung	0:e87aa4c49e95	1024	/* Note : The SPI must be enabled after unlocking current process
phungductung	0:e87aa4c49e95	1025	to avoid the risk of SPI interrupt handle execution before current
phungductung	0:e87aa4c49e95	1026	process unlock */
phungductung	0:e87aa4c49e95	1027
phungductung	0:e87aa4c49e95	1028	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	1030	{
phungductung	0:e87aa4c49e95	1031	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	1032	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	1033	}
phungductung	0:e87aa4c49e95	1034
phungductung	0:e87aa4c49e95	1035	return HAL_OK;
phungductung	0:e87aa4c49e95	1036	}
phungductung	0:e87aa4c49e95	1037	else
phungductung	0:e87aa4c49e95	1038	{
phungductung	0:e87aa4c49e95	1039	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1040	}
phungductung	0:e87aa4c49e95	1041	}
phungductung	0:e87aa4c49e95	1042
phungductung	0:e87aa4c49e95	1043	/**
phungductung	0:e87aa4c49e95	1044	* @brief Receive an amount of data in no-blocking mode with Interrupt
phungductung	0:e87aa4c49e95	1045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1046	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1047	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	1048	* @param Size: amount of data to be sent
phungductung	0:e87aa4c49e95	1049	* @retval HAL status
phungductung	0:e87aa4c49e95	1050	*/
phungductung	0:e87aa4c49e95	1051	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:e87aa4c49e95	1052	{
phungductung	0:e87aa4c49e95	1053	if(hspi->State == HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	1054	{
phungductung	0:e87aa4c49e95	1055	if((pData == NULL) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	1056	{
phungductung	0:e87aa4c49e95	1057	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1058	}
phungductung	0:e87aa4c49e95	1059
phungductung	0:e87aa4c49e95	1060	/* Process Locked */
phungductung	0:e87aa4c49e95	1061	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1062
phungductung	0:e87aa4c49e95	1063	/* Configure communication */
phungductung	0:e87aa4c49e95	1064	hspi->State = HAL_SPI_STATE_BUSY_RX;
phungductung	0:e87aa4c49e95	1065	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1066	hspi->pRxBuffPtr = pData;
phungductung	0:e87aa4c49e95	1067	hspi->RxXferSize = Size;
phungductung	0:e87aa4c49e95	1068	hspi->RxXferCount = Size;
phungductung	0:e87aa4c49e95	1069	hspi->pTxBuffPtr = NULL;
phungductung	0:e87aa4c49e95	1070	hspi->TxXferSize = 0;
phungductung	0:e87aa4c49e95	1071	hspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	1072
phungductung	0:e87aa4c49e95	1073	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
phungductung	0:e87aa4c49e95	1074	{
phungductung	0:e87aa4c49e95	1075	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1076	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1077	/* the receive process is not supported in 2Lines direction master mode */
phungductung	0:e87aa4c49e95	1078	/* in this we call the transmitReceive process */
phungductung	0:e87aa4c49e95	1079	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
phungductung	0:e87aa4c49e95	1080	}
phungductung	0:e87aa4c49e95	1081
phungductung	0:e87aa4c49e95	1082	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1083	{
phungductung	0:e87aa4c49e95	1084	hspi->CRCSize = 1;
phungductung	0:e87aa4c49e95	1085	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
phungductung	0:e87aa4c49e95	1086	{
phungductung	0:e87aa4c49e95	1087	hspi->CRCSize = 2;
phungductung	0:e87aa4c49e95	1088	}
phungductung	0:e87aa4c49e95	1089	}
phungductung	0:e87aa4c49e95	1090	else
phungductung	0:e87aa4c49e95	1091	{
phungductung	0:e87aa4c49e95	1092	hspi->CRCSize = 0;
phungductung	0:e87aa4c49e95	1093	}
phungductung	0:e87aa4c49e95	1094
phungductung	0:e87aa4c49e95	1095	/* check the data size to adapt Rx threshold and the set the function for IT treatment */
phungductung	0:e87aa4c49e95	1096	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
phungductung	0:e87aa4c49e95	1097	{
phungductung	0:e87aa4c49e95	1098	/* set fiforxthreshold according the reception data length: 16 bit */
phungductung	0:e87aa4c49e95	1099	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1100	hspi->RxISR = SPI_RxISR_16BIT;
phungductung	0:e87aa4c49e95	1101	hspi->TxISR = NULL;
phungductung	0:e87aa4c49e95	1102	}
phungductung	0:e87aa4c49e95	1103	else
phungductung	0:e87aa4c49e95	1104	{
phungductung	0:e87aa4c49e95	1105	/* set fiforxthreshold according the reception data length: 8 bit */
phungductung	0:e87aa4c49e95	1106	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1107	hspi->RxISR = SPI_RxISR_8BIT;
phungductung	0:e87aa4c49e95	1108	hspi->TxISR = NULL;
phungductung	0:e87aa4c49e95	1109	}
phungductung	0:e87aa4c49e95	1110
phungductung	0:e87aa4c49e95	1111	/* Configure communication direction : 1Line */
phungductung	0:e87aa4c49e95	1112	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:e87aa4c49e95	1113	{
phungductung	0:e87aa4c49e95	1114	SPI_1LINE_RX(hspi);
phungductung	0:e87aa4c49e95	1115	}
phungductung	0:e87aa4c49e95	1116
phungductung	0:e87aa4c49e95	1117	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	1118	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1119	{
phungductung	0:e87aa4c49e95	1120	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	1121	}
phungductung	0:e87aa4c49e95	1122
phungductung	0:e87aa4c49e95	1123	/* Enable TXE and ERR interrupt */
phungductung	0:e87aa4c49e95	1124	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	1125
phungductung	0:e87aa4c49e95	1126	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1127	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1128
phungductung	0:e87aa4c49e95	1129	/* Note : The SPI must be enabled after unlocking current process
phungductung	0:e87aa4c49e95	1130	to avoid the risk of SPI interrupt handle execution before current
phungductung	0:e87aa4c49e95	1131	process unlock */
phungductung	0:e87aa4c49e95	1132
phungductung	0:e87aa4c49e95	1133	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	1134	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	1135	{
phungductung	0:e87aa4c49e95	1136	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	1137	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	1138	}
phungductung	0:e87aa4c49e95	1139
phungductung	0:e87aa4c49e95	1140	return HAL_OK;
phungductung	0:e87aa4c49e95	1141	}
phungductung	0:e87aa4c49e95	1142	else
phungductung	0:e87aa4c49e95	1143	{
phungductung	0:e87aa4c49e95	1144	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1145	}
phungductung	0:e87aa4c49e95	1146	}
phungductung	0:e87aa4c49e95	1147
phungductung	0:e87aa4c49e95	1148	/**
phungductung	0:e87aa4c49e95	1149	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
phungductung	0:e87aa4c49e95	1150	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1151	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1152	* @param pTxData: pointer to transmission data buffer
phungductung	0:e87aa4c49e95	1153	* @param pRxData: pointer to reception data buffer
phungductung	0:e87aa4c49e95	1154	* @param Size: amount of data to be sent and received
phungductung	0:e87aa4c49e95	1155	* @retval HAL status
phungductung	0:e87aa4c49e95	1156	*/
phungductung	0:e87aa4c49e95	1157	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
phungductung	0:e87aa4c49e95	1158	{
phungductung	0:e87aa4c49e95	1159	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	1160
phungductung	0:e87aa4c49e95	1161	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
phungductung	0:e87aa4c49e95	1162	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
phungductung	0:e87aa4c49e95	1163	{
phungductung	0:e87aa4c49e95	1164	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	1165	{
phungductung	0:e87aa4c49e95	1166	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1167	}
phungductung	0:e87aa4c49e95	1168
phungductung	0:e87aa4c49e95	1169	/* Process locked */
phungductung	0:e87aa4c49e95	1170	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1171
phungductung	0:e87aa4c49e95	1172	hspi->CRCSize = 0;
phungductung	0:e87aa4c49e95	1173	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1174	{
phungductung	0:e87aa4c49e95	1175	hspi->CRCSize = 1;
phungductung	0:e87aa4c49e95	1176	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
phungductung	0:e87aa4c49e95	1177	{
phungductung	0:e87aa4c49e95	1178	hspi->CRCSize = 2;
phungductung	0:e87aa4c49e95	1179	}
phungductung	0:e87aa4c49e95	1180	}
phungductung	0:e87aa4c49e95	1181
phungductung	0:e87aa4c49e95	1182	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
phungductung	0:e87aa4c49e95	1183	{
phungductung	0:e87aa4c49e95	1184	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
phungductung	0:e87aa4c49e95	1185	}
phungductung	0:e87aa4c49e95	1186
phungductung	0:e87aa4c49e95	1187	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1188	hspi->pTxBuffPtr = pTxData;
phungductung	0:e87aa4c49e95	1189	hspi->TxXferSize = Size;
phungductung	0:e87aa4c49e95	1190	hspi->TxXferCount = Size;
phungductung	0:e87aa4c49e95	1191	hspi->pRxBuffPtr = pRxData;
phungductung	0:e87aa4c49e95	1192	hspi->RxXferSize = Size;
phungductung	0:e87aa4c49e95	1193	hspi->RxXferCount = Size;
phungductung	0:e87aa4c49e95	1194
phungductung	0:e87aa4c49e95	1195	/* Set the function for IT treatement */
phungductung	0:e87aa4c49e95	1196	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
phungductung	0:e87aa4c49e95	1197	{
phungductung	0:e87aa4c49e95	1198	hspi->RxISR = SPI_2linesRxISR_16BIT;
phungductung	0:e87aa4c49e95	1199	hspi->TxISR = SPI_2linesTxISR_16BIT;
phungductung	0:e87aa4c49e95	1200	}
phungductung	0:e87aa4c49e95	1201	else
phungductung	0:e87aa4c49e95	1202	{
phungductung	0:e87aa4c49e95	1203	hspi->RxISR = SPI_2linesRxISR_8BIT;
phungductung	0:e87aa4c49e95	1204	hspi->TxISR = SPI_2linesTxISR_8BIT;
phungductung	0:e87aa4c49e95	1205	}
phungductung	0:e87aa4c49e95	1206
phungductung	0:e87aa4c49e95	1207	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	1208	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1209	{
phungductung	0:e87aa4c49e95	1210	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	1211	}
phungductung	0:e87aa4c49e95	1212
phungductung	0:e87aa4c49e95	1213	/* check if packing mode is enabled and if there is more than 2 data to receive */
phungductung	0:e87aa4c49e95	1214	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
phungductung	0:e87aa4c49e95	1215	{
phungductung	0:e87aa4c49e95	1216	/* set fiforxthreshold according the reception data length: 16 bit */
phungductung	0:e87aa4c49e95	1217	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1218	}
phungductung	0:e87aa4c49e95	1219	else
phungductung	0:e87aa4c49e95	1220	{
phungductung	0:e87aa4c49e95	1221	/* set fiforxthreshold according the reception data length: 8 bit */
phungductung	0:e87aa4c49e95	1222	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1223	}
phungductung	0:e87aa4c49e95	1224
phungductung	0:e87aa4c49e95	1225	/* Enable TXE, RXNE and ERR interrupt */
phungductung	0:e87aa4c49e95	1226	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	1227
phungductung	0:e87aa4c49e95	1228	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1229	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1230
phungductung	0:e87aa4c49e95	1231	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	1232	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	1233	{
phungductung	0:e87aa4c49e95	1234	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	1235	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	1236	}
phungductung	0:e87aa4c49e95	1237
phungductung	0:e87aa4c49e95	1238	return HAL_OK;
phungductung	0:e87aa4c49e95	1239	}
phungductung	0:e87aa4c49e95	1240	else
phungductung	0:e87aa4c49e95	1241	{
phungductung	0:e87aa4c49e95	1242	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1243	}
phungductung	0:e87aa4c49e95	1244	}
phungductung	0:e87aa4c49e95	1245
phungductung	0:e87aa4c49e95	1246	/**
phungductung	0:e87aa4c49e95	1247	* @brief Transmit an amount of data in no-blocking mode with DMA
phungductung	0:e87aa4c49e95	1248	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1249	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1250	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	1251	* @param Size: amount of data to be sent
phungductung	0:e87aa4c49e95	1252	* @retval HAL status
phungductung	0:e87aa4c49e95	1253	*/
phungductung	0:e87aa4c49e95	1254	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:e87aa4c49e95	1255	{
phungductung	0:e87aa4c49e95	1256	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	1257
phungductung	0:e87aa4c49e95	1258	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	1259	{
phungductung	0:e87aa4c49e95	1260	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1261	}
phungductung	0:e87aa4c49e95	1262
phungductung	0:e87aa4c49e95	1263	if((pData == NULL) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	1264	{
phungductung	0:e87aa4c49e95	1265	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1266	}
phungductung	0:e87aa4c49e95	1267
phungductung	0:e87aa4c49e95	1268	/* Process Locked */
phungductung	0:e87aa4c49e95	1269	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1270
phungductung	0:e87aa4c49e95	1271	hspi->State = HAL_SPI_STATE_BUSY_TX;
phungductung	0:e87aa4c49e95	1272	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1273	hspi->pTxBuffPtr = pData;
phungductung	0:e87aa4c49e95	1274	hspi->TxXferSize = Size;
phungductung	0:e87aa4c49e95	1275	hspi->TxXferCount = Size;
phungductung	0:e87aa4c49e95	1276	hspi->pRxBuffPtr = (uint8_t *)NULL;
phungductung	0:e87aa4c49e95	1277	hspi->RxXferSize = 0;
phungductung	0:e87aa4c49e95	1278	hspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	1279
phungductung	0:e87aa4c49e95	1280	/* Configure communication direction : 1Line */
phungductung	0:e87aa4c49e95	1281	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:e87aa4c49e95	1282	{
phungductung	0:e87aa4c49e95	1283	SPI_1LINE_TX(hspi);
phungductung	0:e87aa4c49e95	1284	}
phungductung	0:e87aa4c49e95	1285
phungductung	0:e87aa4c49e95	1286	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	1287	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1288	{
phungductung	0:e87aa4c49e95	1289	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	1290	}
phungductung	0:e87aa4c49e95	1291
phungductung	0:e87aa4c49e95	1292	/* Set the SPI TxDMA Half transfer complete callback */
phungductung	0:e87aa4c49e95	1293	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
phungductung	0:e87aa4c49e95	1294
phungductung	0:e87aa4c49e95	1295	/* Set the SPI TxDMA transfer complete callback */
phungductung	0:e87aa4c49e95	1296	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
phungductung	0:e87aa4c49e95	1297
phungductung	0:e87aa4c49e95	1298	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1299	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
phungductung	0:e87aa4c49e95	1300
phungductung	0:e87aa4c49e95	1301	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:e87aa4c49e95	1302	/* packing mode is enabled only if the DMA setting is HALWORD */
phungductung	0:e87aa4c49e95	1303	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
phungductung	0:e87aa4c49e95	1304	{
phungductung	0:e87aa4c49e95	1305	/* Check the even/odd of the data size + crc if enabled */
phungductung	0:e87aa4c49e95	1306	if((hspi->TxXferCount & 0x1) == 0)
phungductung	0:e87aa4c49e95	1307	{
phungductung	0:e87aa4c49e95	1308	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:e87aa4c49e95	1309	hspi->TxXferCount = (hspi->TxXferCount >> 1);
phungductung	0:e87aa4c49e95	1310	}
phungductung	0:e87aa4c49e95	1311	else
phungductung	0:e87aa4c49e95	1312	{
phungductung	0:e87aa4c49e95	1313	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:e87aa4c49e95	1314	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
phungductung	0:e87aa4c49e95	1315	}
phungductung	0:e87aa4c49e95	1316	}
phungductung	0:e87aa4c49e95	1317
phungductung	0:e87aa4c49e95	1318	/* Enable the Tx DMA channel */
phungductung	0:e87aa4c49e95	1319	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
phungductung	0:e87aa4c49e95	1320
phungductung	0:e87aa4c49e95	1321	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	1322	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	1323	{
phungductung	0:e87aa4c49e95	1324	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	1325	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	1326	}
phungductung	0:e87aa4c49e95	1327
phungductung	0:e87aa4c49e95	1328	/* Enable Tx DMA Request */
phungductung	0:e87aa4c49e95	1329	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
phungductung	0:e87aa4c49e95	1330
phungductung	0:e87aa4c49e95	1331	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1332	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1333
phungductung	0:e87aa4c49e95	1334	return HAL_OK;
phungductung	0:e87aa4c49e95	1335	}
phungductung	0:e87aa4c49e95	1336
phungductung	0:e87aa4c49e95	1337	/**
phungductung	0:e87aa4c49e95	1338	* @brief Receive an amount of data in no-blocking mode with DMA
phungductung	0:e87aa4c49e95	1339	* @param hspi: SPI handle
phungductung	0:e87aa4c49e95	1340	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	1341	* @param Size: amount of data to be sent
phungductung	0:e87aa4c49e95	1342	* @retval HAL status
phungductung	0:e87aa4c49e95	1343	*/
phungductung	0:e87aa4c49e95	1344	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:e87aa4c49e95	1345	{
phungductung	0:e87aa4c49e95	1346	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:e87aa4c49e95	1347	{
phungductung	0:e87aa4c49e95	1348	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1349	}
phungductung	0:e87aa4c49e95	1350
phungductung	0:e87aa4c49e95	1351	if((pData == NULL) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	1352	{
phungductung	0:e87aa4c49e95	1353	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1354	}
phungductung	0:e87aa4c49e95	1355
phungductung	0:e87aa4c49e95	1356	/* Process Locked */
phungductung	0:e87aa4c49e95	1357	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1358
phungductung	0:e87aa4c49e95	1359	hspi->State = HAL_SPI_STATE_BUSY_RX;
phungductung	0:e87aa4c49e95	1360	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1361	hspi->pRxBuffPtr = pData;
phungductung	0:e87aa4c49e95	1362	hspi->RxXferSize = Size;
phungductung	0:e87aa4c49e95	1363	hspi->RxXferCount = Size;
phungductung	0:e87aa4c49e95	1364	hspi->pTxBuffPtr = (uint8_t *)NULL;
phungductung	0:e87aa4c49e95	1365	hspi->TxXferSize = 0;
phungductung	0:e87aa4c49e95	1366	hspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	1367
phungductung	0:e87aa4c49e95	1368	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
phungductung	0:e87aa4c49e95	1369	{
phungductung	0:e87aa4c49e95	1370	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1371	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1372	/* the receive process is not supported in 2Lines direction master mode */
phungductung	0:e87aa4c49e95	1373	/* in this case we call the transmitReceive process */
phungductung	0:e87aa4c49e95	1374	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
phungductung	0:e87aa4c49e95	1375	}
phungductung	0:e87aa4c49e95	1376
phungductung	0:e87aa4c49e95	1377	/* Configure communication direction : 1Line */
phungductung	0:e87aa4c49e95	1378	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:e87aa4c49e95	1379	{
phungductung	0:e87aa4c49e95	1380	SPI_1LINE_RX(hspi);
phungductung	0:e87aa4c49e95	1381	}
phungductung	0:e87aa4c49e95	1382
phungductung	0:e87aa4c49e95	1383	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	1384	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1385	{
phungductung	0:e87aa4c49e95	1386	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	1387	}
phungductung	0:e87aa4c49e95	1388
phungductung	0:e87aa4c49e95	1389	/* packing mode management is enabled by the DMA settings */
phungductung	0:e87aa4c49e95	1390	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
phungductung	0:e87aa4c49e95	1391	{
phungductung	0:e87aa4c49e95	1392	/* Process Locked */
phungductung	0:e87aa4c49e95	1393	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1394	/* Restriction the DMA data received is not allowed in this mode */
phungductung	0:e87aa4c49e95	1395	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1396	}
phungductung	0:e87aa4c49e95	1397
phungductung	0:e87aa4c49e95	1398	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:e87aa4c49e95	1399	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	1400	{
phungductung	0:e87aa4c49e95	1401	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:e87aa4c49e95	1402	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1403	}
phungductung	0:e87aa4c49e95	1404	else
phungductung	0:e87aa4c49e95	1405	{
phungductung	0:e87aa4c49e95	1406	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:e87aa4c49e95	1407	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1408	}
phungductung	0:e87aa4c49e95	1409
phungductung	0:e87aa4c49e95	1410	/* Set the SPI RxDMA Half transfer complete callback */
phungductung	0:e87aa4c49e95	1411	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
phungductung	0:e87aa4c49e95	1412
phungductung	0:e87aa4c49e95	1413	/* Set the SPI Rx DMA transfer complete callback */
phungductung	0:e87aa4c49e95	1414	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
phungductung	0:e87aa4c49e95	1415
phungductung	0:e87aa4c49e95	1416	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1417	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
phungductung	0:e87aa4c49e95	1418
phungductung	0:e87aa4c49e95	1419	/* Enable Rx DMA Request */
phungductung	0:e87aa4c49e95	1420	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
phungductung	0:e87aa4c49e95	1421
phungductung	0:e87aa4c49e95	1422	/* Enable the Rx DMA channel */
phungductung	0:e87aa4c49e95	1423	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
phungductung	0:e87aa4c49e95	1424
phungductung	0:e87aa4c49e95	1425	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1426	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1427
phungductung	0:e87aa4c49e95	1428	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	1429	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	1430	{
phungductung	0:e87aa4c49e95	1431	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	1432	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	1433	}
phungductung	0:e87aa4c49e95	1434
phungductung	0:e87aa4c49e95	1435	return HAL_OK;
phungductung	0:e87aa4c49e95	1436	}
phungductung	0:e87aa4c49e95	1437
phungductung	0:e87aa4c49e95	1438	/**
phungductung	0:e87aa4c49e95	1439	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
phungductung	0:e87aa4c49e95	1440	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1441	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1442	* @param pTxData: pointer to transmission data buffer
phungductung	0:e87aa4c49e95	1443	* @param pRxData: pointer to reception data buffer
phungductung	0:e87aa4c49e95	1444	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
phungductung	0:e87aa4c49e95	1445	* @param Size: amount of data to be sent
phungductung	0:e87aa4c49e95	1446	* @retval HAL status
phungductung	0:e87aa4c49e95	1447	*/
phungductung	0:e87aa4c49e95	1448	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
phungductung	0:e87aa4c49e95	1449	{
phungductung	0:e87aa4c49e95	1450	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
phungductung	0:e87aa4c49e95	1451
phungductung	0:e87aa4c49e95	1452	if((hspi->State == HAL_SPI_STATE_READY) \|\|
phungductung	0:e87aa4c49e95	1453	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
phungductung	0:e87aa4c49e95	1454	{
phungductung	0:e87aa4c49e95	1455	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
phungductung	0:e87aa4c49e95	1456	{
phungductung	0:e87aa4c49e95	1457	return HAL_ERROR;
phungductung	0:e87aa4c49e95	1458	}
phungductung	0:e87aa4c49e95	1459
phungductung	0:e87aa4c49e95	1460	/* Process locked */
phungductung	0:e87aa4c49e95	1461	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1462
phungductung	0:e87aa4c49e95	1463	/* check if the transmit Receive function is not called by a receive master */
phungductung	0:e87aa4c49e95	1464	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
phungductung	0:e87aa4c49e95	1465	{
phungductung	0:e87aa4c49e95	1466	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
phungductung	0:e87aa4c49e95	1467	}
phungductung	0:e87aa4c49e95	1468
phungductung	0:e87aa4c49e95	1469	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1470	hspi->pTxBuffPtr = (uint8_t *)pTxData;
phungductung	0:e87aa4c49e95	1471	hspi->TxXferSize = Size;
phungductung	0:e87aa4c49e95	1472	hspi->TxXferCount = Size;
phungductung	0:e87aa4c49e95	1473	hspi->pRxBuffPtr = (uint8_t *)pRxData;
phungductung	0:e87aa4c49e95	1474	hspi->RxXferSize = Size;
phungductung	0:e87aa4c49e95	1475	hspi->RxXferCount = Size;
phungductung	0:e87aa4c49e95	1476
phungductung	0:e87aa4c49e95	1477	/* Reset CRC Calculation + increase the rxsize */
phungductung	0:e87aa4c49e95	1478	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1479	{
phungductung	0:e87aa4c49e95	1480	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	1481	}
phungductung	0:e87aa4c49e95	1482
phungductung	0:e87aa4c49e95	1483	/* Reset the threshold bit */
phungductung	0:e87aa4c49e95	1484	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:e87aa4c49e95	1485	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:e87aa4c49e95	1486
phungductung	0:e87aa4c49e95	1487	/* the packing mode management is enabled by the DMA settings according the spi data size */
phungductung	0:e87aa4c49e95	1488	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	1489	{
phungductung	0:e87aa4c49e95	1490	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:e87aa4c49e95	1491	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1492	}
phungductung	0:e87aa4c49e95	1493	else
phungductung	0:e87aa4c49e95	1494	{
phungductung	0:e87aa4c49e95	1495	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:e87aa4c49e95	1496	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1497
phungductung	0:e87aa4c49e95	1498	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
phungductung	0:e87aa4c49e95	1499	{
phungductung	0:e87aa4c49e95	1500	if((hspi->TxXferSize & 0x1) == 0x0 )
phungductung	0:e87aa4c49e95	1501	{
phungductung	0:e87aa4c49e95	1502	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:e87aa4c49e95	1503	hspi->TxXferCount = hspi->TxXferCount >> 1;
phungductung	0:e87aa4c49e95	1504	}
phungductung	0:e87aa4c49e95	1505	else
phungductung	0:e87aa4c49e95	1506	{
phungductung	0:e87aa4c49e95	1507	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:e87aa4c49e95	1508	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
phungductung	0:e87aa4c49e95	1509	}
phungductung	0:e87aa4c49e95	1510	}
phungductung	0:e87aa4c49e95	1511
phungductung	0:e87aa4c49e95	1512	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
phungductung	0:e87aa4c49e95	1513	{
phungductung	0:e87aa4c49e95	1514	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:e87aa4c49e95	1515	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	1516
phungductung	0:e87aa4c49e95	1517	/* Size must include the CRC length */
phungductung	0:e87aa4c49e95	1518	if((hspi->RxXferCount & 0x1) == 0x0 )
phungductung	0:e87aa4c49e95	1519	{
phungductung	0:e87aa4c49e95	1520	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:e87aa4c49e95	1521	hspi->RxXferCount = hspi->RxXferCount >> 1;
phungductung	0:e87aa4c49e95	1522	}
phungductung	0:e87aa4c49e95	1523	else
phungductung	0:e87aa4c49e95	1524	{
phungductung	0:e87aa4c49e95	1525	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:e87aa4c49e95	1526	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
phungductung	0:e87aa4c49e95	1527	}
phungductung	0:e87aa4c49e95	1528	}
phungductung	0:e87aa4c49e95	1529	}
phungductung	0:e87aa4c49e95	1530
phungductung	0:e87aa4c49e95	1531	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
phungductung	0:e87aa4c49e95	1532	the reception request (RXNE) */
phungductung	0:e87aa4c49e95	1533	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
phungductung	0:e87aa4c49e95	1534	{
phungductung	0:e87aa4c49e95	1535	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
phungductung	0:e87aa4c49e95	1536	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
phungductung	0:e87aa4c49e95	1537	}
phungductung	0:e87aa4c49e95	1538	else
phungductung	0:e87aa4c49e95	1539	{
phungductung	0:e87aa4c49e95	1540	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
phungductung	0:e87aa4c49e95	1541	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
phungductung	0:e87aa4c49e95	1542	}
phungductung	0:e87aa4c49e95	1543	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1544	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
phungductung	0:e87aa4c49e95	1545
phungductung	0:e87aa4c49e95	1546	/* Enable Rx DMA Request */
phungductung	0:e87aa4c49e95	1547	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
phungductung	0:e87aa4c49e95	1548
phungductung	0:e87aa4c49e95	1549	/* Enable the Rx DMA channel */
phungductung	0:e87aa4c49e95	1550	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
phungductung	0:e87aa4c49e95	1551
phungductung	0:e87aa4c49e95	1552	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
phungductung	0:e87aa4c49e95	1553	is performed in DMA reception complete callback */
phungductung	0:e87aa4c49e95	1554	hspi->hdmatx->XferHalfCpltCallback = NULL;
phungductung	0:e87aa4c49e95	1555	hspi->hdmatx->XferCpltCallback = NULL;
phungductung	0:e87aa4c49e95	1556
phungductung	0:e87aa4c49e95	1557	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
phungductung	0:e87aa4c49e95	1558	{
phungductung	0:e87aa4c49e95	1559	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1560	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
phungductung	0:e87aa4c49e95	1561	}
phungductung	0:e87aa4c49e95	1562	else
phungductung	0:e87aa4c49e95	1563	{
phungductung	0:e87aa4c49e95	1564	hspi->hdmatx->XferErrorCallback = NULL;
phungductung	0:e87aa4c49e95	1565	}
phungductung	0:e87aa4c49e95	1566
phungductung	0:e87aa4c49e95	1567	/* Enable the Tx DMA channel */
phungductung	0:e87aa4c49e95	1568	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
phungductung	0:e87aa4c49e95	1569
phungductung	0:e87aa4c49e95	1570	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1571	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1572
phungductung	0:e87aa4c49e95	1573	/* Check if the SPI is already enabled */
phungductung	0:e87aa4c49e95	1574	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:e87aa4c49e95	1575	{
phungductung	0:e87aa4c49e95	1576	/* Enable SPI peripheral */
phungductung	0:e87aa4c49e95	1577	__HAL_SPI_ENABLE(hspi);
phungductung	0:e87aa4c49e95	1578	}
phungductung	0:e87aa4c49e95	1579
phungductung	0:e87aa4c49e95	1580	/* Enable Tx DMA Request */
phungductung	0:e87aa4c49e95	1581	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
phungductung	0:e87aa4c49e95	1582
phungductung	0:e87aa4c49e95	1583	return HAL_OK;
phungductung	0:e87aa4c49e95	1584	}
phungductung	0:e87aa4c49e95	1585	else
phungductung	0:e87aa4c49e95	1586	{
phungductung	0:e87aa4c49e95	1587	return HAL_BUSY;
phungductung	0:e87aa4c49e95	1588	}
phungductung	0:e87aa4c49e95	1589	}
phungductung	0:e87aa4c49e95	1590
phungductung	0:e87aa4c49e95	1591	/**
phungductung	0:e87aa4c49e95	1592	* @brief Pauses the DMA Transfer.
phungductung	0:e87aa4c49e95	1593	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1594	* the configuration information for the specified SPI module.
phungductung	0:e87aa4c49e95	1595	* @retval HAL status
phungductung	0:e87aa4c49e95	1596	*/
phungductung	0:e87aa4c49e95	1597	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1598	{
phungductung	0:e87aa4c49e95	1599	/* Process Locked */
phungductung	0:e87aa4c49e95	1600	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1601
phungductung	0:e87aa4c49e95	1602	/* Disable the SPI DMA Tx & Rx requests */
phungductung	0:e87aa4c49e95	1603	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:e87aa4c49e95	1604
phungductung	0:e87aa4c49e95	1605	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1606	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1607
phungductung	0:e87aa4c49e95	1608	return HAL_OK;
phungductung	0:e87aa4c49e95	1609	}
phungductung	0:e87aa4c49e95	1610
phungductung	0:e87aa4c49e95	1611	/**
phungductung	0:e87aa4c49e95	1612	* @brief Resumes the DMA Transfer.
phungductung	0:e87aa4c49e95	1613	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1614	* the configuration information for the specified SPI module.
phungductung	0:e87aa4c49e95	1615	* @retval HAL status
phungductung	0:e87aa4c49e95	1616	*/
phungductung	0:e87aa4c49e95	1617	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1618	{
phungductung	0:e87aa4c49e95	1619	/* Process Locked */
phungductung	0:e87aa4c49e95	1620	__HAL_LOCK(hspi);
phungductung	0:e87aa4c49e95	1621
phungductung	0:e87aa4c49e95	1622	/* Enable the SPI DMA Tx & Rx requests */
phungductung	0:e87aa4c49e95	1623	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:e87aa4c49e95	1624
phungductung	0:e87aa4c49e95	1625	/* Process Unlocked */
phungductung	0:e87aa4c49e95	1626	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	1627
phungductung	0:e87aa4c49e95	1628	return HAL_OK;
phungductung	0:e87aa4c49e95	1629	}
phungductung	0:e87aa4c49e95	1630
phungductung	0:e87aa4c49e95	1631	/**
phungductung	0:e87aa4c49e95	1632	* @brief Stops the DMA Transfer.
phungductung	0:e87aa4c49e95	1633	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1634	* the configuration information for the specified SPI module.
phungductung	0:e87aa4c49e95	1635	* @retval HAL status
phungductung	0:e87aa4c49e95	1636	*/
phungductung	0:e87aa4c49e95	1637	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1638	{
phungductung	0:e87aa4c49e95	1639	/* The Lock is not implemented on this API to allow the user application
phungductung	0:e87aa4c49e95	1640	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
phungductung	0:e87aa4c49e95	1641	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
phungductung	0:e87aa4c49e95	1642	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
phungductung	0:e87aa4c49e95	1643	*/
phungductung	0:e87aa4c49e95	1644
phungductung	0:e87aa4c49e95	1645	/* Abort the SPI DMA tx Stream */
phungductung	0:e87aa4c49e95	1646	if(hspi->hdmatx != NULL)
phungductung	0:e87aa4c49e95	1647	{
phungductung	0:e87aa4c49e95	1648	HAL_DMA_Abort(hspi->hdmatx);
phungductung	0:e87aa4c49e95	1649	}
phungductung	0:e87aa4c49e95	1650	/* Abort the SPI DMA rx Stream */
phungductung	0:e87aa4c49e95	1651	if(hspi->hdmarx != NULL)
phungductung	0:e87aa4c49e95	1652	{
phungductung	0:e87aa4c49e95	1653	HAL_DMA_Abort(hspi->hdmarx);
phungductung	0:e87aa4c49e95	1654	}
phungductung	0:e87aa4c49e95	1655
phungductung	0:e87aa4c49e95	1656	/* Disable the SPI DMA Tx & Rx requests */
phungductung	0:e87aa4c49e95	1657	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:e87aa4c49e95	1658	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	1659	return HAL_OK;
phungductung	0:e87aa4c49e95	1660	}
phungductung	0:e87aa4c49e95	1661
phungductung	0:e87aa4c49e95	1662	/**
phungductung	0:e87aa4c49e95	1663	* @brief This function handles SPI interrupt request.
phungductung	0:e87aa4c49e95	1664	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1665	* the configuration information for the specified SPI module.
phungductung	0:e87aa4c49e95	1666	* @retval None
phungductung	0:e87aa4c49e95	1667	*/
phungductung	0:e87aa4c49e95	1668	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1669	{
phungductung	0:e87aa4c49e95	1670	/* SPI in mode Receiver ----------------------------------------------------*/
phungductung	0:e87aa4c49e95	1671	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
phungductung	0:e87aa4c49e95	1672	(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
phungductung	0:e87aa4c49e95	1673	{
phungductung	0:e87aa4c49e95	1674	hspi->RxISR(hspi);
phungductung	0:e87aa4c49e95	1675	return;
phungductung	0:e87aa4c49e95	1676	}
phungductung	0:e87aa4c49e95	1677
phungductung	0:e87aa4c49e95	1678	/* SPI in mode Transmitter ---------------------------------------------------*/
phungductung	0:e87aa4c49e95	1679	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
phungductung	0:e87aa4c49e95	1680	{
phungductung	0:e87aa4c49e95	1681	hspi->TxISR(hspi);
phungductung	0:e87aa4c49e95	1682	return;
phungductung	0:e87aa4c49e95	1683	}
phungductung	0:e87aa4c49e95	1684
phungductung	0:e87aa4c49e95	1685	/* SPI in ERROR Treatment ---------------------------------------------------*/
phungductung	0:e87aa4c49e95	1686	if((hspi->Instance->SR & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
phungductung	0:e87aa4c49e95	1687	{
phungductung	0:e87aa4c49e95	1688	/* SPI Overrun error interrupt occurred -------------------------------------*/
phungductung	0:e87aa4c49e95	1689	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
phungductung	0:e87aa4c49e95	1690	{
phungductung	0:e87aa4c49e95	1691	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
phungductung	0:e87aa4c49e95	1692	{
phungductung	0:e87aa4c49e95	1693	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
phungductung	0:e87aa4c49e95	1694	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:e87aa4c49e95	1695	}
phungductung	0:e87aa4c49e95	1696	else
phungductung	0:e87aa4c49e95	1697	{
phungductung	0:e87aa4c49e95	1698	return;
phungductung	0:e87aa4c49e95	1699	}
phungductung	0:e87aa4c49e95	1700	}
phungductung	0:e87aa4c49e95	1701
phungductung	0:e87aa4c49e95	1702	/* SPI Mode Fault error interrupt occurred -------------------------------------*/
phungductung	0:e87aa4c49e95	1703	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
phungductung	0:e87aa4c49e95	1704	{
phungductung	0:e87aa4c49e95	1705	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
phungductung	0:e87aa4c49e95	1706	__HAL_SPI_CLEAR_MODFFLAG(hspi);
phungductung	0:e87aa4c49e95	1707	}
phungductung	0:e87aa4c49e95	1708
phungductung	0:e87aa4c49e95	1709	/* SPI Frame error interrupt occurred ----------------------------------------*/
phungductung	0:e87aa4c49e95	1710	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
phungductung	0:e87aa4c49e95	1711	{
phungductung	0:e87aa4c49e95	1712	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
phungductung	0:e87aa4c49e95	1713	__HAL_SPI_CLEAR_FREFLAG(hspi);
phungductung	0:e87aa4c49e95	1714	}
phungductung	0:e87aa4c49e95	1715
phungductung	0:e87aa4c49e95	1716	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
phungductung	0:e87aa4c49e95	1717	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	1718	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	1719
phungductung	0:e87aa4c49e95	1720	return;
phungductung	0:e87aa4c49e95	1721	}
phungductung	0:e87aa4c49e95	1722	}
phungductung	0:e87aa4c49e95	1723
phungductung	0:e87aa4c49e95	1724	/**
phungductung	0:e87aa4c49e95	1725	* @brief Tx Transfer completed callback
phungductung	0:e87aa4c49e95	1726	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1727	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1728	* @retval None
phungductung	0:e87aa4c49e95	1729	*/
phungductung	0:e87aa4c49e95	1730	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1731	{
phungductung	0:e87aa4c49e95	1732	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1733	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1734
phungductung	0:e87aa4c49e95	1735	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1736	the HAL_SPI_TxCpltCallback should be implemented in the user file
phungductung	0:e87aa4c49e95	1737	*/
phungductung	0:e87aa4c49e95	1738	}
phungductung	0:e87aa4c49e95	1739
phungductung	0:e87aa4c49e95	1740	/**
phungductung	0:e87aa4c49e95	1741	* @brief Rx Transfer completed callbacks
phungductung	0:e87aa4c49e95	1742	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1743	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1744	* @retval None
phungductung	0:e87aa4c49e95	1745	*/
phungductung	0:e87aa4c49e95	1746	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1747	{
phungductung	0:e87aa4c49e95	1748	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1749	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1750
phungductung	0:e87aa4c49e95	1751	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1752	the HAL_SPI_RxCpltCallback should be implemented in the user file
phungductung	0:e87aa4c49e95	1753	*/
phungductung	0:e87aa4c49e95	1754	}
phungductung	0:e87aa4c49e95	1755
phungductung	0:e87aa4c49e95	1756	/**
phungductung	0:e87aa4c49e95	1757	* @brief Tx and Rx Transfer completed callback
phungductung	0:e87aa4c49e95	1758	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1759	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1760	* @retval None
phungductung	0:e87aa4c49e95	1761	*/
phungductung	0:e87aa4c49e95	1762	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1763	{
phungductung	0:e87aa4c49e95	1764	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1765	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1766
phungductung	0:e87aa4c49e95	1767	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1768	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
phungductung	0:e87aa4c49e95	1769	*/
phungductung	0:e87aa4c49e95	1770	}
phungductung	0:e87aa4c49e95	1771
phungductung	0:e87aa4c49e95	1772	/**
phungductung	0:e87aa4c49e95	1773	* @brief Tx Half Transfer completed callback
phungductung	0:e87aa4c49e95	1774	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1775	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1776	* @retval None
phungductung	0:e87aa4c49e95	1777	*/
phungductung	0:e87aa4c49e95	1778	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1779	{
phungductung	0:e87aa4c49e95	1780	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1781	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1782
phungductung	0:e87aa4c49e95	1783	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1784	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
phungductung	0:e87aa4c49e95	1785	*/
phungductung	0:e87aa4c49e95	1786	}
phungductung	0:e87aa4c49e95	1787
phungductung	0:e87aa4c49e95	1788	/**
phungductung	0:e87aa4c49e95	1789	* @brief Rx Half Transfer completed callback
phungductung	0:e87aa4c49e95	1790	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1791	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1792	* @retval None
phungductung	0:e87aa4c49e95	1793	*/
phungductung	0:e87aa4c49e95	1794	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1795	{
phungductung	0:e87aa4c49e95	1796	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1797	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1798
phungductung	0:e87aa4c49e95	1799	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1800	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
phungductung	0:e87aa4c49e95	1801	*/
phungductung	0:e87aa4c49e95	1802	}
phungductung	0:e87aa4c49e95	1803
phungductung	0:e87aa4c49e95	1804	/**
phungductung	0:e87aa4c49e95	1805	* @brief Tx and Rx Half Transfer callback
phungductung	0:e87aa4c49e95	1806	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1807	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1808	* @retval None
phungductung	0:e87aa4c49e95	1809	*/
phungductung	0:e87aa4c49e95	1810	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1811	{
phungductung	0:e87aa4c49e95	1812	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1813	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1814
phungductung	0:e87aa4c49e95	1815	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1816	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
phungductung	0:e87aa4c49e95	1817	*/
phungductung	0:e87aa4c49e95	1818	}
phungductung	0:e87aa4c49e95	1819
phungductung	0:e87aa4c49e95	1820	/**
phungductung	0:e87aa4c49e95	1821	* @brief SPI error callback
phungductung	0:e87aa4c49e95	1822	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1823	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1824	* @retval None
phungductung	0:e87aa4c49e95	1825	*/
phungductung	0:e87aa4c49e95	1826	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1827	{
phungductung	0:e87aa4c49e95	1828	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1829	UNUSED(hspi);
phungductung	0:e87aa4c49e95	1830
phungductung	0:e87aa4c49e95	1831	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1832	the HAL_SPI_ErrorCallback should be implemented in the user file
phungductung	0:e87aa4c49e95	1833	*/
phungductung	0:e87aa4c49e95	1834	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
phungductung	0:e87aa4c49e95	1835	and user can use HAL_SPI_GetError() API to check the latest error occurred
phungductung	0:e87aa4c49e95	1836	*/
phungductung	0:e87aa4c49e95	1837	}
phungductung	0:e87aa4c49e95	1838
phungductung	0:e87aa4c49e95	1839	/**
phungductung	0:e87aa4c49e95	1840	* @}
phungductung	0:e87aa4c49e95	1841	*/
phungductung	0:e87aa4c49e95	1842
phungductung	0:e87aa4c49e95	1843	/**
phungductung	0:e87aa4c49e95	1844	* @}
phungductung	0:e87aa4c49e95	1845	*/
phungductung	0:e87aa4c49e95	1846
phungductung	0:e87aa4c49e95	1847	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
phungductung	0:e87aa4c49e95	1848	* @brief SPI control functions
phungductung	0:e87aa4c49e95	1849	*
phungductung	0:e87aa4c49e95	1850	@verbatim
phungductung	0:e87aa4c49e95	1851	===============================================================================
phungductung	0:e87aa4c49e95	1852	##### Peripheral State and Errors functions #####
phungductung	0:e87aa4c49e95	1853	===============================================================================
phungductung	0:e87aa4c49e95	1854	[..]
phungductung	0:e87aa4c49e95	1855	This subsection provides a set of functions allowing to control the SPI.
phungductung	0:e87aa4c49e95	1856	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
phungductung	0:e87aa4c49e95	1857	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
phungductung	0:e87aa4c49e95	1858	@endverbatim
phungductung	0:e87aa4c49e95	1859	* @{
phungductung	0:e87aa4c49e95	1860	*/
phungductung	0:e87aa4c49e95	1861
phungductung	0:e87aa4c49e95	1862	/**
phungductung	0:e87aa4c49e95	1863	* @brief Return the SPI state
phungductung	0:e87aa4c49e95	1864	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1865	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1866	* @retval SPI state
phungductung	0:e87aa4c49e95	1867	*/
phungductung	0:e87aa4c49e95	1868	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1869	{
phungductung	0:e87aa4c49e95	1870	return hspi->State;
phungductung	0:e87aa4c49e95	1871	}
phungductung	0:e87aa4c49e95	1872
phungductung	0:e87aa4c49e95	1873	/**
phungductung	0:e87aa4c49e95	1874	* @brief Return the SPI error code
phungductung	0:e87aa4c49e95	1875	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1876	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	1877	* @retval SPI error code in bitmap format
phungductung	0:e87aa4c49e95	1878	*/
phungductung	0:e87aa4c49e95	1879	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	1880	{
phungductung	0:e87aa4c49e95	1881	return hspi->ErrorCode;
phungductung	0:e87aa4c49e95	1882	}
phungductung	0:e87aa4c49e95	1883
phungductung	0:e87aa4c49e95	1884	/**
phungductung	0:e87aa4c49e95	1885	* @}
phungductung	0:e87aa4c49e95	1886	*/
phungductung	0:e87aa4c49e95	1887
phungductung	0:e87aa4c49e95	1888	/**
phungductung	0:e87aa4c49e95	1889	* @}
phungductung	0:e87aa4c49e95	1890	*/
phungductung	0:e87aa4c49e95	1891
phungductung	0:e87aa4c49e95	1892	/** @defgroup SPI_Private_Functions SPI Private Functions
phungductung	0:e87aa4c49e95	1893	* @{
phungductung	0:e87aa4c49e95	1894	*/
phungductung	0:e87aa4c49e95	1895
phungductung	0:e87aa4c49e95	1896	/**
phungductung	0:e87aa4c49e95	1897	* @brief DMA SPI transmit process complete callback
phungductung	0:e87aa4c49e95	1898	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1899	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	1900	* @retval None
phungductung	0:e87aa4c49e95	1901	*/
phungductung	0:e87aa4c49e95	1902	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1903	{
phungductung	0:e87aa4c49e95	1904	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	1905
phungductung	0:e87aa4c49e95	1906	/* DMA Normal Mode */
phungductung	0:e87aa4c49e95	1907	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung	0:e87aa4c49e95	1908	{
phungductung	0:e87aa4c49e95	1909	/* Disable Tx DMA Request */
phungductung	0:e87aa4c49e95	1910	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
phungductung	0:e87aa4c49e95	1911
phungductung	0:e87aa4c49e95	1912	/* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
phungductung	0:e87aa4c49e95	1913	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
phungductung	0:e87aa4c49e95	1914	{
phungductung	0:e87aa4c49e95	1915	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:e87aa4c49e95	1916	}
phungductung	0:e87aa4c49e95	1917
phungductung	0:e87aa4c49e95	1918	hspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	1919	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	1920
phungductung	0:e87aa4c49e95	1921	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	1922	{
phungductung	0:e87aa4c49e95	1923	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	1924	return;
phungductung	0:e87aa4c49e95	1925	}
phungductung	0:e87aa4c49e95	1926	}
phungductung	0:e87aa4c49e95	1927	HAL_SPI_TxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	1928	}
phungductung	0:e87aa4c49e95	1929
phungductung	0:e87aa4c49e95	1930	/**
phungductung	0:e87aa4c49e95	1931	* @brief DMA SPI receive process complete callback
phungductung	0:e87aa4c49e95	1932	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	1933	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	1934	* @retval None
phungductung	0:e87aa4c49e95	1935	*/
phungductung	0:e87aa4c49e95	1936	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1937	{
phungductung	0:e87aa4c49e95	1938	__IO uint16_t tmpreg;
phungductung	0:e87aa4c49e95	1939	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	1940
phungductung	0:e87aa4c49e95	1941	/* DMA Normal mode */
phungductung	0:e87aa4c49e95	1942	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung	0:e87aa4c49e95	1943	{
phungductung	0:e87aa4c49e95	1944	/* CRC handling */
phungductung	0:e87aa4c49e95	1945	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	1946	{
phungductung	0:e87aa4c49e95	1947	/* Wait until TXE flag */
phungductung	0:e87aa4c49e95	1948	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:e87aa4c49e95	1949	{
phungductung	0:e87aa4c49e95	1950	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	1951	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	1952	}
phungductung	0:e87aa4c49e95	1953	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:e87aa4c49e95	1954	{
phungductung	0:e87aa4c49e95	1955	tmpreg = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	1956	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	1957	}
phungductung	0:e87aa4c49e95	1958	else
phungductung	0:e87aa4c49e95	1959	{
phungductung	0:e87aa4c49e95	1960	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	1961	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	1962
phungductung	0:e87aa4c49e95	1963	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
phungductung	0:e87aa4c49e95	1964	{
phungductung	0:e87aa4c49e95	1965	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:e87aa4c49e95	1966	{
phungductung	0:e87aa4c49e95	1967	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	1968	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	1969	}
phungductung	0:e87aa4c49e95	1970	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	1971	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	1972	}
phungductung	0:e87aa4c49e95	1973	}
phungductung	0:e87aa4c49e95	1974	}
phungductung	0:e87aa4c49e95	1975
phungductung	0:e87aa4c49e95	1976	/* Disable Rx DMA Request */
phungductung	0:e87aa4c49e95	1977	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
phungductung	0:e87aa4c49e95	1978	/* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
phungductung	0:e87aa4c49e95	1979	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
phungductung	0:e87aa4c49e95	1980
phungductung	0:e87aa4c49e95	1981	/* Check the end of the transaction */
phungductung	0:e87aa4c49e95	1982	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
phungductung	0:e87aa4c49e95	1983
phungductung	0:e87aa4c49e95	1984	hspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	1985	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	1986
phungductung	0:e87aa4c49e95	1987	/* Check if CRC error occurred */
phungductung	0:e87aa4c49e95	1988	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:e87aa4c49e95	1989	{
phungductung	0:e87aa4c49e95	1990	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	1991	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:e87aa4c49e95	1992	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	1993	}
phungductung	0:e87aa4c49e95	1994	else
phungductung	0:e87aa4c49e95	1995	{
phungductung	0:e87aa4c49e95	1996	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	1997	{
phungductung	0:e87aa4c49e95	1998	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	1999	}
phungductung	0:e87aa4c49e95	2000	else
phungductung	0:e87aa4c49e95	2001	{
phungductung	0:e87aa4c49e95	2002	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2003	}
phungductung	0:e87aa4c49e95	2004	}
phungductung	0:e87aa4c49e95	2005	}
phungductung	0:e87aa4c49e95	2006	else
phungductung	0:e87aa4c49e95	2007	{
phungductung	0:e87aa4c49e95	2008	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2009	}
phungductung	0:e87aa4c49e95	2010	}
phungductung	0:e87aa4c49e95	2011
phungductung	0:e87aa4c49e95	2012	/**
phungductung	0:e87aa4c49e95	2013	* @brief DMA SPI transmit receive process complete callback
phungductung	0:e87aa4c49e95	2014	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2015	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	2016	* @retval None
phungductung	0:e87aa4c49e95	2017	*/
phungductung	0:e87aa4c49e95	2018	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	2019	{
phungductung	0:e87aa4c49e95	2020	__IO int16_t tmpreg;
phungductung	0:e87aa4c49e95	2021	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	2022
phungductung	0:e87aa4c49e95	2023	/* CRC handling */
phungductung	0:e87aa4c49e95	2024	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2025	{
phungductung	0:e87aa4c49e95	2026	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
phungductung	0:e87aa4c49e95	2027	{
phungductung	0:e87aa4c49e95	2028	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:e87aa4c49e95	2029	{
phungductung	0:e87aa4c49e95	2030	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	2031	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	2032	}
phungductung	0:e87aa4c49e95	2033	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2034	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2035	}
phungductung	0:e87aa4c49e95	2036	else
phungductung	0:e87aa4c49e95	2037	{
phungductung	0:e87aa4c49e95	2038	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:e87aa4c49e95	2039	{
phungductung	0:e87aa4c49e95	2040	/* Error on the CRC reception */
phungductung	0:e87aa4c49e95	2041	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	2042	}
phungductung	0:e87aa4c49e95	2043	tmpreg = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2044	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2045	}
phungductung	0:e87aa4c49e95	2046	}
phungductung	0:e87aa4c49e95	2047
phungductung	0:e87aa4c49e95	2048	/* Check the end of the transaction */
phungductung	0:e87aa4c49e95	2049	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
phungductung	0:e87aa4c49e95	2050
phungductung	0:e87aa4c49e95	2051	/* Disable Tx DMA Request */
phungductung	0:e87aa4c49e95	2052	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
phungductung	0:e87aa4c49e95	2053
phungductung	0:e87aa4c49e95	2054	/* Disable Rx DMA Request */
phungductung	0:e87aa4c49e95	2055	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
phungductung	0:e87aa4c49e95	2056
phungductung	0:e87aa4c49e95	2057	hspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	2058	hspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	2059	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2060
phungductung	0:e87aa4c49e95	2061	/* Check if CRC error occurred */
phungductung	0:e87aa4c49e95	2062	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:e87aa4c49e95	2063	{
phungductung	0:e87aa4c49e95	2064	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	2065	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:e87aa4c49e95	2066	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2067	}
phungductung	0:e87aa4c49e95	2068	else
phungductung	0:e87aa4c49e95	2069	{
phungductung	0:e87aa4c49e95	2070	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	2071	{
phungductung	0:e87aa4c49e95	2072	HAL_SPI_TxRxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2073	}
phungductung	0:e87aa4c49e95	2074	else
phungductung	0:e87aa4c49e95	2075	{
phungductung	0:e87aa4c49e95	2076	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2077	}
phungductung	0:e87aa4c49e95	2078	}
phungductung	0:e87aa4c49e95	2079	}
phungductung	0:e87aa4c49e95	2080
phungductung	0:e87aa4c49e95	2081	/**
phungductung	0:e87aa4c49e95	2082	* @brief DMA SPI half transmit process complete callback
phungductung	0:e87aa4c49e95	2083	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2084	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	2085	* @retval None
phungductung	0:e87aa4c49e95	2086	*/
phungductung	0:e87aa4c49e95	2087	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	2088	{
phungductung	0:e87aa4c49e95	2089	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	2090
phungductung	0:e87aa4c49e95	2091	HAL_SPI_TxHalfCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2092	}
phungductung	0:e87aa4c49e95	2093
phungductung	0:e87aa4c49e95	2094	/**
phungductung	0:e87aa4c49e95	2095	* @brief DMA SPI half receive process complete callback
phungductung	0:e87aa4c49e95	2096	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2097	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	2098	* @retval None
phungductung	0:e87aa4c49e95	2099	*/
phungductung	0:e87aa4c49e95	2100	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	2101	{
phungductung	0:e87aa4c49e95	2102	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	2103
phungductung	0:e87aa4c49e95	2104	HAL_SPI_RxHalfCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2105	}
phungductung	0:e87aa4c49e95	2106
phungductung	0:e87aa4c49e95	2107	/**
phungductung	0:e87aa4c49e95	2108	* @brief DMA SPI Half transmit receive process complete callback
phungductung	0:e87aa4c49e95	2109	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2110	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	2111	* @retval None
phungductung	0:e87aa4c49e95	2112	*/
phungductung	0:e87aa4c49e95	2113	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	2114	{
phungductung	0:e87aa4c49e95	2115	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	2116
phungductung	0:e87aa4c49e95	2117	HAL_SPI_TxRxHalfCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2118	}
phungductung	0:e87aa4c49e95	2119
phungductung	0:e87aa4c49e95	2120	/**
phungductung	0:e87aa4c49e95	2121	* @brief DMA SPI communication error callback
phungductung	0:e87aa4c49e95	2122	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2123	* the configuration information for the specified DMA module.
phungductung	0:e87aa4c49e95	2124	* @retval None
phungductung	0:e87aa4c49e95	2125	*/
phungductung	0:e87aa4c49e95	2126	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	2127	{
phungductung	0:e87aa4c49e95	2128	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	2129
phungductung	0:e87aa4c49e95	2130	/* Stop the disable DMA transfer on SPI side */
phungductung	0:e87aa4c49e95	2131	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:e87aa4c49e95	2132
phungductung	0:e87aa4c49e95	2133	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
phungductung	0:e87aa4c49e95	2134	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2135	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2136	}
phungductung	0:e87aa4c49e95	2137
phungductung	0:e87aa4c49e95	2138	/**
phungductung	0:e87aa4c49e95	2139	* @brief Rx Handler for Transmit and Receive in Interrupt mode
phungductung	0:e87aa4c49e95	2140	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2141	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2142	* @retval None
phungductung	0:e87aa4c49e95	2143	*/
phungductung	0:e87aa4c49e95	2144	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2145	{
phungductung	0:e87aa4c49e95	2146	/* Receive data in packing mode */
phungductung	0:e87aa4c49e95	2147	if(hspi->RxXferCount > 1)
phungductung	0:e87aa4c49e95	2148	{
phungductung	0:e87aa4c49e95	2149	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2150	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	2151	hspi->RxXferCount -= 2;
phungductung	0:e87aa4c49e95	2152	if(hspi->RxXferCount == 1)
phungductung	0:e87aa4c49e95	2153	{
phungductung	0:e87aa4c49e95	2154	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:e87aa4c49e95	2155	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	2156	}
phungductung	0:e87aa4c49e95	2157	}
phungductung	0:e87aa4c49e95	2158	/* Receive data in 8 Bit mode */
phungductung	0:e87aa4c49e95	2159	else
phungductung	0:e87aa4c49e95	2160	{
phungductung	0:e87aa4c49e95	2161	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
phungductung	0:e87aa4c49e95	2162	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	2163	}
phungductung	0:e87aa4c49e95	2164
phungductung	0:e87aa4c49e95	2165	/* check end of the reception */
phungductung	0:e87aa4c49e95	2166	if(hspi->RxXferCount == 0)
phungductung	0:e87aa4c49e95	2167	{
phungductung	0:e87aa4c49e95	2168	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2169	{
phungductung	0:e87aa4c49e95	2170	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:e87aa4c49e95	2171	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
phungductung	0:e87aa4c49e95	2172	return;
phungductung	0:e87aa4c49e95	2173	}
phungductung	0:e87aa4c49e95	2174
phungductung	0:e87aa4c49e95	2175	/* Disable RXNE interrupt */
phungductung	0:e87aa4c49e95	2176	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:e87aa4c49e95	2177
phungductung	0:e87aa4c49e95	2178	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2179	{
phungductung	0:e87aa4c49e95	2180	SPI_CloseRxTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2181	}
phungductung	0:e87aa4c49e95	2182	}
phungductung	0:e87aa4c49e95	2183	}
phungductung	0:e87aa4c49e95	2184
phungductung	0:e87aa4c49e95	2185	/**
phungductung	0:e87aa4c49e95	2186	* @brief Rx Handler for Transmit and Receive in Interrupt mode
phungductung	0:e87aa4c49e95	2187	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2188	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2189	* @retval None
phungductung	0:e87aa4c49e95	2190	*/
phungductung	0:e87aa4c49e95	2191	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2192	{
phungductung	0:e87aa4c49e95	2193	__IO uint8_t tmpreg;
phungductung	0:e87aa4c49e95	2194
phungductung	0:e87aa4c49e95	2195	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
phungductung	0:e87aa4c49e95	2196	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2197
phungductung	0:e87aa4c49e95	2198	hspi->CRCSize--;
phungductung	0:e87aa4c49e95	2199
phungductung	0:e87aa4c49e95	2200	/* check end of the reception */
phungductung	0:e87aa4c49e95	2201	if(hspi->CRCSize == 0)
phungductung	0:e87aa4c49e95	2202	{
phungductung	0:e87aa4c49e95	2203	/* Disable RXNE interrupt */
phungductung	0:e87aa4c49e95	2204	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:e87aa4c49e95	2205
phungductung	0:e87aa4c49e95	2206	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2207	{
phungductung	0:e87aa4c49e95	2208	SPI_CloseRxTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2209	}
phungductung	0:e87aa4c49e95	2210	}
phungductung	0:e87aa4c49e95	2211	}
phungductung	0:e87aa4c49e95	2212
phungductung	0:e87aa4c49e95	2213	/**
phungductung	0:e87aa4c49e95	2214	* @brief Tx Handler for Transmit and Receive in Interrupt mode
phungductung	0:e87aa4c49e95	2215	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2216	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2217	* @retval None
phungductung	0:e87aa4c49e95	2218	*/
phungductung	0:e87aa4c49e95	2219	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2220	{
phungductung	0:e87aa4c49e95	2221	/* Transmit data in packing Bit mode */
phungductung	0:e87aa4c49e95	2222	if(hspi->TxXferCount >= 2)
phungductung	0:e87aa4c49e95	2223	{
phungductung	0:e87aa4c49e95	2224	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	2225	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	2226	hspi->TxXferCount -= 2;
phungductung	0:e87aa4c49e95	2227	}
phungductung	0:e87aa4c49e95	2228	/* Transmit data in 8 Bit mode */
phungductung	0:e87aa4c49e95	2229	else
phungductung	0:e87aa4c49e95	2230	{
phungductung	0:e87aa4c49e95	2231	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
phungductung	0:e87aa4c49e95	2232	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	2233	}
phungductung	0:e87aa4c49e95	2234
phungductung	0:e87aa4c49e95	2235	/* check the end of the transmission */
phungductung	0:e87aa4c49e95	2236	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2237	{
phungductung	0:e87aa4c49e95	2238	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2239	{
phungductung	0:e87aa4c49e95	2240	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	2241	}
phungductung	0:e87aa4c49e95	2242	/* Disable TXE interrupt */
phungductung	0:e87aa4c49e95	2243	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
phungductung	0:e87aa4c49e95	2244
phungductung	0:e87aa4c49e95	2245	if(hspi->RxXferCount == 0)
phungductung	0:e87aa4c49e95	2246	{
phungductung	0:e87aa4c49e95	2247	SPI_CloseRxTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2248	}
phungductung	0:e87aa4c49e95	2249	}
phungductung	0:e87aa4c49e95	2250	}
phungductung	0:e87aa4c49e95	2251
phungductung	0:e87aa4c49e95	2252	/**
phungductung	0:e87aa4c49e95	2253	* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
phungductung	0:e87aa4c49e95	2254	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2255	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2256	* @retval None
phungductung	0:e87aa4c49e95	2257	*/
phungductung	0:e87aa4c49e95	2258	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2259	{
phungductung	0:e87aa4c49e95	2260	/* Receive data in 16 Bit mode */
phungductung	0:e87aa4c49e95	2261	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2262	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	2263	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	2264
phungductung	0:e87aa4c49e95	2265	if(hspi->RxXferCount == 0)
phungductung	0:e87aa4c49e95	2266	{
phungductung	0:e87aa4c49e95	2267	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2268	{
phungductung	0:e87aa4c49e95	2269	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
phungductung	0:e87aa4c49e95	2270	return;
phungductung	0:e87aa4c49e95	2271	}
phungductung	0:e87aa4c49e95	2272
phungductung	0:e87aa4c49e95	2273	/* Disable RXNE interrupt */
phungductung	0:e87aa4c49e95	2274	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:e87aa4c49e95	2275
phungductung	0:e87aa4c49e95	2276	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2277	{
phungductung	0:e87aa4c49e95	2278	SPI_CloseRxTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2279	}
phungductung	0:e87aa4c49e95	2280	}
phungductung	0:e87aa4c49e95	2281	}
phungductung	0:e87aa4c49e95	2282
phungductung	0:e87aa4c49e95	2283	/**
phungductung	0:e87aa4c49e95	2284	* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
phungductung	0:e87aa4c49e95	2285	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2286	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2287	* @retval None
phungductung	0:e87aa4c49e95	2288	*/
phungductung	0:e87aa4c49e95	2289	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2290	{
phungductung	0:e87aa4c49e95	2291	/* Receive data in 16 Bit mode */
phungductung	0:e87aa4c49e95	2292	__IO uint16_t tmpreg = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2293	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2294
phungductung	0:e87aa4c49e95	2295	/* Disable RXNE interrupt */
phungductung	0:e87aa4c49e95	2296	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:e87aa4c49e95	2297
phungductung	0:e87aa4c49e95	2298	SPI_CloseRxTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2299	}
phungductung	0:e87aa4c49e95	2300
phungductung	0:e87aa4c49e95	2301	/**
phungductung	0:e87aa4c49e95	2302	* @brief Tx Handler for Transmit and Receive in Interrupt mode
phungductung	0:e87aa4c49e95	2303	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2304	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2305	* @retval None
phungductung	0:e87aa4c49e95	2306	*/
phungductung	0:e87aa4c49e95	2307	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2308	{
phungductung	0:e87aa4c49e95	2309	/* Transmit data in 16 Bit mode */
phungductung	0:e87aa4c49e95	2310	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	2311	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	2312	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	2313
phungductung	0:e87aa4c49e95	2314	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	2315	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2316	{
phungductung	0:e87aa4c49e95	2317	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2318	{
phungductung	0:e87aa4c49e95	2319	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	2320	}
phungductung	0:e87aa4c49e95	2321	/* Disable TXE interrupt */
phungductung	0:e87aa4c49e95	2322	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
phungductung	0:e87aa4c49e95	2323
phungductung	0:e87aa4c49e95	2324	if(hspi->RxXferCount == 0)
phungductung	0:e87aa4c49e95	2325	{
phungductung	0:e87aa4c49e95	2326	SPI_CloseRxTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2327	}
phungductung	0:e87aa4c49e95	2328	}
phungductung	0:e87aa4c49e95	2329	}
phungductung	0:e87aa4c49e95	2330
phungductung	0:e87aa4c49e95	2331	/**
phungductung	0:e87aa4c49e95	2332	* @brief Manage the CRC receive in Interrupt context
phungductung	0:e87aa4c49e95	2333	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2334	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2335	* @retval None
phungductung	0:e87aa4c49e95	2336	*/
phungductung	0:e87aa4c49e95	2337	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2338	{
phungductung	0:e87aa4c49e95	2339	__IO uint8_t tmpreg;
phungductung	0:e87aa4c49e95	2340	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
phungductung	0:e87aa4c49e95	2341	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2342
phungductung	0:e87aa4c49e95	2343	hspi->CRCSize--;
phungductung	0:e87aa4c49e95	2344
phungductung	0:e87aa4c49e95	2345	if(hspi->CRCSize == 0)
phungductung	0:e87aa4c49e95	2346	{
phungductung	0:e87aa4c49e95	2347	SPI_CloseRx_ISR(hspi);
phungductung	0:e87aa4c49e95	2348	}
phungductung	0:e87aa4c49e95	2349	}
phungductung	0:e87aa4c49e95	2350
phungductung	0:e87aa4c49e95	2351	/**
phungductung	0:e87aa4c49e95	2352	* @brief Manage the receive in Interrupt context
phungductung	0:e87aa4c49e95	2353	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2354	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2355	* @retval None
phungductung	0:e87aa4c49e95	2356	*/
phungductung	0:e87aa4c49e95	2357	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2358	{
phungductung	0:e87aa4c49e95	2359	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
phungductung	0:e87aa4c49e95	2360	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	2361
phungductung	0:e87aa4c49e95	2362	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	2363	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:e87aa4c49e95	2364	{
phungductung	0:e87aa4c49e95	2365	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	2366	}
phungductung	0:e87aa4c49e95	2367
phungductung	0:e87aa4c49e95	2368	if(hspi->RxXferCount == 0)
phungductung	0:e87aa4c49e95	2369	{
phungductung	0:e87aa4c49e95	2370	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2371	{
phungductung	0:e87aa4c49e95	2372	hspi->RxISR = SPI_RxISR_8BITCRC;
phungductung	0:e87aa4c49e95	2373	return;
phungductung	0:e87aa4c49e95	2374	}
phungductung	0:e87aa4c49e95	2375	SPI_CloseRx_ISR(hspi);
phungductung	0:e87aa4c49e95	2376	}
phungductung	0:e87aa4c49e95	2377	}
phungductung	0:e87aa4c49e95	2378
phungductung	0:e87aa4c49e95	2379	/**
phungductung	0:e87aa4c49e95	2380	* @brief Manage the CRC 16bit receive in Interrupt context
phungductung	0:e87aa4c49e95	2381	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2382	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2383	* @retval None
phungductung	0:e87aa4c49e95	2384	*/
phungductung	0:e87aa4c49e95	2385	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2386	{
phungductung	0:e87aa4c49e95	2387	__IO uint16_t tmpreg;
phungductung	0:e87aa4c49e95	2388
phungductung	0:e87aa4c49e95	2389	tmpreg = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2390	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2391
phungductung	0:e87aa4c49e95	2392	/* Disable RXNE and ERR interrupt */
phungductung	0:e87aa4c49e95	2393	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	2394
phungductung	0:e87aa4c49e95	2395	SPI_CloseRx_ISR(hspi);
phungductung	0:e87aa4c49e95	2396	}
phungductung	0:e87aa4c49e95	2397
phungductung	0:e87aa4c49e95	2398	/**
phungductung	0:e87aa4c49e95	2399	* @brief Manage the 16Bit receive in Interrupt context
phungductung	0:e87aa4c49e95	2400	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2401	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2402	* @retval None
phungductung	0:e87aa4c49e95	2403	*/
phungductung	0:e87aa4c49e95	2404	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2405	{
phungductung	0:e87aa4c49e95	2406	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:e87aa4c49e95	2407	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	2408	hspi->RxXferCount--;
phungductung	0:e87aa4c49e95	2409
phungductung	0:e87aa4c49e95	2410	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	2411	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:e87aa4c49e95	2412	{
phungductung	0:e87aa4c49e95	2413	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	2414	}
phungductung	0:e87aa4c49e95	2415
phungductung	0:e87aa4c49e95	2416	if(hspi->RxXferCount == 0)
phungductung	0:e87aa4c49e95	2417	{
phungductung	0:e87aa4c49e95	2418	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2419	{
phungductung	0:e87aa4c49e95	2420	hspi->RxISR = SPI_RxISR_16BITCRC;
phungductung	0:e87aa4c49e95	2421	return;
phungductung	0:e87aa4c49e95	2422	}
phungductung	0:e87aa4c49e95	2423	SPI_CloseRx_ISR(hspi);
phungductung	0:e87aa4c49e95	2424	}
phungductung	0:e87aa4c49e95	2425	}
phungductung	0:e87aa4c49e95	2426
phungductung	0:e87aa4c49e95	2427	/**
phungductung	0:e87aa4c49e95	2428	* @brief Handle the data 8Bit transmit in Interrupt mode
phungductung	0:e87aa4c49e95	2429	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2430	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2431	* @retval None
phungductung	0:e87aa4c49e95	2432	*/
phungductung	0:e87aa4c49e95	2433	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2434	{
phungductung	0:e87aa4c49e95	2435	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
phungductung	0:e87aa4c49e95	2436	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	2437
phungductung	0:e87aa4c49e95	2438	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2439	{
phungductung	0:e87aa4c49e95	2440	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2441	{
phungductung	0:e87aa4c49e95	2442	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	2443	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	2444	}
phungductung	0:e87aa4c49e95	2445	SPI_CloseTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2446	}
phungductung	0:e87aa4c49e95	2447	}
phungductung	0:e87aa4c49e95	2448
phungductung	0:e87aa4c49e95	2449	/**
phungductung	0:e87aa4c49e95	2450	* @brief Handle the data 16Bit transmit in Interrupt mode
phungductung	0:e87aa4c49e95	2451	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2452	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2453	* @retval None
phungductung	0:e87aa4c49e95	2454	*/
phungductung	0:e87aa4c49e95	2455	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2456	{
phungductung	0:e87aa4c49e95	2457	/* Transmit data in 16 Bit mode */
phungductung	0:e87aa4c49e95	2458	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:e87aa4c49e95	2459	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:e87aa4c49e95	2460	hspi->TxXferCount--;
phungductung	0:e87aa4c49e95	2461
phungductung	0:e87aa4c49e95	2462	if(hspi->TxXferCount == 0)
phungductung	0:e87aa4c49e95	2463	{
phungductung	0:e87aa4c49e95	2464	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2465	{
phungductung	0:e87aa4c49e95	2466	/* Enable CRC Transmission */
phungductung	0:e87aa4c49e95	2467	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:e87aa4c49e95	2468	}
phungductung	0:e87aa4c49e95	2469	SPI_CloseTx_ISR(hspi);
phungductung	0:e87aa4c49e95	2470	}
phungductung	0:e87aa4c49e95	2471	}
phungductung	0:e87aa4c49e95	2472
phungductung	0:e87aa4c49e95	2473	/**
phungductung	0:e87aa4c49e95	2474	* @brief This function handles SPI Communication Timeout.
phungductung	0:e87aa4c49e95	2475	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2476	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2477	* @param Flag : SPI flag to check
phungductung	0:e87aa4c49e95	2478	* @param State : flag state to check
phungductung	0:e87aa4c49e95	2479	* @param Timeout : Timeout duration
phungductung	0:e87aa4c49e95	2480	* @retval HAL status
phungductung	0:e87aa4c49e95	2481	*/
phungductung	0:e87aa4c49e95	2482	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
phungductung	0:e87aa4c49e95	2483	{
phungductung	0:e87aa4c49e95	2484	uint32_t tickstart = HAL_GetTick();
phungductung	0:e87aa4c49e95	2485
phungductung	0:e87aa4c49e95	2486	while((hspi->Instance->SR & Flag) != State)
phungductung	0:e87aa4c49e95	2487	{
phungductung	0:e87aa4c49e95	2488	if(Timeout != HAL_MAX_DELAY)
phungductung	0:e87aa4c49e95	2489	{
phungductung	0:e87aa4c49e95	2490	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
phungductung	0:e87aa4c49e95	2491	{
phungductung	0:e87aa4c49e95	2492	/* Disable the SPI and reset the CRC: the CRC value should be cleared
phungductung	0:e87aa4c49e95	2493	on both master and slave sides in order to resynchronize the master
phungductung	0:e87aa4c49e95	2494	and slave for their respective CRC calculation */
phungductung	0:e87aa4c49e95	2495
phungductung	0:e87aa4c49e95	2496	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
phungductung	0:e87aa4c49e95	2497	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	2498
phungductung	0:e87aa4c49e95	2499	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
phungductung	0:e87aa4c49e95	2500	{
phungductung	0:e87aa4c49e95	2501	/* Disable SPI peripheral */
phungductung	0:e87aa4c49e95	2502	__HAL_SPI_DISABLE(hspi);
phungductung	0:e87aa4c49e95	2503	}
phungductung	0:e87aa4c49e95	2504
phungductung	0:e87aa4c49e95	2505	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	2506	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2507	{
phungductung	0:e87aa4c49e95	2508	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	2509	}
phungductung	0:e87aa4c49e95	2510
phungductung	0:e87aa4c49e95	2511	hspi->State= HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2512
phungductung	0:e87aa4c49e95	2513	/* Process Unlocked */
phungductung	0:e87aa4c49e95	2514	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	2515
phungductung	0:e87aa4c49e95	2516	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2517	}
phungductung	0:e87aa4c49e95	2518	}
phungductung	0:e87aa4c49e95	2519	}
phungductung	0:e87aa4c49e95	2520
phungductung	0:e87aa4c49e95	2521	return HAL_OK;
phungductung	0:e87aa4c49e95	2522	}
phungductung	0:e87aa4c49e95	2523
phungductung	0:e87aa4c49e95	2524	/**
phungductung	0:e87aa4c49e95	2525	* @brief This function handles SPI Communication Timeout.
phungductung	0:e87aa4c49e95	2526	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2527	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2528	* @param Fifo : Fifo to check
phungductung	0:e87aa4c49e95	2529	* @param State : Fifo state to check
phungductung	0:e87aa4c49e95	2530	* @param Timeout : Timeout duration
phungductung	0:e87aa4c49e95	2531	* @retval HAL status
phungductung	0:e87aa4c49e95	2532	*/
phungductung	0:e87aa4c49e95	2533	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
phungductung	0:e87aa4c49e95	2534	{
phungductung	0:e87aa4c49e95	2535	__IO uint8_t tmpreg;
phungductung	0:e87aa4c49e95	2536	uint32_t tickstart = HAL_GetTick();
phungductung	0:e87aa4c49e95	2537
phungductung	0:e87aa4c49e95	2538	while((hspi->Instance->SR & Fifo) != State)
phungductung	0:e87aa4c49e95	2539	{
phungductung	0:e87aa4c49e95	2540	if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
phungductung	0:e87aa4c49e95	2541	{
phungductung	0:e87aa4c49e95	2542	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
phungductung	0:e87aa4c49e95	2543	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:e87aa4c49e95	2544	}
phungductung	0:e87aa4c49e95	2545
phungductung	0:e87aa4c49e95	2546	if(Timeout != HAL_MAX_DELAY)
phungductung	0:e87aa4c49e95	2547	{
phungductung	0:e87aa4c49e95	2548	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
phungductung	0:e87aa4c49e95	2549	{
phungductung	0:e87aa4c49e95	2550	/* Disable the SPI and reset the CRC: the CRC value should be cleared
phungductung	0:e87aa4c49e95	2551	on both master and slave sides in order to resynchronize the master
phungductung	0:e87aa4c49e95	2552	and slave for their respective CRC calculation */
phungductung	0:e87aa4c49e95	2553
phungductung	0:e87aa4c49e95	2554	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
phungductung	0:e87aa4c49e95	2555	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	2556
phungductung	0:e87aa4c49e95	2557	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
phungductung	0:e87aa4c49e95	2558	{
phungductung	0:e87aa4c49e95	2559	/* Disable SPI peripheral */
phungductung	0:e87aa4c49e95	2560	__HAL_SPI_DISABLE(hspi);
phungductung	0:e87aa4c49e95	2561	}
phungductung	0:e87aa4c49e95	2562
phungductung	0:e87aa4c49e95	2563	/* Reset CRC Calculation */
phungductung	0:e87aa4c49e95	2564	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:e87aa4c49e95	2565	{
phungductung	0:e87aa4c49e95	2566	SPI_RESET_CRC(hspi);
phungductung	0:e87aa4c49e95	2567	}
phungductung	0:e87aa4c49e95	2568
phungductung	0:e87aa4c49e95	2569	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2570
phungductung	0:e87aa4c49e95	2571	/* Process Unlocked */
phungductung	0:e87aa4c49e95	2572	__HAL_UNLOCK(hspi);
phungductung	0:e87aa4c49e95	2573
phungductung	0:e87aa4c49e95	2574	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2575	}
phungductung	0:e87aa4c49e95	2576	}
phungductung	0:e87aa4c49e95	2577	}
phungductung	0:e87aa4c49e95	2578
phungductung	0:e87aa4c49e95	2579	return HAL_OK;
phungductung	0:e87aa4c49e95	2580	}
phungductung	0:e87aa4c49e95	2581
phungductung	0:e87aa4c49e95	2582	/**
phungductung	0:e87aa4c49e95	2583	* @brief This function handles the check of the RX transaction complete.
phungductung	0:e87aa4c49e95	2584	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2585	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2586	* @param Timeout : Timeout duration
phungductung	0:e87aa4c49e95	2587	* @retval None
phungductung	0:e87aa4c49e95	2588	*/
phungductung	0:e87aa4c49e95	2589	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
phungductung	0:e87aa4c49e95	2590	{
phungductung	0:e87aa4c49e95	2591	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
phungductung	0:e87aa4c49e95	2592	{
phungductung	0:e87aa4c49e95	2593	/* Disable SPI peripheral */
phungductung	0:e87aa4c49e95	2594	__HAL_SPI_DISABLE(hspi);
phungductung	0:e87aa4c49e95	2595	}
phungductung	0:e87aa4c49e95	2596	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	2597	{
phungductung	0:e87aa4c49e95	2598	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:e87aa4c49e95	2599	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2600	}
phungductung	0:e87aa4c49e95	2601	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	2602	{
phungductung	0:e87aa4c49e95	2603	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:e87aa4c49e95	2604	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2605	}
phungductung	0:e87aa4c49e95	2606
phungductung	0:e87aa4c49e95	2607	return HAL_OK;
phungductung	0:e87aa4c49e95	2608	}
phungductung	0:e87aa4c49e95	2609
phungductung	0:e87aa4c49e95	2610	/**
phungductung	0:e87aa4c49e95	2611	* @brief This function handles the check of the RXTX or TX transaction complete.
phungductung	0:e87aa4c49e95	2612	* @param hspi: SPI handle
phungductung	0:e87aa4c49e95	2613	* @param Timeout : Timeout duration
phungductung	0:e87aa4c49e95	2614	*/
phungductung	0:e87aa4c49e95	2615	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
phungductung	0:e87aa4c49e95	2616	{
phungductung	0:e87aa4c49e95	2617	/* Procedure to check the transaction complete */
phungductung	0:e87aa4c49e95	2618	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	2619	{
phungductung	0:e87aa4c49e95	2620	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:e87aa4c49e95	2621	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2622	}
phungductung	0:e87aa4c49e95	2623	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	2624	{
phungductung	0:e87aa4c49e95	2625	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:e87aa4c49e95	2626	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2627	}
phungductung	0:e87aa4c49e95	2628	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	2629	{
phungductung	0:e87aa4c49e95	2630	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:e87aa4c49e95	2631	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	2632	}
phungductung	0:e87aa4c49e95	2633	return HAL_OK;
phungductung	0:e87aa4c49e95	2634	}
phungductung	0:e87aa4c49e95	2635
phungductung	0:e87aa4c49e95	2636	/**
phungductung	0:e87aa4c49e95	2637	* @brief This function handles the close of the RXTX transaction.
phungductung	0:e87aa4c49e95	2638	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2639	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2640	* @retval None
phungductung	0:e87aa4c49e95	2641	*/
phungductung	0:e87aa4c49e95	2642	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2643	{
phungductung	0:e87aa4c49e95	2644	/* Disable ERR interrupt */
phungductung	0:e87aa4c49e95	2645	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
phungductung	0:e87aa4c49e95	2646
phungductung	0:e87aa4c49e95	2647	/* Check if CRC error occurred */
phungductung	0:e87aa4c49e95	2648	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:e87aa4c49e95	2649	{
phungductung	0:e87aa4c49e95	2650	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2651	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	2652	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:e87aa4c49e95	2653	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2654	}
phungductung	0:e87aa4c49e95	2655	else
phungductung	0:e87aa4c49e95	2656	{
phungductung	0:e87aa4c49e95	2657	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	2658	{
phungductung	0:e87aa4c49e95	2659	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
phungductung	0:e87aa4c49e95	2660	{
phungductung	0:e87aa4c49e95	2661	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2662	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2663	}
phungductung	0:e87aa4c49e95	2664	else
phungductung	0:e87aa4c49e95	2665	{
phungductung	0:e87aa4c49e95	2666	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2667	HAL_SPI_TxRxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2668	}
phungductung	0:e87aa4c49e95	2669	}
phungductung	0:e87aa4c49e95	2670	else
phungductung	0:e87aa4c49e95	2671	{
phungductung	0:e87aa4c49e95	2672	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2673	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2674	}
phungductung	0:e87aa4c49e95	2675	}
phungductung	0:e87aa4c49e95	2676	}
phungductung	0:e87aa4c49e95	2677
phungductung	0:e87aa4c49e95	2678	/**
phungductung	0:e87aa4c49e95	2679	* @brief This function handles the close of the RX transaction.
phungductung	0:e87aa4c49e95	2680	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2681	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2682	* @retval None
phungductung	0:e87aa4c49e95	2683	*/
phungductung	0:e87aa4c49e95	2684	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2685	{
phungductung	0:e87aa4c49e95	2686	/* Disable RXNE and ERR interrupt */
phungductung	0:e87aa4c49e95	2687	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	2688
phungductung	0:e87aa4c49e95	2689	/* Check the end of the transaction */
phungductung	0:e87aa4c49e95	2690	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
phungductung	0:e87aa4c49e95	2691
phungductung	0:e87aa4c49e95	2692	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2693
phungductung	0:e87aa4c49e95	2694	/* Check if CRC error occurred */
phungductung	0:e87aa4c49e95	2695	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:e87aa4c49e95	2696	{
phungductung	0:e87aa4c49e95	2697	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:e87aa4c49e95	2698	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:e87aa4c49e95	2699	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2700	}
phungductung	0:e87aa4c49e95	2701	else
phungductung	0:e87aa4c49e95	2702	{
phungductung	0:e87aa4c49e95	2703	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	2704	{
phungductung	0:e87aa4c49e95	2705	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2706	}
phungductung	0:e87aa4c49e95	2707	else
phungductung	0:e87aa4c49e95	2708	{
phungductung	0:e87aa4c49e95	2709	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2710	}
phungductung	0:e87aa4c49e95	2711	}
phungductung	0:e87aa4c49e95	2712	}
phungductung	0:e87aa4c49e95	2713
phungductung	0:e87aa4c49e95	2714	/**
phungductung	0:e87aa4c49e95	2715	* @brief This function handles the close of the TX transaction.
phungductung	0:e87aa4c49e95	2716	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:e87aa4c49e95	2717	* the configuration information for SPI module.
phungductung	0:e87aa4c49e95	2718	* @retval None
phungductung	0:e87aa4c49e95	2719	*/
phungductung	0:e87aa4c49e95	2720	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
phungductung	0:e87aa4c49e95	2721	{
phungductung	0:e87aa4c49e95	2722	/* Disable TXE and ERR interrupt */
phungductung	0:e87aa4c49e95	2723	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
phungductung	0:e87aa4c49e95	2724
phungductung	0:e87aa4c49e95	2725	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
phungductung	0:e87aa4c49e95	2726	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
phungductung	0:e87aa4c49e95	2727	{
phungductung	0:e87aa4c49e95	2728	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:e87aa4c49e95	2729	}
phungductung	0:e87aa4c49e95	2730
phungductung	0:e87aa4c49e95	2731	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:e87aa4c49e95	2732	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:e87aa4c49e95	2733	{
phungductung	0:e87aa4c49e95	2734	HAL_SPI_ErrorCallback(hspi);
phungductung	0:e87aa4c49e95	2735	}
phungductung	0:e87aa4c49e95	2736	else
phungductung	0:e87aa4c49e95	2737	{
phungductung	0:e87aa4c49e95	2738	HAL_SPI_TxCpltCallback(hspi);
phungductung	0:e87aa4c49e95	2739	}
phungductung	0:e87aa4c49e95	2740	}
phungductung	0:e87aa4c49e95	2741
phungductung	0:e87aa4c49e95	2742	/**
phungductung	0:e87aa4c49e95	2743	* @}
phungductung	0:e87aa4c49e95	2744	*/
phungductung	0:e87aa4c49e95	2745
phungductung	0:e87aa4c49e95	2746	#endif /* HAL_SPI_MODULE_ENABLED */
phungductung	0:e87aa4c49e95	2747	/**
phungductung	0:e87aa4c49e95	2748	* @}
phungductung	0:e87aa4c49e95	2749	*/
phungductung	0:e87aa4c49e95	2750
phungductung	0:e87aa4c49e95	2751	/**
phungductung	0:e87aa4c49e95	2752	* @}
phungductung	0:e87aa4c49e95	2753	*/
phungductung	0:e87aa4c49e95	2754
phungductung	0:e87aa4c49e95	2755	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Jun 2019
Imports:	8
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:e87aa4c49e95, 2019-06-04 (annotated)

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