PHung Tung / SRC_STM32F7

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

Who changed what in which revision?

UserRevisionLine numberNew contents of line
phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_hal_rcc_ex.c
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief Extension RCC HAL module driver.
phungductung 0:e87aa4c49e95 8 * This file provides firmware functions to manage the following
phungductung 0:e87aa4c49e95 9 * functionalities RCC extension peripheral:
phungductung 0:e87aa4c49e95 10 * + Extended Peripheral Control functions
phungductung 0:e87aa4c49e95 11 *
phungductung 0:e87aa4c49e95 12 ******************************************************************************
phungductung 0:e87aa4c49e95 13 * @attention
phungductung 0:e87aa4c49e95 14 *
phungductung 0:e87aa4c49e95 15 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 16 *
phungductung 0:e87aa4c49e95 17 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 18 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 19 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 20 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 22 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 23 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 25 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 26 * without specific prior written permission.
phungductung 0:e87aa4c49e95 27 *
phungductung 0:e87aa4c49e95 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 38 *
phungductung 0:e87aa4c49e95 39 ******************************************************************************
phungductung 0:e87aa4c49e95 40 */
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 43 #include "stm32f7xx_hal.h"
phungductung 0:e87aa4c49e95 44
phungductung 0:e87aa4c49e95 45 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 46 * @{
phungductung 0:e87aa4c49e95 47 */
phungductung 0:e87aa4c49e95 48
phungductung 0:e87aa4c49e95 49 /** @defgroup RCCEx RCCEx
phungductung 0:e87aa4c49e95 50 * @brief RCCEx HAL module driver
phungductung 0:e87aa4c49e95 51 * @{
phungductung 0:e87aa4c49e95 52 */
phungductung 0:e87aa4c49e95 53
phungductung 0:e87aa4c49e95 54 #ifdef HAL_RCC_MODULE_ENABLED
phungductung 0:e87aa4c49e95 55
phungductung 0:e87aa4c49e95 56 /* Private typedef -----------------------------------------------------------*/
phungductung 0:e87aa4c49e95 57 /* Private define ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 58 /** @defgroup RCCEx_Private_Defines RCCEx Private Defines
phungductung 0:e87aa4c49e95 59 * @{
phungductung 0:e87aa4c49e95 60 */
phungductung 0:e87aa4c49e95 61
phungductung 0:e87aa4c49e95 62 #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
phungductung 0:e87aa4c49e95 63 #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
phungductung 0:e87aa4c49e95 64
phungductung 0:e87aa4c49e95 65 /**
phungductung 0:e87aa4c49e95 66 * @}
phungductung 0:e87aa4c49e95 67 */
phungductung 0:e87aa4c49e95 68 /* Private macro -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 69 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
phungductung 0:e87aa4c49e95 70 * @{
phungductung 0:e87aa4c49e95 71 */
phungductung 0:e87aa4c49e95 72 /**
phungductung 0:e87aa4c49e95 73 * @}
phungductung 0:e87aa4c49e95 74 */
phungductung 0:e87aa4c49e95 75
phungductung 0:e87aa4c49e95 76 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
phungductung 0:e87aa4c49e95 77 * @{
phungductung 0:e87aa4c49e95 78 */
phungductung 0:e87aa4c49e95 79
phungductung 0:e87aa4c49e95 80 /**
phungductung 0:e87aa4c49e95 81 * @}
phungductung 0:e87aa4c49e95 82 */
phungductung 0:e87aa4c49e95 83
phungductung 0:e87aa4c49e95 84
phungductung 0:e87aa4c49e95 85 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 86 /* Private function prototypes -----------------------------------------------*/
phungductung 0:e87aa4c49e95 87 /* Private functions ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 88
phungductung 0:e87aa4c49e95 89 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
phungductung 0:e87aa4c49e95 90 * @{
phungductung 0:e87aa4c49e95 91 */
phungductung 0:e87aa4c49e95 92
phungductung 0:e87aa4c49e95 93 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
phungductung 0:e87aa4c49e95 94 * @brief Extended Peripheral Control functions
phungductung 0:e87aa4c49e95 95 *
phungductung 0:e87aa4c49e95 96 @verbatim
phungductung 0:e87aa4c49e95 97 ===============================================================================
phungductung 0:e87aa4c49e95 98 ##### Extended Peripheral Control functions #####
phungductung 0:e87aa4c49e95 99 ===============================================================================
phungductung 0:e87aa4c49e95 100 [..]
phungductung 0:e87aa4c49e95 101 This subsection provides a set of functions allowing to control the RCC Clocks
phungductung 0:e87aa4c49e95 102 frequencies.
phungductung 0:e87aa4c49e95 103 [..]
phungductung 0:e87aa4c49e95 104 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
phungductung 0:e87aa4c49e95 105 select the RTC clock source; in this case the Backup domain will be reset in
phungductung 0:e87aa4c49e95 106 order to modify the RTC Clock source, as consequence RTC registers (including
phungductung 0:e87aa4c49e95 107 the backup registers) and RCC_BDCR register will be set to their reset values.
phungductung 0:e87aa4c49e95 108
phungductung 0:e87aa4c49e95 109 @endverbatim
phungductung 0:e87aa4c49e95 110 * @{
phungductung 0:e87aa4c49e95 111 */
phungductung 0:e87aa4c49e95 112 /**
phungductung 0:e87aa4c49e95 113 * @brief Initializes the RCC extended peripherals clocks according to the specified
phungductung 0:e87aa4c49e95 114 * parameters in the RCC_PeriphCLKInitTypeDef.
phungductung 0:e87aa4c49e95 115 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
phungductung 0:e87aa4c49e95 116 * contains the configuration information for the Extended Peripherals
phungductung 0:e87aa4c49e95 117 * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
phungductung 0:e87aa4c49e95 118 *
phungductung 0:e87aa4c49e95 119 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
phungductung 0:e87aa4c49e95 120 * the RTC clock source; in this case the Backup domain will be reset in
phungductung 0:e87aa4c49e95 121 * order to modify the RTC Clock source, as consequence RTC registers (including
phungductung 0:e87aa4c49e95 122 * the backup registers) and RCC_BDCR register are set to their reset values.
phungductung 0:e87aa4c49e95 123 *
phungductung 0:e87aa4c49e95 124 * @retval HAL status
phungductung 0:e87aa4c49e95 125 */
phungductung 0:e87aa4c49e95 126 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
phungductung 0:e87aa4c49e95 127 {
phungductung 0:e87aa4c49e95 128 uint32_t tickstart = 0;
phungductung 0:e87aa4c49e95 129 uint32_t tmpreg0 = 0;
phungductung 0:e87aa4c49e95 130 uint32_t tmpreg1 = 0;
phungductung 0:e87aa4c49e95 131 uint32_t plli2sused = 0;
phungductung 0:e87aa4c49e95 132 uint32_t pllsaiused = 0;
phungductung 0:e87aa4c49e95 133
phungductung 0:e87aa4c49e95 134 /* Check the parameters */
phungductung 0:e87aa4c49e95 135 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
phungductung 0:e87aa4c49e95 136
phungductung 0:e87aa4c49e95 137 /*----------------------------------- I2S configuration ----------------------------------*/
phungductung 0:e87aa4c49e95 138 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
phungductung 0:e87aa4c49e95 139 {
phungductung 0:e87aa4c49e95 140 /* Check the parameters */
phungductung 0:e87aa4c49e95 141 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
phungductung 0:e87aa4c49e95 142
phungductung 0:e87aa4c49e95 143 /* Configure I2S Clock source */
phungductung 0:e87aa4c49e95 144 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
phungductung 0:e87aa4c49e95 145
phungductung 0:e87aa4c49e95 146 /* Enable the PLLI2S when it's used as clock source for I2S */
phungductung 0:e87aa4c49e95 147 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
phungductung 0:e87aa4c49e95 148 {
phungductung 0:e87aa4c49e95 149 plli2sused = 1;
phungductung 0:e87aa4c49e95 150 }
phungductung 0:e87aa4c49e95 151 }
phungductung 0:e87aa4c49e95 152
phungductung 0:e87aa4c49e95 153 /*------------------------------------ SAI1 configuration --------------------------------------*/
phungductung 0:e87aa4c49e95 154 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
phungductung 0:e87aa4c49e95 155 {
phungductung 0:e87aa4c49e95 156 /* Check the parameters */
phungductung 0:e87aa4c49e95 157 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
phungductung 0:e87aa4c49e95 158
phungductung 0:e87aa4c49e95 159 /* Configure SAI1 Clock source */
phungductung 0:e87aa4c49e95 160 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
phungductung 0:e87aa4c49e95 161 /* Enable the PLLI2S when it's used as clock source for SAI */
phungductung 0:e87aa4c49e95 162 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
phungductung 0:e87aa4c49e95 163 {
phungductung 0:e87aa4c49e95 164 plli2sused = 1;
phungductung 0:e87aa4c49e95 165 }
phungductung 0:e87aa4c49e95 166 /* Enable the PLLSAI when it's used as clock source for SAI */
phungductung 0:e87aa4c49e95 167 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
phungductung 0:e87aa4c49e95 168 {
phungductung 0:e87aa4c49e95 169 pllsaiused = 1;
phungductung 0:e87aa4c49e95 170 }
phungductung 0:e87aa4c49e95 171 }
phungductung 0:e87aa4c49e95 172
phungductung 0:e87aa4c49e95 173 /*------------------------------------ SAI2 configuration --------------------------------------*/
phungductung 0:e87aa4c49e95 174 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
phungductung 0:e87aa4c49e95 175 {
phungductung 0:e87aa4c49e95 176 /* Check the parameters */
phungductung 0:e87aa4c49e95 177 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
phungductung 0:e87aa4c49e95 178
phungductung 0:e87aa4c49e95 179 /* Configure SAI2 Clock source */
phungductung 0:e87aa4c49e95 180 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
phungductung 0:e87aa4c49e95 181
phungductung 0:e87aa4c49e95 182 /* Enable the PLLI2S when it's used as clock source for SAI */
phungductung 0:e87aa4c49e95 183 if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
phungductung 0:e87aa4c49e95 184 {
phungductung 0:e87aa4c49e95 185 plli2sused = 1;
phungductung 0:e87aa4c49e95 186 }
phungductung 0:e87aa4c49e95 187 /* Enable the PLLSAI when it's used as clock source for SAI */
phungductung 0:e87aa4c49e95 188 if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
phungductung 0:e87aa4c49e95 189 {
phungductung 0:e87aa4c49e95 190 pllsaiused = 1;
phungductung 0:e87aa4c49e95 191 }
phungductung 0:e87aa4c49e95 192 }
phungductung 0:e87aa4c49e95 193
phungductung 0:e87aa4c49e95 194 /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 195 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
phungductung 0:e87aa4c49e95 196 {
phungductung 0:e87aa4c49e95 197 plli2sused = 1;
phungductung 0:e87aa4c49e95 198 }
phungductung 0:e87aa4c49e95 199
phungductung 0:e87aa4c49e95 200 /*------------------------------------ RTC configuration --------------------------------------*/
phungductung 0:e87aa4c49e95 201 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
phungductung 0:e87aa4c49e95 202 {
phungductung 0:e87aa4c49e95 203 /* Enable Power Clock*/
phungductung 0:e87aa4c49e95 204 __HAL_RCC_PWR_CLK_ENABLE();
phungductung 0:e87aa4c49e95 205
phungductung 0:e87aa4c49e95 206 /* Enable write access to Backup domain */
phungductung 0:e87aa4c49e95 207 PWR->CR1 |= PWR_CR1_DBP;
phungductung 0:e87aa4c49e95 208
phungductung 0:e87aa4c49e95 209 /* Get Start Tick*/
phungductung 0:e87aa4c49e95 210 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 211
phungductung 0:e87aa4c49e95 212 /* Wait for Backup domain Write protection disable */
phungductung 0:e87aa4c49e95 213 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
phungductung 0:e87aa4c49e95 214 {
phungductung 0:e87aa4c49e95 215 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
phungductung 0:e87aa4c49e95 216 {
phungductung 0:e87aa4c49e95 217 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 218 }
phungductung 0:e87aa4c49e95 219 }
phungductung 0:e87aa4c49e95 220 /* Reset the Backup domain only if the RTC Clock source selection is modified */
phungductung 0:e87aa4c49e95 221 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
phungductung 0:e87aa4c49e95 222 {
phungductung 0:e87aa4c49e95 223 /* Store the content of BDCR register before the reset of Backup Domain */
phungductung 0:e87aa4c49e95 224 tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
phungductung 0:e87aa4c49e95 225
phungductung 0:e87aa4c49e95 226 /* RTC Clock selection can be changed only if the Backup Domain is reset */
phungductung 0:e87aa4c49e95 227 __HAL_RCC_BACKUPRESET_FORCE();
phungductung 0:e87aa4c49e95 228 __HAL_RCC_BACKUPRESET_RELEASE();
phungductung 0:e87aa4c49e95 229
phungductung 0:e87aa4c49e95 230 /* Restore the Content of BDCR register */
phungductung 0:e87aa4c49e95 231 RCC->BDCR = tmpreg0;
phungductung 0:e87aa4c49e95 232
phungductung 0:e87aa4c49e95 233 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
phungductung 0:e87aa4c49e95 234 if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
phungductung 0:e87aa4c49e95 235 {
phungductung 0:e87aa4c49e95 236 /* Get Start Tick*/
phungductung 0:e87aa4c49e95 237 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 238
phungductung 0:e87aa4c49e95 239 /* Wait till LSE is ready */
phungductung 0:e87aa4c49e95 240 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
phungductung 0:e87aa4c49e95 241 {
phungductung 0:e87aa4c49e95 242 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
phungductung 0:e87aa4c49e95 243 {
phungductung 0:e87aa4c49e95 244 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 245 }
phungductung 0:e87aa4c49e95 246 }
phungductung 0:e87aa4c49e95 247 }
phungductung 0:e87aa4c49e95 248 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
phungductung 0:e87aa4c49e95 249 }
phungductung 0:e87aa4c49e95 250 }
phungductung 0:e87aa4c49e95 251
phungductung 0:e87aa4c49e95 252 /*------------------------------------ TIM configuration --------------------------------------*/
phungductung 0:e87aa4c49e95 253 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
phungductung 0:e87aa4c49e95 254 {
phungductung 0:e87aa4c49e95 255 /* Check the parameters */
phungductung 0:e87aa4c49e95 256 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
phungductung 0:e87aa4c49e95 257
phungductung 0:e87aa4c49e95 258 /* Configure Timer Prescaler */
phungductung 0:e87aa4c49e95 259 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
phungductung 0:e87aa4c49e95 260 }
phungductung 0:e87aa4c49e95 261
phungductung 0:e87aa4c49e95 262 /*-------------------------------------- I2C1 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 263 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
phungductung 0:e87aa4c49e95 264 {
phungductung 0:e87aa4c49e95 265 /* Check the parameters */
phungductung 0:e87aa4c49e95 266 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
phungductung 0:e87aa4c49e95 267
phungductung 0:e87aa4c49e95 268 /* Configure the I2C1 clock source */
phungductung 0:e87aa4c49e95 269 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
phungductung 0:e87aa4c49e95 270 }
phungductung 0:e87aa4c49e95 271
phungductung 0:e87aa4c49e95 272 /*-------------------------------------- I2C2 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 273 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
phungductung 0:e87aa4c49e95 274 {
phungductung 0:e87aa4c49e95 275 /* Check the parameters */
phungductung 0:e87aa4c49e95 276 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
phungductung 0:e87aa4c49e95 277
phungductung 0:e87aa4c49e95 278 /* Configure the I2C2 clock source */
phungductung 0:e87aa4c49e95 279 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
phungductung 0:e87aa4c49e95 280 }
phungductung 0:e87aa4c49e95 281
phungductung 0:e87aa4c49e95 282 /*-------------------------------------- I2C3 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 283 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
phungductung 0:e87aa4c49e95 284 {
phungductung 0:e87aa4c49e95 285 /* Check the parameters */
phungductung 0:e87aa4c49e95 286 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
phungductung 0:e87aa4c49e95 287
phungductung 0:e87aa4c49e95 288 /* Configure the I2C3 clock source */
phungductung 0:e87aa4c49e95 289 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
phungductung 0:e87aa4c49e95 290 }
phungductung 0:e87aa4c49e95 291
phungductung 0:e87aa4c49e95 292 /*-------------------------------------- I2C4 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 293 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
phungductung 0:e87aa4c49e95 294 {
phungductung 0:e87aa4c49e95 295 /* Check the parameters */
phungductung 0:e87aa4c49e95 296 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
phungductung 0:e87aa4c49e95 297
phungductung 0:e87aa4c49e95 298 /* Configure the I2C4 clock source */
phungductung 0:e87aa4c49e95 299 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
phungductung 0:e87aa4c49e95 300 }
phungductung 0:e87aa4c49e95 301
phungductung 0:e87aa4c49e95 302 /*-------------------------------------- USART1 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 303 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
phungductung 0:e87aa4c49e95 304 {
phungductung 0:e87aa4c49e95 305 /* Check the parameters */
phungductung 0:e87aa4c49e95 306 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
phungductung 0:e87aa4c49e95 307
phungductung 0:e87aa4c49e95 308 /* Configure the USART1 clock source */
phungductung 0:e87aa4c49e95 309 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
phungductung 0:e87aa4c49e95 310 }
phungductung 0:e87aa4c49e95 311
phungductung 0:e87aa4c49e95 312 /*-------------------------------------- USART2 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 313 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
phungductung 0:e87aa4c49e95 314 {
phungductung 0:e87aa4c49e95 315 /* Check the parameters */
phungductung 0:e87aa4c49e95 316 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
phungductung 0:e87aa4c49e95 317
phungductung 0:e87aa4c49e95 318 /* Configure the USART2 clock source */
phungductung 0:e87aa4c49e95 319 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
phungductung 0:e87aa4c49e95 320 }
phungductung 0:e87aa4c49e95 321
phungductung 0:e87aa4c49e95 322 /*-------------------------------------- USART3 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 323 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
phungductung 0:e87aa4c49e95 324 {
phungductung 0:e87aa4c49e95 325 /* Check the parameters */
phungductung 0:e87aa4c49e95 326 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
phungductung 0:e87aa4c49e95 327
phungductung 0:e87aa4c49e95 328 /* Configure the USART3 clock source */
phungductung 0:e87aa4c49e95 329 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
phungductung 0:e87aa4c49e95 330 }
phungductung 0:e87aa4c49e95 331
phungductung 0:e87aa4c49e95 332 /*-------------------------------------- UART4 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 333 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
phungductung 0:e87aa4c49e95 334 {
phungductung 0:e87aa4c49e95 335 /* Check the parameters */
phungductung 0:e87aa4c49e95 336 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
phungductung 0:e87aa4c49e95 337
phungductung 0:e87aa4c49e95 338 /* Configure the UART4 clock source */
phungductung 0:e87aa4c49e95 339 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
phungductung 0:e87aa4c49e95 340 }
phungductung 0:e87aa4c49e95 341
phungductung 0:e87aa4c49e95 342 /*-------------------------------------- UART5 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 343 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
phungductung 0:e87aa4c49e95 344 {
phungductung 0:e87aa4c49e95 345 /* Check the parameters */
phungductung 0:e87aa4c49e95 346 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
phungductung 0:e87aa4c49e95 347
phungductung 0:e87aa4c49e95 348 /* Configure the UART5 clock source */
phungductung 0:e87aa4c49e95 349 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
phungductung 0:e87aa4c49e95 350 }
phungductung 0:e87aa4c49e95 351
phungductung 0:e87aa4c49e95 352 /*-------------------------------------- USART6 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 353 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
phungductung 0:e87aa4c49e95 354 {
phungductung 0:e87aa4c49e95 355 /* Check the parameters */
phungductung 0:e87aa4c49e95 356 assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
phungductung 0:e87aa4c49e95 357
phungductung 0:e87aa4c49e95 358 /* Configure the USART6 clock source */
phungductung 0:e87aa4c49e95 359 __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
phungductung 0:e87aa4c49e95 360 }
phungductung 0:e87aa4c49e95 361
phungductung 0:e87aa4c49e95 362 /*-------------------------------------- UART7 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 363 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
phungductung 0:e87aa4c49e95 364 {
phungductung 0:e87aa4c49e95 365 /* Check the parameters */
phungductung 0:e87aa4c49e95 366 assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
phungductung 0:e87aa4c49e95 367
phungductung 0:e87aa4c49e95 368 /* Configure the UART7 clock source */
phungductung 0:e87aa4c49e95 369 __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
phungductung 0:e87aa4c49e95 370 }
phungductung 0:e87aa4c49e95 371
phungductung 0:e87aa4c49e95 372 /*-------------------------------------- UART8 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 373 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
phungductung 0:e87aa4c49e95 374 {
phungductung 0:e87aa4c49e95 375 /* Check the parameters */
phungductung 0:e87aa4c49e95 376 assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
phungductung 0:e87aa4c49e95 377
phungductung 0:e87aa4c49e95 378 /* Configure the UART8 clock source */
phungductung 0:e87aa4c49e95 379 __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
phungductung 0:e87aa4c49e95 380 }
phungductung 0:e87aa4c49e95 381
phungductung 0:e87aa4c49e95 382 /*--------------------------------------- CEC Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 383 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
phungductung 0:e87aa4c49e95 384 {
phungductung 0:e87aa4c49e95 385 /* Check the parameters */
phungductung 0:e87aa4c49e95 386 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
phungductung 0:e87aa4c49e95 387
phungductung 0:e87aa4c49e95 388 /* Configure the CEC clock source */
phungductung 0:e87aa4c49e95 389 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
phungductung 0:e87aa4c49e95 390 }
phungductung 0:e87aa4c49e95 391
phungductung 0:e87aa4c49e95 392 /*-------------------------------------- CK48 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 393 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
phungductung 0:e87aa4c49e95 394 {
phungductung 0:e87aa4c49e95 395 /* Check the parameters */
phungductung 0:e87aa4c49e95 396 assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
phungductung 0:e87aa4c49e95 397
phungductung 0:e87aa4c49e95 398 /* Configure the CLK48 source */
phungductung 0:e87aa4c49e95 399 __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
phungductung 0:e87aa4c49e95 400
phungductung 0:e87aa4c49e95 401 /* Enable the PLLSAI when it's used as clock source for CK48 */
phungductung 0:e87aa4c49e95 402 if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
phungductung 0:e87aa4c49e95 403 {
phungductung 0:e87aa4c49e95 404 pllsaiused = 1;
phungductung 0:e87aa4c49e95 405 }
phungductung 0:e87aa4c49e95 406 }
phungductung 0:e87aa4c49e95 407
phungductung 0:e87aa4c49e95 408 /*-------------------------------------- LTDC Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 409 #if defined(STM32F756xx) || defined(STM32F746xx)
phungductung 0:e87aa4c49e95 410 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
phungductung 0:e87aa4c49e95 411 {
phungductung 0:e87aa4c49e95 412 pllsaiused = 1;
phungductung 0:e87aa4c49e95 413 }
phungductung 0:e87aa4c49e95 414 #endif /* STM32F756xx || STM32F746xx */
phungductung 0:e87aa4c49e95 415 /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
phungductung 0:e87aa4c49e95 416 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
phungductung 0:e87aa4c49e95 417 {
phungductung 0:e87aa4c49e95 418 /* Check the parameters */
phungductung 0:e87aa4c49e95 419 assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
phungductung 0:e87aa4c49e95 420
phungductung 0:e87aa4c49e95 421 /* Configure the LTPIM1 clock source */
phungductung 0:e87aa4c49e95 422 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
phungductung 0:e87aa4c49e95 423 }
phungductung 0:e87aa4c49e95 424
phungductung 0:e87aa4c49e95 425 /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
phungductung 0:e87aa4c49e95 426 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
phungductung 0:e87aa4c49e95 427 {
phungductung 0:e87aa4c49e95 428 /* Check the parameters */
phungductung 0:e87aa4c49e95 429 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
phungductung 0:e87aa4c49e95 430
phungductung 0:e87aa4c49e95 431 /* Configure the SDMMC1 clock source */
phungductung 0:e87aa4c49e95 432 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
phungductung 0:e87aa4c49e95 433 }
phungductung 0:e87aa4c49e95 434
phungductung 0:e87aa4c49e95 435 /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
phungductung 0:e87aa4c49e95 436 /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
phungductung 0:e87aa4c49e95 437 if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
phungductung 0:e87aa4c49e95 438 {
phungductung 0:e87aa4c49e95 439 /* Disable the PLLI2S */
phungductung 0:e87aa4c49e95 440 __HAL_RCC_PLLI2S_DISABLE();
phungductung 0:e87aa4c49e95 441
phungductung 0:e87aa4c49e95 442 /* Get Start Tick*/
phungductung 0:e87aa4c49e95 443 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 444
phungductung 0:e87aa4c49e95 445 /* Wait till PLLI2S is disabled */
phungductung 0:e87aa4c49e95 446 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
phungductung 0:e87aa4c49e95 447 {
phungductung 0:e87aa4c49e95 448 if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
phungductung 0:e87aa4c49e95 449 {
phungductung 0:e87aa4c49e95 450 /* return in case of Timeout detected */
phungductung 0:e87aa4c49e95 451 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 452 }
phungductung 0:e87aa4c49e95 453 }
phungductung 0:e87aa4c49e95 454
phungductung 0:e87aa4c49e95 455 /* check for common PLLI2S Parameters */
phungductung 0:e87aa4c49e95 456 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
phungductung 0:e87aa4c49e95 457
phungductung 0:e87aa4c49e95 458 /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
phungductung 0:e87aa4c49e95 459 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
phungductung 0:e87aa4c49e95 460 {
phungductung 0:e87aa4c49e95 461 /* check for Parameters */
phungductung 0:e87aa4c49e95 462 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
phungductung 0:e87aa4c49e95 463
phungductung 0:e87aa4c49e95 464 /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
phungductung 0:e87aa4c49e95 465 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
phungductung 0:e87aa4c49e95 466 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
phungductung 0:e87aa4c49e95 467 /* Configure the PLLI2S division factors */
phungductung 0:e87aa4c49e95 468 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
phungductung 0:e87aa4c49e95 469 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
phungductung 0:e87aa4c49e95 470 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
phungductung 0:e87aa4c49e95 471 }
phungductung 0:e87aa4c49e95 472
phungductung 0:e87aa4c49e95 473 /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
phungductung 0:e87aa4c49e95 474 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
phungductung 0:e87aa4c49e95 475 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
phungductung 0:e87aa4c49e95 476 {
phungductung 0:e87aa4c49e95 477 /* Check for PLLI2S Parameters */
phungductung 0:e87aa4c49e95 478 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
phungductung 0:e87aa4c49e95 479 /* Check for PLLI2S/DIVQ parameters */
phungductung 0:e87aa4c49e95 480 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
phungductung 0:e87aa4c49e95 481
phungductung 0:e87aa4c49e95 482 /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
phungductung 0:e87aa4c49e95 483 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
phungductung 0:e87aa4c49e95 484 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
phungductung 0:e87aa4c49e95 485 /* Configure the PLLI2S division factors */
phungductung 0:e87aa4c49e95 486 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 487 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
phungductung 0:e87aa4c49e95 488 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
phungductung 0:e87aa4c49e95 489 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
phungductung 0:e87aa4c49e95 490
phungductung 0:e87aa4c49e95 491 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
phungductung 0:e87aa4c49e95 492 __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
phungductung 0:e87aa4c49e95 493 }
phungductung 0:e87aa4c49e95 494
phungductung 0:e87aa4c49e95 495 /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
phungductung 0:e87aa4c49e95 496 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
phungductung 0:e87aa4c49e95 497 {
phungductung 0:e87aa4c49e95 498 /* check for Parameters */
phungductung 0:e87aa4c49e95 499 assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
phungductung 0:e87aa4c49e95 500
phungductung 0:e87aa4c49e95 501 /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
phungductung 0:e87aa4c49e95 502 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
phungductung 0:e87aa4c49e95 503 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
phungductung 0:e87aa4c49e95 504 /* Configure the PLLI2S division factors */
phungductung 0:e87aa4c49e95 505 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
phungductung 0:e87aa4c49e95 506 /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
phungductung 0:e87aa4c49e95 507 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
phungductung 0:e87aa4c49e95 508 }
phungductung 0:e87aa4c49e95 509
phungductung 0:e87aa4c49e95 510 /*----------------- In Case of PLLI2S is just selected -----------------*/
phungductung 0:e87aa4c49e95 511 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
phungductung 0:e87aa4c49e95 512 {
phungductung 0:e87aa4c49e95 513 /* Check for Parameters */
phungductung 0:e87aa4c49e95 514 assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
phungductung 0:e87aa4c49e95 515 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
phungductung 0:e87aa4c49e95 516 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
phungductung 0:e87aa4c49e95 517
phungductung 0:e87aa4c49e95 518 /* Configure the PLLI2S division factors */
phungductung 0:e87aa4c49e95 519 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
phungductung 0:e87aa4c49e95 520 /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
phungductung 0:e87aa4c49e95 521 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
phungductung 0:e87aa4c49e95 522 }
phungductung 0:e87aa4c49e95 523
phungductung 0:e87aa4c49e95 524 /* Enable the PLLI2S */
phungductung 0:e87aa4c49e95 525 __HAL_RCC_PLLI2S_ENABLE();
phungductung 0:e87aa4c49e95 526
phungductung 0:e87aa4c49e95 527 /* Get Start Tick*/
phungductung 0:e87aa4c49e95 528 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 529
phungductung 0:e87aa4c49e95 530 /* Wait till PLLI2S is ready */
phungductung 0:e87aa4c49e95 531 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
phungductung 0:e87aa4c49e95 532 {
phungductung 0:e87aa4c49e95 533 if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
phungductung 0:e87aa4c49e95 534 {
phungductung 0:e87aa4c49e95 535 /* return in case of Timeout detected */
phungductung 0:e87aa4c49e95 536 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 537 }
phungductung 0:e87aa4c49e95 538 }
phungductung 0:e87aa4c49e95 539 }
phungductung 0:e87aa4c49e95 540
phungductung 0:e87aa4c49e95 541 /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
phungductung 0:e87aa4c49e95 542 /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
phungductung 0:e87aa4c49e95 543 if(pllsaiused == 1)
phungductung 0:e87aa4c49e95 544 {
phungductung 0:e87aa4c49e95 545 /* Disable PLLSAI Clock */
phungductung 0:e87aa4c49e95 546 __HAL_RCC_PLLSAI_DISABLE();
phungductung 0:e87aa4c49e95 547
phungductung 0:e87aa4c49e95 548 /* Get Start Tick*/
phungductung 0:e87aa4c49e95 549 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 550
phungductung 0:e87aa4c49e95 551 /* Wait till PLLSAI is disabled */
phungductung 0:e87aa4c49e95 552 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
phungductung 0:e87aa4c49e95 553 {
phungductung 0:e87aa4c49e95 554 if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
phungductung 0:e87aa4c49e95 555 {
phungductung 0:e87aa4c49e95 556 /* return in case of Timeout detected */
phungductung 0:e87aa4c49e95 557 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 558 }
phungductung 0:e87aa4c49e95 559 }
phungductung 0:e87aa4c49e95 560
phungductung 0:e87aa4c49e95 561 /* Check the PLLSAI division factors */
phungductung 0:e87aa4c49e95 562 assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
phungductung 0:e87aa4c49e95 563
phungductung 0:e87aa4c49e95 564 /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
phungductung 0:e87aa4c49e95 565 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
phungductung 0:e87aa4c49e95 566 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
phungductung 0:e87aa4c49e95 567 {
phungductung 0:e87aa4c49e95 568 /* check for PLLSAIQ Parameter */
phungductung 0:e87aa4c49e95 569 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
phungductung 0:e87aa4c49e95 570 /* check for PLLSAI/DIVQ Parameter */
phungductung 0:e87aa4c49e95 571 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
phungductung 0:e87aa4c49e95 572
phungductung 0:e87aa4c49e95 573 /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
phungductung 0:e87aa4c49e95 574 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
phungductung 0:e87aa4c49e95 575 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
phungductung 0:e87aa4c49e95 576 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 577 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:e87aa4c49e95 578 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
phungductung 0:e87aa4c49e95 579 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
phungductung 0:e87aa4c49e95 580
phungductung 0:e87aa4c49e95 581 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
phungductung 0:e87aa4c49e95 582 __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
phungductung 0:e87aa4c49e95 583 }
phungductung 0:e87aa4c49e95 584
phungductung 0:e87aa4c49e95 585 /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
phungductung 0:e87aa4c49e95 586 /* In Case of PLLI2S is selected as source clock for CK48 */
phungductung 0:e87aa4c49e95 587 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
phungductung 0:e87aa4c49e95 588 {
phungductung 0:e87aa4c49e95 589 /* check for Parameters */
phungductung 0:e87aa4c49e95 590 assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
phungductung 0:e87aa4c49e95 591 /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
phungductung 0:e87aa4c49e95 592 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
phungductung 0:e87aa4c49e95 593 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
phungductung 0:e87aa4c49e95 594
phungductung 0:e87aa4c49e95 595 /* Configure the PLLSAI division factors */
phungductung 0:e87aa4c49e95 596 /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
phungductung 0:e87aa4c49e95 597 /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
phungductung 0:e87aa4c49e95 598 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
phungductung 0:e87aa4c49e95 599 }
phungductung 0:e87aa4c49e95 600
phungductung 0:e87aa4c49e95 601 #if defined(STM32F756xx) || defined(STM32F746xx)
phungductung 0:e87aa4c49e95 602 /*---------------------------- LTDC configuration -------------------------------*/
phungductung 0:e87aa4c49e95 603 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
phungductung 0:e87aa4c49e95 604 {
phungductung 0:e87aa4c49e95 605 assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
phungductung 0:e87aa4c49e95 606 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
phungductung 0:e87aa4c49e95 607
phungductung 0:e87aa4c49e95 608 /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
phungductung 0:e87aa4c49e95 609 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
phungductung 0:e87aa4c49e95 610 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
phungductung 0:e87aa4c49e95 611
phungductung 0:e87aa4c49e95 612 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 613 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:e87aa4c49e95 614 /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
phungductung 0:e87aa4c49e95 615 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
phungductung 0:e87aa4c49e95 616
phungductung 0:e87aa4c49e95 617 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
phungductung 0:e87aa4c49e95 618 __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
phungductung 0:e87aa4c49e95 619 }
phungductung 0:e87aa4c49e95 620 #endif /* STM32F756xx || STM32F746xx */
phungductung 0:e87aa4c49e95 621
phungductung 0:e87aa4c49e95 622 /* Enable PLLSAI Clock */
phungductung 0:e87aa4c49e95 623 __HAL_RCC_PLLSAI_ENABLE();
phungductung 0:e87aa4c49e95 624
phungductung 0:e87aa4c49e95 625 /* Get Start Tick*/
phungductung 0:e87aa4c49e95 626 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 627
phungductung 0:e87aa4c49e95 628 /* Wait till PLLSAI is ready */
phungductung 0:e87aa4c49e95 629 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
phungductung 0:e87aa4c49e95 630 {
phungductung 0:e87aa4c49e95 631 if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
phungductung 0:e87aa4c49e95 632 {
phungductung 0:e87aa4c49e95 633 /* return in case of Timeout detected */
phungductung 0:e87aa4c49e95 634 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 635 }
phungductung 0:e87aa4c49e95 636 }
phungductung 0:e87aa4c49e95 637 }
phungductung 0:e87aa4c49e95 638 return HAL_OK;
phungductung 0:e87aa4c49e95 639 }
phungductung 0:e87aa4c49e95 640
phungductung 0:e87aa4c49e95 641 /**
phungductung 0:e87aa4c49e95 642 * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
phungductung 0:e87aa4c49e95 643 * RCC configuration registers.
phungductung 0:e87aa4c49e95 644 * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
phungductung 0:e87aa4c49e95 645 * @retval None
phungductung 0:e87aa4c49e95 646 */
phungductung 0:e87aa4c49e95 647 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
phungductung 0:e87aa4c49e95 648 {
phungductung 0:e87aa4c49e95 649 uint32_t tempreg = 0;
phungductung 0:e87aa4c49e95 650
phungductung 0:e87aa4c49e95 651 /* Set all possible values for the extended clock type parameter------------*/
phungductung 0:e87aa4c49e95 652 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
phungductung 0:e87aa4c49e95 653 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
phungductung 0:e87aa4c49e95 654 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
phungductung 0:e87aa4c49e95 655 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
phungductung 0:e87aa4c49e95 656 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
phungductung 0:e87aa4c49e95 657 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
phungductung 0:e87aa4c49e95 658 RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
phungductung 0:e87aa4c49e95 659 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
phungductung 0:e87aa4c49e95 660 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
phungductung 0:e87aa4c49e95 661 RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
phungductung 0:e87aa4c49e95 662 RCC_PERIPHCLK_CLK48;
phungductung 0:e87aa4c49e95 663
phungductung 0:e87aa4c49e95 664
phungductung 0:e87aa4c49e95 665 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
phungductung 0:e87aa4c49e95 666 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
phungductung 0:e87aa4c49e95 667 PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
phungductung 0:e87aa4c49e95 668 PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
phungductung 0:e87aa4c49e95 669 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
phungductung 0:e87aa4c49e95 670
phungductung 0:e87aa4c49e95 671 /* Get the PLLSAI Clock configuration -----------------------------------------------*/
phungductung 0:e87aa4c49e95 672 PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
phungductung 0:e87aa4c49e95 673 PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
phungductung 0:e87aa4c49e95 674 PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
phungductung 0:e87aa4c49e95 675 PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
phungductung 0:e87aa4c49e95 676
phungductung 0:e87aa4c49e95 677 /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
phungductung 0:e87aa4c49e95 678 PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
phungductung 0:e87aa4c49e95 679 PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
phungductung 0:e87aa4c49e95 680 PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
phungductung 0:e87aa4c49e95 681
phungductung 0:e87aa4c49e95 682 /* Get the SAI1 clock configuration ----------------------------------------------*/
phungductung 0:e87aa4c49e95 683 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
phungductung 0:e87aa4c49e95 684
phungductung 0:e87aa4c49e95 685 /* Get the SAI2 clock configuration ----------------------------------------------*/
phungductung 0:e87aa4c49e95 686 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
phungductung 0:e87aa4c49e95 687
phungductung 0:e87aa4c49e95 688 /* Get the I2S clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 689 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
phungductung 0:e87aa4c49e95 690
phungductung 0:e87aa4c49e95 691 /* Get the I2C1 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 692 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
phungductung 0:e87aa4c49e95 693
phungductung 0:e87aa4c49e95 694 /* Get the I2C2 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 695 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
phungductung 0:e87aa4c49e95 696
phungductung 0:e87aa4c49e95 697 /* Get the I2C3 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 698 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
phungductung 0:e87aa4c49e95 699
phungductung 0:e87aa4c49e95 700 /* Get the I2C4 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 701 PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
phungductung 0:e87aa4c49e95 702
phungductung 0:e87aa4c49e95 703 /* Get the USART1 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 704 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
phungductung 0:e87aa4c49e95 705
phungductung 0:e87aa4c49e95 706 /* Get the USART2 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 707 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
phungductung 0:e87aa4c49e95 708
phungductung 0:e87aa4c49e95 709 /* Get the USART3 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 710 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
phungductung 0:e87aa4c49e95 711
phungductung 0:e87aa4c49e95 712 /* Get the UART4 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 713 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
phungductung 0:e87aa4c49e95 714
phungductung 0:e87aa4c49e95 715 /* Get the UART5 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 716 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
phungductung 0:e87aa4c49e95 717
phungductung 0:e87aa4c49e95 718 /* Get the USART6 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 719 PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
phungductung 0:e87aa4c49e95 720
phungductung 0:e87aa4c49e95 721 /* Get the UART7 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 722 PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
phungductung 0:e87aa4c49e95 723
phungductung 0:e87aa4c49e95 724 /* Get the UART8 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 725 PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
phungductung 0:e87aa4c49e95 726
phungductung 0:e87aa4c49e95 727 /* Get the LPTIM1 clock configuration ------------------------------------------*/
phungductung 0:e87aa4c49e95 728 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
phungductung 0:e87aa4c49e95 729
phungductung 0:e87aa4c49e95 730 /* Get the CEC clock configuration -----------------------------------------------*/
phungductung 0:e87aa4c49e95 731 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
phungductung 0:e87aa4c49e95 732
phungductung 0:e87aa4c49e95 733 /* Get the CK48 clock configuration -----------------------------------------------*/
phungductung 0:e87aa4c49e95 734 PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
phungductung 0:e87aa4c49e95 735
phungductung 0:e87aa4c49e95 736 /* Get the SDMMC clock configuration -----------------------------------------------*/
phungductung 0:e87aa4c49e95 737 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
phungductung 0:e87aa4c49e95 738
phungductung 0:e87aa4c49e95 739 /* Get the RTC Clock configuration -----------------------------------------------*/
phungductung 0:e87aa4c49e95 740 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
phungductung 0:e87aa4c49e95 741 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
phungductung 0:e87aa4c49e95 742
phungductung 0:e87aa4c49e95 743 /* Get the TIM Prescaler configuration --------------------------------------------*/
phungductung 0:e87aa4c49e95 744 if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
phungductung 0:e87aa4c49e95 745 {
phungductung 0:e87aa4c49e95 746 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
phungductung 0:e87aa4c49e95 747 }
phungductung 0:e87aa4c49e95 748 else
phungductung 0:e87aa4c49e95 749 {
phungductung 0:e87aa4c49e95 750 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
phungductung 0:e87aa4c49e95 751 }
phungductung 0:e87aa4c49e95 752 }
phungductung 0:e87aa4c49e95 753
phungductung 0:e87aa4c49e95 754 /**
phungductung 0:e87aa4c49e95 755 * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
phungductung 0:e87aa4c49e95 756 * @note Return 0 if peripheral clock identifier not managed by this API
phungductung 0:e87aa4c49e95 757 * @param PeriphClk: Peripheral clock identifier
phungductung 0:e87aa4c49e95 758 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 759 * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
phungductung 0:e87aa4c49e95 760 * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
phungductung 0:e87aa4c49e95 761 * @retval Frequency in KHz
phungductung 0:e87aa4c49e95 762 */
phungductung 0:e87aa4c49e95 763 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
phungductung 0:e87aa4c49e95 764 {
phungductung 0:e87aa4c49e95 765 uint32_t tmpreg = 0;
phungductung 0:e87aa4c49e95 766 /* This variable is used to store the SAI clock frequency (value in Hz) */
phungductung 0:e87aa4c49e95 767 uint32_t frequency = 0;
phungductung 0:e87aa4c49e95 768 /* This variable is used to store the VCO Input (value in Hz) */
phungductung 0:e87aa4c49e95 769 uint32_t vcoinput = 0;
phungductung 0:e87aa4c49e95 770 /* This variable is used to store the SAI clock source */
phungductung 0:e87aa4c49e95 771 uint32_t saiclocksource = 0;
phungductung 0:e87aa4c49e95 772
phungductung 0:e87aa4c49e95 773 if (PeriphClk == RCC_PERIPHCLK_SAI1)
phungductung 0:e87aa4c49e95 774 {
phungductung 0:e87aa4c49e95 775 saiclocksource = RCC->DCKCFGR1;
phungductung 0:e87aa4c49e95 776 saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
phungductung 0:e87aa4c49e95 777 switch (saiclocksource)
phungductung 0:e87aa4c49e95 778 {
phungductung 0:e87aa4c49e95 779 case 0: /* PLLSAI is the clock source for SAI1 */
phungductung 0:e87aa4c49e95 780 {
phungductung 0:e87aa4c49e95 781 /* Configure the PLLSAI division factor */
phungductung 0:e87aa4c49e95 782 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 783 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:e87aa4c49e95 784 {
phungductung 0:e87aa4c49e95 785 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:e87aa4c49e95 786 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:e87aa4c49e95 787 }
phungductung 0:e87aa4c49e95 788 else
phungductung 0:e87aa4c49e95 789 {
phungductung 0:e87aa4c49e95 790 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:e87aa4c49e95 791 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:e87aa4c49e95 792 }
phungductung 0:e87aa4c49e95 793 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:e87aa4c49e95 794 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
phungductung 0:e87aa4c49e95 795 tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
phungductung 0:e87aa4c49e95 796 frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
phungductung 0:e87aa4c49e95 797
phungductung 0:e87aa4c49e95 798 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
phungductung 0:e87aa4c49e95 799 tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
phungductung 0:e87aa4c49e95 800 frequency = frequency/(tmpreg);
phungductung 0:e87aa4c49e95 801 break;
phungductung 0:e87aa4c49e95 802 }
phungductung 0:e87aa4c49e95 803 case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
phungductung 0:e87aa4c49e95 804 {
phungductung 0:e87aa4c49e95 805 /* Configure the PLLI2S division factor */
phungductung 0:e87aa4c49e95 806 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 807 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:e87aa4c49e95 808 {
phungductung 0:e87aa4c49e95 809 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:e87aa4c49e95 810 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:e87aa4c49e95 811 }
phungductung 0:e87aa4c49e95 812 else
phungductung 0:e87aa4c49e95 813 {
phungductung 0:e87aa4c49e95 814 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:e87aa4c49e95 815 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:e87aa4c49e95 816 }
phungductung 0:e87aa4c49e95 817
phungductung 0:e87aa4c49e95 818 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
phungductung 0:e87aa4c49e95 819 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
phungductung 0:e87aa4c49e95 820 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
phungductung 0:e87aa4c49e95 821 frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
phungductung 0:e87aa4c49e95 822
phungductung 0:e87aa4c49e95 823 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
phungductung 0:e87aa4c49e95 824 tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
phungductung 0:e87aa4c49e95 825 frequency = frequency/(tmpreg);
phungductung 0:e87aa4c49e95 826 break;
phungductung 0:e87aa4c49e95 827 }
phungductung 0:e87aa4c49e95 828 case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
phungductung 0:e87aa4c49e95 829 {
phungductung 0:e87aa4c49e95 830 frequency = EXTERNAL_CLOCK_VALUE;
phungductung 0:e87aa4c49e95 831 break;
phungductung 0:e87aa4c49e95 832 }
phungductung 0:e87aa4c49e95 833 default :
phungductung 0:e87aa4c49e95 834 {
phungductung 0:e87aa4c49e95 835 break;
phungductung 0:e87aa4c49e95 836 }
phungductung 0:e87aa4c49e95 837 }
phungductung 0:e87aa4c49e95 838 }
phungductung 0:e87aa4c49e95 839
phungductung 0:e87aa4c49e95 840 if (PeriphClk == RCC_PERIPHCLK_SAI2)
phungductung 0:e87aa4c49e95 841 {
phungductung 0:e87aa4c49e95 842 saiclocksource = RCC->DCKCFGR1;
phungductung 0:e87aa4c49e95 843 saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
phungductung 0:e87aa4c49e95 844 switch (saiclocksource)
phungductung 0:e87aa4c49e95 845 {
phungductung 0:e87aa4c49e95 846 case 0: /* PLLSAI is the clock source for SAI*/
phungductung 0:e87aa4c49e95 847 {
phungductung 0:e87aa4c49e95 848 /* Configure the PLLSAI division factor */
phungductung 0:e87aa4c49e95 849 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 850 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:e87aa4c49e95 851 {
phungductung 0:e87aa4c49e95 852 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:e87aa4c49e95 853 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:e87aa4c49e95 854 }
phungductung 0:e87aa4c49e95 855 else
phungductung 0:e87aa4c49e95 856 {
phungductung 0:e87aa4c49e95 857 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:e87aa4c49e95 858 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:e87aa4c49e95 859 }
phungductung 0:e87aa4c49e95 860 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:e87aa4c49e95 861 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
phungductung 0:e87aa4c49e95 862 tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
phungductung 0:e87aa4c49e95 863 frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
phungductung 0:e87aa4c49e95 864
phungductung 0:e87aa4c49e95 865 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
phungductung 0:e87aa4c49e95 866 tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
phungductung 0:e87aa4c49e95 867 frequency = frequency/(tmpreg);
phungductung 0:e87aa4c49e95 868 break;
phungductung 0:e87aa4c49e95 869 }
phungductung 0:e87aa4c49e95 870 case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
phungductung 0:e87aa4c49e95 871 {
phungductung 0:e87aa4c49e95 872 /* Configure the PLLI2S division factor */
phungductung 0:e87aa4c49e95 873 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:e87aa4c49e95 874 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:e87aa4c49e95 875 {
phungductung 0:e87aa4c49e95 876 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:e87aa4c49e95 877 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:e87aa4c49e95 878 }
phungductung 0:e87aa4c49e95 879 else
phungductung 0:e87aa4c49e95 880 {
phungductung 0:e87aa4c49e95 881 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:e87aa4c49e95 882 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:e87aa4c49e95 883 }
phungductung 0:e87aa4c49e95 884
phungductung 0:e87aa4c49e95 885 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
phungductung 0:e87aa4c49e95 886 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
phungductung 0:e87aa4c49e95 887 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
phungductung 0:e87aa4c49e95 888 frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
phungductung 0:e87aa4c49e95 889
phungductung 0:e87aa4c49e95 890 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
phungductung 0:e87aa4c49e95 891 tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
phungductung 0:e87aa4c49e95 892 frequency = frequency/(tmpreg);
phungductung 0:e87aa4c49e95 893 break;
phungductung 0:e87aa4c49e95 894 }
phungductung 0:e87aa4c49e95 895 case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
phungductung 0:e87aa4c49e95 896 {
phungductung 0:e87aa4c49e95 897 frequency = EXTERNAL_CLOCK_VALUE;
phungductung 0:e87aa4c49e95 898 break;
phungductung 0:e87aa4c49e95 899 }
phungductung 0:e87aa4c49e95 900 default :
phungductung 0:e87aa4c49e95 901 {
phungductung 0:e87aa4c49e95 902 break;
phungductung 0:e87aa4c49e95 903 }
phungductung 0:e87aa4c49e95 904 }
phungductung 0:e87aa4c49e95 905 }
phungductung 0:e87aa4c49e95 906
phungductung 0:e87aa4c49e95 907 return frequency;
phungductung 0:e87aa4c49e95 908 }
phungductung 0:e87aa4c49e95 909 /**
phungductung 0:e87aa4c49e95 910 * @}
phungductung 0:e87aa4c49e95 911 */
phungductung 0:e87aa4c49e95 912
phungductung 0:e87aa4c49e95 913 /**
phungductung 0:e87aa4c49e95 914 * @}
phungductung 0:e87aa4c49e95 915 */
phungductung 0:e87aa4c49e95 916
phungductung 0:e87aa4c49e95 917 #endif /* HAL_RCC_MODULE_ENABLED */
phungductung 0:e87aa4c49e95 918 /**
phungductung 0:e87aa4c49e95 919 * @}
phungductung 0:e87aa4c49e95 920 */
phungductung 0:e87aa4c49e95 921
phungductung 0:e87aa4c49e95 922 /**
phungductung 0:e87aa4c49e95 923 * @}
phungductung 0:e87aa4c49e95 924 */
phungductung 0:e87aa4c49e95 925
phungductung 0:e87aa4c49e95 926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/