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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

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phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_hal_rcc.h
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief Header file of RCC HAL module.
phungductung 0:e87aa4c49e95 8 ******************************************************************************
phungductung 0:e87aa4c49e95 9 * @attention
phungductung 0:e87aa4c49e95 10 *
phungductung 0:e87aa4c49e95 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 12 *
phungductung 0:e87aa4c49e95 13 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 14 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 15 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 16 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 18 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 19 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 21 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 22 * without specific prior written permission.
phungductung 0:e87aa4c49e95 23 *
phungductung 0:e87aa4c49e95 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 34 *
phungductung 0:e87aa4c49e95 35 ******************************************************************************
phungductung 0:e87aa4c49e95 36 */
phungductung 0:e87aa4c49e95 37
phungductung 0:e87aa4c49e95 38 /* Define to prevent recursive inclusion -------------------------------------*/
phungductung 0:e87aa4c49e95 39 #ifndef __STM32F7xx_HAL_RCC_H
phungductung 0:e87aa4c49e95 40 #define __STM32F7xx_HAL_RCC_H
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 43 extern "C" {
phungductung 0:e87aa4c49e95 44 #endif
phungductung 0:e87aa4c49e95 45
phungductung 0:e87aa4c49e95 46 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 47 #include "stm32f7xx_hal_def.h"
phungductung 0:e87aa4c49e95 48
phungductung 0:e87aa4c49e95 49 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 50 * @{
phungductung 0:e87aa4c49e95 51 */
phungductung 0:e87aa4c49e95 52
phungductung 0:e87aa4c49e95 53 /** @addtogroup RCC
phungductung 0:e87aa4c49e95 54 * @{
phungductung 0:e87aa4c49e95 55 */
phungductung 0:e87aa4c49e95 56
phungductung 0:e87aa4c49e95 57 /* Exported types ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 58
phungductung 0:e87aa4c49e95 59 /** @defgroup RCC_Exported_Types RCC Exported Types
phungductung 0:e87aa4c49e95 60 * @{
phungductung 0:e87aa4c49e95 61 */
phungductung 0:e87aa4c49e95 62
phungductung 0:e87aa4c49e95 63 /**
phungductung 0:e87aa4c49e95 64 * @brief RCC PLL configuration structure definition
phungductung 0:e87aa4c49e95 65 */
phungductung 0:e87aa4c49e95 66 typedef struct
phungductung 0:e87aa4c49e95 67 {
phungductung 0:e87aa4c49e95 68 uint32_t PLLState; /*!< The new state of the PLL.
phungductung 0:e87aa4c49e95 69 This parameter can be a value of @ref RCC_PLL_Config */
phungductung 0:e87aa4c49e95 70
phungductung 0:e87aa4c49e95 71 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
phungductung 0:e87aa4c49e95 72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
phungductung 0:e87aa4c49e95 73
phungductung 0:e87aa4c49e95 74 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
phungductung 0:e87aa4c49e95 75 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
phungductung 0:e87aa4c49e95 76
phungductung 0:e87aa4c49e95 77 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
phungductung 0:e87aa4c49e95 78 This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
phungductung 0:e87aa4c49e95 79
phungductung 0:e87aa4c49e95 80 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
phungductung 0:e87aa4c49e95 81 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
phungductung 0:e87aa4c49e95 82
phungductung 0:e87aa4c49e95 83 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
phungductung 0:e87aa4c49e95 84 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
phungductung 0:e87aa4c49e95 85
phungductung 0:e87aa4c49e95 86 }RCC_PLLInitTypeDef;
phungductung 0:e87aa4c49e95 87
phungductung 0:e87aa4c49e95 88 /**
phungductung 0:e87aa4c49e95 89 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
phungductung 0:e87aa4c49e95 90 */
phungductung 0:e87aa4c49e95 91 typedef struct
phungductung 0:e87aa4c49e95 92 {
phungductung 0:e87aa4c49e95 93 uint32_t OscillatorType; /*!< The oscillators to be configured.
phungductung 0:e87aa4c49e95 94 This parameter can be a value of @ref RCC_Oscillator_Type */
phungductung 0:e87aa4c49e95 95
phungductung 0:e87aa4c49e95 96 uint32_t HSEState; /*!< The new state of the HSE.
phungductung 0:e87aa4c49e95 97 This parameter can be a value of @ref RCC_HSE_Config */
phungductung 0:e87aa4c49e95 98
phungductung 0:e87aa4c49e95 99 uint32_t LSEState; /*!< The new state of the LSE.
phungductung 0:e87aa4c49e95 100 This parameter can be a value of @ref RCC_LSE_Config */
phungductung 0:e87aa4c49e95 101
phungductung 0:e87aa4c49e95 102 uint32_t HSIState; /*!< The new state of the HSI.
phungductung 0:e87aa4c49e95 103 This parameter can be a value of @ref RCC_HSI_Config */
phungductung 0:e87aa4c49e95 104
phungductung 0:e87aa4c49e95 105 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
phungductung 0:e87aa4c49e95 106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
phungductung 0:e87aa4c49e95 107
phungductung 0:e87aa4c49e95 108 uint32_t LSIState; /*!< The new state of the LSI.
phungductung 0:e87aa4c49e95 109 This parameter can be a value of @ref RCC_LSI_Config */
phungductung 0:e87aa4c49e95 110
phungductung 0:e87aa4c49e95 111 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
phungductung 0:e87aa4c49e95 112
phungductung 0:e87aa4c49e95 113 }RCC_OscInitTypeDef;
phungductung 0:e87aa4c49e95 114
phungductung 0:e87aa4c49e95 115 /**
phungductung 0:e87aa4c49e95 116 * @brief RCC System, AHB and APB busses clock configuration structure definition
phungductung 0:e87aa4c49e95 117 */
phungductung 0:e87aa4c49e95 118 typedef struct
phungductung 0:e87aa4c49e95 119 {
phungductung 0:e87aa4c49e95 120 uint32_t ClockType; /*!< The clock to be configured.
phungductung 0:e87aa4c49e95 121 This parameter can be a value of @ref RCC_System_Clock_Type */
phungductung 0:e87aa4c49e95 122
phungductung 0:e87aa4c49e95 123 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
phungductung 0:e87aa4c49e95 124 This parameter can be a value of @ref RCC_System_Clock_Source */
phungductung 0:e87aa4c49e95 125
phungductung 0:e87aa4c49e95 126 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
phungductung 0:e87aa4c49e95 127 This parameter can be a value of @ref RCC_AHB_Clock_Source */
phungductung 0:e87aa4c49e95 128
phungductung 0:e87aa4c49e95 129 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
phungductung 0:e87aa4c49e95 130 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
phungductung 0:e87aa4c49e95 131
phungductung 0:e87aa4c49e95 132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
phungductung 0:e87aa4c49e95 133 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
phungductung 0:e87aa4c49e95 134
phungductung 0:e87aa4c49e95 135 }RCC_ClkInitTypeDef;
phungductung 0:e87aa4c49e95 136
phungductung 0:e87aa4c49e95 137 /**
phungductung 0:e87aa4c49e95 138 * @}
phungductung 0:e87aa4c49e95 139 */
phungductung 0:e87aa4c49e95 140
phungductung 0:e87aa4c49e95 141 /* Exported constants --------------------------------------------------------*/
phungductung 0:e87aa4c49e95 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
phungductung 0:e87aa4c49e95 143 * @{
phungductung 0:e87aa4c49e95 144 */
phungductung 0:e87aa4c49e95 145
phungductung 0:e87aa4c49e95 146 /** @defgroup RCC_Oscillator_Type Oscillator Type
phungductung 0:e87aa4c49e95 147 * @{
phungductung 0:e87aa4c49e95 148 */
phungductung 0:e87aa4c49e95 149 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 150 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
phungductung 0:e87aa4c49e95 151 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
phungductung 0:e87aa4c49e95 152 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
phungductung 0:e87aa4c49e95 153 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
phungductung 0:e87aa4c49e95 154 /**
phungductung 0:e87aa4c49e95 155 * @}
phungductung 0:e87aa4c49e95 156 */
phungductung 0:e87aa4c49e95 157
phungductung 0:e87aa4c49e95 158 /** @defgroup RCC_HSE_Config RCC HSE Config
phungductung 0:e87aa4c49e95 159 * @{
phungductung 0:e87aa4c49e95 160 */
phungductung 0:e87aa4c49e95 161 #define RCC_HSE_OFF ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 162 #define RCC_HSE_ON RCC_CR_HSEON
phungductung 0:e87aa4c49e95 163 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
phungductung 0:e87aa4c49e95 164 /**
phungductung 0:e87aa4c49e95 165 * @}
phungductung 0:e87aa4c49e95 166 */
phungductung 0:e87aa4c49e95 167
phungductung 0:e87aa4c49e95 168 /** @defgroup RCC_LSE_Config RCC LSE Config
phungductung 0:e87aa4c49e95 169 * @{
phungductung 0:e87aa4c49e95 170 */
phungductung 0:e87aa4c49e95 171 #define RCC_LSE_OFF ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 172 #define RCC_LSE_ON RCC_BDCR_LSEON
phungductung 0:e87aa4c49e95 173 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
phungductung 0:e87aa4c49e95 174 /**
phungductung 0:e87aa4c49e95 175 * @}
phungductung 0:e87aa4c49e95 176 */
phungductung 0:e87aa4c49e95 177
phungductung 0:e87aa4c49e95 178 /** @defgroup RCC_HSI_Config RCC HSI Config
phungductung 0:e87aa4c49e95 179 * @{
phungductung 0:e87aa4c49e95 180 */
phungductung 0:e87aa4c49e95 181 #define RCC_HSI_OFF ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 182 #define RCC_HSI_ON RCC_CR_HSION
phungductung 0:e87aa4c49e95 183 /**
phungductung 0:e87aa4c49e95 184 * @}
phungductung 0:e87aa4c49e95 185 */
phungductung 0:e87aa4c49e95 186
phungductung 0:e87aa4c49e95 187 /** @defgroup RCC_LSI_Config RCC LSI Config
phungductung 0:e87aa4c49e95 188 * @{
phungductung 0:e87aa4c49e95 189 */
phungductung 0:e87aa4c49e95 190 #define RCC_LSI_OFF ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 191 #define RCC_LSI_ON RCC_CSR_LSION
phungductung 0:e87aa4c49e95 192 /**
phungductung 0:e87aa4c49e95 193 * @}
phungductung 0:e87aa4c49e95 194 */
phungductung 0:e87aa4c49e95 195
phungductung 0:e87aa4c49e95 196 /** @defgroup RCC_PLL_Config RCC PLL Config
phungductung 0:e87aa4c49e95 197 * @{
phungductung 0:e87aa4c49e95 198 */
phungductung 0:e87aa4c49e95 199 #define RCC_PLL_NONE ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 200 #define RCC_PLL_OFF ((uint32_t)0x00000001)
phungductung 0:e87aa4c49e95 201 #define RCC_PLL_ON ((uint32_t)0x00000002)
phungductung 0:e87aa4c49e95 202 /**
phungductung 0:e87aa4c49e95 203 * @}
phungductung 0:e87aa4c49e95 204 */
phungductung 0:e87aa4c49e95 205
phungductung 0:e87aa4c49e95 206 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
phungductung 0:e87aa4c49e95 207 * @{
phungductung 0:e87aa4c49e95 208 */
phungductung 0:e87aa4c49e95 209 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
phungductung 0:e87aa4c49e95 210 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
phungductung 0:e87aa4c49e95 211 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
phungductung 0:e87aa4c49e95 212 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
phungductung 0:e87aa4c49e95 213 /**
phungductung 0:e87aa4c49e95 214 * @}
phungductung 0:e87aa4c49e95 215 */
phungductung 0:e87aa4c49e95 216
phungductung 0:e87aa4c49e95 217 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
phungductung 0:e87aa4c49e95 218 * @{
phungductung 0:e87aa4c49e95 219 */
phungductung 0:e87aa4c49e95 220 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
phungductung 0:e87aa4c49e95 221 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
phungductung 0:e87aa4c49e95 222 /**
phungductung 0:e87aa4c49e95 223 * @}
phungductung 0:e87aa4c49e95 224 */
phungductung 0:e87aa4c49e95 225
phungductung 0:e87aa4c49e95 226 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
phungductung 0:e87aa4c49e95 227 * @{
phungductung 0:e87aa4c49e95 228 */
phungductung 0:e87aa4c49e95 229 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
phungductung 0:e87aa4c49e95 230 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
phungductung 0:e87aa4c49e95 231 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
phungductung 0:e87aa4c49e95 232 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
phungductung 0:e87aa4c49e95 233 /**
phungductung 0:e87aa4c49e95 234 * @}
phungductung 0:e87aa4c49e95 235 */
phungductung 0:e87aa4c49e95 236
phungductung 0:e87aa4c49e95 237 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
phungductung 0:e87aa4c49e95 238 * @{
phungductung 0:e87aa4c49e95 239 */
phungductung 0:e87aa4c49e95 240 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
phungductung 0:e87aa4c49e95 241 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
phungductung 0:e87aa4c49e95 242 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
phungductung 0:e87aa4c49e95 243 /**
phungductung 0:e87aa4c49e95 244 * @}
phungductung 0:e87aa4c49e95 245 */
phungductung 0:e87aa4c49e95 246
phungductung 0:e87aa4c49e95 247
phungductung 0:e87aa4c49e95 248 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
phungductung 0:e87aa4c49e95 249 * @{
phungductung 0:e87aa4c49e95 250 */
phungductung 0:e87aa4c49e95 251 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
phungductung 0:e87aa4c49e95 252 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
phungductung 0:e87aa4c49e95 253 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
phungductung 0:e87aa4c49e95 254 /**
phungductung 0:e87aa4c49e95 255 * @}
phungductung 0:e87aa4c49e95 256 */
phungductung 0:e87aa4c49e95 257
phungductung 0:e87aa4c49e95 258 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
phungductung 0:e87aa4c49e95 259 * @{
phungductung 0:e87aa4c49e95 260 */
phungductung 0:e87aa4c49e95 261 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
phungductung 0:e87aa4c49e95 262 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
phungductung 0:e87aa4c49e95 263 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
phungductung 0:e87aa4c49e95 264 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
phungductung 0:e87aa4c49e95 265 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
phungductung 0:e87aa4c49e95 266 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
phungductung 0:e87aa4c49e95 267 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
phungductung 0:e87aa4c49e95 268 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
phungductung 0:e87aa4c49e95 269 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
phungductung 0:e87aa4c49e95 270 /**
phungductung 0:e87aa4c49e95 271 * @}
phungductung 0:e87aa4c49e95 272 */
phungductung 0:e87aa4c49e95 273
phungductung 0:e87aa4c49e95 274 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
phungductung 0:e87aa4c49e95 275 * @{
phungductung 0:e87aa4c49e95 276 */
phungductung 0:e87aa4c49e95 277 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
phungductung 0:e87aa4c49e95 278 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
phungductung 0:e87aa4c49e95 279 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
phungductung 0:e87aa4c49e95 280 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
phungductung 0:e87aa4c49e95 281 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
phungductung 0:e87aa4c49e95 282 /**
phungductung 0:e87aa4c49e95 283 * @}
phungductung 0:e87aa4c49e95 284 */
phungductung 0:e87aa4c49e95 285
phungductung 0:e87aa4c49e95 286 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
phungductung 0:e87aa4c49e95 287 * @{
phungductung 0:e87aa4c49e95 288 */
phungductung 0:e87aa4c49e95 289 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
phungductung 0:e87aa4c49e95 290 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
phungductung 0:e87aa4c49e95 291 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
phungductung 0:e87aa4c49e95 292 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
phungductung 0:e87aa4c49e95 293 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
phungductung 0:e87aa4c49e95 294 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
phungductung 0:e87aa4c49e95 295 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
phungductung 0:e87aa4c49e95 296 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
phungductung 0:e87aa4c49e95 297 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
phungductung 0:e87aa4c49e95 298 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
phungductung 0:e87aa4c49e95 299 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
phungductung 0:e87aa4c49e95 300 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
phungductung 0:e87aa4c49e95 301 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
phungductung 0:e87aa4c49e95 302 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
phungductung 0:e87aa4c49e95 303 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
phungductung 0:e87aa4c49e95 304 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
phungductung 0:e87aa4c49e95 305 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
phungductung 0:e87aa4c49e95 306 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
phungductung 0:e87aa4c49e95 307 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
phungductung 0:e87aa4c49e95 308 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
phungductung 0:e87aa4c49e95 309 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
phungductung 0:e87aa4c49e95 310 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
phungductung 0:e87aa4c49e95 311 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
phungductung 0:e87aa4c49e95 312 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
phungductung 0:e87aa4c49e95 313 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
phungductung 0:e87aa4c49e95 314 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
phungductung 0:e87aa4c49e95 315 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
phungductung 0:e87aa4c49e95 316 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
phungductung 0:e87aa4c49e95 317 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
phungductung 0:e87aa4c49e95 318 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
phungductung 0:e87aa4c49e95 319 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
phungductung 0:e87aa4c49e95 320 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
phungductung 0:e87aa4c49e95 321 /**
phungductung 0:e87aa4c49e95 322 * @}
phungductung 0:e87aa4c49e95 323 */
phungductung 0:e87aa4c49e95 324
phungductung 0:e87aa4c49e95 325
phungductung 0:e87aa4c49e95 326
phungductung 0:e87aa4c49e95 327 /** @defgroup RCC_MCO_Index RCC MCO Index
phungductung 0:e87aa4c49e95 328 * @{
phungductung 0:e87aa4c49e95 329 */
phungductung 0:e87aa4c49e95 330 #define RCC_MCO1 ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 331 #define RCC_MCO2 ((uint32_t)0x00000001)
phungductung 0:e87aa4c49e95 332 /**
phungductung 0:e87aa4c49e95 333 * @}
phungductung 0:e87aa4c49e95 334 */
phungductung 0:e87aa4c49e95 335
phungductung 0:e87aa4c49e95 336 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
phungductung 0:e87aa4c49e95 337 * @{
phungductung 0:e87aa4c49e95 338 */
phungductung 0:e87aa4c49e95 339 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 340 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
phungductung 0:e87aa4c49e95 341 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
phungductung 0:e87aa4c49e95 342 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
phungductung 0:e87aa4c49e95 343 /**
phungductung 0:e87aa4c49e95 344 * @}
phungductung 0:e87aa4c49e95 345 */
phungductung 0:e87aa4c49e95 346
phungductung 0:e87aa4c49e95 347 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
phungductung 0:e87aa4c49e95 348 * @{
phungductung 0:e87aa4c49e95 349 */
phungductung 0:e87aa4c49e95 350 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 351 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
phungductung 0:e87aa4c49e95 352 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
phungductung 0:e87aa4c49e95 353 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
phungductung 0:e87aa4c49e95 354 /**
phungductung 0:e87aa4c49e95 355 * @}
phungductung 0:e87aa4c49e95 356 */
phungductung 0:e87aa4c49e95 357
phungductung 0:e87aa4c49e95 358 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
phungductung 0:e87aa4c49e95 359 * @{
phungductung 0:e87aa4c49e95 360 */
phungductung 0:e87aa4c49e95 361 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 362 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
phungductung 0:e87aa4c49e95 363 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
phungductung 0:e87aa4c49e95 364 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
phungductung 0:e87aa4c49e95 365 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
phungductung 0:e87aa4c49e95 366 /**
phungductung 0:e87aa4c49e95 367 * @}
phungductung 0:e87aa4c49e95 368 */
phungductung 0:e87aa4c49e95 369
phungductung 0:e87aa4c49e95 370 /** @defgroup RCC_Interrupt RCC Interrupt
phungductung 0:e87aa4c49e95 371 * @{
phungductung 0:e87aa4c49e95 372 */
phungductung 0:e87aa4c49e95 373 #define RCC_IT_LSIRDY ((uint8_t)0x01)
phungductung 0:e87aa4c49e95 374 #define RCC_IT_LSERDY ((uint8_t)0x02)
phungductung 0:e87aa4c49e95 375 #define RCC_IT_HSIRDY ((uint8_t)0x04)
phungductung 0:e87aa4c49e95 376 #define RCC_IT_HSERDY ((uint8_t)0x08)
phungductung 0:e87aa4c49e95 377 #define RCC_IT_PLLRDY ((uint8_t)0x10)
phungductung 0:e87aa4c49e95 378 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
phungductung 0:e87aa4c49e95 379 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
phungductung 0:e87aa4c49e95 380 #define RCC_IT_CSS ((uint8_t)0x80)
phungductung 0:e87aa4c49e95 381 /**
phungductung 0:e87aa4c49e95 382 * @}
phungductung 0:e87aa4c49e95 383 */
phungductung 0:e87aa4c49e95 384
phungductung 0:e87aa4c49e95 385 /** @defgroup RCC_Flag RCC Flags
phungductung 0:e87aa4c49e95 386 * Elements values convention: 0XXYYYYYb
phungductung 0:e87aa4c49e95 387 * - YYYYY : Flag position in the register
phungductung 0:e87aa4c49e95 388 * - 0XX : Register index
phungductung 0:e87aa4c49e95 389 * - 01: CR register
phungductung 0:e87aa4c49e95 390 * - 10: BDCR register
phungductung 0:e87aa4c49e95 391 * - 11: CSR register
phungductung 0:e87aa4c49e95 392 * @{
phungductung 0:e87aa4c49e95 393 */
phungductung 0:e87aa4c49e95 394 /* Flags in the CR register */
phungductung 0:e87aa4c49e95 395 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
phungductung 0:e87aa4c49e95 396 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
phungductung 0:e87aa4c49e95 397 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
phungductung 0:e87aa4c49e95 398 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
phungductung 0:e87aa4c49e95 399 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
phungductung 0:e87aa4c49e95 400
phungductung 0:e87aa4c49e95 401 /* Flags in the BDCR register */
phungductung 0:e87aa4c49e95 402 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
phungductung 0:e87aa4c49e95 403
phungductung 0:e87aa4c49e95 404 /* Flags in the CSR register */
phungductung 0:e87aa4c49e95 405 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
phungductung 0:e87aa4c49e95 406 #define RCC_FLAG_BORRST ((uint8_t)0x79)
phungductung 0:e87aa4c49e95 407 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
phungductung 0:e87aa4c49e95 408 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
phungductung 0:e87aa4c49e95 409 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
phungductung 0:e87aa4c49e95 410 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
phungductung 0:e87aa4c49e95 411 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
phungductung 0:e87aa4c49e95 412 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
phungductung 0:e87aa4c49e95 413 /**
phungductung 0:e87aa4c49e95 414 * @}
phungductung 0:e87aa4c49e95 415 */
phungductung 0:e87aa4c49e95 416
phungductung 0:e87aa4c49e95 417 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
phungductung 0:e87aa4c49e95 418 * @{
phungductung 0:e87aa4c49e95 419 */
phungductung 0:e87aa4c49e95 420 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 421 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
phungductung 0:e87aa4c49e95 422 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
phungductung 0:e87aa4c49e95 423 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
phungductung 0:e87aa4c49e95 424 /**
phungductung 0:e87aa4c49e95 425 * @}
phungductung 0:e87aa4c49e95 426 */
phungductung 0:e87aa4c49e95 427
phungductung 0:e87aa4c49e95 428 /**
phungductung 0:e87aa4c49e95 429 * @}
phungductung 0:e87aa4c49e95 430 */
phungductung 0:e87aa4c49e95 431
phungductung 0:e87aa4c49e95 432 /* Exported macro ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 433 /** @defgroup RCC_Exported_Macros RCC Exported Macros
phungductung 0:e87aa4c49e95 434 * @{
phungductung 0:e87aa4c49e95 435 */
phungductung 0:e87aa4c49e95 436
phungductung 0:e87aa4c49e95 437 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
phungductung 0:e87aa4c49e95 438 * @brief Enable or disable the AHB1 peripheral clock.
phungductung 0:e87aa4c49e95 439 * @note After reset, the peripheral clock (used for registers read/write access)
phungductung 0:e87aa4c49e95 440 * is disabled and the application software has to enable this clock before
phungductung 0:e87aa4c49e95 441 * using it.
phungductung 0:e87aa4c49e95 442 * @{
phungductung 0:e87aa4c49e95 443 */
phungductung 0:e87aa4c49e95 444 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
phungductung 0:e87aa4c49e95 445 __IO uint32_t tmpreg = 0x00; \
phungductung 0:e87aa4c49e95 446 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
phungductung 0:e87aa4c49e95 447 /* Delay after an RCC peripheral clock enabling */ \
phungductung 0:e87aa4c49e95 448 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
phungductung 0:e87aa4c49e95 449 UNUSED(tmpreg); \
phungductung 0:e87aa4c49e95 450 } while(0)
phungductung 0:e87aa4c49e95 451
phungductung 0:e87aa4c49e95 452 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
phungductung 0:e87aa4c49e95 453 __IO uint32_t tmpreg = 0x00; \
phungductung 0:e87aa4c49e95 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
phungductung 0:e87aa4c49e95 455 /* Delay after an RCC peripheral clock enabling */ \
phungductung 0:e87aa4c49e95 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
phungductung 0:e87aa4c49e95 457 UNUSED(tmpreg); \
phungductung 0:e87aa4c49e95 458 } while(0)
phungductung 0:e87aa4c49e95 459
phungductung 0:e87aa4c49e95 460 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
phungductung 0:e87aa4c49e95 461 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
phungductung 0:e87aa4c49e95 462
phungductung 0:e87aa4c49e95 463 /**
phungductung 0:e87aa4c49e95 464 * @}
phungductung 0:e87aa4c49e95 465 */
phungductung 0:e87aa4c49e95 466
phungductung 0:e87aa4c49e95 467 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
phungductung 0:e87aa4c49e95 468 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
phungductung 0:e87aa4c49e95 469 * @note After reset, the peripheral clock (used for registers read/write access)
phungductung 0:e87aa4c49e95 470 * is disabled and the application software has to enable this clock before
phungductung 0:e87aa4c49e95 471 * using it.
phungductung 0:e87aa4c49e95 472 * @{
phungductung 0:e87aa4c49e95 473 */
phungductung 0:e87aa4c49e95 474 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
phungductung 0:e87aa4c49e95 475 __IO uint32_t tmpreg = 0x00; \
phungductung 0:e87aa4c49e95 476 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
phungductung 0:e87aa4c49e95 477 /* Delay after an RCC peripheral clock enabling */ \
phungductung 0:e87aa4c49e95 478 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
phungductung 0:e87aa4c49e95 479 UNUSED(tmpreg); \
phungductung 0:e87aa4c49e95 480 } while(0)
phungductung 0:e87aa4c49e95 481
phungductung 0:e87aa4c49e95 482 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
phungductung 0:e87aa4c49e95 483 __IO uint32_t tmpreg = 0x00; \
phungductung 0:e87aa4c49e95 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
phungductung 0:e87aa4c49e95 485 /* Delay after an RCC peripheral clock enabling */ \
phungductung 0:e87aa4c49e95 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
phungductung 0:e87aa4c49e95 487 UNUSED(tmpreg); \
phungductung 0:e87aa4c49e95 488 } while(0)
phungductung 0:e87aa4c49e95 489
phungductung 0:e87aa4c49e95 490 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
phungductung 0:e87aa4c49e95 491 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
phungductung 0:e87aa4c49e95 492 /**
phungductung 0:e87aa4c49e95 493 * @}
phungductung 0:e87aa4c49e95 494 */
phungductung 0:e87aa4c49e95 495
phungductung 0:e87aa4c49e95 496 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
phungductung 0:e87aa4c49e95 497 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
phungductung 0:e87aa4c49e95 498 * @note After reset, the peripheral clock (used for registers read/write access)
phungductung 0:e87aa4c49e95 499 * is disabled and the application software has to enable this clock before
phungductung 0:e87aa4c49e95 500 * using it.
phungductung 0:e87aa4c49e95 501 * @{
phungductung 0:e87aa4c49e95 502 */
phungductung 0:e87aa4c49e95 503 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
phungductung 0:e87aa4c49e95 504 __IO uint32_t tmpreg = 0x00; \
phungductung 0:e87aa4c49e95 505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
phungductung 0:e87aa4c49e95 506 /* Delay after an RCC peripheral clock enabling */ \
phungductung 0:e87aa4c49e95 507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
phungductung 0:e87aa4c49e95 508 UNUSED(tmpreg); \
phungductung 0:e87aa4c49e95 509 } while(0)
phungductung 0:e87aa4c49e95 510
phungductung 0:e87aa4c49e95 511 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
phungductung 0:e87aa4c49e95 512
phungductung 0:e87aa4c49e95 513 /**
phungductung 0:e87aa4c49e95 514 * @}
phungductung 0:e87aa4c49e95 515 */
phungductung 0:e87aa4c49e95 516
phungductung 0:e87aa4c49e95 517 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
phungductung 0:e87aa4c49e95 518 * @brief Get the enable or disable status of the AHB1 peripheral clock.
phungductung 0:e87aa4c49e95 519 * @note After reset, the peripheral clock (used for registers read/write access)
phungductung 0:e87aa4c49e95 520 * is disabled and the application software has to enable this clock before
phungductung 0:e87aa4c49e95 521 * using it.
phungductung 0:e87aa4c49e95 522 * @{
phungductung 0:e87aa4c49e95 523 */
phungductung 0:e87aa4c49e95 524 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
phungductung 0:e87aa4c49e95 525 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
phungductung 0:e87aa4c49e95 526
phungductung 0:e87aa4c49e95 527 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
phungductung 0:e87aa4c49e95 528 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
phungductung 0:e87aa4c49e95 529 /**
phungductung 0:e87aa4c49e95 530 * @}
phungductung 0:e87aa4c49e95 531 */
phungductung 0:e87aa4c49e95 532
phungductung 0:e87aa4c49e95 533 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
phungductung 0:e87aa4c49e95 534 * @brief Get the enable or disable status of the APB1 peripheral clock.
phungductung 0:e87aa4c49e95 535 * @note After reset, the peripheral clock (used for registers read/write access)
phungductung 0:e87aa4c49e95 536 * is disabled and the application software has to enable this clock before
phungductung 0:e87aa4c49e95 537 * using it.
phungductung 0:e87aa4c49e95 538 * @{
phungductung 0:e87aa4c49e95 539 */
phungductung 0:e87aa4c49e95 540 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
phungductung 0:e87aa4c49e95 541 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
phungductung 0:e87aa4c49e95 542
phungductung 0:e87aa4c49e95 543 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
phungductung 0:e87aa4c49e95 544 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
phungductung 0:e87aa4c49e95 545 /**
phungductung 0:e87aa4c49e95 546 * @}
phungductung 0:e87aa4c49e95 547 */
phungductung 0:e87aa4c49e95 548
phungductung 0:e87aa4c49e95 549 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
phungductung 0:e87aa4c49e95 550 * @brief EGet the enable or disable status of the APB2 peripheral clock.
phungductung 0:e87aa4c49e95 551 * @note After reset, the peripheral clock (used for registers read/write access)
phungductung 0:e87aa4c49e95 552 * is disabled and the application software has to enable this clock before
phungductung 0:e87aa4c49e95 553 * using it.
phungductung 0:e87aa4c49e95 554 * @{
phungductung 0:e87aa4c49e95 555 */
phungductung 0:e87aa4c49e95 556 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
phungductung 0:e87aa4c49e95 557 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
phungductung 0:e87aa4c49e95 558 /**
phungductung 0:e87aa4c49e95 559 * @}
phungductung 0:e87aa4c49e95 560 */
phungductung 0:e87aa4c49e95 561
phungductung 0:e87aa4c49e95 562 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
phungductung 0:e87aa4c49e95 563 * @brief Force or release AHB peripheral reset.
phungductung 0:e87aa4c49e95 564 * @{
phungductung 0:e87aa4c49e95 565 */
phungductung 0:e87aa4c49e95 566 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
phungductung 0:e87aa4c49e95 567 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
phungductung 0:e87aa4c49e95 568 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
phungductung 0:e87aa4c49e95 569
phungductung 0:e87aa4c49e95 570 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
phungductung 0:e87aa4c49e95 571 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
phungductung 0:e87aa4c49e95 572 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
phungductung 0:e87aa4c49e95 573 /**
phungductung 0:e87aa4c49e95 574 * @}
phungductung 0:e87aa4c49e95 575 */
phungductung 0:e87aa4c49e95 576
phungductung 0:e87aa4c49e95 577 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
phungductung 0:e87aa4c49e95 578 * @brief Force or release APB1 peripheral reset.
phungductung 0:e87aa4c49e95 579 * @{
phungductung 0:e87aa4c49e95 580 */
phungductung 0:e87aa4c49e95 581 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
phungductung 0:e87aa4c49e95 582 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
phungductung 0:e87aa4c49e95 583 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
phungductung 0:e87aa4c49e95 584
phungductung 0:e87aa4c49e95 585 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
phungductung 0:e87aa4c49e95 586 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
phungductung 0:e87aa4c49e95 587 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
phungductung 0:e87aa4c49e95 588 /**
phungductung 0:e87aa4c49e95 589 * @}
phungductung 0:e87aa4c49e95 590 */
phungductung 0:e87aa4c49e95 591
phungductung 0:e87aa4c49e95 592 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
phungductung 0:e87aa4c49e95 593 * @brief Force or release APB2 peripheral reset.
phungductung 0:e87aa4c49e95 594 * @{
phungductung 0:e87aa4c49e95 595 */
phungductung 0:e87aa4c49e95 596 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
phungductung 0:e87aa4c49e95 597 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
phungductung 0:e87aa4c49e95 598
phungductung 0:e87aa4c49e95 599 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
phungductung 0:e87aa4c49e95 600 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
phungductung 0:e87aa4c49e95 601
phungductung 0:e87aa4c49e95 602 /**
phungductung 0:e87aa4c49e95 603 * @}
phungductung 0:e87aa4c49e95 604 */
phungductung 0:e87aa4c49e95 605
phungductung 0:e87aa4c49e95 606 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
phungductung 0:e87aa4c49e95 607 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
phungductung 0:e87aa4c49e95 608 * power consumption.
phungductung 0:e87aa4c49e95 609 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
phungductung 0:e87aa4c49e95 610 * @note By default, all peripheral clocks are enabled during SLEEP mode.
phungductung 0:e87aa4c49e95 611 * @{
phungductung 0:e87aa4c49e95 612 */
phungductung 0:e87aa4c49e95 613 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
phungductung 0:e87aa4c49e95 614 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
phungductung 0:e87aa4c49e95 615
phungductung 0:e87aa4c49e95 616 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
phungductung 0:e87aa4c49e95 617 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
phungductung 0:e87aa4c49e95 618
phungductung 0:e87aa4c49e95 619 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
phungductung 0:e87aa4c49e95 620 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
phungductung 0:e87aa4c49e95 621 * power consumption.
phungductung 0:e87aa4c49e95 622 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
phungductung 0:e87aa4c49e95 623 * @note By default, all peripheral clocks are enabled during SLEEP mode.
phungductung 0:e87aa4c49e95 624 */
phungductung 0:e87aa4c49e95 625 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
phungductung 0:e87aa4c49e95 626 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
phungductung 0:e87aa4c49e95 627
phungductung 0:e87aa4c49e95 628 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
phungductung 0:e87aa4c49e95 629 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
phungductung 0:e87aa4c49e95 630
phungductung 0:e87aa4c49e95 631 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
phungductung 0:e87aa4c49e95 632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
phungductung 0:e87aa4c49e95 633 * power consumption.
phungductung 0:e87aa4c49e95 634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
phungductung 0:e87aa4c49e95 635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
phungductung 0:e87aa4c49e95 636 */
phungductung 0:e87aa4c49e95 637 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
phungductung 0:e87aa4c49e95 638 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
phungductung 0:e87aa4c49e95 639
phungductung 0:e87aa4c49e95 640 /**
phungductung 0:e87aa4c49e95 641 * @}
phungductung 0:e87aa4c49e95 642 */
phungductung 0:e87aa4c49e95 643
phungductung 0:e87aa4c49e95 644 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
phungductung 0:e87aa4c49e95 645 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
phungductung 0:e87aa4c49e95 646 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
phungductung 0:e87aa4c49e95 647 * power consumption.
phungductung 0:e87aa4c49e95 648 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
phungductung 0:e87aa4c49e95 649 * @note By default, all peripheral clocks are enabled during SLEEP mode.
phungductung 0:e87aa4c49e95 650 * @{
phungductung 0:e87aa4c49e95 651 */
phungductung 0:e87aa4c49e95 652 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
phungductung 0:e87aa4c49e95 653 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
phungductung 0:e87aa4c49e95 654
phungductung 0:e87aa4c49e95 655 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
phungductung 0:e87aa4c49e95 656 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
phungductung 0:e87aa4c49e95 657 /**
phungductung 0:e87aa4c49e95 658 * @}
phungductung 0:e87aa4c49e95 659 */
phungductung 0:e87aa4c49e95 660
phungductung 0:e87aa4c49e95 661 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
phungductung 0:e87aa4c49e95 662 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
phungductung 0:e87aa4c49e95 663 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
phungductung 0:e87aa4c49e95 664 * power consumption.
phungductung 0:e87aa4c49e95 665 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
phungductung 0:e87aa4c49e95 666 * @note By default, all peripheral clocks are enabled during SLEEP mode.
phungductung 0:e87aa4c49e95 667 * @{
phungductung 0:e87aa4c49e95 668 */
phungductung 0:e87aa4c49e95 669 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
phungductung 0:e87aa4c49e95 670 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
phungductung 0:e87aa4c49e95 671
phungductung 0:e87aa4c49e95 672 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
phungductung 0:e87aa4c49e95 673 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
phungductung 0:e87aa4c49e95 674 /**
phungductung 0:e87aa4c49e95 675 * @}
phungductung 0:e87aa4c49e95 676 */
phungductung 0:e87aa4c49e95 677
phungductung 0:e87aa4c49e95 678 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
phungductung 0:e87aa4c49e95 679 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
phungductung 0:e87aa4c49e95 680 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
phungductung 0:e87aa4c49e95 681 * power consumption.
phungductung 0:e87aa4c49e95 682 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
phungductung 0:e87aa4c49e95 683 * @note By default, all peripheral clocks are enabled during SLEEP mode.
phungductung 0:e87aa4c49e95 684 * @{
phungductung 0:e87aa4c49e95 685 */
phungductung 0:e87aa4c49e95 686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
phungductung 0:e87aa4c49e95 687 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
phungductung 0:e87aa4c49e95 688 /**
phungductung 0:e87aa4c49e95 689 * @}
phungductung 0:e87aa4c49e95 690 */
phungductung 0:e87aa4c49e95 691
phungductung 0:e87aa4c49e95 692 /** @defgroup RCC_HSI_Configuration HSI Configuration
phungductung 0:e87aa4c49e95 693 * @{
phungductung 0:e87aa4c49e95 694 */
phungductung 0:e87aa4c49e95 695
phungductung 0:e87aa4c49e95 696 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
phungductung 0:e87aa4c49e95 697 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
phungductung 0:e87aa4c49e95 698 * It is used (enabled by hardware) as system clock source after startup
phungductung 0:e87aa4c49e95 699 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
phungductung 0:e87aa4c49e95 700 * of the HSE used directly or indirectly as system clock (if the Clock
phungductung 0:e87aa4c49e95 701 * Security System CSS is enabled).
phungductung 0:e87aa4c49e95 702 * @note HSI can not be stopped if it is used as system clock source. In this case,
phungductung 0:e87aa4c49e95 703 * you have to select another source of the system clock then stop the HSI.
phungductung 0:e87aa4c49e95 704 * @note After enabling the HSI, the application software should wait on HSIRDY
phungductung 0:e87aa4c49e95 705 * flag to be set indicating that HSI clock is stable and can be used as
phungductung 0:e87aa4c49e95 706 * system clock source.
phungductung 0:e87aa4c49e95 707 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
phungductung 0:e87aa4c49e95 708 * clock cycles.
phungductung 0:e87aa4c49e95 709 */
phungductung 0:e87aa4c49e95 710 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
phungductung 0:e87aa4c49e95 711 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
phungductung 0:e87aa4c49e95 712
phungductung 0:e87aa4c49e95 713 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
phungductung 0:e87aa4c49e95 714 * @note The calibration is used to compensate for the variations in voltage
phungductung 0:e87aa4c49e95 715 * and temperature that influence the frequency of the internal HSI RC.
phungductung 0:e87aa4c49e95 716 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
phungductung 0:e87aa4c49e95 717 * This parameter must be a number between 0 and 0x1F.
phungductung 0:e87aa4c49e95 718 */
phungductung 0:e87aa4c49e95 719 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
phungductung 0:e87aa4c49e95 720 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
phungductung 0:e87aa4c49e95 721 /**
phungductung 0:e87aa4c49e95 722 * @}
phungductung 0:e87aa4c49e95 723 */
phungductung 0:e87aa4c49e95 724
phungductung 0:e87aa4c49e95 725 /** @defgroup RCC_LSI_Configuration LSI Configuration
phungductung 0:e87aa4c49e95 726 * @{
phungductung 0:e87aa4c49e95 727 */
phungductung 0:e87aa4c49e95 728
phungductung 0:e87aa4c49e95 729 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
phungductung 0:e87aa4c49e95 730 * @note After enabling the LSI, the application software should wait on
phungductung 0:e87aa4c49e95 731 * LSIRDY flag to be set indicating that LSI clock is stable and can
phungductung 0:e87aa4c49e95 732 * be used to clock the IWDG and/or the RTC.
phungductung 0:e87aa4c49e95 733 * @note LSI can not be disabled if the IWDG is running.
phungductung 0:e87aa4c49e95 734 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
phungductung 0:e87aa4c49e95 735 * clock cycles.
phungductung 0:e87aa4c49e95 736 */
phungductung 0:e87aa4c49e95 737 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
phungductung 0:e87aa4c49e95 738 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
phungductung 0:e87aa4c49e95 739 /**
phungductung 0:e87aa4c49e95 740 * @}
phungductung 0:e87aa4c49e95 741 */
phungductung 0:e87aa4c49e95 742
phungductung 0:e87aa4c49e95 743 /** @defgroup RCC_HSE_Configuration HSE Configuration
phungductung 0:e87aa4c49e95 744 * @{
phungductung 0:e87aa4c49e95 745 */
phungductung 0:e87aa4c49e95 746 /**
phungductung 0:e87aa4c49e95 747 * @brief Macro to configure the External High Speed oscillator (__HSE__).
phungductung 0:e87aa4c49e95 748 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
phungductung 0:e87aa4c49e95 749 * software should wait on HSERDY flag to be set indicating that HSE clock
phungductung 0:e87aa4c49e95 750 * is stable and can be used to clock the PLL and/or system clock.
phungductung 0:e87aa4c49e95 751 * @note HSE state can not be changed if it is used directly or through the
phungductung 0:e87aa4c49e95 752 * PLL as system clock. In this case, you have to select another source
phungductung 0:e87aa4c49e95 753 * of the system clock then change the HSE state (ex. disable it).
phungductung 0:e87aa4c49e95 754 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
phungductung 0:e87aa4c49e95 755 * @note This function reset the CSSON bit, so if the clock security system(CSS)
phungductung 0:e87aa4c49e95 756 * was previously enabled you have to enable it again after calling this
phungductung 0:e87aa4c49e95 757 * function.
phungductung 0:e87aa4c49e95 758 * @param __STATE__: specifies the new state of the HSE.
phungductung 0:e87aa4c49e95 759 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 760 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
phungductung 0:e87aa4c49e95 761 * 6 HSE oscillator clock cycles.
phungductung 0:e87aa4c49e95 762 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
phungductung 0:e87aa4c49e95 763 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
phungductung 0:e87aa4c49e95 764 */
phungductung 0:e87aa4c49e95 765 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
phungductung 0:e87aa4c49e95 766 do { \
phungductung 0:e87aa4c49e95 767 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
phungductung 0:e87aa4c49e95 768 if((__STATE__) == RCC_HSE_ON) \
phungductung 0:e87aa4c49e95 769 { \
phungductung 0:e87aa4c49e95 770 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
phungductung 0:e87aa4c49e95 771 SET_BIT(RCC->CR, RCC_CR_HSEON); \
phungductung 0:e87aa4c49e95 772 } \
phungductung 0:e87aa4c49e95 773 else if((__STATE__) == RCC_HSE_BYPASS) \
phungductung 0:e87aa4c49e95 774 { \
phungductung 0:e87aa4c49e95 775 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
phungductung 0:e87aa4c49e95 776 SET_BIT(RCC->CR, RCC_CR_HSEON); \
phungductung 0:e87aa4c49e95 777 } \
phungductung 0:e87aa4c49e95 778 else \
phungductung 0:e87aa4c49e95 779 { \
phungductung 0:e87aa4c49e95 780 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
phungductung 0:e87aa4c49e95 781 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
phungductung 0:e87aa4c49e95 782 } \
phungductung 0:e87aa4c49e95 783 } while(0)
phungductung 0:e87aa4c49e95 784 /**
phungductung 0:e87aa4c49e95 785 * @}
phungductung 0:e87aa4c49e95 786 */
phungductung 0:e87aa4c49e95 787
phungductung 0:e87aa4c49e95 788 /** @defgroup RCC_LSE_Configuration LSE Configuration
phungductung 0:e87aa4c49e95 789 * @{
phungductung 0:e87aa4c49e95 790 */
phungductung 0:e87aa4c49e95 791
phungductung 0:e87aa4c49e95 792 /**
phungductung 0:e87aa4c49e95 793 * @brief Macro to configure the External Low Speed oscillator (LSE).
phungductung 0:e87aa4c49e95 794 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
phungductung 0:e87aa4c49e95 795 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
phungductung 0:e87aa4c49e95 796 * @note As the LSE is in the Backup domain and write access is denied to
phungductung 0:e87aa4c49e95 797 * this domain after reset, you have to enable write access using
phungductung 0:e87aa4c49e95 798 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
phungductung 0:e87aa4c49e95 799 * (to be done once after reset).
phungductung 0:e87aa4c49e95 800 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
phungductung 0:e87aa4c49e95 801 * software should wait on LSERDY flag to be set indicating that LSE clock
phungductung 0:e87aa4c49e95 802 * is stable and can be used to clock the RTC.
phungductung 0:e87aa4c49e95 803 * @param __STATE__: specifies the new state of the LSE.
phungductung 0:e87aa4c49e95 804 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 805 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
phungductung 0:e87aa4c49e95 806 * 6 LSE oscillator clock cycles.
phungductung 0:e87aa4c49e95 807 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
phungductung 0:e87aa4c49e95 808 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
phungductung 0:e87aa4c49e95 809 */
phungductung 0:e87aa4c49e95 810 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
phungductung 0:e87aa4c49e95 811 do { \
phungductung 0:e87aa4c49e95 812 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
phungductung 0:e87aa4c49e95 813 if((__STATE__) == RCC_LSE_ON) \
phungductung 0:e87aa4c49e95 814 { \
phungductung 0:e87aa4c49e95 815 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
phungductung 0:e87aa4c49e95 816 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
phungductung 0:e87aa4c49e95 817 } \
phungductung 0:e87aa4c49e95 818 else if((__STATE__) == RCC_LSE_BYPASS) \
phungductung 0:e87aa4c49e95 819 { \
phungductung 0:e87aa4c49e95 820 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
phungductung 0:e87aa4c49e95 821 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
phungductung 0:e87aa4c49e95 822 } \
phungductung 0:e87aa4c49e95 823 else \
phungductung 0:e87aa4c49e95 824 { \
phungductung 0:e87aa4c49e95 825 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
phungductung 0:e87aa4c49e95 826 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
phungductung 0:e87aa4c49e95 827 } \
phungductung 0:e87aa4c49e95 828 } while(0)
phungductung 0:e87aa4c49e95 829 /**
phungductung 0:e87aa4c49e95 830 * @}
phungductung 0:e87aa4c49e95 831 */
phungductung 0:e87aa4c49e95 832
phungductung 0:e87aa4c49e95 833 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
phungductung 0:e87aa4c49e95 834 * @{
phungductung 0:e87aa4c49e95 835 */
phungductung 0:e87aa4c49e95 836
phungductung 0:e87aa4c49e95 837 /** @brief Macros to enable or disable the RTC clock.
phungductung 0:e87aa4c49e95 838 * @note These macros must be used only after the RTC clock source was selected.
phungductung 0:e87aa4c49e95 839 */
phungductung 0:e87aa4c49e95 840 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
phungductung 0:e87aa4c49e95 841 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
phungductung 0:e87aa4c49e95 842
phungductung 0:e87aa4c49e95 843 /** @brief Macros to configure the RTC clock (RTCCLK).
phungductung 0:e87aa4c49e95 844 * @note As the RTC clock configuration bits are in the Backup domain and write
phungductung 0:e87aa4c49e95 845 * access is denied to this domain after reset, you have to enable write
phungductung 0:e87aa4c49e95 846 * access using the Power Backup Access macro before to configure
phungductung 0:e87aa4c49e95 847 * the RTC clock source (to be done once after reset).
phungductung 0:e87aa4c49e95 848 * @note Once the RTC clock is configured it can't be changed unless the
phungductung 0:e87aa4c49e95 849 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
phungductung 0:e87aa4c49e95 850 * a Power On Reset (POR).
phungductung 0:e87aa4c49e95 851 * @param __RTCCLKSource__: specifies the RTC clock source.
phungductung 0:e87aa4c49e95 852 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 853 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
phungductung 0:e87aa4c49e95 854 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
phungductung 0:e87aa4c49e95 855 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
phungductung 0:e87aa4c49e95 856 * as RTC clock, where x:[2,31]
phungductung 0:e87aa4c49e95 857 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
phungductung 0:e87aa4c49e95 858 * work in STOP and STANDBY modes, and can be used as wakeup source.
phungductung 0:e87aa4c49e95 859 * However, when the HSE clock is used as RTC clock source, the RTC
phungductung 0:e87aa4c49e95 860 * cannot be used in STOP and STANDBY modes.
phungductung 0:e87aa4c49e95 861 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
phungductung 0:e87aa4c49e95 862 * RTC clock source).
phungductung 0:e87aa4c49e95 863 */
phungductung 0:e87aa4c49e95 864 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
phungductung 0:e87aa4c49e95 865 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
phungductung 0:e87aa4c49e95 866
phungductung 0:e87aa4c49e95 867 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
phungductung 0:e87aa4c49e95 868 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
phungductung 0:e87aa4c49e95 869 } while (0)
phungductung 0:e87aa4c49e95 870
phungductung 0:e87aa4c49e95 871 /** @brief Macros to force or release the Backup domain reset.
phungductung 0:e87aa4c49e95 872 * @note This function resets the RTC peripheral (including the backup registers)
phungductung 0:e87aa4c49e95 873 * and the RTC clock source selection in RCC_CSR register.
phungductung 0:e87aa4c49e95 874 * @note The BKPSRAM is not affected by this reset.
phungductung 0:e87aa4c49e95 875 */
phungductung 0:e87aa4c49e95 876 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
phungductung 0:e87aa4c49e95 877 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
phungductung 0:e87aa4c49e95 878 /**
phungductung 0:e87aa4c49e95 879 * @}
phungductung 0:e87aa4c49e95 880 */
phungductung 0:e87aa4c49e95 881
phungductung 0:e87aa4c49e95 882 /** @defgroup RCC_PLL_Configuration PLL Configuration
phungductung 0:e87aa4c49e95 883 * @{
phungductung 0:e87aa4c49e95 884 */
phungductung 0:e87aa4c49e95 885
phungductung 0:e87aa4c49e95 886 /** @brief Macros to enable or disable the main PLL.
phungductung 0:e87aa4c49e95 887 * @note After enabling the main PLL, the application software should wait on
phungductung 0:e87aa4c49e95 888 * PLLRDY flag to be set indicating that PLL clock is stable and can
phungductung 0:e87aa4c49e95 889 * be used as system clock source.
phungductung 0:e87aa4c49e95 890 * @note The main PLL can not be disabled if it is used as system clock source
phungductung 0:e87aa4c49e95 891 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
phungductung 0:e87aa4c49e95 892 */
phungductung 0:e87aa4c49e95 893 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
phungductung 0:e87aa4c49e95 894 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
phungductung 0:e87aa4c49e95 895
phungductung 0:e87aa4c49e95 896
phungductung 0:e87aa4c49e95 897 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
phungductung 0:e87aa4c49e95 898 * @note This function must be used only when the main PLL is disabled.
phungductung 0:e87aa4c49e95 899 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
phungductung 0:e87aa4c49e95 900 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 901 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
phungductung 0:e87aa4c49e95 902 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
phungductung 0:e87aa4c49e95 903 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
phungductung 0:e87aa4c49e95 904 * @param __PLLM__: specifies the division factor for PLL VCO input clock
phungductung 0:e87aa4c49e95 905 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
phungductung 0:e87aa4c49e95 906 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
phungductung 0:e87aa4c49e95 907 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
phungductung 0:e87aa4c49e95 908 * of 2 MHz to limit PLL jitter.
phungductung 0:e87aa4c49e95 909 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
phungductung 0:e87aa4c49e95 910 * This parameter must be a number between Min_Data = 100 and Max_Data = 432.
phungductung 0:e87aa4c49e95 911 * @note You have to set the PLLN parameter correctly to ensure that the VCO
phungductung 0:e87aa4c49e95 912 * output frequency is between 100 and 432 MHz.
phungductung 0:e87aa4c49e95 913 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
phungductung 0:e87aa4c49e95 914 * This parameter must be a number in the range {2, 4, 6, or 8}.
phungductung 0:e87aa4c49e95 915 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
phungductung 0:e87aa4c49e95 916 * the System clock frequency.
phungductung 0:e87aa4c49e95 917 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
phungductung 0:e87aa4c49e95 918 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
phungductung 0:e87aa4c49e95 919 * @note If the USB OTG FS is used in your application, you have to set the
phungductung 0:e87aa4c49e95 920 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
phungductung 0:e87aa4c49e95 921 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
phungductung 0:e87aa4c49e95 922 * correctly.
phungductung 0:e87aa4c49e95 923 */
phungductung 0:e87aa4c49e95 924 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
phungductung 0:e87aa4c49e95 925 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
phungductung 0:e87aa4c49e95 926 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
phungductung 0:e87aa4c49e95 927 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
phungductung 0:e87aa4c49e95 928
phungductung 0:e87aa4c49e95 929 /** @brief Macro to configure the PLL clock source.
phungductung 0:e87aa4c49e95 930 * @note This function must be used only when the main PLL is disabled.
phungductung 0:e87aa4c49e95 931 * @param __PLLSOURCE__: specifies the PLL entry clock source.
phungductung 0:e87aa4c49e95 932 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 933 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
phungductung 0:e87aa4c49e95 934 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
phungductung 0:e87aa4c49e95 935 *
phungductung 0:e87aa4c49e95 936 */
phungductung 0:e87aa4c49e95 937 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
phungductung 0:e87aa4c49e95 938
phungductung 0:e87aa4c49e95 939 /** @brief Macro to configure the PLL multiplication factor.
phungductung 0:e87aa4c49e95 940 * @note This function must be used only when the main PLL is disabled.
phungductung 0:e87aa4c49e95 941 * @param __PLLM__: specifies the division factor for PLL VCO input clock
phungductung 0:e87aa4c49e95 942 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
phungductung 0:e87aa4c49e95 943 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
phungductung 0:e87aa4c49e95 944 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
phungductung 0:e87aa4c49e95 945 * of 2 MHz to limit PLL jitter.
phungductung 0:e87aa4c49e95 946 *
phungductung 0:e87aa4c49e95 947 */
phungductung 0:e87aa4c49e95 948 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
phungductung 0:e87aa4c49e95 949 /**
phungductung 0:e87aa4c49e95 950 * @}
phungductung 0:e87aa4c49e95 951 */
phungductung 0:e87aa4c49e95 952
phungductung 0:e87aa4c49e95 953 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
phungductung 0:e87aa4c49e95 954 * @{
phungductung 0:e87aa4c49e95 955 */
phungductung 0:e87aa4c49e95 956
phungductung 0:e87aa4c49e95 957 /** @brief Macro to configure the I2S clock source (I2SCLK).
phungductung 0:e87aa4c49e95 958 * @note This function must be called before enabling the I2S APB clock.
phungductung 0:e87aa4c49e95 959 * @param __SOURCE__: specifies the I2S clock source.
phungductung 0:e87aa4c49e95 960 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 961 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
phungductung 0:e87aa4c49e95 962 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
phungductung 0:e87aa4c49e95 963 * used as I2S clock source.
phungductung 0:e87aa4c49e95 964 */
phungductung 0:e87aa4c49e95 965 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
phungductung 0:e87aa4c49e95 966 RCC->CFGR |= (__SOURCE__); \
phungductung 0:e87aa4c49e95 967 }while(0)
phungductung 0:e87aa4c49e95 968
phungductung 0:e87aa4c49e95 969 /** @brief Macros to enable or disable the PLLI2S.
phungductung 0:e87aa4c49e95 970 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
phungductung 0:e87aa4c49e95 971 */
phungductung 0:e87aa4c49e95 972 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
phungductung 0:e87aa4c49e95 973 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
phungductung 0:e87aa4c49e95 974 /**
phungductung 0:e87aa4c49e95 975 * @}
phungductung 0:e87aa4c49e95 976 */
phungductung 0:e87aa4c49e95 977
phungductung 0:e87aa4c49e95 978 /** @defgroup RCC_Get_Clock_source Get Clock source
phungductung 0:e87aa4c49e95 979 * @{
phungductung 0:e87aa4c49e95 980 */
phungductung 0:e87aa4c49e95 981 /**
phungductung 0:e87aa4c49e95 982 * @brief Macro to configure the system clock source.
phungductung 0:e87aa4c49e95 983 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
phungductung 0:e87aa4c49e95 984 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 985 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
phungductung 0:e87aa4c49e95 986 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
phungductung 0:e87aa4c49e95 987 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
phungductung 0:e87aa4c49e95 988 */
phungductung 0:e87aa4c49e95 989 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
phungductung 0:e87aa4c49e95 990
phungductung 0:e87aa4c49e95 991 /** @brief Macro to get the clock source used as system clock.
phungductung 0:e87aa4c49e95 992 * @retval The clock source used as system clock. The returned value can be one
phungductung 0:e87aa4c49e95 993 * of the following:
phungductung 0:e87aa4c49e95 994 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
phungductung 0:e87aa4c49e95 995 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
phungductung 0:e87aa4c49e95 996 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
phungductung 0:e87aa4c49e95 997 */
phungductung 0:e87aa4c49e95 998 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
phungductung 0:e87aa4c49e95 999
phungductung 0:e87aa4c49e95 1000 /**
phungductung 0:e87aa4c49e95 1001 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
phungductung 0:e87aa4c49e95 1002 * @note As the LSE is in the Backup domain and write access is denied to
phungductung 0:e87aa4c49e95 1003 * this domain after reset, you have to enable write access using
phungductung 0:e87aa4c49e95 1004 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
phungductung 0:e87aa4c49e95 1005 * (to be done once after reset).
phungductung 0:e87aa4c49e95 1006 * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
phungductung 0:e87aa4c49e95 1007 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1008 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
phungductung 0:e87aa4c49e95 1009 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
phungductung 0:e87aa4c49e95 1010 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
phungductung 0:e87aa4c49e95 1011 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
phungductung 0:e87aa4c49e95 1012 * @retval None
phungductung 0:e87aa4c49e95 1013 */
phungductung 0:e87aa4c49e95 1014 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
phungductung 0:e87aa4c49e95 1015 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
phungductung 0:e87aa4c49e95 1016
phungductung 0:e87aa4c49e95 1017 /** @brief Macro to get the oscillator used as PLL clock source.
phungductung 0:e87aa4c49e95 1018 * @retval The oscillator used as PLL clock source. The returned value can be one
phungductung 0:e87aa4c49e95 1019 * of the following:
phungductung 0:e87aa4c49e95 1020 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
phungductung 0:e87aa4c49e95 1021 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
phungductung 0:e87aa4c49e95 1022 */
phungductung 0:e87aa4c49e95 1023 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
phungductung 0:e87aa4c49e95 1024 /**
phungductung 0:e87aa4c49e95 1025 * @}
phungductung 0:e87aa4c49e95 1026 */
phungductung 0:e87aa4c49e95 1027
phungductung 0:e87aa4c49e95 1028 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
phungductung 0:e87aa4c49e95 1029 * @{
phungductung 0:e87aa4c49e95 1030 */
phungductung 0:e87aa4c49e95 1031
phungductung 0:e87aa4c49e95 1032 /** @brief Macro to configure the MCO1 clock.
phungductung 0:e87aa4c49e95 1033 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
phungductung 0:e87aa4c49e95 1034 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1035 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
phungductung 0:e87aa4c49e95 1036 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
phungductung 0:e87aa4c49e95 1037 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
phungductung 0:e87aa4c49e95 1038 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
phungductung 0:e87aa4c49e95 1039 * @param __MCODIV__ specifies the MCO clock prescaler.
phungductung 0:e87aa4c49e95 1040 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1041 * @arg RCC_MCODIV_1: no division applied to MCOx clock
phungductung 0:e87aa4c49e95 1042 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
phungductung 0:e87aa4c49e95 1043 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
phungductung 0:e87aa4c49e95 1044 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
phungductung 0:e87aa4c49e95 1045 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
phungductung 0:e87aa4c49e95 1046 */
phungductung 0:e87aa4c49e95 1047
phungductung 0:e87aa4c49e95 1048 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
phungductung 0:e87aa4c49e95 1049 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
phungductung 0:e87aa4c49e95 1050
phungductung 0:e87aa4c49e95 1051 /** @brief Macro to configure the MCO2 clock.
phungductung 0:e87aa4c49e95 1052 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
phungductung 0:e87aa4c49e95 1053 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1054 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
phungductung 0:e87aa4c49e95 1055 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
phungductung 0:e87aa4c49e95 1056 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
phungductung 0:e87aa4c49e95 1057 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
phungductung 0:e87aa4c49e95 1058 * @param __MCODIV__ specifies the MCO clock prescaler.
phungductung 0:e87aa4c49e95 1059 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1060 * @arg RCC_MCODIV_1: no division applied to MCOx clock
phungductung 0:e87aa4c49e95 1061 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
phungductung 0:e87aa4c49e95 1062 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
phungductung 0:e87aa4c49e95 1063 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
phungductung 0:e87aa4c49e95 1064 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
phungductung 0:e87aa4c49e95 1065 */
phungductung 0:e87aa4c49e95 1066
phungductung 0:e87aa4c49e95 1067 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
phungductung 0:e87aa4c49e95 1068 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
phungductung 0:e87aa4c49e95 1069 /**
phungductung 0:e87aa4c49e95 1070 * @}
phungductung 0:e87aa4c49e95 1071 */
phungductung 0:e87aa4c49e95 1072
phungductung 0:e87aa4c49e95 1073 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
phungductung 0:e87aa4c49e95 1074 * @brief macros to manage the specified RCC Flags and interrupts.
phungductung 0:e87aa4c49e95 1075 * @{
phungductung 0:e87aa4c49e95 1076 */
phungductung 0:e87aa4c49e95 1077
phungductung 0:e87aa4c49e95 1078 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
phungductung 0:e87aa4c49e95 1079 * the selected interrupts).
phungductung 0:e87aa4c49e95 1080 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
phungductung 0:e87aa4c49e95 1081 * This parameter can be any combination of the following values:
phungductung 0:e87aa4c49e95 1082 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
phungductung 0:e87aa4c49e95 1083 * @arg RCC_IT_LSERDY: LSE ready interrupt.
phungductung 0:e87aa4c49e95 1084 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
phungductung 0:e87aa4c49e95 1085 * @arg RCC_IT_HSERDY: HSE ready interrupt.
phungductung 0:e87aa4c49e95 1086 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
phungductung 0:e87aa4c49e95 1087 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
phungductung 0:e87aa4c49e95 1088 */
phungductung 0:e87aa4c49e95 1089 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
phungductung 0:e87aa4c49e95 1090
phungductung 0:e87aa4c49e95 1091 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
phungductung 0:e87aa4c49e95 1092 * the selected interrupts).
phungductung 0:e87aa4c49e95 1093 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
phungductung 0:e87aa4c49e95 1094 * This parameter can be any combination of the following values:
phungductung 0:e87aa4c49e95 1095 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
phungductung 0:e87aa4c49e95 1096 * @arg RCC_IT_LSERDY: LSE ready interrupt.
phungductung 0:e87aa4c49e95 1097 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
phungductung 0:e87aa4c49e95 1098 * @arg RCC_IT_HSERDY: HSE ready interrupt.
phungductung 0:e87aa4c49e95 1099 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
phungductung 0:e87aa4c49e95 1100 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
phungductung 0:e87aa4c49e95 1101 */
phungductung 0:e87aa4c49e95 1102 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
phungductung 0:e87aa4c49e95 1103
phungductung 0:e87aa4c49e95 1104 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
phungductung 0:e87aa4c49e95 1105 * bits to clear the selected interrupt pending bits.
phungductung 0:e87aa4c49e95 1106 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
phungductung 0:e87aa4c49e95 1107 * This parameter can be any combination of the following values:
phungductung 0:e87aa4c49e95 1108 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
phungductung 0:e87aa4c49e95 1109 * @arg RCC_IT_LSERDY: LSE ready interrupt.
phungductung 0:e87aa4c49e95 1110 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
phungductung 0:e87aa4c49e95 1111 * @arg RCC_IT_HSERDY: HSE ready interrupt.
phungductung 0:e87aa4c49e95 1112 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
phungductung 0:e87aa4c49e95 1113 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
phungductung 0:e87aa4c49e95 1114 * @arg RCC_IT_CSS: Clock Security System interrupt
phungductung 0:e87aa4c49e95 1115 */
phungductung 0:e87aa4c49e95 1116 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
phungductung 0:e87aa4c49e95 1117
phungductung 0:e87aa4c49e95 1118 /** @brief Check the RCC's interrupt has occurred or not.
phungductung 0:e87aa4c49e95 1119 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
phungductung 0:e87aa4c49e95 1120 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1121 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
phungductung 0:e87aa4c49e95 1122 * @arg RCC_IT_LSERDY: LSE ready interrupt.
phungductung 0:e87aa4c49e95 1123 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
phungductung 0:e87aa4c49e95 1124 * @arg RCC_IT_HSERDY: HSE ready interrupt.
phungductung 0:e87aa4c49e95 1125 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
phungductung 0:e87aa4c49e95 1126 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
phungductung 0:e87aa4c49e95 1127 * @arg RCC_IT_CSS: Clock Security System interrupt
phungductung 0:e87aa4c49e95 1128 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
phungductung 0:e87aa4c49e95 1129 */
phungductung 0:e87aa4c49e95 1130 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
phungductung 0:e87aa4c49e95 1131
phungductung 0:e87aa4c49e95 1132 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
phungductung 0:e87aa4c49e95 1133 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
phungductung 0:e87aa4c49e95 1134 */
phungductung 0:e87aa4c49e95 1135 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
phungductung 0:e87aa4c49e95 1136
phungductung 0:e87aa4c49e95 1137 /** @brief Check RCC flag is set or not.
phungductung 0:e87aa4c49e95 1138 * @param __FLAG__: specifies the flag to check.
phungductung 0:e87aa4c49e95 1139 * This parameter can be one of the following values:
phungductung 0:e87aa4c49e95 1140 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
phungductung 0:e87aa4c49e95 1141 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
phungductung 0:e87aa4c49e95 1142 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
phungductung 0:e87aa4c49e95 1143 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
phungductung 0:e87aa4c49e95 1144 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
phungductung 0:e87aa4c49e95 1145 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
phungductung 0:e87aa4c49e95 1146 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
phungductung 0:e87aa4c49e95 1147 * @arg RCC_FLAG_PINRST: Pin reset.
phungductung 0:e87aa4c49e95 1148 * @arg RCC_FLAG_PORRST: POR/PDR reset.
phungductung 0:e87aa4c49e95 1149 * @arg RCC_FLAG_SFTRST: Software reset.
phungductung 0:e87aa4c49e95 1150 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
phungductung 0:e87aa4c49e95 1151 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
phungductung 0:e87aa4c49e95 1152 * @arg RCC_FLAG_LPWRRST: Low Power reset.
phungductung 0:e87aa4c49e95 1153 * @retval The new state of __FLAG__ (TRUE or FALSE).
phungductung 0:e87aa4c49e95 1154 */
phungductung 0:e87aa4c49e95 1155 #define RCC_FLAG_MASK ((uint8_t)0x1F)
phungductung 0:e87aa4c49e95 1156 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
phungductung 0:e87aa4c49e95 1157
phungductung 0:e87aa4c49e95 1158 /**
phungductung 0:e87aa4c49e95 1159 * @}
phungductung 0:e87aa4c49e95 1160 */
phungductung 0:e87aa4c49e95 1161
phungductung 0:e87aa4c49e95 1162 /**
phungductung 0:e87aa4c49e95 1163 * @}
phungductung 0:e87aa4c49e95 1164 */
phungductung 0:e87aa4c49e95 1165
phungductung 0:e87aa4c49e95 1166 /* Include RCC HAL Extension module */
phungductung 0:e87aa4c49e95 1167 #include "stm32f7xx_hal_rcc_ex.h"
phungductung 0:e87aa4c49e95 1168
phungductung 0:e87aa4c49e95 1169 /* Exported functions --------------------------------------------------------*/
phungductung 0:e87aa4c49e95 1170 /** @addtogroup RCC_Exported_Functions
phungductung 0:e87aa4c49e95 1171 * @{
phungductung 0:e87aa4c49e95 1172 */
phungductung 0:e87aa4c49e95 1173
phungductung 0:e87aa4c49e95 1174 /** @addtogroup RCC_Exported_Functions_Group1
phungductung 0:e87aa4c49e95 1175 * @{
phungductung 0:e87aa4c49e95 1176 */
phungductung 0:e87aa4c49e95 1177 /* Initialization and de-initialization functions ******************************/
phungductung 0:e87aa4c49e95 1178 void HAL_RCC_DeInit(void);
phungductung 0:e87aa4c49e95 1179 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
phungductung 0:e87aa4c49e95 1180 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
phungductung 0:e87aa4c49e95 1181 /**
phungductung 0:e87aa4c49e95 1182 * @}
phungductung 0:e87aa4c49e95 1183 */
phungductung 0:e87aa4c49e95 1184
phungductung 0:e87aa4c49e95 1185 /** @addtogroup RCC_Exported_Functions_Group2
phungductung 0:e87aa4c49e95 1186 * @{
phungductung 0:e87aa4c49e95 1187 */
phungductung 0:e87aa4c49e95 1188 /* Peripheral Control functions ************************************************/
phungductung 0:e87aa4c49e95 1189 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
phungductung 0:e87aa4c49e95 1190 void HAL_RCC_EnableCSS(void);
phungductung 0:e87aa4c49e95 1191 void HAL_RCC_DisableCSS(void);
phungductung 0:e87aa4c49e95 1192 uint32_t HAL_RCC_GetSysClockFreq(void);
phungductung 0:e87aa4c49e95 1193 uint32_t HAL_RCC_GetHCLKFreq(void);
phungductung 0:e87aa4c49e95 1194 uint32_t HAL_RCC_GetPCLK1Freq(void);
phungductung 0:e87aa4c49e95 1195 uint32_t HAL_RCC_GetPCLK2Freq(void);
phungductung 0:e87aa4c49e95 1196 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
phungductung 0:e87aa4c49e95 1197 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
phungductung 0:e87aa4c49e95 1198
phungductung 0:e87aa4c49e95 1199 /* CSS NMI IRQ handler */
phungductung 0:e87aa4c49e95 1200 void HAL_RCC_NMI_IRQHandler(void);
phungductung 0:e87aa4c49e95 1201
phungductung 0:e87aa4c49e95 1202 /* User Callbacks in non blocking mode (IT mode) */
phungductung 0:e87aa4c49e95 1203 void HAL_RCC_CSSCallback(void);
phungductung 0:e87aa4c49e95 1204 /**
phungductung 0:e87aa4c49e95 1205 * @}
phungductung 0:e87aa4c49e95 1206 */
phungductung 0:e87aa4c49e95 1207
phungductung 0:e87aa4c49e95 1208 /**
phungductung 0:e87aa4c49e95 1209 * @}
phungductung 0:e87aa4c49e95 1210 */
phungductung 0:e87aa4c49e95 1211
phungductung 0:e87aa4c49e95 1212 /* Private types -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 1213 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 1214 /* Private constants ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 1215 /** @defgroup RCC_Private_Constants RCC Private Constants
phungductung 0:e87aa4c49e95 1216 * @{
phungductung 0:e87aa4c49e95 1217 */
phungductung 0:e87aa4c49e95 1218 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
phungductung 0:e87aa4c49e95 1219 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
phungductung 0:e87aa4c49e95 1220 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
phungductung 0:e87aa4c49e95 1221 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
phungductung 0:e87aa4c49e95 1222 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
phungductung 0:e87aa4c49e95 1223
phungductung 0:e87aa4c49e95 1224 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
phungductung 0:e87aa4c49e95 1225 * @brief RCC registers bit address alias
phungductung 0:e87aa4c49e95 1226 * @{
phungductung 0:e87aa4c49e95 1227 */
phungductung 0:e87aa4c49e95 1228 /* CIR register byte 2 (Bits[15:8]) base address */
phungductung 0:e87aa4c49e95 1229 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
phungductung 0:e87aa4c49e95 1230
phungductung 0:e87aa4c49e95 1231 /* CIR register byte 3 (Bits[23:16]) base address */
phungductung 0:e87aa4c49e95 1232 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
phungductung 0:e87aa4c49e95 1233
phungductung 0:e87aa4c49e95 1234 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
phungductung 0:e87aa4c49e95 1235 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
phungductung 0:e87aa4c49e95 1236 /**
phungductung 0:e87aa4c49e95 1237 * @}
phungductung 0:e87aa4c49e95 1238 */
phungductung 0:e87aa4c49e95 1239 /**
phungductung 0:e87aa4c49e95 1240 * @}
phungductung 0:e87aa4c49e95 1241 */
phungductung 0:e87aa4c49e95 1242
phungductung 0:e87aa4c49e95 1243 /* Private macros ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 1244 /** @addtogroup RCC_Private_Macros RCC Private Macros
phungductung 0:e87aa4c49e95 1245 * @{
phungductung 0:e87aa4c49e95 1246 */
phungductung 0:e87aa4c49e95 1247
phungductung 0:e87aa4c49e95 1248 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
phungductung 0:e87aa4c49e95 1249 * @{
phungductung 0:e87aa4c49e95 1250 */
phungductung 0:e87aa4c49e95 1251 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
phungductung 0:e87aa4c49e95 1252
phungductung 0:e87aa4c49e95 1253 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
phungductung 0:e87aa4c49e95 1254 ((HSE) == RCC_HSE_BYPASS))
phungductung 0:e87aa4c49e95 1255
phungductung 0:e87aa4c49e95 1256 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
phungductung 0:e87aa4c49e95 1257 ((LSE) == RCC_LSE_BYPASS))
phungductung 0:e87aa4c49e95 1258
phungductung 0:e87aa4c49e95 1259 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
phungductung 0:e87aa4c49e95 1260
phungductung 0:e87aa4c49e95 1261 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
phungductung 0:e87aa4c49e95 1262
phungductung 0:e87aa4c49e95 1263 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
phungductung 0:e87aa4c49e95 1264
phungductung 0:e87aa4c49e95 1265 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
phungductung 0:e87aa4c49e95 1266 ((SOURCE) == RCC_PLLSOURCE_HSE))
phungductung 0:e87aa4c49e95 1267
phungductung 0:e87aa4c49e95 1268 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
phungductung 0:e87aa4c49e95 1269 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
phungductung 0:e87aa4c49e95 1270 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
phungductung 0:e87aa4c49e95 1271 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
phungductung 0:e87aa4c49e95 1272
phungductung 0:e87aa4c49e95 1273 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
phungductung 0:e87aa4c49e95 1274
phungductung 0:e87aa4c49e95 1275 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
phungductung 0:e87aa4c49e95 1276 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
phungductung 0:e87aa4c49e95 1277 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
phungductung 0:e87aa4c49e95 1278
phungductung 0:e87aa4c49e95 1279 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
phungductung 0:e87aa4c49e95 1280 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
phungductung 0:e87aa4c49e95 1281 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
phungductung 0:e87aa4c49e95 1282 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
phungductung 0:e87aa4c49e95 1283 ((HCLK) == RCC_SYSCLK_DIV512))
phungductung 0:e87aa4c49e95 1284
phungductung 0:e87aa4c49e95 1285 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
phungductung 0:e87aa4c49e95 1286
phungductung 0:e87aa4c49e95 1287 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
phungductung 0:e87aa4c49e95 1288 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
phungductung 0:e87aa4c49e95 1289 ((PCLK) == RCC_HCLK_DIV16))
phungductung 0:e87aa4c49e95 1290
phungductung 0:e87aa4c49e95 1291 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
phungductung 0:e87aa4c49e95 1292
phungductung 0:e87aa4c49e95 1293
phungductung 0:e87aa4c49e95 1294 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
phungductung 0:e87aa4c49e95 1295 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
phungductung 0:e87aa4c49e95 1296
phungductung 0:e87aa4c49e95 1297 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
phungductung 0:e87aa4c49e95 1298 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
phungductung 0:e87aa4c49e95 1299
phungductung 0:e87aa4c49e95 1300 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
phungductung 0:e87aa4c49e95 1301 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
phungductung 0:e87aa4c49e95 1302 ((DIV) == RCC_MCODIV_5))
phungductung 0:e87aa4c49e95 1303 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
phungductung 0:e87aa4c49e95 1304
phungductung 0:e87aa4c49e95 1305 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
phungductung 0:e87aa4c49e95 1306 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
phungductung 0:e87aa4c49e95 1307 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
phungductung 0:e87aa4c49e95 1308 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
phungductung 0:e87aa4c49e95 1309 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
phungductung 0:e87aa4c49e95 1310 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
phungductung 0:e87aa4c49e95 1311 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
phungductung 0:e87aa4c49e95 1312 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
phungductung 0:e87aa4c49e95 1313 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
phungductung 0:e87aa4c49e95 1314 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
phungductung 0:e87aa4c49e95 1315 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
phungductung 0:e87aa4c49e95 1316 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
phungductung 0:e87aa4c49e95 1317 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
phungductung 0:e87aa4c49e95 1318 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
phungductung 0:e87aa4c49e95 1319 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
phungductung 0:e87aa4c49e95 1320 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
phungductung 0:e87aa4c49e95 1321
phungductung 0:e87aa4c49e95 1322
phungductung 0:e87aa4c49e95 1323 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
phungductung 0:e87aa4c49e95 1324 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
phungductung 0:e87aa4c49e95 1325 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
phungductung 0:e87aa4c49e95 1326 ((DRIVE) == RCC_LSEDRIVE_HIGH))
phungductung 0:e87aa4c49e95 1327 /**
phungductung 0:e87aa4c49e95 1328 * @}
phungductung 0:e87aa4c49e95 1329 */
phungductung 0:e87aa4c49e95 1330
phungductung 0:e87aa4c49e95 1331 /**
phungductung 0:e87aa4c49e95 1332 * @}
phungductung 0:e87aa4c49e95 1333 */
phungductung 0:e87aa4c49e95 1334
phungductung 0:e87aa4c49e95 1335 /**
phungductung 0:e87aa4c49e95 1336 * @}
phungductung 0:e87aa4c49e95 1337 */
phungductung 0:e87aa4c49e95 1338
phungductung 0:e87aa4c49e95 1339 /**
phungductung 0:e87aa4c49e95 1340 * @}
phungductung 0:e87aa4c49e95 1341 */
phungductung 0:e87aa4c49e95 1342
phungductung 0:e87aa4c49e95 1343 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 1344 }
phungductung 0:e87aa4c49e95 1345 #endif
phungductung 0:e87aa4c49e95 1346
phungductung 0:e87aa4c49e95 1347 #endif /* __STM32F7xx_HAL_RCC_H */
phungductung 0:e87aa4c49e95 1348
phungductung 0:e87aa4c49e95 1349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/