PHung Tung / SRC_STM32F7

SPKT

Dependents:   WAV

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

Who changed what in which revision?

UserRevisionLine numberNew contents of line
phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_hal_nand.h
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief Header file of NAND HAL module.
phungductung 0:e87aa4c49e95 8 ******************************************************************************
phungductung 0:e87aa4c49e95 9 * @attention
phungductung 0:e87aa4c49e95 10 *
phungductung 0:e87aa4c49e95 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 12 *
phungductung 0:e87aa4c49e95 13 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 14 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 15 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 16 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 18 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 19 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 21 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 22 * without specific prior written permission.
phungductung 0:e87aa4c49e95 23 *
phungductung 0:e87aa4c49e95 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 34 *
phungductung 0:e87aa4c49e95 35 ******************************************************************************
phungductung 0:e87aa4c49e95 36 */
phungductung 0:e87aa4c49e95 37
phungductung 0:e87aa4c49e95 38 /* Define to prevent recursive inclusion -------------------------------------*/
phungductung 0:e87aa4c49e95 39 #ifndef __STM32F7xx_HAL_NAND_H
phungductung 0:e87aa4c49e95 40 #define __STM32F7xx_HAL_NAND_H
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 43 extern "C" {
phungductung 0:e87aa4c49e95 44 #endif
phungductung 0:e87aa4c49e95 45
phungductung 0:e87aa4c49e95 46 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 47 #include "stm32f7xx_ll_fmc.h"
phungductung 0:e87aa4c49e95 48
phungductung 0:e87aa4c49e95 49 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 50 * @{
phungductung 0:e87aa4c49e95 51 */
phungductung 0:e87aa4c49e95 52
phungductung 0:e87aa4c49e95 53 /** @addtogroup NAND
phungductung 0:e87aa4c49e95 54 * @{
phungductung 0:e87aa4c49e95 55 */
phungductung 0:e87aa4c49e95 56
phungductung 0:e87aa4c49e95 57 /* Exported typedef ----------------------------------------------------------*/
phungductung 0:e87aa4c49e95 58 /* Exported types ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 59 /** @defgroup NAND_Exported_Types NAND Exported Types
phungductung 0:e87aa4c49e95 60 * @{
phungductung 0:e87aa4c49e95 61 */
phungductung 0:e87aa4c49e95 62
phungductung 0:e87aa4c49e95 63 /**
phungductung 0:e87aa4c49e95 64 * @brief HAL NAND State structures definition
phungductung 0:e87aa4c49e95 65 */
phungductung 0:e87aa4c49e95 66 typedef enum
phungductung 0:e87aa4c49e95 67 {
phungductung 0:e87aa4c49e95 68 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
phungductung 0:e87aa4c49e95 69 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
phungductung 0:e87aa4c49e95 70 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
phungductung 0:e87aa4c49e95 71 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
phungductung 0:e87aa4c49e95 72 }HAL_NAND_StateTypeDef;
phungductung 0:e87aa4c49e95 73
phungductung 0:e87aa4c49e95 74 /**
phungductung 0:e87aa4c49e95 75 * @brief NAND Memory electronic signature Structure definition
phungductung 0:e87aa4c49e95 76 */
phungductung 0:e87aa4c49e95 77 typedef struct
phungductung 0:e87aa4c49e95 78 {
phungductung 0:e87aa4c49e95 79 /*<! NAND memory electronic signature maker and device IDs */
phungductung 0:e87aa4c49e95 80
phungductung 0:e87aa4c49e95 81 uint8_t Maker_Id;
phungductung 0:e87aa4c49e95 82
phungductung 0:e87aa4c49e95 83 uint8_t Device_Id;
phungductung 0:e87aa4c49e95 84
phungductung 0:e87aa4c49e95 85 uint8_t Third_Id;
phungductung 0:e87aa4c49e95 86
phungductung 0:e87aa4c49e95 87 uint8_t Fourth_Id;
phungductung 0:e87aa4c49e95 88 }NAND_IDTypeDef;
phungductung 0:e87aa4c49e95 89
phungductung 0:e87aa4c49e95 90 /**
phungductung 0:e87aa4c49e95 91 * @brief NAND Memory address Structure definition
phungductung 0:e87aa4c49e95 92 */
phungductung 0:e87aa4c49e95 93 typedef struct
phungductung 0:e87aa4c49e95 94 {
phungductung 0:e87aa4c49e95 95 uint16_t Page; /*!< NAND memory Page address */
phungductung 0:e87aa4c49e95 96
phungductung 0:e87aa4c49e95 97 uint16_t Zone; /*!< NAND memory Zone address */
phungductung 0:e87aa4c49e95 98
phungductung 0:e87aa4c49e95 99 uint16_t Block; /*!< NAND memory Block address */
phungductung 0:e87aa4c49e95 100
phungductung 0:e87aa4c49e95 101 }NAND_AddressTypeDef;
phungductung 0:e87aa4c49e95 102
phungductung 0:e87aa4c49e95 103 /**
phungductung 0:e87aa4c49e95 104 * @brief NAND Memory info Structure definition
phungductung 0:e87aa4c49e95 105 */
phungductung 0:e87aa4c49e95 106 typedef struct
phungductung 0:e87aa4c49e95 107 {
phungductung 0:e87aa4c49e95 108 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
phungductung 0:e87aa4c49e95 109
phungductung 0:e87aa4c49e95 110 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
phungductung 0:e87aa4c49e95 111
phungductung 0:e87aa4c49e95 112 uint32_t BlockSize; /*!< NAND memory block size number of pages */
phungductung 0:e87aa4c49e95 113
phungductung 0:e87aa4c49e95 114 uint32_t BlockNbr; /*!< NAND memory number of blocks */
phungductung 0:e87aa4c49e95 115
phungductung 0:e87aa4c49e95 116 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
phungductung 0:e87aa4c49e95 117 }NAND_InfoTypeDef;
phungductung 0:e87aa4c49e95 118
phungductung 0:e87aa4c49e95 119 /**
phungductung 0:e87aa4c49e95 120 * @brief NAND handle Structure definition
phungductung 0:e87aa4c49e95 121 */
phungductung 0:e87aa4c49e95 122 typedef struct
phungductung 0:e87aa4c49e95 123 {
phungductung 0:e87aa4c49e95 124 FMC_NAND_TypeDef *Instance; /*!< Register base address */
phungductung 0:e87aa4c49e95 125
phungductung 0:e87aa4c49e95 126 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
phungductung 0:e87aa4c49e95 127
phungductung 0:e87aa4c49e95 128 HAL_LockTypeDef Lock; /*!< NAND locking object */
phungductung 0:e87aa4c49e95 129
phungductung 0:e87aa4c49e95 130 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
phungductung 0:e87aa4c49e95 131
phungductung 0:e87aa4c49e95 132 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
phungductung 0:e87aa4c49e95 133 }NAND_HandleTypeDef;
phungductung 0:e87aa4c49e95 134 /**
phungductung 0:e87aa4c49e95 135 * @}
phungductung 0:e87aa4c49e95 136 */
phungductung 0:e87aa4c49e95 137
phungductung 0:e87aa4c49e95 138 /* Exported constants --------------------------------------------------------*/
phungductung 0:e87aa4c49e95 139 /* Exported macro ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 140 /** @defgroup NAND_Exported_Macros NAND Exported Macros
phungductung 0:e87aa4c49e95 141 * @{
phungductung 0:e87aa4c49e95 142 */
phungductung 0:e87aa4c49e95 143
phungductung 0:e87aa4c49e95 144 /** @brief Reset NAND handle state
phungductung 0:e87aa4c49e95 145 * @param __HANDLE__: specifies the NAND handle.
phungductung 0:e87aa4c49e95 146 * @retval None
phungductung 0:e87aa4c49e95 147 */
phungductung 0:e87aa4c49e95 148 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
phungductung 0:e87aa4c49e95 149
phungductung 0:e87aa4c49e95 150 /**
phungductung 0:e87aa4c49e95 151 * @}
phungductung 0:e87aa4c49e95 152 */
phungductung 0:e87aa4c49e95 153
phungductung 0:e87aa4c49e95 154 /* Exported functions --------------------------------------------------------*/
phungductung 0:e87aa4c49e95 155 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
phungductung 0:e87aa4c49e95 156 * @{
phungductung 0:e87aa4c49e95 157 */
phungductung 0:e87aa4c49e95 158
phungductung 0:e87aa4c49e95 159 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung 0:e87aa4c49e95 160 * @{
phungductung 0:e87aa4c49e95 161 */
phungductung 0:e87aa4c49e95 162
phungductung 0:e87aa4c49e95 163 /* Initialization/de-initialization functions ********************************/
phungductung 0:e87aa4c49e95 164 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
phungductung 0:e87aa4c49e95 165 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 166 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 167 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 168 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 169 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 170
phungductung 0:e87aa4c49e95 171 /**
phungductung 0:e87aa4c49e95 172 * @}
phungductung 0:e87aa4c49e95 173 */
phungductung 0:e87aa4c49e95 174
phungductung 0:e87aa4c49e95 175 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
phungductung 0:e87aa4c49e95 176 * @{
phungductung 0:e87aa4c49e95 177 */
phungductung 0:e87aa4c49e95 178
phungductung 0:e87aa4c49e95 179 /* IO operation functions ****************************************************/
phungductung 0:e87aa4c49e95 180 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
phungductung 0:e87aa4c49e95 181 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 182 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
phungductung 0:e87aa4c49e95 183 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
phungductung 0:e87aa4c49e95 184 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
phungductung 0:e87aa4c49e95 185 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
phungductung 0:e87aa4c49e95 186 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
phungductung 0:e87aa4c49e95 187 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 188 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
phungductung 0:e87aa4c49e95 189
phungductung 0:e87aa4c49e95 190 /**
phungductung 0:e87aa4c49e95 191 * @}
phungductung 0:e87aa4c49e95 192 */
phungductung 0:e87aa4c49e95 193
phungductung 0:e87aa4c49e95 194 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
phungductung 0:e87aa4c49e95 195 * @{
phungductung 0:e87aa4c49e95 196 */
phungductung 0:e87aa4c49e95 197
phungductung 0:e87aa4c49e95 198 /* NAND Control functions ****************************************************/
phungductung 0:e87aa4c49e95 199 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 200 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 201 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
phungductung 0:e87aa4c49e95 202
phungductung 0:e87aa4c49e95 203 /**
phungductung 0:e87aa4c49e95 204 * @}
phungductung 0:e87aa4c49e95 205 */
phungductung 0:e87aa4c49e95 206
phungductung 0:e87aa4c49e95 207 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
phungductung 0:e87aa4c49e95 208 * @{
phungductung 0:e87aa4c49e95 209 */
phungductung 0:e87aa4c49e95 210 /* NAND State functions *******************************************************/
phungductung 0:e87aa4c49e95 211 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 212 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
phungductung 0:e87aa4c49e95 213 /**
phungductung 0:e87aa4c49e95 214 * @}
phungductung 0:e87aa4c49e95 215 */
phungductung 0:e87aa4c49e95 216
phungductung 0:e87aa4c49e95 217 /**
phungductung 0:e87aa4c49e95 218 * @}
phungductung 0:e87aa4c49e95 219 */
phungductung 0:e87aa4c49e95 220 /* Private types -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 221 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 222 /* Private constants ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 223 /** @defgroup NAND_Private_Constants NAND Private Constants
phungductung 0:e87aa4c49e95 224 * @{
phungductung 0:e87aa4c49e95 225 */
phungductung 0:e87aa4c49e95 226 #define NAND_DEVICE ((uint32_t)0x80000000)
phungductung 0:e87aa4c49e95 227 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
phungductung 0:e87aa4c49e95 228
phungductung 0:e87aa4c49e95 229 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
phungductung 0:e87aa4c49e95 230 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
phungductung 0:e87aa4c49e95 231
phungductung 0:e87aa4c49e95 232 #define NAND_CMD_AREA_A ((uint8_t)0x00)
phungductung 0:e87aa4c49e95 233 #define NAND_CMD_AREA_B ((uint8_t)0x01)
phungductung 0:e87aa4c49e95 234 #define NAND_CMD_AREA_C ((uint8_t)0x50)
phungductung 0:e87aa4c49e95 235 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
phungductung 0:e87aa4c49e95 236
phungductung 0:e87aa4c49e95 237 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
phungductung 0:e87aa4c49e95 238 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
phungductung 0:e87aa4c49e95 239 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
phungductung 0:e87aa4c49e95 240 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
phungductung 0:e87aa4c49e95 241 #define NAND_CMD_READID ((uint8_t)0x90)
phungductung 0:e87aa4c49e95 242 #define NAND_CMD_STATUS ((uint8_t)0x70)
phungductung 0:e87aa4c49e95 243 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
phungductung 0:e87aa4c49e95 244 #define NAND_CMD_RESET ((uint8_t)0xFF)
phungductung 0:e87aa4c49e95 245
phungductung 0:e87aa4c49e95 246 /* NAND memory status */
phungductung 0:e87aa4c49e95 247 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
phungductung 0:e87aa4c49e95 248 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
phungductung 0:e87aa4c49e95 249 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
phungductung 0:e87aa4c49e95 250 #define NAND_BUSY ((uint32_t)0x00000000)
phungductung 0:e87aa4c49e95 251 #define NAND_ERROR ((uint32_t)0x00000001)
phungductung 0:e87aa4c49e95 252 #define NAND_READY ((uint32_t)0x00000040)
phungductung 0:e87aa4c49e95 253 /**
phungductung 0:e87aa4c49e95 254 * @}
phungductung 0:e87aa4c49e95 255 */
phungductung 0:e87aa4c49e95 256
phungductung 0:e87aa4c49e95 257 /* Private macros ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 258 /** @defgroup NAND_Private_Macros NAND Private Macros
phungductung 0:e87aa4c49e95 259 * @{
phungductung 0:e87aa4c49e95 260 */
phungductung 0:e87aa4c49e95 261
phungductung 0:e87aa4c49e95 262 /**
phungductung 0:e87aa4c49e95 263 * @brief NAND memory address computation.
phungductung 0:e87aa4c49e95 264 * @param __ADDRESS__: NAND memory address.
phungductung 0:e87aa4c49e95 265 * @param __HANDLE__ : NAND handle.
phungductung 0:e87aa4c49e95 266 * @retval NAND Raw address value
phungductung 0:e87aa4c49e95 267 */
phungductung 0:e87aa4c49e95 268 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
phungductung 0:e87aa4c49e95 269 (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
phungductung 0:e87aa4c49e95 270
phungductung 0:e87aa4c49e95 271 /**
phungductung 0:e87aa4c49e95 272 * @brief NAND memory address cycling.
phungductung 0:e87aa4c49e95 273 * @param __ADDRESS__: NAND memory address.
phungductung 0:e87aa4c49e95 274 * @retval NAND address cycling value.
phungductung 0:e87aa4c49e95 275 */
phungductung 0:e87aa4c49e95 276 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
phungductung 0:e87aa4c49e95 277 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
phungductung 0:e87aa4c49e95 278 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
phungductung 0:e87aa4c49e95 279 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
phungductung 0:e87aa4c49e95 280 /**
phungductung 0:e87aa4c49e95 281 * @}
phungductung 0:e87aa4c49e95 282 */
phungductung 0:e87aa4c49e95 283
phungductung 0:e87aa4c49e95 284 /**
phungductung 0:e87aa4c49e95 285 * @}
phungductung 0:e87aa4c49e95 286 */
phungductung 0:e87aa4c49e95 287 /**
phungductung 0:e87aa4c49e95 288 * @}
phungductung 0:e87aa4c49e95 289 */
phungductung 0:e87aa4c49e95 290
phungductung 0:e87aa4c49e95 291 /**
phungductung 0:e87aa4c49e95 292 * @}
phungductung 0:e87aa4c49e95 293 */
phungductung 0:e87aa4c49e95 294
phungductung 0:e87aa4c49e95 295 #ifdef __cplusplus
phungductung 0:e87aa4c49e95 296 }
phungductung 0:e87aa4c49e95 297 #endif
phungductung 0:e87aa4c49e95 298
phungductung 0:e87aa4c49e95 299 #endif /* __STM32F7xx_HAL_NAND_H */
phungductung 0:e87aa4c49e95 300
phungductung 0:e87aa4c49e95 301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/