PHung Tung / SRC_STM32F7

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

Who changed what in which revision?

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phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_hal_dma.c
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief DMA HAL module driver.
phungductung 0:e87aa4c49e95 8 *
phungductung 0:e87aa4c49e95 9 * This file provides firmware functions to manage the following
phungductung 0:e87aa4c49e95 10 * functionalities of the Direct Memory Access (DMA) peripheral:
phungductung 0:e87aa4c49e95 11 * + Initialization and de-initialization functions
phungductung 0:e87aa4c49e95 12 * + IO operation functions
phungductung 0:e87aa4c49e95 13 * + Peripheral State and errors functions
phungductung 0:e87aa4c49e95 14 @verbatim
phungductung 0:e87aa4c49e95 15 ==============================================================================
phungductung 0:e87aa4c49e95 16 ##### How to use this driver #####
phungductung 0:e87aa4c49e95 17 ==============================================================================
phungductung 0:e87aa4c49e95 18 [..]
phungductung 0:e87aa4c49e95 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
phungductung 0:e87aa4c49e95 20 (except for internal SRAM/FLASH memories: no initialization is
phungductung 0:e87aa4c49e95 21 necessary) please refer to Reference manual for connection between peripherals
phungductung 0:e87aa4c49e95 22 and DMA requests .
phungductung 0:e87aa4c49e95 23
phungductung 0:e87aa4c49e95 24 (#) For a given Stream, program the required configuration through the following parameters:
phungductung 0:e87aa4c49e95 25 Transfer Direction, Source and Destination data formats,
phungductung 0:e87aa4c49e95 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
phungductung 0:e87aa4c49e95 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
phungductung 0:e87aa4c49e95 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
phungductung 0:e87aa4c49e95 29
phungductung 0:e87aa4c49e95 30 *** Polling mode IO operation ***
phungductung 0:e87aa4c49e95 31 =================================
phungductung 0:e87aa4c49e95 32 [..]
phungductung 0:e87aa4c49e95 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
phungductung 0:e87aa4c49e95 34 address and destination address and the Length of data to be transferred
phungductung 0:e87aa4c49e95 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
phungductung 0:e87aa4c49e95 36 case a fixed Timeout can be configured by User depending from his application.
phungductung 0:e87aa4c49e95 37
phungductung 0:e87aa4c49e95 38 *** Interrupt mode IO operation ***
phungductung 0:e87aa4c49e95 39 ===================================
phungductung 0:e87aa4c49e95 40 [..]
phungductung 0:e87aa4c49e95 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
phungductung 0:e87aa4c49e95 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
phungductung 0:e87aa4c49e95 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
phungductung 0:e87aa4c49e95 44 Source address and destination address and the Length of data to be transferred. In this
phungductung 0:e87aa4c49e95 45 case the DMA interrupt is configured
phungductung 0:e87aa4c49e95 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
phungductung 0:e87aa4c49e95 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
phungductung 0:e87aa4c49e95 48 add his own function by customization of function pointer XferCpltCallback and
phungductung 0:e87aa4c49e95 49 XferErrorCallback (i.e a member of DMA handle structure).
phungductung 0:e87aa4c49e95 50 [..]
phungductung 0:e87aa4c49e95 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
phungductung 0:e87aa4c49e95 52 detection.
phungductung 0:e87aa4c49e95 53
phungductung 0:e87aa4c49e95 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
phungductung 0:e87aa4c49e95 55
phungductung 0:e87aa4c49e95 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
phungductung 0:e87aa4c49e95 57
phungductung 0:e87aa4c49e95 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
phungductung 0:e87aa4c49e95 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
phungductung 0:e87aa4c49e95 60 Half-Word data size for the peripheral to access its data register and set Word data size
phungductung 0:e87aa4c49e95 61 for the Memory to gain in access time. Each two half words will be packed and written in
phungductung 0:e87aa4c49e95 62 a single access to a Word in the Memory).
phungductung 0:e87aa4c49e95 63
phungductung 0:e87aa4c49e95 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
phungductung 0:e87aa4c49e95 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
phungductung 0:e87aa4c49e95 66 and Destination.
phungductung 0:e87aa4c49e95 67
phungductung 0:e87aa4c49e95 68 *** DMA HAL driver macros list ***
phungductung 0:e87aa4c49e95 69 =============================================
phungductung 0:e87aa4c49e95 70 [..]
phungductung 0:e87aa4c49e95 71 Below the list of most used macros in DMA HAL driver.
phungductung 0:e87aa4c49e95 72
phungductung 0:e87aa4c49e95 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
phungductung 0:e87aa4c49e95 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
phungductung 0:e87aa4c49e95 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
phungductung 0:e87aa4c49e95 76 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
phungductung 0:e87aa4c49e95 77 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
phungductung 0:e87aa4c49e95 78 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
phungductung 0:e87aa4c49e95 79
phungductung 0:e87aa4c49e95 80 [..]
phungductung 0:e87aa4c49e95 81 (@) You can refer to the DMA HAL driver header file for more useful macros
phungductung 0:e87aa4c49e95 82
phungductung 0:e87aa4c49e95 83 @endverbatim
phungductung 0:e87aa4c49e95 84 ******************************************************************************
phungductung 0:e87aa4c49e95 85 * @attention
phungductung 0:e87aa4c49e95 86 *
phungductung 0:e87aa4c49e95 87 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 88 *
phungductung 0:e87aa4c49e95 89 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 90 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 91 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 92 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 93 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 94 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 95 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 96 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 97 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 98 * without specific prior written permission.
phungductung 0:e87aa4c49e95 99 *
phungductung 0:e87aa4c49e95 100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 110 *
phungductung 0:e87aa4c49e95 111 ******************************************************************************
phungductung 0:e87aa4c49e95 112 */
phungductung 0:e87aa4c49e95 113
phungductung 0:e87aa4c49e95 114 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 115 #include "stm32f7xx_hal.h"
phungductung 0:e87aa4c49e95 116
phungductung 0:e87aa4c49e95 117 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 118 * @{
phungductung 0:e87aa4c49e95 119 */
phungductung 0:e87aa4c49e95 120
phungductung 0:e87aa4c49e95 121 /** @defgroup DMA DMA
phungductung 0:e87aa4c49e95 122 * @brief DMA HAL module driver
phungductung 0:e87aa4c49e95 123 * @{
phungductung 0:e87aa4c49e95 124 */
phungductung 0:e87aa4c49e95 125
phungductung 0:e87aa4c49e95 126 #ifdef HAL_DMA_MODULE_ENABLED
phungductung 0:e87aa4c49e95 127
phungductung 0:e87aa4c49e95 128 /* Private types -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 129 typedef struct
phungductung 0:e87aa4c49e95 130 {
phungductung 0:e87aa4c49e95 131 __IO uint32_t ISR; /*!< DMA interrupt status register */
phungductung 0:e87aa4c49e95 132 __IO uint32_t Reserved0;
phungductung 0:e87aa4c49e95 133 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
phungductung 0:e87aa4c49e95 134 } DMA_Base_Registers;
phungductung 0:e87aa4c49e95 135
phungductung 0:e87aa4c49e95 136 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 137 /* Private constants ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 138 /** @addtogroup DMA_Private_Constants
phungductung 0:e87aa4c49e95 139 * @{
phungductung 0:e87aa4c49e95 140 */
phungductung 0:e87aa4c49e95 141 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
phungductung 0:e87aa4c49e95 142 /**
phungductung 0:e87aa4c49e95 143 * @}
phungductung 0:e87aa4c49e95 144 */
phungductung 0:e87aa4c49e95 145 /* Private macros ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 146 /* Private functions ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 147 /** @addtogroup DMA_Private_Functions
phungductung 0:e87aa4c49e95 148 * @{
phungductung 0:e87aa4c49e95 149 */
phungductung 0:e87aa4c49e95 150 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
phungductung 0:e87aa4c49e95 151 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
phungductung 0:e87aa4c49e95 152
phungductung 0:e87aa4c49e95 153 /**
phungductung 0:e87aa4c49e95 154 * @brief Sets the DMA Transfer parameter.
phungductung 0:e87aa4c49e95 155 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 156 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 157 * @param SrcAddress: The source memory Buffer address
phungductung 0:e87aa4c49e95 158 * @param DstAddress: The destination memory Buffer address
phungductung 0:e87aa4c49e95 159 * @param DataLength: The length of data to be transferred from source to destination
phungductung 0:e87aa4c49e95 160 * @retval HAL status
phungductung 0:e87aa4c49e95 161 */
phungductung 0:e87aa4c49e95 162 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
phungductung 0:e87aa4c49e95 163 {
phungductung 0:e87aa4c49e95 164 /* Clear DBM bit */
phungductung 0:e87aa4c49e95 165 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
phungductung 0:e87aa4c49e95 166
phungductung 0:e87aa4c49e95 167 /* Configure DMA Stream data length */
phungductung 0:e87aa4c49e95 168 hdma->Instance->NDTR = DataLength;
phungductung 0:e87aa4c49e95 169
phungductung 0:e87aa4c49e95 170 /* Peripheral to Memory */
phungductung 0:e87aa4c49e95 171 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
phungductung 0:e87aa4c49e95 172 {
phungductung 0:e87aa4c49e95 173 /* Configure DMA Stream destination address */
phungductung 0:e87aa4c49e95 174 hdma->Instance->PAR = DstAddress;
phungductung 0:e87aa4c49e95 175
phungductung 0:e87aa4c49e95 176 /* Configure DMA Stream source address */
phungductung 0:e87aa4c49e95 177 hdma->Instance->M0AR = SrcAddress;
phungductung 0:e87aa4c49e95 178 }
phungductung 0:e87aa4c49e95 179 /* Memory to Peripheral */
phungductung 0:e87aa4c49e95 180 else
phungductung 0:e87aa4c49e95 181 {
phungductung 0:e87aa4c49e95 182 /* Configure DMA Stream source address */
phungductung 0:e87aa4c49e95 183 hdma->Instance->PAR = SrcAddress;
phungductung 0:e87aa4c49e95 184
phungductung 0:e87aa4c49e95 185 /* Configure DMA Stream destination address */
phungductung 0:e87aa4c49e95 186 hdma->Instance->M0AR = DstAddress;
phungductung 0:e87aa4c49e95 187 }
phungductung 0:e87aa4c49e95 188 }
phungductung 0:e87aa4c49e95 189
phungductung 0:e87aa4c49e95 190 /**
phungductung 0:e87aa4c49e95 191 * @}
phungductung 0:e87aa4c49e95 192 */
phungductung 0:e87aa4c49e95 193
phungductung 0:e87aa4c49e95 194 /* Exported functions ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 195 /** @addtogroup DMA_Exported_Functions
phungductung 0:e87aa4c49e95 196 * @{
phungductung 0:e87aa4c49e95 197 */
phungductung 0:e87aa4c49e95 198
phungductung 0:e87aa4c49e95 199 /** @addtogroup DMA_Exported_Functions_Group1
phungductung 0:e87aa4c49e95 200 *
phungductung 0:e87aa4c49e95 201 @verbatim
phungductung 0:e87aa4c49e95 202 ===============================================================================
phungductung 0:e87aa4c49e95 203 ##### Initialization and de-initialization functions #####
phungductung 0:e87aa4c49e95 204 ===============================================================================
phungductung 0:e87aa4c49e95 205 [..]
phungductung 0:e87aa4c49e95 206 This section provides functions allowing to initialize the DMA Stream source
phungductung 0:e87aa4c49e95 207 and destination addresses, incrementation and data sizes, transfer direction,
phungductung 0:e87aa4c49e95 208 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
phungductung 0:e87aa4c49e95 209 [..]
phungductung 0:e87aa4c49e95 210 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
phungductung 0:e87aa4c49e95 211 reference manual.
phungductung 0:e87aa4c49e95 212
phungductung 0:e87aa4c49e95 213 @endverbatim
phungductung 0:e87aa4c49e95 214 * @{
phungductung 0:e87aa4c49e95 215 */
phungductung 0:e87aa4c49e95 216
phungductung 0:e87aa4c49e95 217 /**
phungductung 0:e87aa4c49e95 218 * @brief Initializes the DMA according to the specified
phungductung 0:e87aa4c49e95 219 * parameters in the DMA_InitTypeDef and create the associated handle.
phungductung 0:e87aa4c49e95 220 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 221 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 222 * @retval HAL status
phungductung 0:e87aa4c49e95 223 */
phungductung 0:e87aa4c49e95 224 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 225 {
phungductung 0:e87aa4c49e95 226 uint32_t tmp = 0;
phungductung 0:e87aa4c49e95 227
phungductung 0:e87aa4c49e95 228 /* Check the DMA peripheral state */
phungductung 0:e87aa4c49e95 229 if(hdma == NULL)
phungductung 0:e87aa4c49e95 230 {
phungductung 0:e87aa4c49e95 231 return HAL_ERROR;
phungductung 0:e87aa4c49e95 232 }
phungductung 0:e87aa4c49e95 233
phungductung 0:e87aa4c49e95 234 /* Check the parameters */
phungductung 0:e87aa4c49e95 235 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
phungductung 0:e87aa4c49e95 236 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
phungductung 0:e87aa4c49e95 237 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
phungductung 0:e87aa4c49e95 238 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
phungductung 0:e87aa4c49e95 239 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
phungductung 0:e87aa4c49e95 240 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
phungductung 0:e87aa4c49e95 241 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
phungductung 0:e87aa4c49e95 242 assert_param(IS_DMA_MODE(hdma->Init.Mode));
phungductung 0:e87aa4c49e95 243 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
phungductung 0:e87aa4c49e95 244 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
phungductung 0:e87aa4c49e95 245 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
phungductung 0:e87aa4c49e95 246 when FIFO mode is enabled */
phungductung 0:e87aa4c49e95 247 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
phungductung 0:e87aa4c49e95 248 {
phungductung 0:e87aa4c49e95 249 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
phungductung 0:e87aa4c49e95 250 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
phungductung 0:e87aa4c49e95 251 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
phungductung 0:e87aa4c49e95 252 }
phungductung 0:e87aa4c49e95 253
phungductung 0:e87aa4c49e95 254 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 255 hdma->State = HAL_DMA_STATE_BUSY;
phungductung 0:e87aa4c49e95 256
phungductung 0:e87aa4c49e95 257 /* Get the CR register value */
phungductung 0:e87aa4c49e95 258 tmp = hdma->Instance->CR;
phungductung 0:e87aa4c49e95 259
phungductung 0:e87aa4c49e95 260 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
phungductung 0:e87aa4c49e95 261 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
phungductung 0:e87aa4c49e95 262 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
phungductung 0:e87aa4c49e95 263 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
phungductung 0:e87aa4c49e95 264 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
phungductung 0:e87aa4c49e95 265
phungductung 0:e87aa4c49e95 266 /* Prepare the DMA Stream configuration */
phungductung 0:e87aa4c49e95 267 tmp |= hdma->Init.Channel | hdma->Init.Direction |
phungductung 0:e87aa4c49e95 268 hdma->Init.PeriphInc | hdma->Init.MemInc |
phungductung 0:e87aa4c49e95 269 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
phungductung 0:e87aa4c49e95 270 hdma->Init.Mode | hdma->Init.Priority;
phungductung 0:e87aa4c49e95 271
phungductung 0:e87aa4c49e95 272 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
phungductung 0:e87aa4c49e95 273 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
phungductung 0:e87aa4c49e95 274 {
phungductung 0:e87aa4c49e95 275 /* Get memory burst and peripheral burst */
phungductung 0:e87aa4c49e95 276 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
phungductung 0:e87aa4c49e95 277 }
phungductung 0:e87aa4c49e95 278
phungductung 0:e87aa4c49e95 279 /* Write to DMA Stream CR register */
phungductung 0:e87aa4c49e95 280 hdma->Instance->CR = tmp;
phungductung 0:e87aa4c49e95 281
phungductung 0:e87aa4c49e95 282 /* Get the FCR register value */
phungductung 0:e87aa4c49e95 283 tmp = hdma->Instance->FCR;
phungductung 0:e87aa4c49e95 284
phungductung 0:e87aa4c49e95 285 /* Clear Direct mode and FIFO threshold bits */
phungductung 0:e87aa4c49e95 286 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
phungductung 0:e87aa4c49e95 287
phungductung 0:e87aa4c49e95 288 /* Prepare the DMA Stream FIFO configuration */
phungductung 0:e87aa4c49e95 289 tmp |= hdma->Init.FIFOMode;
phungductung 0:e87aa4c49e95 290
phungductung 0:e87aa4c49e95 291 /* the FIFO threshold is not used when the FIFO mode is disabled */
phungductung 0:e87aa4c49e95 292 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
phungductung 0:e87aa4c49e95 293 {
phungductung 0:e87aa4c49e95 294 /* Get the FIFO threshold */
phungductung 0:e87aa4c49e95 295 tmp |= hdma->Init.FIFOThreshold;
phungductung 0:e87aa4c49e95 296 }
phungductung 0:e87aa4c49e95 297
phungductung 0:e87aa4c49e95 298 /* Write to DMA Stream FCR */
phungductung 0:e87aa4c49e95 299 hdma->Instance->FCR = tmp;
phungductung 0:e87aa4c49e95 300
phungductung 0:e87aa4c49e95 301 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
phungductung 0:e87aa4c49e95 302 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
phungductung 0:e87aa4c49e95 303 DMA_CalcBaseAndBitshift(hdma);
phungductung 0:e87aa4c49e95 304
phungductung 0:e87aa4c49e95 305 /* Initialize the error code */
phungductung 0:e87aa4c49e95 306 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
phungductung 0:e87aa4c49e95 307
phungductung 0:e87aa4c49e95 308 /* Initialize the DMA state */
phungductung 0:e87aa4c49e95 309 hdma->State = HAL_DMA_STATE_READY;
phungductung 0:e87aa4c49e95 310
phungductung 0:e87aa4c49e95 311 return HAL_OK;
phungductung 0:e87aa4c49e95 312 }
phungductung 0:e87aa4c49e95 313
phungductung 0:e87aa4c49e95 314 /**
phungductung 0:e87aa4c49e95 315 * @brief DeInitializes the DMA peripheral
phungductung 0:e87aa4c49e95 316 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 317 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 318 * @retval HAL status
phungductung 0:e87aa4c49e95 319 */
phungductung 0:e87aa4c49e95 320 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 321 {
phungductung 0:e87aa4c49e95 322 DMA_Base_Registers *regs;
phungductung 0:e87aa4c49e95 323
phungductung 0:e87aa4c49e95 324 /* Check the DMA peripheral state */
phungductung 0:e87aa4c49e95 325 if(hdma == NULL)
phungductung 0:e87aa4c49e95 326 {
phungductung 0:e87aa4c49e95 327 return HAL_ERROR;
phungductung 0:e87aa4c49e95 328 }
phungductung 0:e87aa4c49e95 329
phungductung 0:e87aa4c49e95 330 /* Check the DMA peripheral state */
phungductung 0:e87aa4c49e95 331 if(hdma->State == HAL_DMA_STATE_BUSY)
phungductung 0:e87aa4c49e95 332 {
phungductung 0:e87aa4c49e95 333 return HAL_ERROR;
phungductung 0:e87aa4c49e95 334 }
phungductung 0:e87aa4c49e95 335
phungductung 0:e87aa4c49e95 336 /* Disable the selected DMA Streamx */
phungductung 0:e87aa4c49e95 337 __HAL_DMA_DISABLE(hdma);
phungductung 0:e87aa4c49e95 338
phungductung 0:e87aa4c49e95 339 /* Reset DMA Streamx control register */
phungductung 0:e87aa4c49e95 340 hdma->Instance->CR = 0;
phungductung 0:e87aa4c49e95 341
phungductung 0:e87aa4c49e95 342 /* Reset DMA Streamx number of data to transfer register */
phungductung 0:e87aa4c49e95 343 hdma->Instance->NDTR = 0;
phungductung 0:e87aa4c49e95 344
phungductung 0:e87aa4c49e95 345 /* Reset DMA Streamx peripheral address register */
phungductung 0:e87aa4c49e95 346 hdma->Instance->PAR = 0;
phungductung 0:e87aa4c49e95 347
phungductung 0:e87aa4c49e95 348 /* Reset DMA Streamx memory 0 address register */
phungductung 0:e87aa4c49e95 349 hdma->Instance->M0AR = 0;
phungductung 0:e87aa4c49e95 350
phungductung 0:e87aa4c49e95 351 /* Reset DMA Streamx memory 1 address register */
phungductung 0:e87aa4c49e95 352 hdma->Instance->M1AR = 0;
phungductung 0:e87aa4c49e95 353
phungductung 0:e87aa4c49e95 354 /* Reset DMA Streamx FIFO control register */
phungductung 0:e87aa4c49e95 355 hdma->Instance->FCR = (uint32_t)0x00000021;
phungductung 0:e87aa4c49e95 356
phungductung 0:e87aa4c49e95 357 /* Get DMA steam Base Address */
phungductung 0:e87aa4c49e95 358 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
phungductung 0:e87aa4c49e95 359
phungductung 0:e87aa4c49e95 360 /* Clear all interrupt flags at correct offset within the register */
phungductung 0:e87aa4c49e95 361 regs->IFCR = 0x3F << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 362
phungductung 0:e87aa4c49e95 363 /* Initialize the error code */
phungductung 0:e87aa4c49e95 364 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
phungductung 0:e87aa4c49e95 365
phungductung 0:e87aa4c49e95 366 /* Initialize the DMA state */
phungductung 0:e87aa4c49e95 367 hdma->State = HAL_DMA_STATE_RESET;
phungductung 0:e87aa4c49e95 368
phungductung 0:e87aa4c49e95 369 /* Release Lock */
phungductung 0:e87aa4c49e95 370 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 371
phungductung 0:e87aa4c49e95 372 return HAL_OK;
phungductung 0:e87aa4c49e95 373 }
phungductung 0:e87aa4c49e95 374
phungductung 0:e87aa4c49e95 375 /**
phungductung 0:e87aa4c49e95 376 * @}
phungductung 0:e87aa4c49e95 377 */
phungductung 0:e87aa4c49e95 378
phungductung 0:e87aa4c49e95 379 /** @addtogroup DMA_Exported_Functions_Group2
phungductung 0:e87aa4c49e95 380 *
phungductung 0:e87aa4c49e95 381 @verbatim
phungductung 0:e87aa4c49e95 382 ===============================================================================
phungductung 0:e87aa4c49e95 383 ##### IO operation functions #####
phungductung 0:e87aa4c49e95 384 ===============================================================================
phungductung 0:e87aa4c49e95 385 [..] This section provides functions allowing to:
phungductung 0:e87aa4c49e95 386 (+) Configure the source, destination address and data length and Start DMA transfer
phungductung 0:e87aa4c49e95 387 (+) Configure the source, destination address and data length and
phungductung 0:e87aa4c49e95 388 Start DMA transfer with interrupt
phungductung 0:e87aa4c49e95 389 (+) Abort DMA transfer
phungductung 0:e87aa4c49e95 390 (+) Poll for transfer complete
phungductung 0:e87aa4c49e95 391 (+) Handle DMA interrupt request
phungductung 0:e87aa4c49e95 392
phungductung 0:e87aa4c49e95 393 @endverbatim
phungductung 0:e87aa4c49e95 394 * @{
phungductung 0:e87aa4c49e95 395 */
phungductung 0:e87aa4c49e95 396
phungductung 0:e87aa4c49e95 397 /**
phungductung 0:e87aa4c49e95 398 * @brief Starts the DMA Transfer.
phungductung 0:e87aa4c49e95 399 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 400 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 401 * @param SrcAddress: The source memory Buffer address
phungductung 0:e87aa4c49e95 402 * @param DstAddress: The destination memory Buffer address
phungductung 0:e87aa4c49e95 403 * @param DataLength: The length of data to be transferred from source to destination
phungductung 0:e87aa4c49e95 404 * @retval HAL status
phungductung 0:e87aa4c49e95 405 */
phungductung 0:e87aa4c49e95 406 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
phungductung 0:e87aa4c49e95 407 {
phungductung 0:e87aa4c49e95 408 /* Process locked */
phungductung 0:e87aa4c49e95 409 __HAL_LOCK(hdma);
phungductung 0:e87aa4c49e95 410
phungductung 0:e87aa4c49e95 411 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 412 hdma->State = HAL_DMA_STATE_BUSY;
phungductung 0:e87aa4c49e95 413
phungductung 0:e87aa4c49e95 414 /* Check the parameters */
phungductung 0:e87aa4c49e95 415 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
phungductung 0:e87aa4c49e95 416
phungductung 0:e87aa4c49e95 417 /* Disable the peripheral */
phungductung 0:e87aa4c49e95 418 __HAL_DMA_DISABLE(hdma);
phungductung 0:e87aa4c49e95 419
phungductung 0:e87aa4c49e95 420 /* Configure the source, destination address and the data length */
phungductung 0:e87aa4c49e95 421 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
phungductung 0:e87aa4c49e95 422
phungductung 0:e87aa4c49e95 423 /* Enable the Peripheral */
phungductung 0:e87aa4c49e95 424 __HAL_DMA_ENABLE(hdma);
phungductung 0:e87aa4c49e95 425
phungductung 0:e87aa4c49e95 426 return HAL_OK;
phungductung 0:e87aa4c49e95 427 }
phungductung 0:e87aa4c49e95 428
phungductung 0:e87aa4c49e95 429 /**
phungductung 0:e87aa4c49e95 430 * @brief Start the DMA Transfer with interrupt enabled.
phungductung 0:e87aa4c49e95 431 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 432 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 433 * @param SrcAddress: The source memory Buffer address
phungductung 0:e87aa4c49e95 434 * @param DstAddress: The destination memory Buffer address
phungductung 0:e87aa4c49e95 435 * @param DataLength: The length of data to be transferred from source to destination
phungductung 0:e87aa4c49e95 436 * @retval HAL status
phungductung 0:e87aa4c49e95 437 */
phungductung 0:e87aa4c49e95 438 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
phungductung 0:e87aa4c49e95 439 {
phungductung 0:e87aa4c49e95 440 /* Process locked */
phungductung 0:e87aa4c49e95 441 __HAL_LOCK(hdma);
phungductung 0:e87aa4c49e95 442
phungductung 0:e87aa4c49e95 443 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 444 hdma->State = HAL_DMA_STATE_BUSY;
phungductung 0:e87aa4c49e95 445
phungductung 0:e87aa4c49e95 446 /* Check the parameters */
phungductung 0:e87aa4c49e95 447 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
phungductung 0:e87aa4c49e95 448
phungductung 0:e87aa4c49e95 449 /* Disable the peripheral */
phungductung 0:e87aa4c49e95 450 __HAL_DMA_DISABLE(hdma);
phungductung 0:e87aa4c49e95 451
phungductung 0:e87aa4c49e95 452 /* Configure the source, destination address and the data length */
phungductung 0:e87aa4c49e95 453 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
phungductung 0:e87aa4c49e95 454
phungductung 0:e87aa4c49e95 455 /* Enable all interrupts */
phungductung 0:e87aa4c49e95 456 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
phungductung 0:e87aa4c49e95 457 hdma->Instance->FCR |= DMA_IT_FE;
phungductung 0:e87aa4c49e95 458
phungductung 0:e87aa4c49e95 459 /* Enable the Peripheral */
phungductung 0:e87aa4c49e95 460 __HAL_DMA_ENABLE(hdma);
phungductung 0:e87aa4c49e95 461
phungductung 0:e87aa4c49e95 462 return HAL_OK;
phungductung 0:e87aa4c49e95 463 }
phungductung 0:e87aa4c49e95 464
phungductung 0:e87aa4c49e95 465 /**
phungductung 0:e87aa4c49e95 466 * @brief Aborts the DMA Transfer.
phungductung 0:e87aa4c49e95 467 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 468 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 469 *
phungductung 0:e87aa4c49e95 470 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
phungductung 0:e87aa4c49e95 471 * effectively disabled is added. If a Stream is disabled
phungductung 0:e87aa4c49e95 472 * while a data transfer is ongoing, the current data will be transferred
phungductung 0:e87aa4c49e95 473 * and the Stream will be effectively disabled only after the transfer of
phungductung 0:e87aa4c49e95 474 * this single data is finished.
phungductung 0:e87aa4c49e95 475 * @retval HAL status
phungductung 0:e87aa4c49e95 476 */
phungductung 0:e87aa4c49e95 477 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 478 {
phungductung 0:e87aa4c49e95 479 uint32_t tickstart = 0;
phungductung 0:e87aa4c49e95 480
phungductung 0:e87aa4c49e95 481 /* Disable the stream */
phungductung 0:e87aa4c49e95 482 __HAL_DMA_DISABLE(hdma);
phungductung 0:e87aa4c49e95 483
phungductung 0:e87aa4c49e95 484 /* Get tick */
phungductung 0:e87aa4c49e95 485 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 486
phungductung 0:e87aa4c49e95 487 /* Check if the DMA Stream is effectively disabled */
phungductung 0:e87aa4c49e95 488 while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
phungductung 0:e87aa4c49e95 489 {
phungductung 0:e87aa4c49e95 490 /* Check for the Timeout */
phungductung 0:e87aa4c49e95 491 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
phungductung 0:e87aa4c49e95 492 {
phungductung 0:e87aa4c49e95 493 /* Update error code */
phungductung 0:e87aa4c49e95 494 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
phungductung 0:e87aa4c49e95 495
phungductung 0:e87aa4c49e95 496 /* Process Unlocked */
phungductung 0:e87aa4c49e95 497 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 498
phungductung 0:e87aa4c49e95 499 /* Change the DMA state */
phungductung 0:e87aa4c49e95 500 hdma->State = HAL_DMA_STATE_TIMEOUT;
phungductung 0:e87aa4c49e95 501
phungductung 0:e87aa4c49e95 502 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 503 }
phungductung 0:e87aa4c49e95 504 }
phungductung 0:e87aa4c49e95 505 /* Process Unlocked */
phungductung 0:e87aa4c49e95 506 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 507
phungductung 0:e87aa4c49e95 508 /* Change the DMA state*/
phungductung 0:e87aa4c49e95 509 hdma->State = HAL_DMA_STATE_READY;
phungductung 0:e87aa4c49e95 510
phungductung 0:e87aa4c49e95 511 return HAL_OK;
phungductung 0:e87aa4c49e95 512 }
phungductung 0:e87aa4c49e95 513
phungductung 0:e87aa4c49e95 514 /**
phungductung 0:e87aa4c49e95 515 * @brief Polling for transfer complete.
phungductung 0:e87aa4c49e95 516 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 517 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 518 * @param CompleteLevel: Specifies the DMA level complete.
phungductung 0:e87aa4c49e95 519 * @param Timeout: Timeout duration.
phungductung 0:e87aa4c49e95 520 * @retval HAL status
phungductung 0:e87aa4c49e95 521 */
phungductung 0:e87aa4c49e95 522 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
phungductung 0:e87aa4c49e95 523 {
phungductung 0:e87aa4c49e95 524 uint32_t temp, tmp, tmp1, tmp2;
phungductung 0:e87aa4c49e95 525 uint32_t tickstart = 0;
phungductung 0:e87aa4c49e95 526
phungductung 0:e87aa4c49e95 527 /* calculate DMA base and stream number */
phungductung 0:e87aa4c49e95 528 DMA_Base_Registers *regs;
phungductung 0:e87aa4c49e95 529
phungductung 0:e87aa4c49e95 530 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
phungductung 0:e87aa4c49e95 531
phungductung 0:e87aa4c49e95 532 /* Get the level transfer complete flag */
phungductung 0:e87aa4c49e95 533 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
phungductung 0:e87aa4c49e95 534 {
phungductung 0:e87aa4c49e95 535 /* Transfer Complete flag */
phungductung 0:e87aa4c49e95 536 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 537 }
phungductung 0:e87aa4c49e95 538 else
phungductung 0:e87aa4c49e95 539 {
phungductung 0:e87aa4c49e95 540 /* Half Transfer Complete flag */
phungductung 0:e87aa4c49e95 541 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 542 }
phungductung 0:e87aa4c49e95 543
phungductung 0:e87aa4c49e95 544 /* Get tick */
phungductung 0:e87aa4c49e95 545 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 546
phungductung 0:e87aa4c49e95 547 while((regs->ISR & temp) == RESET)
phungductung 0:e87aa4c49e95 548 {
phungductung 0:e87aa4c49e95 549 tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
phungductung 0:e87aa4c49e95 550 tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
phungductung 0:e87aa4c49e95 551 tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
phungductung 0:e87aa4c49e95 552 if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
phungductung 0:e87aa4c49e95 553 {
phungductung 0:e87aa4c49e95 554 if(tmp != RESET)
phungductung 0:e87aa4c49e95 555 {
phungductung 0:e87aa4c49e95 556 /* Update error code */
phungductung 0:e87aa4c49e95 557 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
phungductung 0:e87aa4c49e95 558
phungductung 0:e87aa4c49e95 559 /* Clear the transfer error flag */
phungductung 0:e87aa4c49e95 560 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 561 }
phungductung 0:e87aa4c49e95 562 if(tmp1 != RESET)
phungductung 0:e87aa4c49e95 563 {
phungductung 0:e87aa4c49e95 564 /* Update error code */
phungductung 0:e87aa4c49e95 565 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
phungductung 0:e87aa4c49e95 566
phungductung 0:e87aa4c49e95 567 /* Clear the FIFO error flag */
phungductung 0:e87aa4c49e95 568 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 569 }
phungductung 0:e87aa4c49e95 570 if(tmp2 != RESET)
phungductung 0:e87aa4c49e95 571 {
phungductung 0:e87aa4c49e95 572 /* Update error code */
phungductung 0:e87aa4c49e95 573 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
phungductung 0:e87aa4c49e95 574
phungductung 0:e87aa4c49e95 575 /* Clear the Direct Mode error flag */
phungductung 0:e87aa4c49e95 576 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 577 }
phungductung 0:e87aa4c49e95 578 /* Change the DMA state */
phungductung 0:e87aa4c49e95 579 hdma->State= HAL_DMA_STATE_ERROR;
phungductung 0:e87aa4c49e95 580
phungductung 0:e87aa4c49e95 581 /* Process Unlocked */
phungductung 0:e87aa4c49e95 582 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 583
phungductung 0:e87aa4c49e95 584 return HAL_ERROR;
phungductung 0:e87aa4c49e95 585 }
phungductung 0:e87aa4c49e95 586 /* Check for the Timeout */
phungductung 0:e87aa4c49e95 587 if(Timeout != HAL_MAX_DELAY)
phungductung 0:e87aa4c49e95 588 {
phungductung 0:e87aa4c49e95 589 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
phungductung 0:e87aa4c49e95 590 {
phungductung 0:e87aa4c49e95 591 /* Update error code */
phungductung 0:e87aa4c49e95 592 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
phungductung 0:e87aa4c49e95 593
phungductung 0:e87aa4c49e95 594 /* Change the DMA state */
phungductung 0:e87aa4c49e95 595 hdma->State = HAL_DMA_STATE_TIMEOUT;
phungductung 0:e87aa4c49e95 596
phungductung 0:e87aa4c49e95 597 /* Process Unlocked */
phungductung 0:e87aa4c49e95 598 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 599
phungductung 0:e87aa4c49e95 600 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 601 }
phungductung 0:e87aa4c49e95 602 }
phungductung 0:e87aa4c49e95 603 }
phungductung 0:e87aa4c49e95 604
phungductung 0:e87aa4c49e95 605 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
phungductung 0:e87aa4c49e95 606 {
phungductung 0:e87aa4c49e95 607 /* Clear the half transfer and transfer complete flags */
phungductung 0:e87aa4c49e95 608 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 609
phungductung 0:e87aa4c49e95 610 /* Multi_Buffering mode enabled */
phungductung 0:e87aa4c49e95 611 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:e87aa4c49e95 612 {
phungductung 0:e87aa4c49e95 613 /* Current memory buffer used is Memory 0 */
phungductung 0:e87aa4c49e95 614 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:e87aa4c49e95 615 {
phungductung 0:e87aa4c49e95 616 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 617 hdma->State = HAL_DMA_STATE_READY_MEM0;
phungductung 0:e87aa4c49e95 618 }
phungductung 0:e87aa4c49e95 619 /* Current memory buffer used is Memory 1 */
phungductung 0:e87aa4c49e95 620 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:e87aa4c49e95 621 {
phungductung 0:e87aa4c49e95 622 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 623 hdma->State = HAL_DMA_STATE_READY_MEM1;
phungductung 0:e87aa4c49e95 624 }
phungductung 0:e87aa4c49e95 625 }
phungductung 0:e87aa4c49e95 626 else
phungductung 0:e87aa4c49e95 627 {
phungductung 0:e87aa4c49e95 628 /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
phungductung 0:e87aa4c49e95 629 are complete) */
phungductung 0:e87aa4c49e95 630 hdma->State = HAL_DMA_STATE_READY_MEM0;
phungductung 0:e87aa4c49e95 631 }
phungductung 0:e87aa4c49e95 632 /* Process Unlocked */
phungductung 0:e87aa4c49e95 633 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 634 }
phungductung 0:e87aa4c49e95 635 else
phungductung 0:e87aa4c49e95 636 {
phungductung 0:e87aa4c49e95 637 /* Clear the half transfer complete flag */
phungductung 0:e87aa4c49e95 638 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 639
phungductung 0:e87aa4c49e95 640 /* Multi_Buffering mode enabled */
phungductung 0:e87aa4c49e95 641 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:e87aa4c49e95 642 {
phungductung 0:e87aa4c49e95 643 /* Current memory buffer used is Memory 0 */
phungductung 0:e87aa4c49e95 644 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:e87aa4c49e95 645 {
phungductung 0:e87aa4c49e95 646 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 647 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:e87aa4c49e95 648 }
phungductung 0:e87aa4c49e95 649 /* Current memory buffer used is Memory 1 */
phungductung 0:e87aa4c49e95 650 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:e87aa4c49e95 651 {
phungductung 0:e87aa4c49e95 652 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 653 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
phungductung 0:e87aa4c49e95 654 }
phungductung 0:e87aa4c49e95 655 }
phungductung 0:e87aa4c49e95 656 else
phungductung 0:e87aa4c49e95 657 {
phungductung 0:e87aa4c49e95 658 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 659 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:e87aa4c49e95 660 }
phungductung 0:e87aa4c49e95 661 }
phungductung 0:e87aa4c49e95 662 return HAL_OK;
phungductung 0:e87aa4c49e95 663 }
phungductung 0:e87aa4c49e95 664
phungductung 0:e87aa4c49e95 665 /**
phungductung 0:e87aa4c49e95 666 * @brief Handles DMA interrupt request.
phungductung 0:e87aa4c49e95 667 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 668 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 669 * @retval None
phungductung 0:e87aa4c49e95 670 */
phungductung 0:e87aa4c49e95 671 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 672 {
phungductung 0:e87aa4c49e95 673 /* calculate DMA base and stream number */
phungductung 0:e87aa4c49e95 674 DMA_Base_Registers *regs;
phungductung 0:e87aa4c49e95 675
phungductung 0:e87aa4c49e95 676 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
phungductung 0:e87aa4c49e95 677
phungductung 0:e87aa4c49e95 678 /* Transfer Error Interrupt management ***************************************/
phungductung 0:e87aa4c49e95 679 if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:e87aa4c49e95 680 {
phungductung 0:e87aa4c49e95 681 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
phungductung 0:e87aa4c49e95 682 {
phungductung 0:e87aa4c49e95 683 /* Disable the transfer error interrupt */
phungductung 0:e87aa4c49e95 684 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
phungductung 0:e87aa4c49e95 685
phungductung 0:e87aa4c49e95 686 /* Clear the transfer error flag */
phungductung 0:e87aa4c49e95 687 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 688
phungductung 0:e87aa4c49e95 689 /* Update error code */
phungductung 0:e87aa4c49e95 690 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
phungductung 0:e87aa4c49e95 691
phungductung 0:e87aa4c49e95 692 /* Change the DMA state */
phungductung 0:e87aa4c49e95 693 hdma->State = HAL_DMA_STATE_ERROR;
phungductung 0:e87aa4c49e95 694
phungductung 0:e87aa4c49e95 695 /* Process Unlocked */
phungductung 0:e87aa4c49e95 696 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 697
phungductung 0:e87aa4c49e95 698 if(hdma->XferErrorCallback != NULL)
phungductung 0:e87aa4c49e95 699 {
phungductung 0:e87aa4c49e95 700 /* Transfer error callback */
phungductung 0:e87aa4c49e95 701 hdma->XferErrorCallback(hdma);
phungductung 0:e87aa4c49e95 702 }
phungductung 0:e87aa4c49e95 703 }
phungductung 0:e87aa4c49e95 704 }
phungductung 0:e87aa4c49e95 705 /* FIFO Error Interrupt management ******************************************/
phungductung 0:e87aa4c49e95 706 if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:e87aa4c49e95 707 {
phungductung 0:e87aa4c49e95 708 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
phungductung 0:e87aa4c49e95 709 {
phungductung 0:e87aa4c49e95 710 /* Disable the FIFO Error interrupt */
phungductung 0:e87aa4c49e95 711 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
phungductung 0:e87aa4c49e95 712
phungductung 0:e87aa4c49e95 713 /* Clear the FIFO error flag */
phungductung 0:e87aa4c49e95 714 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 715
phungductung 0:e87aa4c49e95 716 /* Update error code */
phungductung 0:e87aa4c49e95 717 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
phungductung 0:e87aa4c49e95 718
phungductung 0:e87aa4c49e95 719 /* Change the DMA state */
phungductung 0:e87aa4c49e95 720 hdma->State = HAL_DMA_STATE_ERROR;
phungductung 0:e87aa4c49e95 721
phungductung 0:e87aa4c49e95 722 /* Process Unlocked */
phungductung 0:e87aa4c49e95 723 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 724
phungductung 0:e87aa4c49e95 725 if(hdma->XferErrorCallback != NULL)
phungductung 0:e87aa4c49e95 726 {
phungductung 0:e87aa4c49e95 727 /* Transfer error callback */
phungductung 0:e87aa4c49e95 728 hdma->XferErrorCallback(hdma);
phungductung 0:e87aa4c49e95 729 }
phungductung 0:e87aa4c49e95 730 }
phungductung 0:e87aa4c49e95 731 }
phungductung 0:e87aa4c49e95 732 /* Direct Mode Error Interrupt management ***********************************/
phungductung 0:e87aa4c49e95 733 if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:e87aa4c49e95 734 {
phungductung 0:e87aa4c49e95 735 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
phungductung 0:e87aa4c49e95 736 {
phungductung 0:e87aa4c49e95 737 /* Disable the direct mode Error interrupt */
phungductung 0:e87aa4c49e95 738 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
phungductung 0:e87aa4c49e95 739
phungductung 0:e87aa4c49e95 740 /* Clear the direct mode error flag */
phungductung 0:e87aa4c49e95 741 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 742
phungductung 0:e87aa4c49e95 743 /* Update error code */
phungductung 0:e87aa4c49e95 744 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
phungductung 0:e87aa4c49e95 745
phungductung 0:e87aa4c49e95 746 /* Change the DMA state */
phungductung 0:e87aa4c49e95 747 hdma->State = HAL_DMA_STATE_ERROR;
phungductung 0:e87aa4c49e95 748
phungductung 0:e87aa4c49e95 749 /* Process Unlocked */
phungductung 0:e87aa4c49e95 750 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 751
phungductung 0:e87aa4c49e95 752 if(hdma->XferErrorCallback != NULL)
phungductung 0:e87aa4c49e95 753 {
phungductung 0:e87aa4c49e95 754 /* Transfer error callback */
phungductung 0:e87aa4c49e95 755 hdma->XferErrorCallback(hdma);
phungductung 0:e87aa4c49e95 756 }
phungductung 0:e87aa4c49e95 757 }
phungductung 0:e87aa4c49e95 758 }
phungductung 0:e87aa4c49e95 759 /* Half Transfer Complete Interrupt management ******************************/
phungductung 0:e87aa4c49e95 760 if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:e87aa4c49e95 761 {
phungductung 0:e87aa4c49e95 762 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
phungductung 0:e87aa4c49e95 763 {
phungductung 0:e87aa4c49e95 764 /* Multi_Buffering mode enabled */
phungductung 0:e87aa4c49e95 765 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:e87aa4c49e95 766 {
phungductung 0:e87aa4c49e95 767 /* Clear the half transfer complete flag */
phungductung 0:e87aa4c49e95 768 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 769
phungductung 0:e87aa4c49e95 770 /* Current memory buffer used is Memory 0 */
phungductung 0:e87aa4c49e95 771 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:e87aa4c49e95 772 {
phungductung 0:e87aa4c49e95 773 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 774 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:e87aa4c49e95 775 }
phungductung 0:e87aa4c49e95 776 /* Current memory buffer used is Memory 1 */
phungductung 0:e87aa4c49e95 777 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:e87aa4c49e95 778 {
phungductung 0:e87aa4c49e95 779 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 780 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
phungductung 0:e87aa4c49e95 781 }
phungductung 0:e87aa4c49e95 782 }
phungductung 0:e87aa4c49e95 783 else
phungductung 0:e87aa4c49e95 784 {
phungductung 0:e87aa4c49e95 785 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
phungductung 0:e87aa4c49e95 786 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung 0:e87aa4c49e95 787 {
phungductung 0:e87aa4c49e95 788 /* Disable the half transfer interrupt */
phungductung 0:e87aa4c49e95 789 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
phungductung 0:e87aa4c49e95 790 }
phungductung 0:e87aa4c49e95 791 /* Clear the half transfer complete flag */
phungductung 0:e87aa4c49e95 792 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 793
phungductung 0:e87aa4c49e95 794 /* Change DMA peripheral state */
phungductung 0:e87aa4c49e95 795 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:e87aa4c49e95 796 }
phungductung 0:e87aa4c49e95 797
phungductung 0:e87aa4c49e95 798 if(hdma->XferHalfCpltCallback != NULL)
phungductung 0:e87aa4c49e95 799 {
phungductung 0:e87aa4c49e95 800 /* Half transfer callback */
phungductung 0:e87aa4c49e95 801 hdma->XferHalfCpltCallback(hdma);
phungductung 0:e87aa4c49e95 802 }
phungductung 0:e87aa4c49e95 803 }
phungductung 0:e87aa4c49e95 804 }
phungductung 0:e87aa4c49e95 805 /* Transfer Complete Interrupt management ***********************************/
phungductung 0:e87aa4c49e95 806 if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:e87aa4c49e95 807 {
phungductung 0:e87aa4c49e95 808 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
phungductung 0:e87aa4c49e95 809 {
phungductung 0:e87aa4c49e95 810 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:e87aa4c49e95 811 {
phungductung 0:e87aa4c49e95 812 /* Clear the transfer complete flag */
phungductung 0:e87aa4c49e95 813 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 814
phungductung 0:e87aa4c49e95 815 /* Current memory buffer used is Memory 1 */
phungductung 0:e87aa4c49e95 816 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:e87aa4c49e95 817 {
phungductung 0:e87aa4c49e95 818 if(hdma->XferM1CpltCallback != NULL)
phungductung 0:e87aa4c49e95 819 {
phungductung 0:e87aa4c49e95 820 /* Transfer complete Callback for memory1 */
phungductung 0:e87aa4c49e95 821 hdma->XferM1CpltCallback(hdma);
phungductung 0:e87aa4c49e95 822 }
phungductung 0:e87aa4c49e95 823 }
phungductung 0:e87aa4c49e95 824 /* Current memory buffer used is Memory 0 */
phungductung 0:e87aa4c49e95 825 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:e87aa4c49e95 826 {
phungductung 0:e87aa4c49e95 827 if(hdma->XferCpltCallback != NULL)
phungductung 0:e87aa4c49e95 828 {
phungductung 0:e87aa4c49e95 829 /* Transfer complete Callback for memory0 */
phungductung 0:e87aa4c49e95 830 hdma->XferCpltCallback(hdma);
phungductung 0:e87aa4c49e95 831 }
phungductung 0:e87aa4c49e95 832 }
phungductung 0:e87aa4c49e95 833 }
phungductung 0:e87aa4c49e95 834 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
phungductung 0:e87aa4c49e95 835 else
phungductung 0:e87aa4c49e95 836 {
phungductung 0:e87aa4c49e95 837 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung 0:e87aa4c49e95 838 {
phungductung 0:e87aa4c49e95 839 /* Disable the transfer complete interrupt */
phungductung 0:e87aa4c49e95 840 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
phungductung 0:e87aa4c49e95 841 }
phungductung 0:e87aa4c49e95 842 /* Clear the transfer complete flag */
phungductung 0:e87aa4c49e95 843 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
phungductung 0:e87aa4c49e95 844
phungductung 0:e87aa4c49e95 845 /* Update error code */
phungductung 0:e87aa4c49e95 846 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
phungductung 0:e87aa4c49e95 847
phungductung 0:e87aa4c49e95 848 /* Change the DMA state */
phungductung 0:e87aa4c49e95 849 hdma->State = HAL_DMA_STATE_READY_MEM0;
phungductung 0:e87aa4c49e95 850
phungductung 0:e87aa4c49e95 851 /* Process Unlocked */
phungductung 0:e87aa4c49e95 852 __HAL_UNLOCK(hdma);
phungductung 0:e87aa4c49e95 853
phungductung 0:e87aa4c49e95 854 if(hdma->XferCpltCallback != NULL)
phungductung 0:e87aa4c49e95 855 {
phungductung 0:e87aa4c49e95 856 /* Transfer complete callback */
phungductung 0:e87aa4c49e95 857 hdma->XferCpltCallback(hdma);
phungductung 0:e87aa4c49e95 858 }
phungductung 0:e87aa4c49e95 859 }
phungductung 0:e87aa4c49e95 860 }
phungductung 0:e87aa4c49e95 861 }
phungductung 0:e87aa4c49e95 862 }
phungductung 0:e87aa4c49e95 863
phungductung 0:e87aa4c49e95 864
phungductung 0:e87aa4c49e95 865 /**
phungductung 0:e87aa4c49e95 866 * @}
phungductung 0:e87aa4c49e95 867 */
phungductung 0:e87aa4c49e95 868
phungductung 0:e87aa4c49e95 869 /** @addtogroup DMA_Exported_Functions_Group3
phungductung 0:e87aa4c49e95 870 *
phungductung 0:e87aa4c49e95 871 @verbatim
phungductung 0:e87aa4c49e95 872 ===============================================================================
phungductung 0:e87aa4c49e95 873 ##### State and Errors functions #####
phungductung 0:e87aa4c49e95 874 ===============================================================================
phungductung 0:e87aa4c49e95 875 [..]
phungductung 0:e87aa4c49e95 876 This subsection provides functions allowing to
phungductung 0:e87aa4c49e95 877 (+) Check the DMA state
phungductung 0:e87aa4c49e95 878 (+) Get error code
phungductung 0:e87aa4c49e95 879
phungductung 0:e87aa4c49e95 880 @endverbatim
phungductung 0:e87aa4c49e95 881 * @{
phungductung 0:e87aa4c49e95 882 */
phungductung 0:e87aa4c49e95 883
phungductung 0:e87aa4c49e95 884 /**
phungductung 0:e87aa4c49e95 885 * @brief Returns the DMA state.
phungductung 0:e87aa4c49e95 886 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 887 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 888 * @retval HAL state
phungductung 0:e87aa4c49e95 889 */
phungductung 0:e87aa4c49e95 890 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 891 {
phungductung 0:e87aa4c49e95 892 return hdma->State;
phungductung 0:e87aa4c49e95 893 }
phungductung 0:e87aa4c49e95 894
phungductung 0:e87aa4c49e95 895 /**
phungductung 0:e87aa4c49e95 896 * @brief Return the DMA error code
phungductung 0:e87aa4c49e95 897 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 898 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 899 * @retval DMA Error Code
phungductung 0:e87aa4c49e95 900 */
phungductung 0:e87aa4c49e95 901 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 902 {
phungductung 0:e87aa4c49e95 903 return hdma->ErrorCode;
phungductung 0:e87aa4c49e95 904 }
phungductung 0:e87aa4c49e95 905
phungductung 0:e87aa4c49e95 906 /**
phungductung 0:e87aa4c49e95 907 * @}
phungductung 0:e87aa4c49e95 908 */
phungductung 0:e87aa4c49e95 909
phungductung 0:e87aa4c49e95 910 /**
phungductung 0:e87aa4c49e95 911 * @brief Returns the DMA Stream base address depending on stream number
phungductung 0:e87aa4c49e95 912 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 913 * the configuration information for the specified DMA Stream.
phungductung 0:e87aa4c49e95 914 * @retval Stream base address
phungductung 0:e87aa4c49e95 915 */
phungductung 0:e87aa4c49e95 916 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
phungductung 0:e87aa4c49e95 917 {
phungductung 0:e87aa4c49e95 918 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
phungductung 0:e87aa4c49e95 919
phungductung 0:e87aa4c49e95 920 /* lookup table for necessary bitshift of flags within status registers */
phungductung 0:e87aa4c49e95 921 static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
phungductung 0:e87aa4c49e95 922 hdma->StreamIndex = flagBitshiftOffset[stream_number];
phungductung 0:e87aa4c49e95 923
phungductung 0:e87aa4c49e95 924 if (stream_number > 3)
phungductung 0:e87aa4c49e95 925 {
phungductung 0:e87aa4c49e95 926 /* return pointer to HISR and HIFCR */
phungductung 0:e87aa4c49e95 927 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
phungductung 0:e87aa4c49e95 928 }
phungductung 0:e87aa4c49e95 929 else
phungductung 0:e87aa4c49e95 930 {
phungductung 0:e87aa4c49e95 931 /* return pointer to LISR and LIFCR */
phungductung 0:e87aa4c49e95 932 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
phungductung 0:e87aa4c49e95 933 }
phungductung 0:e87aa4c49e95 934
phungductung 0:e87aa4c49e95 935 return hdma->StreamBaseAddress;
phungductung 0:e87aa4c49e95 936 }
phungductung 0:e87aa4c49e95 937 /**
phungductung 0:e87aa4c49e95 938 * @}
phungductung 0:e87aa4c49e95 939 */
phungductung 0:e87aa4c49e95 940
phungductung 0:e87aa4c49e95 941 #endif /* HAL_DMA_MODULE_ENABLED */
phungductung 0:e87aa4c49e95 942 /**
phungductung 0:e87aa4c49e95 943 * @}
phungductung 0:e87aa4c49e95 944 */
phungductung 0:e87aa4c49e95 945
phungductung 0:e87aa4c49e95 946 /**
phungductung 0:e87aa4c49e95 947 * @}
phungductung 0:e87aa4c49e95 948 */
phungductung 0:e87aa4c49e95 949
phungductung 0:e87aa4c49e95 950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/