PHung Tung
SPKT
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h@0:e87aa4c49e95, 2019-06-04 (annotated)
- Committer:
- phungductung
- Date:
- Tue Jun 04 21:51:46 2019 +0000
- Revision:
- 0:e87aa4c49e95
libray
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| phungductung | 0:e87aa4c49e95 | 1 | /** |
| phungductung | 0:e87aa4c49e95 | 2 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 3 | * @file stm32f7xx_hal_cortex.h |
| phungductung | 0:e87aa4c49e95 | 4 | * @author MCD Application Team |
| phungductung | 0:e87aa4c49e95 | 5 | * @version V1.0.4 |
| phungductung | 0:e87aa4c49e95 | 6 | * @date 09-December-2015 |
| phungductung | 0:e87aa4c49e95 | 7 | * @brief Header file of CORTEX HAL module. |
| phungductung | 0:e87aa4c49e95 | 8 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 9 | * @attention |
| phungductung | 0:e87aa4c49e95 | 10 | * |
| phungductung | 0:e87aa4c49e95 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| phungductung | 0:e87aa4c49e95 | 12 | * |
| phungductung | 0:e87aa4c49e95 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| phungductung | 0:e87aa4c49e95 | 14 | * are permitted provided that the following conditions are met: |
| phungductung | 0:e87aa4c49e95 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| phungductung | 0:e87aa4c49e95 | 16 | * this list of conditions and the following disclaimer. |
| phungductung | 0:e87aa4c49e95 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| phungductung | 0:e87aa4c49e95 | 18 | * this list of conditions and the following disclaimer in the documentation |
| phungductung | 0:e87aa4c49e95 | 19 | * and/or other materials provided with the distribution. |
| phungductung | 0:e87aa4c49e95 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| phungductung | 0:e87aa4c49e95 | 21 | * may be used to endorse or promote products derived from this software |
| phungductung | 0:e87aa4c49e95 | 22 | * without specific prior written permission. |
| phungductung | 0:e87aa4c49e95 | 23 | * |
| phungductung | 0:e87aa4c49e95 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| phungductung | 0:e87aa4c49e95 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| phungductung | 0:e87aa4c49e95 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| phungductung | 0:e87aa4c49e95 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| phungductung | 0:e87aa4c49e95 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| phungductung | 0:e87aa4c49e95 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| phungductung | 0:e87aa4c49e95 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| phungductung | 0:e87aa4c49e95 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| phungductung | 0:e87aa4c49e95 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| phungductung | 0:e87aa4c49e95 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| phungductung | 0:e87aa4c49e95 | 34 | * |
| phungductung | 0:e87aa4c49e95 | 35 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 36 | */ |
| phungductung | 0:e87aa4c49e95 | 37 | |
| phungductung | 0:e87aa4c49e95 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 39 | #ifndef __STM32F7xx_HAL_CORTEX_H |
| phungductung | 0:e87aa4c49e95 | 40 | #define __STM32F7xx_HAL_CORTEX_H |
| phungductung | 0:e87aa4c49e95 | 41 | |
| phungductung | 0:e87aa4c49e95 | 42 | #ifdef __cplusplus |
| phungductung | 0:e87aa4c49e95 | 43 | extern "C" { |
| phungductung | 0:e87aa4c49e95 | 44 | #endif |
| phungductung | 0:e87aa4c49e95 | 45 | |
| phungductung | 0:e87aa4c49e95 | 46 | /* Includes ------------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 47 | #include "stm32f7xx_hal_def.h" |
| phungductung | 0:e87aa4c49e95 | 48 | |
| phungductung | 0:e87aa4c49e95 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| phungductung | 0:e87aa4c49e95 | 50 | * @{ |
| phungductung | 0:e87aa4c49e95 | 51 | */ |
| phungductung | 0:e87aa4c49e95 | 52 | |
| phungductung | 0:e87aa4c49e95 | 53 | /** @addtogroup CORTEX |
| phungductung | 0:e87aa4c49e95 | 54 | * @{ |
| phungductung | 0:e87aa4c49e95 | 55 | */ |
| phungductung | 0:e87aa4c49e95 | 56 | /* Exported types ------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 57 | /** @defgroup CORTEX_Exported_Types Cortex Exported Types |
| phungductung | 0:e87aa4c49e95 | 58 | * @{ |
| phungductung | 0:e87aa4c49e95 | 59 | */ |
| phungductung | 0:e87aa4c49e95 | 60 | |
| phungductung | 0:e87aa4c49e95 | 61 | #if (__MPU_PRESENT == 1) |
| phungductung | 0:e87aa4c49e95 | 62 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
| phungductung | 0:e87aa4c49e95 | 63 | * @brief MPU Region initialization structure |
| phungductung | 0:e87aa4c49e95 | 64 | * @{ |
| phungductung | 0:e87aa4c49e95 | 65 | */ |
| phungductung | 0:e87aa4c49e95 | 66 | typedef struct |
| phungductung | 0:e87aa4c49e95 | 67 | { |
| phungductung | 0:e87aa4c49e95 | 68 | uint8_t Enable; /*!< Specifies the status of the region. |
| phungductung | 0:e87aa4c49e95 | 69 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
| phungductung | 0:e87aa4c49e95 | 70 | uint8_t Number; /*!< Specifies the number of the region to protect. |
| phungductung | 0:e87aa4c49e95 | 71 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
| phungductung | 0:e87aa4c49e95 | 72 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
| phungductung | 0:e87aa4c49e95 | 73 | uint8_t Size; /*!< Specifies the size of the region to protect. |
| phungductung | 0:e87aa4c49e95 | 74 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
| phungductung | 0:e87aa4c49e95 | 75 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
| phungductung | 0:e87aa4c49e95 | 76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| phungductung | 0:e87aa4c49e95 | 77 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
| phungductung | 0:e87aa4c49e95 | 78 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
| phungductung | 0:e87aa4c49e95 | 79 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
| phungductung | 0:e87aa4c49e95 | 80 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
| phungductung | 0:e87aa4c49e95 | 81 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
| phungductung | 0:e87aa4c49e95 | 82 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
| phungductung | 0:e87aa4c49e95 | 83 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
| phungductung | 0:e87aa4c49e95 | 84 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
| phungductung | 0:e87aa4c49e95 | 85 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
| phungductung | 0:e87aa4c49e95 | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
| phungductung | 0:e87aa4c49e95 | 87 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
| phungductung | 0:e87aa4c49e95 | 88 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
| phungductung | 0:e87aa4c49e95 | 89 | }MPU_Region_InitTypeDef; |
| phungductung | 0:e87aa4c49e95 | 90 | /** |
| phungductung | 0:e87aa4c49e95 | 91 | * @} |
| phungductung | 0:e87aa4c49e95 | 92 | */ |
| phungductung | 0:e87aa4c49e95 | 93 | #endif /* __MPU_PRESENT */ |
| phungductung | 0:e87aa4c49e95 | 94 | |
| phungductung | 0:e87aa4c49e95 | 95 | /** |
| phungductung | 0:e87aa4c49e95 | 96 | * @} |
| phungductung | 0:e87aa4c49e95 | 97 | */ |
| phungductung | 0:e87aa4c49e95 | 98 | |
| phungductung | 0:e87aa4c49e95 | 99 | /* Exported constants --------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 100 | |
| phungductung | 0:e87aa4c49e95 | 101 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
| phungductung | 0:e87aa4c49e95 | 102 | * @{ |
| phungductung | 0:e87aa4c49e95 | 103 | */ |
| phungductung | 0:e87aa4c49e95 | 104 | |
| phungductung | 0:e87aa4c49e95 | 105 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
| phungductung | 0:e87aa4c49e95 | 106 | * @{ |
| phungductung | 0:e87aa4c49e95 | 107 | */ |
| phungductung | 0:e87aa4c49e95 | 108 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority |
| phungductung | 0:e87aa4c49e95 | 109 | 4 bits for subpriority */ |
| phungductung | 0:e87aa4c49e95 | 110 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority |
| phungductung | 0:e87aa4c49e95 | 111 | 3 bits for subpriority */ |
| phungductung | 0:e87aa4c49e95 | 112 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority |
| phungductung | 0:e87aa4c49e95 | 113 | 2 bits for subpriority */ |
| phungductung | 0:e87aa4c49e95 | 114 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority |
| phungductung | 0:e87aa4c49e95 | 115 | 1 bits for subpriority */ |
| phungductung | 0:e87aa4c49e95 | 116 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority |
| phungductung | 0:e87aa4c49e95 | 117 | 0 bits for subpriority */ |
| phungductung | 0:e87aa4c49e95 | 118 | /** |
| phungductung | 0:e87aa4c49e95 | 119 | * @} |
| phungductung | 0:e87aa4c49e95 | 120 | */ |
| phungductung | 0:e87aa4c49e95 | 121 | |
| phungductung | 0:e87aa4c49e95 | 122 | /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source |
| phungductung | 0:e87aa4c49e95 | 123 | * @{ |
| phungductung | 0:e87aa4c49e95 | 124 | */ |
| phungductung | 0:e87aa4c49e95 | 125 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) |
| phungductung | 0:e87aa4c49e95 | 126 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) |
| phungductung | 0:e87aa4c49e95 | 127 | |
| phungductung | 0:e87aa4c49e95 | 128 | /** |
| phungductung | 0:e87aa4c49e95 | 129 | * @} |
| phungductung | 0:e87aa4c49e95 | 130 | */ |
| phungductung | 0:e87aa4c49e95 | 131 | |
| phungductung | 0:e87aa4c49e95 | 132 | #if (__MPU_PRESENT == 1) |
| phungductung | 0:e87aa4c49e95 | 133 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control |
| phungductung | 0:e87aa4c49e95 | 134 | * @{ |
| phungductung | 0:e87aa4c49e95 | 135 | */ |
| phungductung | 0:e87aa4c49e95 | 136 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) |
| phungductung | 0:e87aa4c49e95 | 137 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) |
| phungductung | 0:e87aa4c49e95 | 138 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) |
| phungductung | 0:e87aa4c49e95 | 139 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) |
| phungductung | 0:e87aa4c49e95 | 140 | /** |
| phungductung | 0:e87aa4c49e95 | 141 | * @} |
| phungductung | 0:e87aa4c49e95 | 142 | */ |
| phungductung | 0:e87aa4c49e95 | 143 | |
| phungductung | 0:e87aa4c49e95 | 144 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
| phungductung | 0:e87aa4c49e95 | 145 | * @{ |
| phungductung | 0:e87aa4c49e95 | 146 | */ |
| phungductung | 0:e87aa4c49e95 | 147 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 148 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 149 | /** |
| phungductung | 0:e87aa4c49e95 | 150 | * @} |
| phungductung | 0:e87aa4c49e95 | 151 | */ |
| phungductung | 0:e87aa4c49e95 | 152 | |
| phungductung | 0:e87aa4c49e95 | 153 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
| phungductung | 0:e87aa4c49e95 | 154 | * @{ |
| phungductung | 0:e87aa4c49e95 | 155 | */ |
| phungductung | 0:e87aa4c49e95 | 156 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 157 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 158 | /** |
| phungductung | 0:e87aa4c49e95 | 159 | * @} |
| phungductung | 0:e87aa4c49e95 | 160 | */ |
| phungductung | 0:e87aa4c49e95 | 161 | |
| phungductung | 0:e87aa4c49e95 | 162 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
| phungductung | 0:e87aa4c49e95 | 163 | * @{ |
| phungductung | 0:e87aa4c49e95 | 164 | */ |
| phungductung | 0:e87aa4c49e95 | 165 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 166 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 167 | /** |
| phungductung | 0:e87aa4c49e95 | 168 | * @} |
| phungductung | 0:e87aa4c49e95 | 169 | */ |
| phungductung | 0:e87aa4c49e95 | 170 | |
| phungductung | 0:e87aa4c49e95 | 171 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
| phungductung | 0:e87aa4c49e95 | 172 | * @{ |
| phungductung | 0:e87aa4c49e95 | 173 | */ |
| phungductung | 0:e87aa4c49e95 | 174 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 175 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 176 | /** |
| phungductung | 0:e87aa4c49e95 | 177 | * @} |
| phungductung | 0:e87aa4c49e95 | 178 | */ |
| phungductung | 0:e87aa4c49e95 | 179 | |
| phungductung | 0:e87aa4c49e95 | 180 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
| phungductung | 0:e87aa4c49e95 | 181 | * @{ |
| phungductung | 0:e87aa4c49e95 | 182 | */ |
| phungductung | 0:e87aa4c49e95 | 183 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 184 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 185 | /** |
| phungductung | 0:e87aa4c49e95 | 186 | * @} |
| phungductung | 0:e87aa4c49e95 | 187 | */ |
| phungductung | 0:e87aa4c49e95 | 188 | |
| phungductung | 0:e87aa4c49e95 | 189 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels |
| phungductung | 0:e87aa4c49e95 | 190 | * @{ |
| phungductung | 0:e87aa4c49e95 | 191 | */ |
| phungductung | 0:e87aa4c49e95 | 192 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 193 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 194 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
| phungductung | 0:e87aa4c49e95 | 195 | /** |
| phungductung | 0:e87aa4c49e95 | 196 | * @} |
| phungductung | 0:e87aa4c49e95 | 197 | */ |
| phungductung | 0:e87aa4c49e95 | 198 | |
| phungductung | 0:e87aa4c49e95 | 199 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
| phungductung | 0:e87aa4c49e95 | 200 | * @{ |
| phungductung | 0:e87aa4c49e95 | 201 | */ |
| phungductung | 0:e87aa4c49e95 | 202 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
| phungductung | 0:e87aa4c49e95 | 203 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
| phungductung | 0:e87aa4c49e95 | 204 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
| phungductung | 0:e87aa4c49e95 | 205 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
| phungductung | 0:e87aa4c49e95 | 206 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
| phungductung | 0:e87aa4c49e95 | 207 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
| phungductung | 0:e87aa4c49e95 | 208 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
| phungductung | 0:e87aa4c49e95 | 209 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
| phungductung | 0:e87aa4c49e95 | 210 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
| phungductung | 0:e87aa4c49e95 | 211 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
| phungductung | 0:e87aa4c49e95 | 212 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
| phungductung | 0:e87aa4c49e95 | 213 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
| phungductung | 0:e87aa4c49e95 | 214 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
| phungductung | 0:e87aa4c49e95 | 215 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
| phungductung | 0:e87aa4c49e95 | 216 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
| phungductung | 0:e87aa4c49e95 | 217 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
| phungductung | 0:e87aa4c49e95 | 218 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
| phungductung | 0:e87aa4c49e95 | 219 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
| phungductung | 0:e87aa4c49e95 | 220 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
| phungductung | 0:e87aa4c49e95 | 221 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
| phungductung | 0:e87aa4c49e95 | 222 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
| phungductung | 0:e87aa4c49e95 | 223 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
| phungductung | 0:e87aa4c49e95 | 224 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
| phungductung | 0:e87aa4c49e95 | 225 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
| phungductung | 0:e87aa4c49e95 | 226 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
| phungductung | 0:e87aa4c49e95 | 227 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
| phungductung | 0:e87aa4c49e95 | 228 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
| phungductung | 0:e87aa4c49e95 | 229 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
| phungductung | 0:e87aa4c49e95 | 230 | /** |
| phungductung | 0:e87aa4c49e95 | 231 | * @} |
| phungductung | 0:e87aa4c49e95 | 232 | */ |
| phungductung | 0:e87aa4c49e95 | 233 | |
| phungductung | 0:e87aa4c49e95 | 234 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
| phungductung | 0:e87aa4c49e95 | 235 | * @{ |
| phungductung | 0:e87aa4c49e95 | 236 | */ |
| phungductung | 0:e87aa4c49e95 | 237 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 238 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 239 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
| phungductung | 0:e87aa4c49e95 | 240 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
| phungductung | 0:e87aa4c49e95 | 241 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
| phungductung | 0:e87aa4c49e95 | 242 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
| phungductung | 0:e87aa4c49e95 | 243 | /** |
| phungductung | 0:e87aa4c49e95 | 244 | * @} |
| phungductung | 0:e87aa4c49e95 | 245 | */ |
| phungductung | 0:e87aa4c49e95 | 246 | |
| phungductung | 0:e87aa4c49e95 | 247 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
| phungductung | 0:e87aa4c49e95 | 248 | * @{ |
| phungductung | 0:e87aa4c49e95 | 249 | */ |
| phungductung | 0:e87aa4c49e95 | 250 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
| phungductung | 0:e87aa4c49e95 | 251 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
| phungductung | 0:e87aa4c49e95 | 252 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
| phungductung | 0:e87aa4c49e95 | 253 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
| phungductung | 0:e87aa4c49e95 | 254 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
| phungductung | 0:e87aa4c49e95 | 255 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
| phungductung | 0:e87aa4c49e95 | 256 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
| phungductung | 0:e87aa4c49e95 | 257 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
| phungductung | 0:e87aa4c49e95 | 258 | /** |
| phungductung | 0:e87aa4c49e95 | 259 | * @} |
| phungductung | 0:e87aa4c49e95 | 260 | */ |
| phungductung | 0:e87aa4c49e95 | 261 | #endif /* __MPU_PRESENT */ |
| phungductung | 0:e87aa4c49e95 | 262 | |
| phungductung | 0:e87aa4c49e95 | 263 | /** |
| phungductung | 0:e87aa4c49e95 | 264 | * @} |
| phungductung | 0:e87aa4c49e95 | 265 | */ |
| phungductung | 0:e87aa4c49e95 | 266 | |
| phungductung | 0:e87aa4c49e95 | 267 | |
| phungductung | 0:e87aa4c49e95 | 268 | /* Exported Macros -----------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 269 | |
| phungductung | 0:e87aa4c49e95 | 270 | /* Exported functions --------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 271 | /** @addtogroup CORTEX_Exported_Functions |
| phungductung | 0:e87aa4c49e95 | 272 | * @{ |
| phungductung | 0:e87aa4c49e95 | 273 | */ |
| phungductung | 0:e87aa4c49e95 | 274 | |
| phungductung | 0:e87aa4c49e95 | 275 | /** @addtogroup CORTEX_Exported_Functions_Group1 |
| phungductung | 0:e87aa4c49e95 | 276 | * @{ |
| phungductung | 0:e87aa4c49e95 | 277 | */ |
| phungductung | 0:e87aa4c49e95 | 278 | /* Initialization and de-initialization functions *****************************/ |
| phungductung | 0:e87aa4c49e95 | 279 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
| phungductung | 0:e87aa4c49e95 | 280 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
| phungductung | 0:e87aa4c49e95 | 281 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
| phungductung | 0:e87aa4c49e95 | 282 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
| phungductung | 0:e87aa4c49e95 | 283 | void HAL_NVIC_SystemReset(void); |
| phungductung | 0:e87aa4c49e95 | 284 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
| phungductung | 0:e87aa4c49e95 | 285 | /** |
| phungductung | 0:e87aa4c49e95 | 286 | * @} |
| phungductung | 0:e87aa4c49e95 | 287 | */ |
| phungductung | 0:e87aa4c49e95 | 288 | |
| phungductung | 0:e87aa4c49e95 | 289 | /** @addtogroup CORTEX_Exported_Functions_Group2 |
| phungductung | 0:e87aa4c49e95 | 290 | * @{ |
| phungductung | 0:e87aa4c49e95 | 291 | */ |
| phungductung | 0:e87aa4c49e95 | 292 | /* Peripheral Control functions ***********************************************/ |
| phungductung | 0:e87aa4c49e95 | 293 | #if (__MPU_PRESENT == 1) |
| phungductung | 0:e87aa4c49e95 | 294 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
| phungductung | 0:e87aa4c49e95 | 295 | #endif /* __MPU_PRESENT */ |
| phungductung | 0:e87aa4c49e95 | 296 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
| phungductung | 0:e87aa4c49e95 | 297 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
| phungductung | 0:e87aa4c49e95 | 298 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
| phungductung | 0:e87aa4c49e95 | 299 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
| phungductung | 0:e87aa4c49e95 | 300 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
| phungductung | 0:e87aa4c49e95 | 301 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
| phungductung | 0:e87aa4c49e95 | 302 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
| phungductung | 0:e87aa4c49e95 | 303 | void HAL_SYSTICK_IRQHandler(void); |
| phungductung | 0:e87aa4c49e95 | 304 | void HAL_SYSTICK_Callback(void); |
| phungductung | 0:e87aa4c49e95 | 305 | /** |
| phungductung | 0:e87aa4c49e95 | 306 | * @} |
| phungductung | 0:e87aa4c49e95 | 307 | */ |
| phungductung | 0:e87aa4c49e95 | 308 | |
| phungductung | 0:e87aa4c49e95 | 309 | /** |
| phungductung | 0:e87aa4c49e95 | 310 | * @} |
| phungductung | 0:e87aa4c49e95 | 311 | */ |
| phungductung | 0:e87aa4c49e95 | 312 | |
| phungductung | 0:e87aa4c49e95 | 313 | /* Private types -------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 314 | /* Private variables ---------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 315 | /* Private constants ---------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 316 | /* Private macros ------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 317 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
| phungductung | 0:e87aa4c49e95 | 318 | * @{ |
| phungductung | 0:e87aa4c49e95 | 319 | */ |
| phungductung | 0:e87aa4c49e95 | 320 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
| phungductung | 0:e87aa4c49e95 | 321 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
| phungductung | 0:e87aa4c49e95 | 322 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
| phungductung | 0:e87aa4c49e95 | 323 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
| phungductung | 0:e87aa4c49e95 | 324 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
| phungductung | 0:e87aa4c49e95 | 325 | |
| phungductung | 0:e87aa4c49e95 | 326 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
| phungductung | 0:e87aa4c49e95 | 327 | |
| phungductung | 0:e87aa4c49e95 | 328 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
| phungductung | 0:e87aa4c49e95 | 329 | |
| phungductung | 0:e87aa4c49e95 | 330 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) |
| phungductung | 0:e87aa4c49e95 | 331 | |
| phungductung | 0:e87aa4c49e95 | 332 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
| phungductung | 0:e87aa4c49e95 | 333 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
| phungductung | 0:e87aa4c49e95 | 334 | |
| phungductung | 0:e87aa4c49e95 | 335 | #if (__MPU_PRESENT == 1) |
| phungductung | 0:e87aa4c49e95 | 336 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 337 | ((STATE) == MPU_REGION_DISABLE)) |
| phungductung | 0:e87aa4c49e95 | 338 | |
| phungductung | 0:e87aa4c49e95 | 339 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 340 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
| phungductung | 0:e87aa4c49e95 | 341 | |
| phungductung | 0:e87aa4c49e95 | 342 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 343 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
| phungductung | 0:e87aa4c49e95 | 344 | |
| phungductung | 0:e87aa4c49e95 | 345 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 346 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
| phungductung | 0:e87aa4c49e95 | 347 | |
| phungductung | 0:e87aa4c49e95 | 348 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
| phungductung | 0:e87aa4c49e95 | 349 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
| phungductung | 0:e87aa4c49e95 | 350 | |
| phungductung | 0:e87aa4c49e95 | 351 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
| phungductung | 0:e87aa4c49e95 | 352 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
| phungductung | 0:e87aa4c49e95 | 353 | ((TYPE) == MPU_TEX_LEVEL2)) |
| phungductung | 0:e87aa4c49e95 | 354 | |
| phungductung | 0:e87aa4c49e95 | 355 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
| phungductung | 0:e87aa4c49e95 | 356 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
| phungductung | 0:e87aa4c49e95 | 357 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
| phungductung | 0:e87aa4c49e95 | 358 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
| phungductung | 0:e87aa4c49e95 | 359 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
| phungductung | 0:e87aa4c49e95 | 360 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
| phungductung | 0:e87aa4c49e95 | 361 | |
| phungductung | 0:e87aa4c49e95 | 362 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
| phungductung | 0:e87aa4c49e95 | 363 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
| phungductung | 0:e87aa4c49e95 | 364 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
| phungductung | 0:e87aa4c49e95 | 365 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
| phungductung | 0:e87aa4c49e95 | 366 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
| phungductung | 0:e87aa4c49e95 | 367 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
| phungductung | 0:e87aa4c49e95 | 368 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
| phungductung | 0:e87aa4c49e95 | 369 | ((NUMBER) == MPU_REGION_NUMBER7)) |
| phungductung | 0:e87aa4c49e95 | 370 | |
| phungductung | 0:e87aa4c49e95 | 371 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
| phungductung | 0:e87aa4c49e95 | 372 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
| phungductung | 0:e87aa4c49e95 | 373 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
| phungductung | 0:e87aa4c49e95 | 374 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
| phungductung | 0:e87aa4c49e95 | 375 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
| phungductung | 0:e87aa4c49e95 | 376 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
| phungductung | 0:e87aa4c49e95 | 377 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
| phungductung | 0:e87aa4c49e95 | 378 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
| phungductung | 0:e87aa4c49e95 | 379 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
| phungductung | 0:e87aa4c49e95 | 380 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
| phungductung | 0:e87aa4c49e95 | 381 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
| phungductung | 0:e87aa4c49e95 | 382 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
| phungductung | 0:e87aa4c49e95 | 383 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
| phungductung | 0:e87aa4c49e95 | 384 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
| phungductung | 0:e87aa4c49e95 | 385 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
| phungductung | 0:e87aa4c49e95 | 386 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
| phungductung | 0:e87aa4c49e95 | 387 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
| phungductung | 0:e87aa4c49e95 | 388 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
| phungductung | 0:e87aa4c49e95 | 389 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
| phungductung | 0:e87aa4c49e95 | 390 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
| phungductung | 0:e87aa4c49e95 | 391 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
| phungductung | 0:e87aa4c49e95 | 392 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
| phungductung | 0:e87aa4c49e95 | 393 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
| phungductung | 0:e87aa4c49e95 | 394 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
| phungductung | 0:e87aa4c49e95 | 395 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
| phungductung | 0:e87aa4c49e95 | 396 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
| phungductung | 0:e87aa4c49e95 | 397 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
| phungductung | 0:e87aa4c49e95 | 398 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
| phungductung | 0:e87aa4c49e95 | 399 | |
| phungductung | 0:e87aa4c49e95 | 400 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
| phungductung | 0:e87aa4c49e95 | 401 | #endif /* __MPU_PRESENT */ |
| phungductung | 0:e87aa4c49e95 | 402 | |
| phungductung | 0:e87aa4c49e95 | 403 | /** |
| phungductung | 0:e87aa4c49e95 | 404 | * @} |
| phungductung | 0:e87aa4c49e95 | 405 | */ |
| phungductung | 0:e87aa4c49e95 | 406 | |
| phungductung | 0:e87aa4c49e95 | 407 | /* Private functions ---------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 408 | /** @defgroup CORTEX_Private_Functions CORTEX Private Functions |
| phungductung | 0:e87aa4c49e95 | 409 | * @brief CORTEX private functions |
| phungductung | 0:e87aa4c49e95 | 410 | * @{ |
| phungductung | 0:e87aa4c49e95 | 411 | */ |
| phungductung | 0:e87aa4c49e95 | 412 | |
| phungductung | 0:e87aa4c49e95 | 413 | #if (__MPU_PRESENT == 1) |
| phungductung | 0:e87aa4c49e95 | 414 | /** |
| phungductung | 0:e87aa4c49e95 | 415 | * @brief Disables the MPU |
| phungductung | 0:e87aa4c49e95 | 416 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 417 | */ |
| phungductung | 0:e87aa4c49e95 | 418 | __STATIC_INLINE void HAL_MPU_Disable(void) |
| phungductung | 0:e87aa4c49e95 | 419 | { |
| phungductung | 0:e87aa4c49e95 | 420 | /* Disable fault exceptions */ |
| phungductung | 0:e87aa4c49e95 | 421 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
| phungductung | 0:e87aa4c49e95 | 422 | |
| phungductung | 0:e87aa4c49e95 | 423 | /* Disable the MPU */ |
| phungductung | 0:e87aa4c49e95 | 424 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
| phungductung | 0:e87aa4c49e95 | 425 | } |
| phungductung | 0:e87aa4c49e95 | 426 | |
| phungductung | 0:e87aa4c49e95 | 427 | /** |
| phungductung | 0:e87aa4c49e95 | 428 | * @brief Enables the MPU |
| phungductung | 0:e87aa4c49e95 | 429 | * @param MPU_Control: Specifies the control mode of the MPU during hard fault, |
| phungductung | 0:e87aa4c49e95 | 430 | * NMI, FAULTMASK and privileged access to the default memory |
| phungductung | 0:e87aa4c49e95 | 431 | * This parameter can be one of the following values: |
| phungductung | 0:e87aa4c49e95 | 432 | * @arg MPU_HFNMI_PRIVDEF_NONE |
| phungductung | 0:e87aa4c49e95 | 433 | * @arg MPU_HARDFAULT_NMI |
| phungductung | 0:e87aa4c49e95 | 434 | * @arg MPU_PRIVILEGED_DEFAULT |
| phungductung | 0:e87aa4c49e95 | 435 | * @arg MPU_HFNMI_PRIVDEF |
| phungductung | 0:e87aa4c49e95 | 436 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 437 | */ |
| phungductung | 0:e87aa4c49e95 | 438 | __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) |
| phungductung | 0:e87aa4c49e95 | 439 | { |
| phungductung | 0:e87aa4c49e95 | 440 | /* Enable the MPU */ |
| phungductung | 0:e87aa4c49e95 | 441 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
| phungductung | 0:e87aa4c49e95 | 442 | |
| phungductung | 0:e87aa4c49e95 | 443 | /* Enable fault exceptions */ |
| phungductung | 0:e87aa4c49e95 | 444 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
| phungductung | 0:e87aa4c49e95 | 445 | } |
| phungductung | 0:e87aa4c49e95 | 446 | #endif /* __MPU_PRESENT */ |
| phungductung | 0:e87aa4c49e95 | 447 | |
| phungductung | 0:e87aa4c49e95 | 448 | /** |
| phungductung | 0:e87aa4c49e95 | 449 | * @} |
| phungductung | 0:e87aa4c49e95 | 450 | */ |
| phungductung | 0:e87aa4c49e95 | 451 | |
| phungductung | 0:e87aa4c49e95 | 452 | /** |
| phungductung | 0:e87aa4c49e95 | 453 | * @} |
| phungductung | 0:e87aa4c49e95 | 454 | */ |
| phungductung | 0:e87aa4c49e95 | 455 | |
| phungductung | 0:e87aa4c49e95 | 456 | /** |
| phungductung | 0:e87aa4c49e95 | 457 | * @} |
| phungductung | 0:e87aa4c49e95 | 458 | */ |
| phungductung | 0:e87aa4c49e95 | 459 | |
| phungductung | 0:e87aa4c49e95 | 460 | #ifdef __cplusplus |
| phungductung | 0:e87aa4c49e95 | 461 | } |
| phungductung | 0:e87aa4c49e95 | 462 | #endif |
| phungductung | 0:e87aa4c49e95 | 463 | |
| phungductung | 0:e87aa4c49e95 | 464 | #endif /* __STM32F7xx_HAL_CORTEX_H */ |
| phungductung | 0:e87aa4c49e95 | 465 | |
| phungductung | 0:e87aa4c49e95 | 466 | |
| phungductung | 0:e87aa4c49e95 | 467 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |