PHung Tung
SPKT
targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c@0:e87aa4c49e95, 2019-06-04 (annotated)
- Committer:
- phungductung
- Date:
- Tue Jun 04 21:51:46 2019 +0000
- Revision:
- 0:e87aa4c49e95
libray
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| phungductung | 0:e87aa4c49e95 | 1 | /** |
| phungductung | 0:e87aa4c49e95 | 2 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 3 | * @file system_stm32f7xx.c |
| phungductung | 0:e87aa4c49e95 | 4 | * @author MCD Application Team |
| phungductung | 0:e87aa4c49e95 | 5 | * @version V1.0.2 |
| phungductung | 0:e87aa4c49e95 | 6 | * @date 21-September-2015 |
| phungductung | 0:e87aa4c49e95 | 7 | * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. |
| phungductung | 0:e87aa4c49e95 | 8 | * |
| phungductung | 0:e87aa4c49e95 | 9 | * This file provides two functions and one global variable to be called from |
| phungductung | 0:e87aa4c49e95 | 10 | * user application: |
| phungductung | 0:e87aa4c49e95 | 11 | * - SystemInit(): This function is called at startup just after reset and |
| phungductung | 0:e87aa4c49e95 | 12 | * before branch to main program. This call is made inside |
| phungductung | 0:e87aa4c49e95 | 13 | * the "startup_stm32f7xx.s" file. |
| phungductung | 0:e87aa4c49e95 | 14 | * |
| phungductung | 0:e87aa4c49e95 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| phungductung | 0:e87aa4c49e95 | 16 | * by the user application to setup the SysTick |
| phungductung | 0:e87aa4c49e95 | 17 | * timer or configure other parameters. |
| phungductung | 0:e87aa4c49e95 | 18 | * |
| phungductung | 0:e87aa4c49e95 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| phungductung | 0:e87aa4c49e95 | 20 | * be called whenever the core clock is changed |
| phungductung | 0:e87aa4c49e95 | 21 | * during program execution. |
| phungductung | 0:e87aa4c49e95 | 22 | * |
| phungductung | 0:e87aa4c49e95 | 23 | * This file configures the system clock as follows: |
| phungductung | 0:e87aa4c49e95 | 24 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 25 | * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails |
| phungductung | 0:e87aa4c49e95 | 26 | * | (external 25MHz xtal) | (internal 16MHz clock) |
| phungductung | 0:e87aa4c49e95 | 27 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 28 | * SYSCLK(MHz) | 216 | 216 |
| phungductung | 0:e87aa4c49e95 | 29 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 30 | * AHBCLK (MHz) | 216 | 216 |
| phungductung | 0:e87aa4c49e95 | 31 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 32 | * APB1CLK (MHz) | 54 | 54 |
| phungductung | 0:e87aa4c49e95 | 33 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 34 | * APB2CLK (MHz) | 108 | 108 |
| phungductung | 0:e87aa4c49e95 | 35 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 36 | * USB capable | YES | NO |
| phungductung | 0:e87aa4c49e95 | 37 | * with 48 MHz precise clock | | |
| phungductung | 0:e87aa4c49e95 | 38 | *----------------------------------------------------------------------------- |
| phungductung | 0:e87aa4c49e95 | 39 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 40 | * @attention |
| phungductung | 0:e87aa4c49e95 | 41 | * |
| phungductung | 0:e87aa4c49e95 | 42 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| phungductung | 0:e87aa4c49e95 | 43 | * |
| phungductung | 0:e87aa4c49e95 | 44 | * Redistribution and use in source and binary forms, with or without modification, |
| phungductung | 0:e87aa4c49e95 | 45 | * are permitted provided that the following conditions are met: |
| phungductung | 0:e87aa4c49e95 | 46 | * 1. Redistributions of source code must retain the above copyright notice, |
| phungductung | 0:e87aa4c49e95 | 47 | * this list of conditions and the following disclaimer. |
| phungductung | 0:e87aa4c49e95 | 48 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| phungductung | 0:e87aa4c49e95 | 49 | * this list of conditions and the following disclaimer in the documentation |
| phungductung | 0:e87aa4c49e95 | 50 | * and/or other materials provided with the distribution. |
| phungductung | 0:e87aa4c49e95 | 51 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| phungductung | 0:e87aa4c49e95 | 52 | * may be used to endorse or promote products derived from this software |
| phungductung | 0:e87aa4c49e95 | 53 | * without specific prior written permission. |
| phungductung | 0:e87aa4c49e95 | 54 | * |
| phungductung | 0:e87aa4c49e95 | 55 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| phungductung | 0:e87aa4c49e95 | 56 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| phungductung | 0:e87aa4c49e95 | 57 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| phungductung | 0:e87aa4c49e95 | 58 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| phungductung | 0:e87aa4c49e95 | 59 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| phungductung | 0:e87aa4c49e95 | 60 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| phungductung | 0:e87aa4c49e95 | 61 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| phungductung | 0:e87aa4c49e95 | 62 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| phungductung | 0:e87aa4c49e95 | 63 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| phungductung | 0:e87aa4c49e95 | 64 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| phungductung | 0:e87aa4c49e95 | 65 | * |
| phungductung | 0:e87aa4c49e95 | 66 | ****************************************************************************** |
| phungductung | 0:e87aa4c49e95 | 67 | */ |
| phungductung | 0:e87aa4c49e95 | 68 | |
| phungductung | 0:e87aa4c49e95 | 69 | /** @addtogroup CMSIS |
| phungductung | 0:e87aa4c49e95 | 70 | * @{ |
| phungductung | 0:e87aa4c49e95 | 71 | */ |
| phungductung | 0:e87aa4c49e95 | 72 | |
| phungductung | 0:e87aa4c49e95 | 73 | /** @addtogroup stm32f7xx_system |
| phungductung | 0:e87aa4c49e95 | 74 | * @{ |
| phungductung | 0:e87aa4c49e95 | 75 | */ |
| phungductung | 0:e87aa4c49e95 | 76 | |
| phungductung | 0:e87aa4c49e95 | 77 | /** @addtogroup STM32F7xx_System_Private_Includes |
| phungductung | 0:e87aa4c49e95 | 78 | * @{ |
| phungductung | 0:e87aa4c49e95 | 79 | */ |
| phungductung | 0:e87aa4c49e95 | 80 | |
| phungductung | 0:e87aa4c49e95 | 81 | #include "stm32f7xx.h" |
| phungductung | 0:e87aa4c49e95 | 82 | #include "hal_tick.h" |
| phungductung | 0:e87aa4c49e95 | 83 | |
| phungductung | 0:e87aa4c49e95 | 84 | HAL_StatusTypeDef HAL_Init(void); |
| phungductung | 0:e87aa4c49e95 | 85 | |
| phungductung | 0:e87aa4c49e95 | 86 | #if !defined (HSE_VALUE) |
| phungductung | 0:e87aa4c49e95 | 87 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ |
| phungductung | 0:e87aa4c49e95 | 88 | #endif /* HSE_VALUE */ |
| phungductung | 0:e87aa4c49e95 | 89 | |
| phungductung | 0:e87aa4c49e95 | 90 | #if !defined (HSI_VALUE) |
| phungductung | 0:e87aa4c49e95 | 91 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| phungductung | 0:e87aa4c49e95 | 92 | #endif /* HSI_VALUE */ |
| phungductung | 0:e87aa4c49e95 | 93 | |
| phungductung | 0:e87aa4c49e95 | 94 | /** |
| phungductung | 0:e87aa4c49e95 | 95 | * @} |
| phungductung | 0:e87aa4c49e95 | 96 | */ |
| phungductung | 0:e87aa4c49e95 | 97 | |
| phungductung | 0:e87aa4c49e95 | 98 | /** @addtogroup STM32F7xx_System_Private_TypesDefinitions |
| phungductung | 0:e87aa4c49e95 | 99 | * @{ |
| phungductung | 0:e87aa4c49e95 | 100 | */ |
| phungductung | 0:e87aa4c49e95 | 101 | |
| phungductung | 0:e87aa4c49e95 | 102 | /** |
| phungductung | 0:e87aa4c49e95 | 103 | * @} |
| phungductung | 0:e87aa4c49e95 | 104 | */ |
| phungductung | 0:e87aa4c49e95 | 105 | |
| phungductung | 0:e87aa4c49e95 | 106 | /** @addtogroup STM32F7xx_System_Private_Defines |
| phungductung | 0:e87aa4c49e95 | 107 | * @{ |
| phungductung | 0:e87aa4c49e95 | 108 | */ |
| phungductung | 0:e87aa4c49e95 | 109 | |
| phungductung | 0:e87aa4c49e95 | 110 | /************************* Miscellaneous Configuration ************************/ |
| phungductung | 0:e87aa4c49e95 | 111 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted |
| phungductung | 0:e87aa4c49e95 | 112 | on STMicroelectronics EVAL/Discovery boards as data memory */ |
| phungductung | 0:e87aa4c49e95 | 113 | /*!< In case of EVAL/Discoverys LCD use in application code, the DATA_IN_ExtSDRAM define |
| phungductung | 0:e87aa4c49e95 | 114 | need to be added in the project preprocessor to avoid SDRAM multiple configuration |
| phungductung | 0:e87aa4c49e95 | 115 | (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */ |
| phungductung | 0:e87aa4c49e95 | 116 | /* #define DATA_IN_ExtSRAM */ |
| phungductung | 0:e87aa4c49e95 | 117 | /* #define DATA_IN_ExtSDRAM */ |
| phungductung | 0:e87aa4c49e95 | 118 | |
| phungductung | 0:e87aa4c49e95 | 119 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| phungductung | 0:e87aa4c49e95 | 120 | Internal SRAM. */ |
| phungductung | 0:e87aa4c49e95 | 121 | /* #define VECT_TAB_SRAM */ |
| phungductung | 0:e87aa4c49e95 | 122 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| phungductung | 0:e87aa4c49e95 | 123 | This value must be a multiple of 0x200. */ |
| phungductung | 0:e87aa4c49e95 | 124 | /******************************************************************************/ |
| phungductung | 0:e87aa4c49e95 | 125 | |
| phungductung | 0:e87aa4c49e95 | 126 | /** |
| phungductung | 0:e87aa4c49e95 | 127 | * @} |
| phungductung | 0:e87aa4c49e95 | 128 | */ |
| phungductung | 0:e87aa4c49e95 | 129 | |
| phungductung | 0:e87aa4c49e95 | 130 | /** @addtogroup STM32F7xx_System_Private_Macros |
| phungductung | 0:e87aa4c49e95 | 131 | * @{ |
| phungductung | 0:e87aa4c49e95 | 132 | */ |
| phungductung | 0:e87aa4c49e95 | 133 | |
| phungductung | 0:e87aa4c49e95 | 134 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| phungductung | 0:e87aa4c49e95 | 135 | #define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */ |
| phungductung | 0:e87aa4c49e95 | 136 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| phungductung | 0:e87aa4c49e95 | 137 | |
| phungductung | 0:e87aa4c49e95 | 138 | /** |
| phungductung | 0:e87aa4c49e95 | 139 | * @} |
| phungductung | 0:e87aa4c49e95 | 140 | */ |
| phungductung | 0:e87aa4c49e95 | 141 | |
| phungductung | 0:e87aa4c49e95 | 142 | /** @addtogroup STM32F7xx_System_Private_Variables |
| phungductung | 0:e87aa4c49e95 | 143 | * @{ |
| phungductung | 0:e87aa4c49e95 | 144 | */ |
| phungductung | 0:e87aa4c49e95 | 145 | |
| phungductung | 0:e87aa4c49e95 | 146 | /* This variable is updated in three ways: |
| phungductung | 0:e87aa4c49e95 | 147 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| phungductung | 0:e87aa4c49e95 | 148 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| phungductung | 0:e87aa4c49e95 | 149 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| phungductung | 0:e87aa4c49e95 | 150 | Note: If you use this function to configure the system clock; then there |
| phungductung | 0:e87aa4c49e95 | 151 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| phungductung | 0:e87aa4c49e95 | 152 | variable is updated automatically. |
| phungductung | 0:e87aa4c49e95 | 153 | */ |
| phungductung | 0:e87aa4c49e95 | 154 | uint32_t SystemCoreClock = HSI_VALUE; |
| phungductung | 0:e87aa4c49e95 | 155 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| phungductung | 0:e87aa4c49e95 | 156 | |
| phungductung | 0:e87aa4c49e95 | 157 | /** |
| phungductung | 0:e87aa4c49e95 | 158 | * @} |
| phungductung | 0:e87aa4c49e95 | 159 | */ |
| phungductung | 0:e87aa4c49e95 | 160 | |
| phungductung | 0:e87aa4c49e95 | 161 | /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes |
| phungductung | 0:e87aa4c49e95 | 162 | * @{ |
| phungductung | 0:e87aa4c49e95 | 163 | */ |
| phungductung | 0:e87aa4c49e95 | 164 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| phungductung | 0:e87aa4c49e95 | 165 | static void SystemInit_ExtMemCtl(void); |
| phungductung | 0:e87aa4c49e95 | 166 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| phungductung | 0:e87aa4c49e95 | 167 | |
| phungductung | 0:e87aa4c49e95 | 168 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| phungductung | 0:e87aa4c49e95 | 169 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| phungductung | 0:e87aa4c49e95 | 170 | #endif |
| phungductung | 0:e87aa4c49e95 | 171 | |
| phungductung | 0:e87aa4c49e95 | 172 | uint8_t SetSysClock_PLL_HSI(void); |
| phungductung | 0:e87aa4c49e95 | 173 | |
| phungductung | 0:e87aa4c49e95 | 174 | /** |
| phungductung | 0:e87aa4c49e95 | 175 | * @} |
| phungductung | 0:e87aa4c49e95 | 176 | */ |
| phungductung | 0:e87aa4c49e95 | 177 | |
| phungductung | 0:e87aa4c49e95 | 178 | /** @addtogroup STM32F7xx_System_Private_Functions |
| phungductung | 0:e87aa4c49e95 | 179 | * @{ |
| phungductung | 0:e87aa4c49e95 | 180 | */ |
| phungductung | 0:e87aa4c49e95 | 181 | |
| phungductung | 0:e87aa4c49e95 | 182 | /** |
| phungductung | 0:e87aa4c49e95 | 183 | * @brief Setup the microcontroller system |
| phungductung | 0:e87aa4c49e95 | 184 | * Initialize the Embedded Flash Interface, the PLL and update the |
| phungductung | 0:e87aa4c49e95 | 185 | * SystemFrequency variable. |
| phungductung | 0:e87aa4c49e95 | 186 | * @param None |
| phungductung | 0:e87aa4c49e95 | 187 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 188 | */ |
| phungductung | 0:e87aa4c49e95 | 189 | void SystemInit(void) |
| phungductung | 0:e87aa4c49e95 | 190 | { |
| phungductung | 0:e87aa4c49e95 | 191 | /* FPU settings ------------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 192 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| phungductung | 0:e87aa4c49e95 | 193 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| phungductung | 0:e87aa4c49e95 | 194 | #endif |
| phungductung | 0:e87aa4c49e95 | 195 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| phungductung | 0:e87aa4c49e95 | 196 | /* Set HSION bit */ |
| phungductung | 0:e87aa4c49e95 | 197 | RCC->CR |= (uint32_t)0x00000001; |
| phungductung | 0:e87aa4c49e95 | 198 | |
| phungductung | 0:e87aa4c49e95 | 199 | /* Reset CFGR register */ |
| phungductung | 0:e87aa4c49e95 | 200 | RCC->CFGR = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 201 | |
| phungductung | 0:e87aa4c49e95 | 202 | /* Reset HSEON, CSSON and PLLON bits */ |
| phungductung | 0:e87aa4c49e95 | 203 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| phungductung | 0:e87aa4c49e95 | 204 | |
| phungductung | 0:e87aa4c49e95 | 205 | /* Reset PLLCFGR register */ |
| phungductung | 0:e87aa4c49e95 | 206 | RCC->PLLCFGR = 0x24003010; |
| phungductung | 0:e87aa4c49e95 | 207 | |
| phungductung | 0:e87aa4c49e95 | 208 | /* Reset HSEBYP bit */ |
| phungductung | 0:e87aa4c49e95 | 209 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| phungductung | 0:e87aa4c49e95 | 210 | |
| phungductung | 0:e87aa4c49e95 | 211 | /* Disable all interrupts */ |
| phungductung | 0:e87aa4c49e95 | 212 | RCC->CIR = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 213 | |
| phungductung | 0:e87aa4c49e95 | 214 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| phungductung | 0:e87aa4c49e95 | 215 | SystemInit_ExtMemCtl(); |
| phungductung | 0:e87aa4c49e95 | 216 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| phungductung | 0:e87aa4c49e95 | 217 | |
| phungductung | 0:e87aa4c49e95 | 218 | /* Configure the Vector Table location add offset address ------------------*/ |
| phungductung | 0:e87aa4c49e95 | 219 | #ifdef VECT_TAB_SRAM |
| phungductung | 0:e87aa4c49e95 | 220 | SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| phungductung | 0:e87aa4c49e95 | 221 | #else |
| phungductung | 0:e87aa4c49e95 | 222 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| phungductung | 0:e87aa4c49e95 | 223 | #endif |
| phungductung | 0:e87aa4c49e95 | 224 | |
| phungductung | 0:e87aa4c49e95 | 225 | /* Configure the Cube driver */ |
| phungductung | 0:e87aa4c49e95 | 226 | SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock |
| phungductung | 0:e87aa4c49e95 | 227 | HAL_Init(); |
| phungductung | 0:e87aa4c49e95 | 228 | |
| phungductung | 0:e87aa4c49e95 | 229 | // Enable CPU L1-Cache |
| phungductung | 0:e87aa4c49e95 | 230 | SCB_EnableICache(); |
| phungductung | 0:e87aa4c49e95 | 231 | SCB_EnableDCache(); |
| phungductung | 0:e87aa4c49e95 | 232 | |
| phungductung | 0:e87aa4c49e95 | 233 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| phungductung | 0:e87aa4c49e95 | 234 | AHB/APBx prescalers and Flash settings */ |
| phungductung | 0:e87aa4c49e95 | 235 | SetSysClock(); |
| phungductung | 0:e87aa4c49e95 | 236 | |
| phungductung | 0:e87aa4c49e95 | 237 | /* Reset the timer to avoid issues after the RAM initialization */ |
| phungductung | 0:e87aa4c49e95 | 238 | TIM_MST_RESET_ON; |
| phungductung | 0:e87aa4c49e95 | 239 | TIM_MST_RESET_OFF; |
| phungductung | 0:e87aa4c49e95 | 240 | } |
| phungductung | 0:e87aa4c49e95 | 241 | |
| phungductung | 0:e87aa4c49e95 | 242 | /** |
| phungductung | 0:e87aa4c49e95 | 243 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| phungductung | 0:e87aa4c49e95 | 244 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| phungductung | 0:e87aa4c49e95 | 245 | * be used by the user application to setup the SysTick timer or configure |
| phungductung | 0:e87aa4c49e95 | 246 | * other parameters. |
| phungductung | 0:e87aa4c49e95 | 247 | * |
| phungductung | 0:e87aa4c49e95 | 248 | * @note Each time the core clock (HCLK) changes, this function must be called |
| phungductung | 0:e87aa4c49e95 | 249 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| phungductung | 0:e87aa4c49e95 | 250 | * based on this variable will be incorrect. |
| phungductung | 0:e87aa4c49e95 | 251 | * |
| phungductung | 0:e87aa4c49e95 | 252 | * @note - The system frequency computed by this function is not the real |
| phungductung | 0:e87aa4c49e95 | 253 | * frequency in the chip. It is calculated based on the predefined |
| phungductung | 0:e87aa4c49e95 | 254 | * constant and the selected clock source: |
| phungductung | 0:e87aa4c49e95 | 255 | * |
| phungductung | 0:e87aa4c49e95 | 256 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| phungductung | 0:e87aa4c49e95 | 257 | * |
| phungductung | 0:e87aa4c49e95 | 258 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| phungductung | 0:e87aa4c49e95 | 259 | * |
| phungductung | 0:e87aa4c49e95 | 260 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| phungductung | 0:e87aa4c49e95 | 261 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| phungductung | 0:e87aa4c49e95 | 262 | * |
| phungductung | 0:e87aa4c49e95 | 263 | * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value |
| phungductung | 0:e87aa4c49e95 | 264 | * 16 MHz) but the real value may vary depending on the variations |
| phungductung | 0:e87aa4c49e95 | 265 | * in voltage and temperature. |
| phungductung | 0:e87aa4c49e95 | 266 | * |
| phungductung | 0:e87aa4c49e95 | 267 | * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value |
| phungductung | 0:e87aa4c49e95 | 268 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real |
| phungductung | 0:e87aa4c49e95 | 269 | * frequency of the crystal used. Otherwise, this function may |
| phungductung | 0:e87aa4c49e95 | 270 | * have wrong result. |
| phungductung | 0:e87aa4c49e95 | 271 | * |
| phungductung | 0:e87aa4c49e95 | 272 | * - The result of this function could be not correct when using fractional |
| phungductung | 0:e87aa4c49e95 | 273 | * value for HSE crystal. |
| phungductung | 0:e87aa4c49e95 | 274 | * |
| phungductung | 0:e87aa4c49e95 | 275 | * @param None |
| phungductung | 0:e87aa4c49e95 | 276 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 277 | */ |
| phungductung | 0:e87aa4c49e95 | 278 | void SystemCoreClockUpdate(void) |
| phungductung | 0:e87aa4c49e95 | 279 | { |
| phungductung | 0:e87aa4c49e95 | 280 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| phungductung | 0:e87aa4c49e95 | 281 | |
| phungductung | 0:e87aa4c49e95 | 282 | /* Get SYSCLK source -------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 283 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| phungductung | 0:e87aa4c49e95 | 284 | |
| phungductung | 0:e87aa4c49e95 | 285 | switch (tmp) |
| phungductung | 0:e87aa4c49e95 | 286 | { |
| phungductung | 0:e87aa4c49e95 | 287 | case 0x00: /* HSI used as system clock source */ |
| phungductung | 0:e87aa4c49e95 | 288 | SystemCoreClock = HSI_VALUE; |
| phungductung | 0:e87aa4c49e95 | 289 | break; |
| phungductung | 0:e87aa4c49e95 | 290 | case 0x04: /* HSE used as system clock source */ |
| phungductung | 0:e87aa4c49e95 | 291 | SystemCoreClock = HSE_VALUE; |
| phungductung | 0:e87aa4c49e95 | 292 | break; |
| phungductung | 0:e87aa4c49e95 | 293 | case 0x08: /* PLL used as system clock source */ |
| phungductung | 0:e87aa4c49e95 | 294 | |
| phungductung | 0:e87aa4c49e95 | 295 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| phungductung | 0:e87aa4c49e95 | 296 | SYSCLK = PLL_VCO / PLL_P |
| phungductung | 0:e87aa4c49e95 | 297 | */ |
| phungductung | 0:e87aa4c49e95 | 298 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| phungductung | 0:e87aa4c49e95 | 299 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| phungductung | 0:e87aa4c49e95 | 300 | |
| phungductung | 0:e87aa4c49e95 | 301 | if (pllsource != 0) |
| phungductung | 0:e87aa4c49e95 | 302 | { |
| phungductung | 0:e87aa4c49e95 | 303 | /* HSE used as PLL clock source */ |
| phungductung | 0:e87aa4c49e95 | 304 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| phungductung | 0:e87aa4c49e95 | 305 | } |
| phungductung | 0:e87aa4c49e95 | 306 | else |
| phungductung | 0:e87aa4c49e95 | 307 | { |
| phungductung | 0:e87aa4c49e95 | 308 | /* HSI used as PLL clock source */ |
| phungductung | 0:e87aa4c49e95 | 309 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| phungductung | 0:e87aa4c49e95 | 310 | } |
| phungductung | 0:e87aa4c49e95 | 311 | |
| phungductung | 0:e87aa4c49e95 | 312 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| phungductung | 0:e87aa4c49e95 | 313 | SystemCoreClock = pllvco/pllp; |
| phungductung | 0:e87aa4c49e95 | 314 | break; |
| phungductung | 0:e87aa4c49e95 | 315 | default: |
| phungductung | 0:e87aa4c49e95 | 316 | SystemCoreClock = HSI_VALUE; |
| phungductung | 0:e87aa4c49e95 | 317 | break; |
| phungductung | 0:e87aa4c49e95 | 318 | } |
| phungductung | 0:e87aa4c49e95 | 319 | /* Compute HCLK frequency --------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 320 | /* Get HCLK prescaler */ |
| phungductung | 0:e87aa4c49e95 | 321 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| phungductung | 0:e87aa4c49e95 | 322 | /* HCLK frequency */ |
| phungductung | 0:e87aa4c49e95 | 323 | SystemCoreClock >>= tmp; |
| phungductung | 0:e87aa4c49e95 | 324 | } |
| phungductung | 0:e87aa4c49e95 | 325 | |
| phungductung | 0:e87aa4c49e95 | 326 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| phungductung | 0:e87aa4c49e95 | 327 | /** |
| phungductung | 0:e87aa4c49e95 | 328 | * @brief Setup the external memory controller. |
| phungductung | 0:e87aa4c49e95 | 329 | * Called in startup_stm32f7xx.s before jump to main. |
| phungductung | 0:e87aa4c49e95 | 330 | * This function configures the external memories (SRAM/SDRAM) |
| phungductung | 0:e87aa4c49e95 | 331 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| phungductung | 0:e87aa4c49e95 | 332 | * @param None |
| phungductung | 0:e87aa4c49e95 | 333 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 334 | */ |
| phungductung | 0:e87aa4c49e95 | 335 | void SystemInit_ExtMemCtl(void) |
| phungductung | 0:e87aa4c49e95 | 336 | { |
| phungductung | 0:e87aa4c49e95 | 337 | __IO uint32_t tmp = 0; |
| phungductung | 0:e87aa4c49e95 | 338 | #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM) |
| phungductung | 0:e87aa4c49e95 | 339 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 340 | register uint32_t index; |
| phungductung | 0:e87aa4c49e95 | 341 | |
| phungductung | 0:e87aa4c49e95 | 342 | /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| phungductung | 0:e87aa4c49e95 | 343 | clock */ |
| phungductung | 0:e87aa4c49e95 | 344 | RCC->AHB1ENR |= 0x000001F8; |
| phungductung | 0:e87aa4c49e95 | 345 | |
| phungductung | 0:e87aa4c49e95 | 346 | /* Delay after an RCC peripheral clock enabling */ |
| phungductung | 0:e87aa4c49e95 | 347 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); |
| phungductung | 0:e87aa4c49e95 | 348 | |
| phungductung | 0:e87aa4c49e95 | 349 | /* Connect PDx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 350 | GPIOD->AFR[0] = 0x00CCC0CC; |
| phungductung | 0:e87aa4c49e95 | 351 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 352 | /* Configure PDx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 353 | GPIOD->MODER = 0xAAAA0A8A; |
| phungductung | 0:e87aa4c49e95 | 354 | |
| phungductung | 0:e87aa4c49e95 | 355 | /* Configure PDx pins speed to 100 MHz */ |
| phungductung | 0:e87aa4c49e95 | 356 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| phungductung | 0:e87aa4c49e95 | 357 | /* Configure PDx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 358 | GPIOD->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 359 | /* No pull-up, pull-down for PDx pins */ |
| phungductung | 0:e87aa4c49e95 | 360 | GPIOD->PUPDR = 0x55550545; |
| phungductung | 0:e87aa4c49e95 | 361 | |
| phungductung | 0:e87aa4c49e95 | 362 | /* Connect PEx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 363 | GPIOE->AFR[0] = 0xC00CC0CC; |
| phungductung | 0:e87aa4c49e95 | 364 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 365 | /* Configure PEx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 366 | GPIOE->MODER = 0xAAAA828A; |
| phungductung | 0:e87aa4c49e95 | 367 | /* Configure PEx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 368 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| phungductung | 0:e87aa4c49e95 | 369 | /* Configure PEx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 370 | GPIOE->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 371 | /* No pull-up, pull-down for PEx pins */ |
| phungductung | 0:e87aa4c49e95 | 372 | GPIOE->PUPDR = 0x55554145; |
| phungductung | 0:e87aa4c49e95 | 373 | |
| phungductung | 0:e87aa4c49e95 | 374 | /* Connect PFx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 375 | GPIOF->AFR[0] = 0x00CCCCCC; |
| phungductung | 0:e87aa4c49e95 | 376 | GPIOF->AFR[1] = 0xCCCCC000; |
| phungductung | 0:e87aa4c49e95 | 377 | /* Configure PFx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 378 | GPIOF->MODER = 0xAA800AAA; |
| phungductung | 0:e87aa4c49e95 | 379 | /* Configure PFx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 380 | GPIOF->OSPEEDR = 0xFF800FFF; |
| phungductung | 0:e87aa4c49e95 | 381 | /* Configure PFx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 382 | GPIOF->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 383 | /* No pull-up, pull-down for PFx pins */ |
| phungductung | 0:e87aa4c49e95 | 384 | GPIOF->PUPDR = 0x55400555; |
| phungductung | 0:e87aa4c49e95 | 385 | |
| phungductung | 0:e87aa4c49e95 | 386 | /* Connect PGx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 387 | GPIOG->AFR[0] = 0x00CC00CC; |
| phungductung | 0:e87aa4c49e95 | 388 | GPIOG->AFR[1] = 0xC00000CC; |
| phungductung | 0:e87aa4c49e95 | 389 | /* Configure PGx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 390 | GPIOG->MODER = 0x80220AAA; |
| phungductung | 0:e87aa4c49e95 | 391 | /* Configure PGx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 392 | GPIOG->OSPEEDR = 0x80320FFF; |
| phungductung | 0:e87aa4c49e95 | 393 | /* Configure PGx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 394 | GPIOG->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 395 | /* No pull-up, pull-down for PGx pins */ |
| phungductung | 0:e87aa4c49e95 | 396 | GPIOG->PUPDR = 0x40110555; |
| phungductung | 0:e87aa4c49e95 | 397 | |
| phungductung | 0:e87aa4c49e95 | 398 | /* Connect PHx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 399 | GPIOH->AFR[0] = 0x00C0CC00; |
| phungductung | 0:e87aa4c49e95 | 400 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 401 | /* Configure PHx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 402 | GPIOH->MODER = 0xAAAA08A0; |
| phungductung | 0:e87aa4c49e95 | 403 | /* Configure PHx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 404 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| phungductung | 0:e87aa4c49e95 | 405 | /* Configure PHx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 406 | GPIOH->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 407 | /* No pull-up, pull-down for PHx pins */ |
| phungductung | 0:e87aa4c49e95 | 408 | GPIOH->PUPDR = 0x55550450; |
| phungductung | 0:e87aa4c49e95 | 409 | |
| phungductung | 0:e87aa4c49e95 | 410 | /* Connect PIx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 411 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 412 | GPIOI->AFR[1] = 0x00000CC0; |
| phungductung | 0:e87aa4c49e95 | 413 | /* Configure PIx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 414 | GPIOI->MODER = 0x0028AAAA; |
| phungductung | 0:e87aa4c49e95 | 415 | /* Configure PIx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 416 | GPIOI->OSPEEDR = 0x0028AAAA; |
| phungductung | 0:e87aa4c49e95 | 417 | /* Configure PIx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 418 | GPIOI->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 419 | /* No pull-up, pull-down for PIx pins */ |
| phungductung | 0:e87aa4c49e95 | 420 | GPIOI->PUPDR = 0x00145555; |
| phungductung | 0:e87aa4c49e95 | 421 | |
| phungductung | 0:e87aa4c49e95 | 422 | /*-- FMC Configuration ------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 423 | /* Enable the FMC interface clock */ |
| phungductung | 0:e87aa4c49e95 | 424 | RCC->AHB3ENR |= 0x00000001; |
| phungductung | 0:e87aa4c49e95 | 425 | |
| phungductung | 0:e87aa4c49e95 | 426 | /* Delay after an RCC peripheral clock enabling */ |
| phungductung | 0:e87aa4c49e95 | 427 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| phungductung | 0:e87aa4c49e95 | 428 | |
| phungductung | 0:e87aa4c49e95 | 429 | /* Configure and enable Bank1_SRAM2 */ |
| phungductung | 0:e87aa4c49e95 | 430 | FMC_Bank1->BTCR[4] = 0x00001091; |
| phungductung | 0:e87aa4c49e95 | 431 | FMC_Bank1->BTCR[5] = 0x00110212; |
| phungductung | 0:e87aa4c49e95 | 432 | FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; |
| phungductung | 0:e87aa4c49e95 | 433 | |
| phungductung | 0:e87aa4c49e95 | 434 | /* Configure and enable SDRAM bank1 */ |
| phungductung | 0:e87aa4c49e95 | 435 | FMC_Bank5_6->SDCR[0] = 0x000019E5; |
| phungductung | 0:e87aa4c49e95 | 436 | FMC_Bank5_6->SDTR[0] = 0x01116361; |
| phungductung | 0:e87aa4c49e95 | 437 | |
| phungductung | 0:e87aa4c49e95 | 438 | /* SDRAM initialization sequence */ |
| phungductung | 0:e87aa4c49e95 | 439 | /* Clock enable command */ |
| phungductung | 0:e87aa4c49e95 | 440 | FMC_Bank5_6->SDCMR = 0x00000011; |
| phungductung | 0:e87aa4c49e95 | 441 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 442 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 443 | { |
| phungductung | 0:e87aa4c49e95 | 444 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 445 | } |
| phungductung | 0:e87aa4c49e95 | 446 | |
| phungductung | 0:e87aa4c49e95 | 447 | /* Delay */ |
| phungductung | 0:e87aa4c49e95 | 448 | for (index = 0; index<1000; index++); |
| phungductung | 0:e87aa4c49e95 | 449 | |
| phungductung | 0:e87aa4c49e95 | 450 | /* PALL command */ |
| phungductung | 0:e87aa4c49e95 | 451 | FMC_Bank5_6->SDCMR = 0x00000012; |
| phungductung | 0:e87aa4c49e95 | 452 | timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 453 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 454 | { |
| phungductung | 0:e87aa4c49e95 | 455 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 456 | } |
| phungductung | 0:e87aa4c49e95 | 457 | |
| phungductung | 0:e87aa4c49e95 | 458 | /* Auto refresh command */ |
| phungductung | 0:e87aa4c49e95 | 459 | FMC_Bank5_6->SDCMR = 0x000000F3; |
| phungductung | 0:e87aa4c49e95 | 460 | timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 461 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 462 | { |
| phungductung | 0:e87aa4c49e95 | 463 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 464 | } |
| phungductung | 0:e87aa4c49e95 | 465 | |
| phungductung | 0:e87aa4c49e95 | 466 | /* MRD register program */ |
| phungductung | 0:e87aa4c49e95 | 467 | FMC_Bank5_6->SDCMR = 0x00046014; |
| phungductung | 0:e87aa4c49e95 | 468 | timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 469 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 470 | { |
| phungductung | 0:e87aa4c49e95 | 471 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 472 | } |
| phungductung | 0:e87aa4c49e95 | 473 | |
| phungductung | 0:e87aa4c49e95 | 474 | /* Set refresh count */ |
| phungductung | 0:e87aa4c49e95 | 475 | tmpreg = FMC_Bank5_6->SDRTR; |
| phungductung | 0:e87aa4c49e95 | 476 | FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); |
| phungductung | 0:e87aa4c49e95 | 477 | |
| phungductung | 0:e87aa4c49e95 | 478 | /* Disable write protection */ |
| phungductung | 0:e87aa4c49e95 | 479 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| phungductung | 0:e87aa4c49e95 | 480 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| phungductung | 0:e87aa4c49e95 | 481 | |
| phungductung | 0:e87aa4c49e95 | 482 | #elif defined (DATA_IN_ExtSDRAM) |
| phungductung | 0:e87aa4c49e95 | 483 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 484 | register uint32_t index; |
| phungductung | 0:e87aa4c49e95 | 485 | |
| phungductung | 0:e87aa4c49e95 | 486 | /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| phungductung | 0:e87aa4c49e95 | 487 | clock */ |
| phungductung | 0:e87aa4c49e95 | 488 | RCC->AHB1ENR |= 0x000001F8; |
| phungductung | 0:e87aa4c49e95 | 489 | |
| phungductung | 0:e87aa4c49e95 | 490 | /* Delay after an RCC peripheral clock enabling */ |
| phungductung | 0:e87aa4c49e95 | 491 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); |
| phungductung | 0:e87aa4c49e95 | 492 | |
| phungductung | 0:e87aa4c49e95 | 493 | /* Connect PDx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 494 | GPIOD->AFR[0] = 0x000000CC; |
| phungductung | 0:e87aa4c49e95 | 495 | GPIOD->AFR[1] = 0xCC000CCC; |
| phungductung | 0:e87aa4c49e95 | 496 | /* Configure PDx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 497 | GPIOD->MODER = 0xA02A000A; |
| phungductung | 0:e87aa4c49e95 | 498 | /* Configure PDx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 499 | GPIOD->OSPEEDR = 0xA02A000A; |
| phungductung | 0:e87aa4c49e95 | 500 | /* Configure PDx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 501 | GPIOD->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 502 | /* No pull-up, pull-down for PDx pins */ |
| phungductung | 0:e87aa4c49e95 | 503 | GPIOD->PUPDR = 0x50150005; |
| phungductung | 0:e87aa4c49e95 | 504 | |
| phungductung | 0:e87aa4c49e95 | 505 | /* Connect PEx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 506 | GPIOE->AFR[0] = 0xC00000CC; |
| phungductung | 0:e87aa4c49e95 | 507 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 508 | /* Configure PEx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 509 | GPIOE->MODER = 0xAAAA800A; |
| phungductung | 0:e87aa4c49e95 | 510 | /* Configure PEx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 511 | GPIOE->OSPEEDR = 0xAAAA800A; |
| phungductung | 0:e87aa4c49e95 | 512 | /* Configure PEx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 513 | GPIOE->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 514 | /* No pull-up, pull-down for PEx pins */ |
| phungductung | 0:e87aa4c49e95 | 515 | GPIOE->PUPDR = 0x55554005; |
| phungductung | 0:e87aa4c49e95 | 516 | |
| phungductung | 0:e87aa4c49e95 | 517 | /* Connect PFx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 518 | GPIOF->AFR[0] = 0x00CCCCCC; |
| phungductung | 0:e87aa4c49e95 | 519 | GPIOF->AFR[1] = 0xCCCCC000; |
| phungductung | 0:e87aa4c49e95 | 520 | /* Configure PFx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 521 | GPIOF->MODER = 0xAA800AAA; |
| phungductung | 0:e87aa4c49e95 | 522 | /* Configure PFx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 523 | GPIOF->OSPEEDR = 0xAA800AAA; |
| phungductung | 0:e87aa4c49e95 | 524 | /* Configure PFx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 525 | GPIOF->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 526 | /* No pull-up, pull-down for PFx pins */ |
| phungductung | 0:e87aa4c49e95 | 527 | GPIOF->PUPDR = 0x55400555; |
| phungductung | 0:e87aa4c49e95 | 528 | |
| phungductung | 0:e87aa4c49e95 | 529 | /* Connect PGx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 530 | GPIOG->AFR[0] = 0x00CC00CC; |
| phungductung | 0:e87aa4c49e95 | 531 | GPIOG->AFR[1] = 0xC000000C; |
| phungductung | 0:e87aa4c49e95 | 532 | /* Configure PGx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 533 | GPIOG->MODER = 0x80020A0A; |
| phungductung | 0:e87aa4c49e95 | 534 | /* Configure PGx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 535 | GPIOG->OSPEEDR = 0x80020A0A; |
| phungductung | 0:e87aa4c49e95 | 536 | /* Configure PGx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 537 | GPIOG->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 538 | /* No pull-up, pull-down for PGx pins */ |
| phungductung | 0:e87aa4c49e95 | 539 | GPIOG->PUPDR = 0x40010505; |
| phungductung | 0:e87aa4c49e95 | 540 | |
| phungductung | 0:e87aa4c49e95 | 541 | /* Connect PHx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 542 | GPIOH->AFR[0] = 0x00C0CC00; |
| phungductung | 0:e87aa4c49e95 | 543 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 544 | /* Configure PHx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 545 | GPIOH->MODER = 0xAAAA08A0; |
| phungductung | 0:e87aa4c49e95 | 546 | /* Configure PHx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 547 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| phungductung | 0:e87aa4c49e95 | 548 | /* Configure PHx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 549 | GPIOH->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 550 | /* No pull-up, pull-down for PHx pins */ |
| phungductung | 0:e87aa4c49e95 | 551 | GPIOH->PUPDR = 0x55550450; |
| phungductung | 0:e87aa4c49e95 | 552 | |
| phungductung | 0:e87aa4c49e95 | 553 | /* Connect PIx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 554 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 555 | GPIOI->AFR[1] = 0x00000CC0; |
| phungductung | 0:e87aa4c49e95 | 556 | /* Configure PIx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 557 | GPIOI->MODER = 0x0028AAAA; |
| phungductung | 0:e87aa4c49e95 | 558 | /* Configure PIx pins speed to 50 MHz */ |
| phungductung | 0:e87aa4c49e95 | 559 | GPIOI->OSPEEDR = 0x0028AAAA; |
| phungductung | 0:e87aa4c49e95 | 560 | /* Configure PIx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 561 | GPIOI->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 562 | /* No pull-up, pull-down for PIx pins */ |
| phungductung | 0:e87aa4c49e95 | 563 | GPIOI->PUPDR = 0x00145555; |
| phungductung | 0:e87aa4c49e95 | 564 | |
| phungductung | 0:e87aa4c49e95 | 565 | /*-- FMC Configuration ------------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 566 | /* Enable the FMC interface clock */ |
| phungductung | 0:e87aa4c49e95 | 567 | RCC->AHB3ENR |= 0x00000001; |
| phungductung | 0:e87aa4c49e95 | 568 | |
| phungductung | 0:e87aa4c49e95 | 569 | /* Delay after an RCC peripheral clock enabling */ |
| phungductung | 0:e87aa4c49e95 | 570 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| phungductung | 0:e87aa4c49e95 | 571 | |
| phungductung | 0:e87aa4c49e95 | 572 | /* Configure and enable SDRAM bank1 */ |
| phungductung | 0:e87aa4c49e95 | 573 | FMC_Bank5_6->SDCR[0] = 0x000019E5; |
| phungductung | 0:e87aa4c49e95 | 574 | FMC_Bank5_6->SDTR[0] = 0x01116361; |
| phungductung | 0:e87aa4c49e95 | 575 | |
| phungductung | 0:e87aa4c49e95 | 576 | /* SDRAM initialization sequence */ |
| phungductung | 0:e87aa4c49e95 | 577 | /* Clock enable command */ |
| phungductung | 0:e87aa4c49e95 | 578 | FMC_Bank5_6->SDCMR = 0x00000011; |
| phungductung | 0:e87aa4c49e95 | 579 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 580 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 581 | { |
| phungductung | 0:e87aa4c49e95 | 582 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 583 | } |
| phungductung | 0:e87aa4c49e95 | 584 | |
| phungductung | 0:e87aa4c49e95 | 585 | /* Delay */ |
| phungductung | 0:e87aa4c49e95 | 586 | for (index = 0; index<1000; index++); |
| phungductung | 0:e87aa4c49e95 | 587 | |
| phungductung | 0:e87aa4c49e95 | 588 | /* PALL command */ |
| phungductung | 0:e87aa4c49e95 | 589 | FMC_Bank5_6->SDCMR = 0x00000012; |
| phungductung | 0:e87aa4c49e95 | 590 | timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 591 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 592 | { |
| phungductung | 0:e87aa4c49e95 | 593 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 594 | } |
| phungductung | 0:e87aa4c49e95 | 595 | |
| phungductung | 0:e87aa4c49e95 | 596 | /* Auto refresh command */ |
| phungductung | 0:e87aa4c49e95 | 597 | FMC_Bank5_6->SDCMR = 0x000000F3; |
| phungductung | 0:e87aa4c49e95 | 598 | timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 599 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 600 | { |
| phungductung | 0:e87aa4c49e95 | 601 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 602 | } |
| phungductung | 0:e87aa4c49e95 | 603 | |
| phungductung | 0:e87aa4c49e95 | 604 | /* MRD register program */ |
| phungductung | 0:e87aa4c49e95 | 605 | FMC_Bank5_6->SDCMR = 0x00046014; |
| phungductung | 0:e87aa4c49e95 | 606 | timeout = 0xFFFF; |
| phungductung | 0:e87aa4c49e95 | 607 | while((tmpreg != 0) && (timeout-- > 0)) |
| phungductung | 0:e87aa4c49e95 | 608 | { |
| phungductung | 0:e87aa4c49e95 | 609 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| phungductung | 0:e87aa4c49e95 | 610 | } |
| phungductung | 0:e87aa4c49e95 | 611 | |
| phungductung | 0:e87aa4c49e95 | 612 | /* Set refresh count */ |
| phungductung | 0:e87aa4c49e95 | 613 | tmpreg = FMC_Bank5_6->SDRTR; |
| phungductung | 0:e87aa4c49e95 | 614 | FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); |
| phungductung | 0:e87aa4c49e95 | 615 | |
| phungductung | 0:e87aa4c49e95 | 616 | /* Disable write protection */ |
| phungductung | 0:e87aa4c49e95 | 617 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| phungductung | 0:e87aa4c49e95 | 618 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| phungductung | 0:e87aa4c49e95 | 619 | |
| phungductung | 0:e87aa4c49e95 | 620 | #elif defined(DATA_IN_ExtSRAM) |
| phungductung | 0:e87aa4c49e95 | 621 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 622 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| phungductung | 0:e87aa4c49e95 | 623 | RCC->AHB1ENR |= 0x00000078; |
| phungductung | 0:e87aa4c49e95 | 624 | |
| phungductung | 0:e87aa4c49e95 | 625 | /* Delay after an RCC peripheral clock enabling */ |
| phungductung | 0:e87aa4c49e95 | 626 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); |
| phungductung | 0:e87aa4c49e95 | 627 | |
| phungductung | 0:e87aa4c49e95 | 628 | /* Connect PDx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 629 | GPIOD->AFR[0] = 0x00CCC0CC; |
| phungductung | 0:e87aa4c49e95 | 630 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 631 | /* Configure PDx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 632 | GPIOD->MODER = 0xAAAA0A8A; |
| phungductung | 0:e87aa4c49e95 | 633 | /* Configure PDx pins speed to 100 MHz */ |
| phungductung | 0:e87aa4c49e95 | 634 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| phungductung | 0:e87aa4c49e95 | 635 | /* Configure PDx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 636 | GPIOD->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 637 | /* No pull-up, pull-down for PDx pins */ |
| phungductung | 0:e87aa4c49e95 | 638 | GPIOD->PUPDR = 0x55550545; |
| phungductung | 0:e87aa4c49e95 | 639 | |
| phungductung | 0:e87aa4c49e95 | 640 | /* Connect PEx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 641 | GPIOE->AFR[0] = 0xC00CC0CC; |
| phungductung | 0:e87aa4c49e95 | 642 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| phungductung | 0:e87aa4c49e95 | 643 | /* Configure PEx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 644 | GPIOE->MODER = 0xAAAA828A; |
| phungductung | 0:e87aa4c49e95 | 645 | /* Configure PEx pins speed to 100 MHz */ |
| phungductung | 0:e87aa4c49e95 | 646 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| phungductung | 0:e87aa4c49e95 | 647 | /* Configure PEx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 648 | GPIOE->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 649 | /* No pull-up, pull-down for PEx pins */ |
| phungductung | 0:e87aa4c49e95 | 650 | GPIOE->PUPDR = 0x55554145; |
| phungductung | 0:e87aa4c49e95 | 651 | |
| phungductung | 0:e87aa4c49e95 | 652 | /* Connect PFx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 653 | GPIOF->AFR[0] = 0x00CCCCCC; |
| phungductung | 0:e87aa4c49e95 | 654 | GPIOF->AFR[1] = 0xCCCC0000; |
| phungductung | 0:e87aa4c49e95 | 655 | /* Configure PFx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 656 | GPIOF->MODER = 0xAA000AAA; |
| phungductung | 0:e87aa4c49e95 | 657 | /* Configure PFx pins speed to 100 MHz */ |
| phungductung | 0:e87aa4c49e95 | 658 | GPIOF->OSPEEDR = 0xFF000FFF; |
| phungductung | 0:e87aa4c49e95 | 659 | /* Configure PFx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 660 | GPIOF->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 661 | /* No pull-up, pull-down for PFx pins */ |
| phungductung | 0:e87aa4c49e95 | 662 | GPIOF->PUPDR = 0x55000555; |
| phungductung | 0:e87aa4c49e95 | 663 | |
| phungductung | 0:e87aa4c49e95 | 664 | /* Connect PGx pins to FMC Alternate function */ |
| phungductung | 0:e87aa4c49e95 | 665 | GPIOG->AFR[0] = 0x00CCCCCC; |
| phungductung | 0:e87aa4c49e95 | 666 | GPIOG->AFR[1] = 0x000000C0; |
| phungductung | 0:e87aa4c49e95 | 667 | /* Configure PGx pins in Alternate function mode */ |
| phungductung | 0:e87aa4c49e95 | 668 | GPIOG->MODER = 0x00200AAA; |
| phungductung | 0:e87aa4c49e95 | 669 | /* Configure PGx pins speed to 100 MHz */ |
| phungductung | 0:e87aa4c49e95 | 670 | GPIOG->OSPEEDR = 0x00300FFF; |
| phungductung | 0:e87aa4c49e95 | 671 | /* Configure PGx pins Output type to push-pull */ |
| phungductung | 0:e87aa4c49e95 | 672 | GPIOG->OTYPER = 0x00000000; |
| phungductung | 0:e87aa4c49e95 | 673 | /* No pull-up, pull-down for PGx pins */ |
| phungductung | 0:e87aa4c49e95 | 674 | GPIOG->PUPDR = 0x00100555; |
| phungductung | 0:e87aa4c49e95 | 675 | |
| phungductung | 0:e87aa4c49e95 | 676 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| phungductung | 0:e87aa4c49e95 | 677 | /* Enable the FMC/FSMC interface clock */ |
| phungductung | 0:e87aa4c49e95 | 678 | RCC->AHB3ENR |= 0x00000001; |
| phungductung | 0:e87aa4c49e95 | 679 | |
| phungductung | 0:e87aa4c49e95 | 680 | /* Delay after an RCC peripheral clock enabling */ |
| phungductung | 0:e87aa4c49e95 | 681 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| phungductung | 0:e87aa4c49e95 | 682 | |
| phungductung | 0:e87aa4c49e95 | 683 | /* Configure and enable Bank1_SRAM2 */ |
| phungductung | 0:e87aa4c49e95 | 684 | FMC_Bank1->BTCR[4] = 0x00001091; |
| phungductung | 0:e87aa4c49e95 | 685 | FMC_Bank1->BTCR[5] = 0x00110212; |
| phungductung | 0:e87aa4c49e95 | 686 | FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; |
| phungductung | 0:e87aa4c49e95 | 687 | |
| phungductung | 0:e87aa4c49e95 | 688 | #endif /* DATA_IN_ExtSRAM */ |
| phungductung | 0:e87aa4c49e95 | 689 | |
| phungductung | 0:e87aa4c49e95 | 690 | (void)(tmp); |
| phungductung | 0:e87aa4c49e95 | 691 | } |
| phungductung | 0:e87aa4c49e95 | 692 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| phungductung | 0:e87aa4c49e95 | 693 | |
| phungductung | 0:e87aa4c49e95 | 694 | /** |
| phungductung | 0:e87aa4c49e95 | 695 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| phungductung | 0:e87aa4c49e95 | 696 | * AHB/APBx prescalers and Flash settings |
| phungductung | 0:e87aa4c49e95 | 697 | * @note This function should be called only once the RCC clock configuration |
| phungductung | 0:e87aa4c49e95 | 698 | * is reset to the default reset state (done in SystemInit() function). |
| phungductung | 0:e87aa4c49e95 | 699 | * @param None |
| phungductung | 0:e87aa4c49e95 | 700 | * @retval None |
| phungductung | 0:e87aa4c49e95 | 701 | */ |
| phungductung | 0:e87aa4c49e95 | 702 | void SetSysClock(void) |
| phungductung | 0:e87aa4c49e95 | 703 | { |
| phungductung | 0:e87aa4c49e95 | 704 | /* 1- Try to start with HSE and external clock */ |
| phungductung | 0:e87aa4c49e95 | 705 | #if USE_PLL_HSE_EXTC != 0 |
| phungductung | 0:e87aa4c49e95 | 706 | if (SetSysClock_PLL_HSE(1) == 0) |
| phungductung | 0:e87aa4c49e95 | 707 | #endif |
| phungductung | 0:e87aa4c49e95 | 708 | { |
| phungductung | 0:e87aa4c49e95 | 709 | /* 2- If fail try to start with HSE and external xtal */ |
| phungductung | 0:e87aa4c49e95 | 710 | #if USE_PLL_HSE_XTAL != 0 |
| phungductung | 0:e87aa4c49e95 | 711 | if (SetSysClock_PLL_HSE(0) == 0) |
| phungductung | 0:e87aa4c49e95 | 712 | #endif |
| phungductung | 0:e87aa4c49e95 | 713 | { |
| phungductung | 0:e87aa4c49e95 | 714 | /* 3- If fail start with HSI clock */ |
| phungductung | 0:e87aa4c49e95 | 715 | if (SetSysClock_PLL_HSI() == 0) |
| phungductung | 0:e87aa4c49e95 | 716 | { |
| phungductung | 0:e87aa4c49e95 | 717 | while(1) |
| phungductung | 0:e87aa4c49e95 | 718 | { |
| phungductung | 0:e87aa4c49e95 | 719 | // [TODO] Put something here to tell the user that a problem occured... |
| phungductung | 0:e87aa4c49e95 | 720 | } |
| phungductung | 0:e87aa4c49e95 | 721 | } |
| phungductung | 0:e87aa4c49e95 | 722 | } |
| phungductung | 0:e87aa4c49e95 | 723 | } |
| phungductung | 0:e87aa4c49e95 | 724 | |
| phungductung | 0:e87aa4c49e95 | 725 | // Output clock on MCO2 pin(PC9) for debugging purpose |
| phungductung | 0:e87aa4c49e95 | 726 | // Can be visualized on uSD card CN3 connector pin 8 |
| phungductung | 0:e87aa4c49e95 | 727 | //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz |
| phungductung | 0:e87aa4c49e95 | 728 | } |
| phungductung | 0:e87aa4c49e95 | 729 | |
| phungductung | 0:e87aa4c49e95 | 730 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| phungductung | 0:e87aa4c49e95 | 731 | /******************************************************************************/ |
| phungductung | 0:e87aa4c49e95 | 732 | /* PLL (clocked by HSE) used as System clock source */ |
| phungductung | 0:e87aa4c49e95 | 733 | /******************************************************************************/ |
| phungductung | 0:e87aa4c49e95 | 734 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| phungductung | 0:e87aa4c49e95 | 735 | { |
| phungductung | 0:e87aa4c49e95 | 736 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| phungductung | 0:e87aa4c49e95 | 737 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| phungductung | 0:e87aa4c49e95 | 738 | |
| phungductung | 0:e87aa4c49e95 | 739 | // Enable power clock |
| phungductung | 0:e87aa4c49e95 | 740 | __PWR_CLK_ENABLE(); |
| phungductung | 0:e87aa4c49e95 | 741 | |
| phungductung | 0:e87aa4c49e95 | 742 | // Enable HSE oscillator and activate PLL with HSE as source |
| phungductung | 0:e87aa4c49e95 | 743 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| phungductung | 0:e87aa4c49e95 | 744 | if (bypass == 0) |
| phungductung | 0:e87aa4c49e95 | 745 | { |
| phungductung | 0:e87aa4c49e95 | 746 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */ |
| phungductung | 0:e87aa4c49e95 | 747 | } |
| phungductung | 0:e87aa4c49e95 | 748 | else |
| phungductung | 0:e87aa4c49e95 | 749 | { |
| phungductung | 0:e87aa4c49e95 | 750 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */ |
| phungductung | 0:e87aa4c49e95 | 751 | } |
| phungductung | 0:e87aa4c49e95 | 752 | // Warning: this configuration is for a 25 MHz xtal clock only |
| phungductung | 0:e87aa4c49e95 | 753 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| phungductung | 0:e87aa4c49e95 | 754 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| phungductung | 0:e87aa4c49e95 | 755 | RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25) |
| phungductung | 0:e87aa4c49e95 | 756 | RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432) |
| phungductung | 0:e87aa4c49e95 | 757 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) |
| phungductung | 0:e87aa4c49e95 | 758 | RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB |
| phungductung | 0:e87aa4c49e95 | 759 | |
| phungductung | 0:e87aa4c49e95 | 760 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| phungductung | 0:e87aa4c49e95 | 761 | { |
| phungductung | 0:e87aa4c49e95 | 762 | return 0; // FAIL |
| phungductung | 0:e87aa4c49e95 | 763 | } |
| phungductung | 0:e87aa4c49e95 | 764 | |
| phungductung | 0:e87aa4c49e95 | 765 | // Activate the OverDrive to reach the 216 MHz Frequency |
| phungductung | 0:e87aa4c49e95 | 766 | if (HAL_PWREx_EnableOverDrive() != HAL_OK) |
| phungductung | 0:e87aa4c49e95 | 767 | { |
| phungductung | 0:e87aa4c49e95 | 768 | return 0; // FAIL |
| phungductung | 0:e87aa4c49e95 | 769 | } |
| phungductung | 0:e87aa4c49e95 | 770 | |
| phungductung | 0:e87aa4c49e95 | 771 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
| phungductung | 0:e87aa4c49e95 | 772 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| phungductung | 0:e87aa4c49e95 | 773 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz |
| phungductung | 0:e87aa4c49e95 | 774 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz |
| phungductung | 0:e87aa4c49e95 | 775 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz |
| phungductung | 0:e87aa4c49e95 | 776 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz |
| phungductung | 0:e87aa4c49e95 | 777 | |
| phungductung | 0:e87aa4c49e95 | 778 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) |
| phungductung | 0:e87aa4c49e95 | 779 | { |
| phungductung | 0:e87aa4c49e95 | 780 | return 0; // FAIL |
| phungductung | 0:e87aa4c49e95 | 781 | } |
| phungductung | 0:e87aa4c49e95 | 782 | |
| phungductung | 0:e87aa4c49e95 | 783 | return 1; // OK |
| phungductung | 0:e87aa4c49e95 | 784 | } |
| phungductung | 0:e87aa4c49e95 | 785 | #endif |
| phungductung | 0:e87aa4c49e95 | 786 | |
| phungductung | 0:e87aa4c49e95 | 787 | /******************************************************************************/ |
| phungductung | 0:e87aa4c49e95 | 788 | /* PLL (clocked by HSI) used as System clock source */ |
| phungductung | 0:e87aa4c49e95 | 789 | /******************************************************************************/ |
| phungductung | 0:e87aa4c49e95 | 790 | uint8_t SetSysClock_PLL_HSI(void) |
| phungductung | 0:e87aa4c49e95 | 791 | { |
| phungductung | 0:e87aa4c49e95 | 792 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| phungductung | 0:e87aa4c49e95 | 793 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| phungductung | 0:e87aa4c49e95 | 794 | |
| phungductung | 0:e87aa4c49e95 | 795 | // Enable CPU L1-Cache |
| phungductung | 0:e87aa4c49e95 | 796 | SCB_EnableICache(); |
| phungductung | 0:e87aa4c49e95 | 797 | SCB_EnableDCache(); |
| phungductung | 0:e87aa4c49e95 | 798 | |
| phungductung | 0:e87aa4c49e95 | 799 | // Enable power clock |
| phungductung | 0:e87aa4c49e95 | 800 | __PWR_CLK_ENABLE(); |
| phungductung | 0:e87aa4c49e95 | 801 | |
| phungductung | 0:e87aa4c49e95 | 802 | // Enable HSI oscillator and activate PLL with HSI as source |
| phungductung | 0:e87aa4c49e95 | 803 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| phungductung | 0:e87aa4c49e95 | 804 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| phungductung | 0:e87aa4c49e95 | 805 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| phungductung | 0:e87aa4c49e95 | 806 | RCC_OscInitStruct.HSICalibrationValue = 16; |
| phungductung | 0:e87aa4c49e95 | 807 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| phungductung | 0:e87aa4c49e95 | 808 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
| phungductung | 0:e87aa4c49e95 | 809 | RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) |
| phungductung | 0:e87aa4c49e95 | 810 | RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432) |
| phungductung | 0:e87aa4c49e95 | 811 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) |
| phungductung | 0:e87aa4c49e95 | 812 | RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB |
| phungductung | 0:e87aa4c49e95 | 813 | |
| phungductung | 0:e87aa4c49e95 | 814 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| phungductung | 0:e87aa4c49e95 | 815 | { |
| phungductung | 0:e87aa4c49e95 | 816 | return 0; // FAIL |
| phungductung | 0:e87aa4c49e95 | 817 | } |
| phungductung | 0:e87aa4c49e95 | 818 | |
| phungductung | 0:e87aa4c49e95 | 819 | // Activate the OverDrive to reach the 216 MHz Frequency |
| phungductung | 0:e87aa4c49e95 | 820 | if (HAL_PWREx_EnableOverDrive() != HAL_OK) |
| phungductung | 0:e87aa4c49e95 | 821 | { |
| phungductung | 0:e87aa4c49e95 | 822 | return 0; // FAIL |
| phungductung | 0:e87aa4c49e95 | 823 | } |
| phungductung | 0:e87aa4c49e95 | 824 | |
| phungductung | 0:e87aa4c49e95 | 825 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
| phungductung | 0:e87aa4c49e95 | 826 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| phungductung | 0:e87aa4c49e95 | 827 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz |
| phungductung | 0:e87aa4c49e95 | 828 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz |
| phungductung | 0:e87aa4c49e95 | 829 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz |
| phungductung | 0:e87aa4c49e95 | 830 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz |
| phungductung | 0:e87aa4c49e95 | 831 | |
| phungductung | 0:e87aa4c49e95 | 832 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) |
| phungductung | 0:e87aa4c49e95 | 833 | { |
| phungductung | 0:e87aa4c49e95 | 834 | return 0; // FAIL |
| phungductung | 0:e87aa4c49e95 | 835 | } |
| phungductung | 0:e87aa4c49e95 | 836 | |
| phungductung | 0:e87aa4c49e95 | 837 | return 1; // OK |
| phungductung | 0:e87aa4c49e95 | 838 | } |
| phungductung | 0:e87aa4c49e95 | 839 | |
| phungductung | 0:e87aa4c49e95 | 840 | /** |
| phungductung | 0:e87aa4c49e95 | 841 | * @} |
| phungductung | 0:e87aa4c49e95 | 842 | */ |
| phungductung | 0:e87aa4c49e95 | 843 | |
| phungductung | 0:e87aa4c49e95 | 844 | /** |
| phungductung | 0:e87aa4c49e95 | 845 | * @} |
| phungductung | 0:e87aa4c49e95 | 846 | */ |
| phungductung | 0:e87aa4c49e95 | 847 | |
| phungductung | 0:e87aa4c49e95 | 848 | /** |
| phungductung | 0:e87aa4c49e95 | 849 | * @} |
| phungductung | 0:e87aa4c49e95 | 850 | */ |
| phungductung | 0:e87aa4c49e95 | 851 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |