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BSP_DISCO_F746NG/stm32746g_discovery_sdram.c@0:4e245f4bc8ac, 2019-06-07 (annotated)

Committer:
phungductung
Date:
Fri Jun 07 05:06:42 2019 +0000
Revision:
0:4e245f4bc8ac
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phungductung 0:4e245f4bc8ac 1 /**
phungductung 0:4e245f4bc8ac 2 ******************************************************************************
phungductung 0:4e245f4bc8ac 3 * @file stm32746g_discovery_sdram.c
phungductung 0:4e245f4bc8ac 4 * @author MCD Application Team
phungductung 0:4e245f4bc8ac 5 * @version V1.0.0
phungductung 0:4e245f4bc8ac 6 * @date 25-June-2015
phungductung 0:4e245f4bc8ac 7 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
phungductung 0:4e245f4bc8ac 8 * device mounted on STM32746G-Discovery board.
phungductung 0:4e245f4bc8ac 9 @verbatim
phungductung 0:4e245f4bc8ac 10 1. How To use this driver:
phungductung 0:4e245f4bc8ac 11 --------------------------
phungductung 0:4e245f4bc8ac 12 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
phungductung 0:4e245f4bc8ac 13 on STM32746G-Discovery board.
phungductung 0:4e245f4bc8ac 14 - This driver does not need a specific component driver for the SDRAM device
phungductung 0:4e245f4bc8ac 15 to be included with.
phungductung 0:4e245f4bc8ac 16
phungductung 0:4e245f4bc8ac 17 2. Driver description:
phungductung 0:4e245f4bc8ac 18 ---------------------
phungductung 0:4e245f4bc8ac 19 + Initialization steps:
phungductung 0:4e245f4bc8ac 20 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
phungductung 0:4e245f4bc8ac 21 function includes the MSP layer hardware resources initialization and the
phungductung 0:4e245f4bc8ac 22 FMC controller configuration to interface with the external SDRAM memory.
phungductung 0:4e245f4bc8ac 23 o It contains the SDRAM initialization sequence to program the SDRAM external
phungductung 0:4e245f4bc8ac 24 device using the function BSP_SDRAM_Initialization_sequence(). Note that this
phungductung 0:4e245f4bc8ac 25 sequence is standard for all SDRAM devices, but can include some differences
phungductung 0:4e245f4bc8ac 26 from a device to another. If it is the case, the right sequence should be
phungductung 0:4e245f4bc8ac 27 implemented separately.
phungductung 0:4e245f4bc8ac 28
phungductung 0:4e245f4bc8ac 29 + SDRAM read/write operations
phungductung 0:4e245f4bc8ac 30 o SDRAM external memory can be accessed with read/write operations once it is
phungductung 0:4e245f4bc8ac 31 initialized.
phungductung 0:4e245f4bc8ac 32 Read/write operation can be performed with AHB access using the functions
phungductung 0:4e245f4bc8ac 33 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
phungductung 0:4e245f4bc8ac 34 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
phungductung 0:4e245f4bc8ac 35 o The AHB access is performed with 32-bit width transaction, the DMA transfer
phungductung 0:4e245f4bc8ac 36 configuration is fixed at single (no burst) word transfer (see the
phungductung 0:4e245f4bc8ac 37 SDRAM_MspInit() static function).
phungductung 0:4e245f4bc8ac 38 o User can implement his own functions for read/write access with his desired
phungductung 0:4e245f4bc8ac 39 configurations.
phungductung 0:4e245f4bc8ac 40 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
phungductung 0:4e245f4bc8ac 41 is called in IRQ handler file, to serve the generated interrupt once the DMA
phungductung 0:4e245f4bc8ac 42 transfer is complete.
phungductung 0:4e245f4bc8ac 43 o You can send a command to the SDRAM device in runtime using the function
phungductung 0:4e245f4bc8ac 44 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
phungductung 0:4e245f4bc8ac 45 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
phungductung 0:4e245f4bc8ac 46
phungductung 0:4e245f4bc8ac 47 @endverbatim
phungductung 0:4e245f4bc8ac 48 ******************************************************************************
phungductung 0:4e245f4bc8ac 49 * @attention
phungductung 0:4e245f4bc8ac 50 *
phungductung 0:4e245f4bc8ac 51 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:4e245f4bc8ac 52 *
phungductung 0:4e245f4bc8ac 53 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:4e245f4bc8ac 54 * are permitted provided that the following conditions are met:
phungductung 0:4e245f4bc8ac 55 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:4e245f4bc8ac 56 * this list of conditions and the following disclaimer.
phungductung 0:4e245f4bc8ac 57 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:4e245f4bc8ac 58 * this list of conditions and the following disclaimer in the documentation
phungductung 0:4e245f4bc8ac 59 * and/or other materials provided with the distribution.
phungductung 0:4e245f4bc8ac 60 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:4e245f4bc8ac 61 * may be used to endorse or promote products derived from this software
phungductung 0:4e245f4bc8ac 62 * without specific prior written permission.
phungductung 0:4e245f4bc8ac 63 *
phungductung 0:4e245f4bc8ac 64 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:4e245f4bc8ac 65 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:4e245f4bc8ac 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:4e245f4bc8ac 67 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:4e245f4bc8ac 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:4e245f4bc8ac 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:4e245f4bc8ac 70 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:4e245f4bc8ac 71 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:4e245f4bc8ac 72 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:4e245f4bc8ac 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:4e245f4bc8ac 74 *
phungductung 0:4e245f4bc8ac 75 ******************************************************************************
phungductung 0:4e245f4bc8ac 76 */
phungductung 0:4e245f4bc8ac 77
phungductung 0:4e245f4bc8ac 78 /* Includes ------------------------------------------------------------------*/
phungductung 0:4e245f4bc8ac 79 #include "stm32746g_discovery_sdram.h"
phungductung 0:4e245f4bc8ac 80
phungductung 0:4e245f4bc8ac 81 void wait_ms(int ms); // MBED to replace HAL_Delay function
phungductung 0:4e245f4bc8ac 82
phungductung 0:4e245f4bc8ac 83 /** @addtogroup BSP
phungductung 0:4e245f4bc8ac 84 * @{
phungductung 0:4e245f4bc8ac 85 */
phungductung 0:4e245f4bc8ac 86
phungductung 0:4e245f4bc8ac 87 /** @addtogroup STM32746G_DISCOVERY
phungductung 0:4e245f4bc8ac 88 * @{
phungductung 0:4e245f4bc8ac 89 */
phungductung 0:4e245f4bc8ac 90
phungductung 0:4e245f4bc8ac 91 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
phungductung 0:4e245f4bc8ac 92 * @{
phungductung 0:4e245f4bc8ac 93 */
phungductung 0:4e245f4bc8ac 94
phungductung 0:4e245f4bc8ac 95 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
phungductung 0:4e245f4bc8ac 96 * @{
phungductung 0:4e245f4bc8ac 97 */
phungductung 0:4e245f4bc8ac 98 /**
phungductung 0:4e245f4bc8ac 99 * @}
phungductung 0:4e245f4bc8ac 100 */
phungductung 0:4e245f4bc8ac 101
phungductung 0:4e245f4bc8ac 102 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
phungductung 0:4e245f4bc8ac 103 * @{
phungductung 0:4e245f4bc8ac 104 */
phungductung 0:4e245f4bc8ac 105 /**
phungductung 0:4e245f4bc8ac 106 * @}
phungductung 0:4e245f4bc8ac 107 */
phungductung 0:4e245f4bc8ac 108
phungductung 0:4e245f4bc8ac 109 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
phungductung 0:4e245f4bc8ac 110 * @{
phungductung 0:4e245f4bc8ac 111 */
phungductung 0:4e245f4bc8ac 112 /**
phungductung 0:4e245f4bc8ac 113 * @}
phungductung 0:4e245f4bc8ac 114 */
phungductung 0:4e245f4bc8ac 115
phungductung 0:4e245f4bc8ac 116 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
phungductung 0:4e245f4bc8ac 117 * @{
phungductung 0:4e245f4bc8ac 118 */
phungductung 0:4e245f4bc8ac 119 static SDRAM_HandleTypeDef sdramHandle;
phungductung 0:4e245f4bc8ac 120 static FMC_SDRAM_TimingTypeDef Timing;
phungductung 0:4e245f4bc8ac 121 static FMC_SDRAM_CommandTypeDef Command;
phungductung 0:4e245f4bc8ac 122 /**
phungductung 0:4e245f4bc8ac 123 * @}
phungductung 0:4e245f4bc8ac 124 */
phungductung 0:4e245f4bc8ac 125
phungductung 0:4e245f4bc8ac 126 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
phungductung 0:4e245f4bc8ac 127 * @{
phungductung 0:4e245f4bc8ac 128 */
phungductung 0:4e245f4bc8ac 129 /**
phungductung 0:4e245f4bc8ac 130 * @}
phungductung 0:4e245f4bc8ac 131 */
phungductung 0:4e245f4bc8ac 132
phungductung 0:4e245f4bc8ac 133 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
phungductung 0:4e245f4bc8ac 134 * @{
phungductung 0:4e245f4bc8ac 135 */
phungductung 0:4e245f4bc8ac 136
phungductung 0:4e245f4bc8ac 137 /**
phungductung 0:4e245f4bc8ac 138 * @brief Initializes the SDRAM device.
phungductung 0:4e245f4bc8ac 139 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 140 */
phungductung 0:4e245f4bc8ac 141 uint8_t BSP_SDRAM_Init(void)
phungductung 0:4e245f4bc8ac 142 {
phungductung 0:4e245f4bc8ac 143 static uint8_t sdramstatus = SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 144 /* SDRAM device configuration */
phungductung 0:4e245f4bc8ac 145 sdramHandle.Instance = FMC_SDRAM_DEVICE;
phungductung 0:4e245f4bc8ac 146
phungductung 0:4e245f4bc8ac 147 /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
phungductung 0:4e245f4bc8ac 148 Timing.LoadToActiveDelay = 2;
phungductung 0:4e245f4bc8ac 149 Timing.ExitSelfRefreshDelay = 7;
phungductung 0:4e245f4bc8ac 150 Timing.SelfRefreshTime = 4;
phungductung 0:4e245f4bc8ac 151 Timing.RowCycleDelay = 7;
phungductung 0:4e245f4bc8ac 152 Timing.WriteRecoveryTime = 2;
phungductung 0:4e245f4bc8ac 153 Timing.RPDelay = 2;
phungductung 0:4e245f4bc8ac 154 Timing.RCDDelay = 2;
phungductung 0:4e245f4bc8ac 155
phungductung 0:4e245f4bc8ac 156 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
phungductung 0:4e245f4bc8ac 157 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
phungductung 0:4e245f4bc8ac 158 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
phungductung 0:4e245f4bc8ac 159 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
phungductung 0:4e245f4bc8ac 160 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
phungductung 0:4e245f4bc8ac 161 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
phungductung 0:4e245f4bc8ac 162 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
phungductung 0:4e245f4bc8ac 163 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
phungductung 0:4e245f4bc8ac 164 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
phungductung 0:4e245f4bc8ac 165 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
phungductung 0:4e245f4bc8ac 166
phungductung 0:4e245f4bc8ac 167 /* SDRAM controller initialization */
phungductung 0:4e245f4bc8ac 168
phungductung 0:4e245f4bc8ac 169 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
phungductung 0:4e245f4bc8ac 170
phungductung 0:4e245f4bc8ac 171 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
phungductung 0:4e245f4bc8ac 172 {
phungductung 0:4e245f4bc8ac 173 sdramstatus = SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 174 }
phungductung 0:4e245f4bc8ac 175 else
phungductung 0:4e245f4bc8ac 176 {
phungductung 0:4e245f4bc8ac 177 sdramstatus = SDRAM_OK;
phungductung 0:4e245f4bc8ac 178 }
phungductung 0:4e245f4bc8ac 179
phungductung 0:4e245f4bc8ac 180 /* SDRAM initialization sequence */
phungductung 0:4e245f4bc8ac 181 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
phungductung 0:4e245f4bc8ac 182
phungductung 0:4e245f4bc8ac 183 return sdramstatus;
phungductung 0:4e245f4bc8ac 184 }
phungductung 0:4e245f4bc8ac 185
phungductung 0:4e245f4bc8ac 186 /**
phungductung 0:4e245f4bc8ac 187 * @brief DeInitializes the SDRAM device.
phungductung 0:4e245f4bc8ac 188 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 189 */
phungductung 0:4e245f4bc8ac 190 uint8_t BSP_SDRAM_DeInit(void)
phungductung 0:4e245f4bc8ac 191 {
phungductung 0:4e245f4bc8ac 192 static uint8_t sdramstatus = SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 193 /* SDRAM device de-initialization */
phungductung 0:4e245f4bc8ac 194 sdramHandle.Instance = FMC_SDRAM_DEVICE;
phungductung 0:4e245f4bc8ac 195
phungductung 0:4e245f4bc8ac 196 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
phungductung 0:4e245f4bc8ac 197 {
phungductung 0:4e245f4bc8ac 198 sdramstatus = SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 199 }
phungductung 0:4e245f4bc8ac 200 else
phungductung 0:4e245f4bc8ac 201 {
phungductung 0:4e245f4bc8ac 202 sdramstatus = SDRAM_OK;
phungductung 0:4e245f4bc8ac 203 }
phungductung 0:4e245f4bc8ac 204
phungductung 0:4e245f4bc8ac 205 /* SDRAM controller de-initialization */
phungductung 0:4e245f4bc8ac 206 BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
phungductung 0:4e245f4bc8ac 207
phungductung 0:4e245f4bc8ac 208 return sdramstatus;
phungductung 0:4e245f4bc8ac 209 }
phungductung 0:4e245f4bc8ac 210
phungductung 0:4e245f4bc8ac 211 /**
phungductung 0:4e245f4bc8ac 212 * @brief Programs the SDRAM device.
phungductung 0:4e245f4bc8ac 213 * @param RefreshCount: SDRAM refresh counter value
phungductung 0:4e245f4bc8ac 214 * @retval None
phungductung 0:4e245f4bc8ac 215 */
phungductung 0:4e245f4bc8ac 216 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
phungductung 0:4e245f4bc8ac 217 {
phungductung 0:4e245f4bc8ac 218 __IO uint32_t tmpmrd = 0;
phungductung 0:4e245f4bc8ac 219
phungductung 0:4e245f4bc8ac 220 /* Step 1: Configure a clock configuration enable command */
phungductung 0:4e245f4bc8ac 221 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
phungductung 0:4e245f4bc8ac 222 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
phungductung 0:4e245f4bc8ac 223 Command.AutoRefreshNumber = 1;
phungductung 0:4e245f4bc8ac 224 Command.ModeRegisterDefinition = 0;
phungductung 0:4e245f4bc8ac 225
phungductung 0:4e245f4bc8ac 226 /* Send the command */
phungductung 0:4e245f4bc8ac 227 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
phungductung 0:4e245f4bc8ac 228
phungductung 0:4e245f4bc8ac 229 /* Step 2: Insert 100 us minimum delay */
phungductung 0:4e245f4bc8ac 230 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
phungductung 0:4e245f4bc8ac 231 //HAL_Delay(1); // MBED
phungductung 0:4e245f4bc8ac 232 wait_ms(1); // MBED
phungductung 0:4e245f4bc8ac 233
phungductung 0:4e245f4bc8ac 234 /* Step 3: Configure a PALL (precharge all) command */
phungductung 0:4e245f4bc8ac 235 Command.CommandMode = FMC_SDRAM_CMD_PALL;
phungductung 0:4e245f4bc8ac 236 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
phungductung 0:4e245f4bc8ac 237 Command.AutoRefreshNumber = 1;
phungductung 0:4e245f4bc8ac 238 Command.ModeRegisterDefinition = 0;
phungductung 0:4e245f4bc8ac 239
phungductung 0:4e245f4bc8ac 240 /* Send the command */
phungductung 0:4e245f4bc8ac 241 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
phungductung 0:4e245f4bc8ac 242
phungductung 0:4e245f4bc8ac 243 /* Step 4: Configure an Auto Refresh command */
phungductung 0:4e245f4bc8ac 244 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
phungductung 0:4e245f4bc8ac 245 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
phungductung 0:4e245f4bc8ac 246 Command.AutoRefreshNumber = 8;
phungductung 0:4e245f4bc8ac 247 Command.ModeRegisterDefinition = 0;
phungductung 0:4e245f4bc8ac 248
phungductung 0:4e245f4bc8ac 249 /* Send the command */
phungductung 0:4e245f4bc8ac 250 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
phungductung 0:4e245f4bc8ac 251
phungductung 0:4e245f4bc8ac 252 /* Step 5: Program the external memory mode register */
phungductung 0:4e245f4bc8ac 253 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
phungductung 0:4e245f4bc8ac 254 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
phungductung 0:4e245f4bc8ac 255 SDRAM_MODEREG_CAS_LATENCY_2 |\
phungductung 0:4e245f4bc8ac 256 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
phungductung 0:4e245f4bc8ac 257 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
phungductung 0:4e245f4bc8ac 258
phungductung 0:4e245f4bc8ac 259 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
phungductung 0:4e245f4bc8ac 260 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
phungductung 0:4e245f4bc8ac 261 Command.AutoRefreshNumber = 1;
phungductung 0:4e245f4bc8ac 262 Command.ModeRegisterDefinition = tmpmrd;
phungductung 0:4e245f4bc8ac 263
phungductung 0:4e245f4bc8ac 264 /* Send the command */
phungductung 0:4e245f4bc8ac 265 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
phungductung 0:4e245f4bc8ac 266
phungductung 0:4e245f4bc8ac 267 /* Step 6: Set the refresh rate counter */
phungductung 0:4e245f4bc8ac 268 /* Set the device refresh rate */
phungductung 0:4e245f4bc8ac 269 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
phungductung 0:4e245f4bc8ac 270 }
phungductung 0:4e245f4bc8ac 271
phungductung 0:4e245f4bc8ac 272 /**
phungductung 0:4e245f4bc8ac 273 * @brief Reads an amount of data from the SDRAM memory in polling mode.
phungductung 0:4e245f4bc8ac 274 * @param uwStartAddress: Read start address
phungductung 0:4e245f4bc8ac 275 * @param pData: Pointer to data to be read
phungductung 0:4e245f4bc8ac 276 * @param uwDataSize: Size of read data from the memory
phungductung 0:4e245f4bc8ac 277 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 278 */
phungductung 0:4e245f4bc8ac 279 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
phungductung 0:4e245f4bc8ac 280 {
phungductung 0:4e245f4bc8ac 281 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
phungductung 0:4e245f4bc8ac 282 {
phungductung 0:4e245f4bc8ac 283 return SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 284 }
phungductung 0:4e245f4bc8ac 285 else
phungductung 0:4e245f4bc8ac 286 {
phungductung 0:4e245f4bc8ac 287 return SDRAM_OK;
phungductung 0:4e245f4bc8ac 288 }
phungductung 0:4e245f4bc8ac 289 }
phungductung 0:4e245f4bc8ac 290
phungductung 0:4e245f4bc8ac 291 /**
phungductung 0:4e245f4bc8ac 292 * @brief Reads an amount of data from the SDRAM memory in DMA mode.
phungductung 0:4e245f4bc8ac 293 * @param uwStartAddress: Read start address
phungductung 0:4e245f4bc8ac 294 * @param pData: Pointer to data to be read
phungductung 0:4e245f4bc8ac 295 * @param uwDataSize: Size of read data from the memory
phungductung 0:4e245f4bc8ac 296 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 297 */
phungductung 0:4e245f4bc8ac 298 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
phungductung 0:4e245f4bc8ac 299 {
phungductung 0:4e245f4bc8ac 300 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
phungductung 0:4e245f4bc8ac 301 {
phungductung 0:4e245f4bc8ac 302 return SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 303 }
phungductung 0:4e245f4bc8ac 304 else
phungductung 0:4e245f4bc8ac 305 {
phungductung 0:4e245f4bc8ac 306 return SDRAM_OK;
phungductung 0:4e245f4bc8ac 307 }
phungductung 0:4e245f4bc8ac 308 }
phungductung 0:4e245f4bc8ac 309
phungductung 0:4e245f4bc8ac 310 /**
phungductung 0:4e245f4bc8ac 311 * @brief Writes an amount of data to the SDRAM memory in polling mode.
phungductung 0:4e245f4bc8ac 312 * @param uwStartAddress: Write start address
phungductung 0:4e245f4bc8ac 313 * @param pData: Pointer to data to be written
phungductung 0:4e245f4bc8ac 314 * @param uwDataSize: Size of written data from the memory
phungductung 0:4e245f4bc8ac 315 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 316 */
phungductung 0:4e245f4bc8ac 317 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
phungductung 0:4e245f4bc8ac 318 {
phungductung 0:4e245f4bc8ac 319 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
phungductung 0:4e245f4bc8ac 320 {
phungductung 0:4e245f4bc8ac 321 return SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 322 }
phungductung 0:4e245f4bc8ac 323 else
phungductung 0:4e245f4bc8ac 324 {
phungductung 0:4e245f4bc8ac 325 return SDRAM_OK;
phungductung 0:4e245f4bc8ac 326 }
phungductung 0:4e245f4bc8ac 327 }
phungductung 0:4e245f4bc8ac 328
phungductung 0:4e245f4bc8ac 329 /**
phungductung 0:4e245f4bc8ac 330 * @brief Writes an amount of data to the SDRAM memory in DMA mode.
phungductung 0:4e245f4bc8ac 331 * @param uwStartAddress: Write start address
phungductung 0:4e245f4bc8ac 332 * @param pData: Pointer to data to be written
phungductung 0:4e245f4bc8ac 333 * @param uwDataSize: Size of written data from the memory
phungductung 0:4e245f4bc8ac 334 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 335 */
phungductung 0:4e245f4bc8ac 336 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
phungductung 0:4e245f4bc8ac 337 {
phungductung 0:4e245f4bc8ac 338 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
phungductung 0:4e245f4bc8ac 339 {
phungductung 0:4e245f4bc8ac 340 return SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 341 }
phungductung 0:4e245f4bc8ac 342 else
phungductung 0:4e245f4bc8ac 343 {
phungductung 0:4e245f4bc8ac 344 return SDRAM_OK;
phungductung 0:4e245f4bc8ac 345 }
phungductung 0:4e245f4bc8ac 346 }
phungductung 0:4e245f4bc8ac 347
phungductung 0:4e245f4bc8ac 348 /**
phungductung 0:4e245f4bc8ac 349 * @brief Sends command to the SDRAM bank.
phungductung 0:4e245f4bc8ac 350 * @param SdramCmd: Pointer to SDRAM command structure
phungductung 0:4e245f4bc8ac 351 * @retval SDRAM status
phungductung 0:4e245f4bc8ac 352 */
phungductung 0:4e245f4bc8ac 353 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
phungductung 0:4e245f4bc8ac 354 {
phungductung 0:4e245f4bc8ac 355 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
phungductung 0:4e245f4bc8ac 356 {
phungductung 0:4e245f4bc8ac 357 return SDRAM_ERROR;
phungductung 0:4e245f4bc8ac 358 }
phungductung 0:4e245f4bc8ac 359 else
phungductung 0:4e245f4bc8ac 360 {
phungductung 0:4e245f4bc8ac 361 return SDRAM_OK;
phungductung 0:4e245f4bc8ac 362 }
phungductung 0:4e245f4bc8ac 363 }
phungductung 0:4e245f4bc8ac 364
phungductung 0:4e245f4bc8ac 365 /**
phungductung 0:4e245f4bc8ac 366 * @brief Handles SDRAM DMA transfer interrupt request.
phungductung 0:4e245f4bc8ac 367 * @retval None
phungductung 0:4e245f4bc8ac 368 */
phungductung 0:4e245f4bc8ac 369 void BSP_SDRAM_DMA_IRQHandler(void)
phungductung 0:4e245f4bc8ac 370 {
phungductung 0:4e245f4bc8ac 371 HAL_DMA_IRQHandler(sdramHandle.hdma);
phungductung 0:4e245f4bc8ac 372 }
phungductung 0:4e245f4bc8ac 373
phungductung 0:4e245f4bc8ac 374 /**
phungductung 0:4e245f4bc8ac 375 * @brief Initializes SDRAM MSP.
phungductung 0:4e245f4bc8ac 376 * @param hsdram: SDRAM handle
phungductung 0:4e245f4bc8ac 377 * @param Params
phungductung 0:4e245f4bc8ac 378 * @retval None
phungductung 0:4e245f4bc8ac 379 */
phungductung 0:4e245f4bc8ac 380 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
phungductung 0:4e245f4bc8ac 381 {
phungductung 0:4e245f4bc8ac 382 static DMA_HandleTypeDef dma_handle;
phungductung 0:4e245f4bc8ac 383 GPIO_InitTypeDef gpio_init_structure;
phungductung 0:4e245f4bc8ac 384
phungductung 0:4e245f4bc8ac 385 /* Enable FMC clock */
phungductung 0:4e245f4bc8ac 386 __HAL_RCC_FMC_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 387
phungductung 0:4e245f4bc8ac 388 /* Enable chosen DMAx clock */
phungductung 0:4e245f4bc8ac 389 __DMAx_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 390
phungductung 0:4e245f4bc8ac 391 /* Enable GPIOs clock */
phungductung 0:4e245f4bc8ac 392 __HAL_RCC_GPIOC_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 393 __HAL_RCC_GPIOD_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 394 __HAL_RCC_GPIOE_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 395 __HAL_RCC_GPIOF_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 396 __HAL_RCC_GPIOG_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 397 __HAL_RCC_GPIOH_CLK_ENABLE();
phungductung 0:4e245f4bc8ac 398
phungductung 0:4e245f4bc8ac 399 /* Common GPIO configuration */
phungductung 0:4e245f4bc8ac 400 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
phungductung 0:4e245f4bc8ac 401 gpio_init_structure.Pull = GPIO_PULLUP;
phungductung 0:4e245f4bc8ac 402 gpio_init_structure.Speed = GPIO_SPEED_FAST;
phungductung 0:4e245f4bc8ac 403 gpio_init_structure.Alternate = GPIO_AF12_FMC;
phungductung 0:4e245f4bc8ac 404
phungductung 0:4e245f4bc8ac 405 /* GPIOC configuration */
phungductung 0:4e245f4bc8ac 406 gpio_init_structure.Pin = GPIO_PIN_3;
phungductung 0:4e245f4bc8ac 407 HAL_GPIO_Init(GPIOC, &gpio_init_structure);
phungductung 0:4e245f4bc8ac 408
phungductung 0:4e245f4bc8ac 409 /* GPIOD configuration */
phungductung 0:4e245f4bc8ac 410 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |
phungductung 0:4e245f4bc8ac 411 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
phungductung 0:4e245f4bc8ac 412 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
phungductung 0:4e245f4bc8ac 413
phungductung 0:4e245f4bc8ac 414 /* GPIOE configuration */
phungductung 0:4e245f4bc8ac 415 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
phungductung 0:4e245f4bc8ac 416 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
phungductung 0:4e245f4bc8ac 417 GPIO_PIN_15;
phungductung 0:4e245f4bc8ac 418 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
phungductung 0:4e245f4bc8ac 419
phungductung 0:4e245f4bc8ac 420 /* GPIOF configuration */
phungductung 0:4e245f4bc8ac 421 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
phungductung 0:4e245f4bc8ac 422 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
phungductung 0:4e245f4bc8ac 423 GPIO_PIN_15;
phungductung 0:4e245f4bc8ac 424 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
phungductung 0:4e245f4bc8ac 425
phungductung 0:4e245f4bc8ac 426 /* GPIOG configuration */
phungductung 0:4e245f4bc8ac 427 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
phungductung 0:4e245f4bc8ac 428 GPIO_PIN_15;
phungductung 0:4e245f4bc8ac 429 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
phungductung 0:4e245f4bc8ac 430
phungductung 0:4e245f4bc8ac 431 /* GPIOH configuration */
phungductung 0:4e245f4bc8ac 432 gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
phungductung 0:4e245f4bc8ac 433 HAL_GPIO_Init(GPIOH, &gpio_init_structure);
phungductung 0:4e245f4bc8ac 434
phungductung 0:4e245f4bc8ac 435 /* Configure common DMA parameters */
phungductung 0:4e245f4bc8ac 436 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
phungductung 0:4e245f4bc8ac 437 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
phungductung 0:4e245f4bc8ac 438 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
phungductung 0:4e245f4bc8ac 439 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
phungductung 0:4e245f4bc8ac 440 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
phungductung 0:4e245f4bc8ac 441 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
phungductung 0:4e245f4bc8ac 442 dma_handle.Init.Mode = DMA_NORMAL;
phungductung 0:4e245f4bc8ac 443 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
phungductung 0:4e245f4bc8ac 444 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
phungductung 0:4e245f4bc8ac 445 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
phungductung 0:4e245f4bc8ac 446 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
phungductung 0:4e245f4bc8ac 447 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
phungductung 0:4e245f4bc8ac 448
phungductung 0:4e245f4bc8ac 449 dma_handle.Instance = SDRAM_DMAx_STREAM;
phungductung 0:4e245f4bc8ac 450
phungductung 0:4e245f4bc8ac 451 /* Associate the DMA handle */
phungductung 0:4e245f4bc8ac 452 __HAL_LINKDMA(hsdram, hdma, dma_handle);
phungductung 0:4e245f4bc8ac 453
phungductung 0:4e245f4bc8ac 454 /* Deinitialize the stream for new transfer */
phungductung 0:4e245f4bc8ac 455 HAL_DMA_DeInit(&dma_handle);
phungductung 0:4e245f4bc8ac 456
phungductung 0:4e245f4bc8ac 457 /* Configure the DMA stream */
phungductung 0:4e245f4bc8ac 458 HAL_DMA_Init(&dma_handle);
phungductung 0:4e245f4bc8ac 459
phungductung 0:4e245f4bc8ac 460 /* NVIC configuration for DMA transfer complete interrupt */
phungductung 0:4e245f4bc8ac 461 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
phungductung 0:4e245f4bc8ac 462 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
phungductung 0:4e245f4bc8ac 463 }
phungductung 0:4e245f4bc8ac 464
phungductung 0:4e245f4bc8ac 465 /**
phungductung 0:4e245f4bc8ac 466 * @brief DeInitializes SDRAM MSP.
phungductung 0:4e245f4bc8ac 467 * @param hsdram: SDRAM handle
phungductung 0:4e245f4bc8ac 468 * @param Params
phungductung 0:4e245f4bc8ac 469 * @retval None
phungductung 0:4e245f4bc8ac 470 */
phungductung 0:4e245f4bc8ac 471 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
phungductung 0:4e245f4bc8ac 472 {
phungductung 0:4e245f4bc8ac 473 static DMA_HandleTypeDef dma_handle;
phungductung 0:4e245f4bc8ac 474
phungductung 0:4e245f4bc8ac 475 /* Disable NVIC configuration for DMA interrupt */
phungductung 0:4e245f4bc8ac 476 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
phungductung 0:4e245f4bc8ac 477
phungductung 0:4e245f4bc8ac 478 /* Deinitialize the stream for new transfer */
phungductung 0:4e245f4bc8ac 479 dma_handle.Instance = SDRAM_DMAx_STREAM;
phungductung 0:4e245f4bc8ac 480 HAL_DMA_DeInit(&dma_handle);
phungductung 0:4e245f4bc8ac 481
phungductung 0:4e245f4bc8ac 482 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
phungductung 0:4e245f4bc8ac 483 by surcharging this __weak function */
phungductung 0:4e245f4bc8ac 484 }
phungductung 0:4e245f4bc8ac 485
phungductung 0:4e245f4bc8ac 486 /**
phungductung 0:4e245f4bc8ac 487 * @}
phungductung 0:4e245f4bc8ac 488 */
phungductung 0:4e245f4bc8ac 489
phungductung 0:4e245f4bc8ac 490 /**
phungductung 0:4e245f4bc8ac 491 * @}
phungductung 0:4e245f4bc8ac 492 */
phungductung 0:4e245f4bc8ac 493
phungductung 0:4e245f4bc8ac 494 /**
phungductung 0:4e245f4bc8ac 495 * @}
phungductung 0:4e245f4bc8ac 496 */
phungductung 0:4e245f4bc8ac 497
phungductung 0:4e245f4bc8ac 498 /**
phungductung 0:4e245f4bc8ac 499 * @}
phungductung 0:4e245f4bc8ac 500 */
phungductung 0:4e245f4bc8ac 501
phungductung 0:4e245f4bc8ac 502 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/