PHung Tung
SPKT
Dependencies: F746_GUI SD_PlayerSkeleton F746_SAI_IO
SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h@0:8ede47d38d10, 2019-06-04 (annotated)
- Committer:
- phungductung
- Date:
- Tue Jun 04 21:37:21 2019 +0000
- Revision:
- 0:8ede47d38d10
SPKT
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| phungductung | 0:8ede47d38d10 | 1 | /** |
| phungductung | 0:8ede47d38d10 | 2 | ****************************************************************************** |
| phungductung | 0:8ede47d38d10 | 3 | * @file stm32f7xx_hal_rcc_ex.h |
| phungductung | 0:8ede47d38d10 | 4 | * @author MCD Application Team |
| phungductung | 0:8ede47d38d10 | 5 | * @version V1.0.4 |
| phungductung | 0:8ede47d38d10 | 6 | * @date 09-December-2015 |
| phungductung | 0:8ede47d38d10 | 7 | * @brief Header file of RCC HAL Extension module. |
| phungductung | 0:8ede47d38d10 | 8 | ****************************************************************************** |
| phungductung | 0:8ede47d38d10 | 9 | * @attention |
| phungductung | 0:8ede47d38d10 | 10 | * |
| phungductung | 0:8ede47d38d10 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| phungductung | 0:8ede47d38d10 | 12 | * |
| phungductung | 0:8ede47d38d10 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| phungductung | 0:8ede47d38d10 | 14 | * are permitted provided that the following conditions are met: |
| phungductung | 0:8ede47d38d10 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| phungductung | 0:8ede47d38d10 | 16 | * this list of conditions and the following disclaimer. |
| phungductung | 0:8ede47d38d10 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| phungductung | 0:8ede47d38d10 | 18 | * this list of conditions and the following disclaimer in the documentation |
| phungductung | 0:8ede47d38d10 | 19 | * and/or other materials provided with the distribution. |
| phungductung | 0:8ede47d38d10 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| phungductung | 0:8ede47d38d10 | 21 | * may be used to endorse or promote products derived from this software |
| phungductung | 0:8ede47d38d10 | 22 | * without specific prior written permission. |
| phungductung | 0:8ede47d38d10 | 23 | * |
| phungductung | 0:8ede47d38d10 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| phungductung | 0:8ede47d38d10 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| phungductung | 0:8ede47d38d10 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| phungductung | 0:8ede47d38d10 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| phungductung | 0:8ede47d38d10 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| phungductung | 0:8ede47d38d10 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| phungductung | 0:8ede47d38d10 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| phungductung | 0:8ede47d38d10 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| phungductung | 0:8ede47d38d10 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| phungductung | 0:8ede47d38d10 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| phungductung | 0:8ede47d38d10 | 34 | * |
| phungductung | 0:8ede47d38d10 | 35 | ****************************************************************************** |
| phungductung | 0:8ede47d38d10 | 36 | */ |
| phungductung | 0:8ede47d38d10 | 37 | |
| phungductung | 0:8ede47d38d10 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 39 | #ifndef __STM32F7xx_HAL_RCC_EX_H |
| phungductung | 0:8ede47d38d10 | 40 | #define __STM32F7xx_HAL_RCC_EX_H |
| phungductung | 0:8ede47d38d10 | 41 | |
| phungductung | 0:8ede47d38d10 | 42 | #ifdef __cplusplus |
| phungductung | 0:8ede47d38d10 | 43 | extern "C" { |
| phungductung | 0:8ede47d38d10 | 44 | #endif |
| phungductung | 0:8ede47d38d10 | 45 | |
| phungductung | 0:8ede47d38d10 | 46 | /* Includes ------------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 47 | #include "stm32f7xx_hal_def.h" |
| phungductung | 0:8ede47d38d10 | 48 | |
| phungductung | 0:8ede47d38d10 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| phungductung | 0:8ede47d38d10 | 50 | * @{ |
| phungductung | 0:8ede47d38d10 | 51 | */ |
| phungductung | 0:8ede47d38d10 | 52 | |
| phungductung | 0:8ede47d38d10 | 53 | /** @addtogroup RCCEx |
| phungductung | 0:8ede47d38d10 | 54 | * @{ |
| phungductung | 0:8ede47d38d10 | 55 | */ |
| phungductung | 0:8ede47d38d10 | 56 | |
| phungductung | 0:8ede47d38d10 | 57 | /* Exported types ------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 58 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
| phungductung | 0:8ede47d38d10 | 59 | * @{ |
| phungductung | 0:8ede47d38d10 | 60 | */ |
| phungductung | 0:8ede47d38d10 | 61 | |
| phungductung | 0:8ede47d38d10 | 62 | /** |
| phungductung | 0:8ede47d38d10 | 63 | * @brief PLLI2S Clock structure definition |
| phungductung | 0:8ede47d38d10 | 64 | */ |
| phungductung | 0:8ede47d38d10 | 65 | typedef struct |
| phungductung | 0:8ede47d38d10 | 66 | { |
| phungductung | 0:8ede47d38d10 | 67 | uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| phungductung | 0:8ede47d38d10 | 68 | This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
| phungductung | 0:8ede47d38d10 | 69 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| phungductung | 0:8ede47d38d10 | 70 | |
| phungductung | 0:8ede47d38d10 | 71 | uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| phungductung | 0:8ede47d38d10 | 72 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| phungductung | 0:8ede47d38d10 | 73 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| phungductung | 0:8ede47d38d10 | 74 | |
| phungductung | 0:8ede47d38d10 | 75 | uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 76 | This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| phungductung | 0:8ede47d38d10 | 77 | This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| phungductung | 0:8ede47d38d10 | 78 | |
| phungductung | 0:8ede47d38d10 | 79 | uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. |
| phungductung | 0:8ede47d38d10 | 80 | This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. |
| phungductung | 0:8ede47d38d10 | 81 | This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ |
| phungductung | 0:8ede47d38d10 | 82 | }RCC_PLLI2SInitTypeDef; |
| phungductung | 0:8ede47d38d10 | 83 | |
| phungductung | 0:8ede47d38d10 | 84 | /** |
| phungductung | 0:8ede47d38d10 | 85 | * @brief PLLSAI Clock structure definition |
| phungductung | 0:8ede47d38d10 | 86 | */ |
| phungductung | 0:8ede47d38d10 | 87 | typedef struct |
| phungductung | 0:8ede47d38d10 | 88 | { |
| phungductung | 0:8ede47d38d10 | 89 | uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| phungductung | 0:8ede47d38d10 | 90 | This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
| phungductung | 0:8ede47d38d10 | 91 | This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
| phungductung | 0:8ede47d38d10 | 92 | |
| phungductung | 0:8ede47d38d10 | 93 | uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 94 | This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| phungductung | 0:8ede47d38d10 | 95 | This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
| phungductung | 0:8ede47d38d10 | 96 | |
| phungductung | 0:8ede47d38d10 | 97 | uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock |
| phungductung | 0:8ede47d38d10 | 98 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| phungductung | 0:8ede47d38d10 | 99 | This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ |
| phungductung | 0:8ede47d38d10 | 100 | |
| phungductung | 0:8ede47d38d10 | 101 | uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. |
| phungductung | 0:8ede47d38d10 | 102 | This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider |
| phungductung | 0:8ede47d38d10 | 103 | This parameter will be used only when PLLSAI is disabled */ |
| phungductung | 0:8ede47d38d10 | 104 | }RCC_PLLSAIInitTypeDef; |
| phungductung | 0:8ede47d38d10 | 105 | |
| phungductung | 0:8ede47d38d10 | 106 | /** |
| phungductung | 0:8ede47d38d10 | 107 | * @brief RCC extended clocks structure definition |
| phungductung | 0:8ede47d38d10 | 108 | */ |
| phungductung | 0:8ede47d38d10 | 109 | typedef struct |
| phungductung | 0:8ede47d38d10 | 110 | { |
| phungductung | 0:8ede47d38d10 | 111 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| phungductung | 0:8ede47d38d10 | 112 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| phungductung | 0:8ede47d38d10 | 113 | |
| phungductung | 0:8ede47d38d10 | 114 | RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| phungductung | 0:8ede47d38d10 | 115 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
| phungductung | 0:8ede47d38d10 | 116 | |
| phungductung | 0:8ede47d38d10 | 117 | RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. |
| phungductung | 0:8ede47d38d10 | 118 | This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ |
| phungductung | 0:8ede47d38d10 | 119 | |
| phungductung | 0:8ede47d38d10 | 120 | uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 121 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| phungductung | 0:8ede47d38d10 | 122 | This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
| phungductung | 0:8ede47d38d10 | 123 | |
| phungductung | 0:8ede47d38d10 | 124 | uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 125 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
| phungductung | 0:8ede47d38d10 | 126 | This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
| phungductung | 0:8ede47d38d10 | 127 | |
| phungductung | 0:8ede47d38d10 | 128 | uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. |
| phungductung | 0:8ede47d38d10 | 129 | This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ |
| phungductung | 0:8ede47d38d10 | 130 | |
| phungductung | 0:8ede47d38d10 | 131 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. |
| phungductung | 0:8ede47d38d10 | 132 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 133 | |
| phungductung | 0:8ede47d38d10 | 134 | uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. |
| phungductung | 0:8ede47d38d10 | 135 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 136 | |
| phungductung | 0:8ede47d38d10 | 137 | uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. |
| phungductung | 0:8ede47d38d10 | 138 | This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ |
| phungductung | 0:8ede47d38d10 | 139 | |
| phungductung | 0:8ede47d38d10 | 140 | uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection |
| phungductung | 0:8ede47d38d10 | 141 | This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 142 | |
| phungductung | 0:8ede47d38d10 | 143 | uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection |
| phungductung | 0:8ede47d38d10 | 144 | This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 145 | |
| phungductung | 0:8ede47d38d10 | 146 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
| phungductung | 0:8ede47d38d10 | 147 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 148 | |
| phungductung | 0:8ede47d38d10 | 149 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
| phungductung | 0:8ede47d38d10 | 150 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 151 | |
| phungductung | 0:8ede47d38d10 | 152 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
| phungductung | 0:8ede47d38d10 | 153 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 154 | |
| phungductung | 0:8ede47d38d10 | 155 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
| phungductung | 0:8ede47d38d10 | 156 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 157 | |
| phungductung | 0:8ede47d38d10 | 158 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
| phungductung | 0:8ede47d38d10 | 159 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 160 | |
| phungductung | 0:8ede47d38d10 | 161 | uint32_t Usart6ClockSelection; /*!< USART6 clock source |
| phungductung | 0:8ede47d38d10 | 162 | This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 163 | |
| phungductung | 0:8ede47d38d10 | 164 | uint32_t Uart7ClockSelection; /*!< UART7 clock source |
| phungductung | 0:8ede47d38d10 | 165 | This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 166 | |
| phungductung | 0:8ede47d38d10 | 167 | uint32_t Uart8ClockSelection; /*!< UART8 clock source |
| phungductung | 0:8ede47d38d10 | 168 | This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 169 | |
| phungductung | 0:8ede47d38d10 | 170 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
| phungductung | 0:8ede47d38d10 | 171 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 172 | |
| phungductung | 0:8ede47d38d10 | 173 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
| phungductung | 0:8ede47d38d10 | 174 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 175 | |
| phungductung | 0:8ede47d38d10 | 176 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
| phungductung | 0:8ede47d38d10 | 177 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 178 | |
| phungductung | 0:8ede47d38d10 | 179 | uint32_t I2c4ClockSelection; /*!< I2C4 clock source |
| phungductung | 0:8ede47d38d10 | 180 | This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 181 | |
| phungductung | 0:8ede47d38d10 | 182 | uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source |
| phungductung | 0:8ede47d38d10 | 183 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 184 | |
| phungductung | 0:8ede47d38d10 | 185 | uint32_t CecClockSelection; /*!< CEC clock source |
| phungductung | 0:8ede47d38d10 | 186 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 187 | |
| phungductung | 0:8ede47d38d10 | 188 | uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC |
| phungductung | 0:8ede47d38d10 | 189 | This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 190 | |
| phungductung | 0:8ede47d38d10 | 191 | uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source |
| phungductung | 0:8ede47d38d10 | 192 | This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ |
| phungductung | 0:8ede47d38d10 | 193 | }RCC_PeriphCLKInitTypeDef; |
| phungductung | 0:8ede47d38d10 | 194 | /** |
| phungductung | 0:8ede47d38d10 | 195 | * @} |
| phungductung | 0:8ede47d38d10 | 196 | */ |
| phungductung | 0:8ede47d38d10 | 197 | |
| phungductung | 0:8ede47d38d10 | 198 | /* Exported constants --------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 199 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
| phungductung | 0:8ede47d38d10 | 200 | * @{ |
| phungductung | 0:8ede47d38d10 | 201 | */ |
| phungductung | 0:8ede47d38d10 | 202 | |
| phungductung | 0:8ede47d38d10 | 203 | /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection |
| phungductung | 0:8ede47d38d10 | 204 | * @{ |
| phungductung | 0:8ede47d38d10 | 205 | */ |
| phungductung | 0:8ede47d38d10 | 206 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) |
| phungductung | 0:8ede47d38d10 | 207 | #if defined(STM32F746xx) || defined(STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 208 | #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) |
| phungductung | 0:8ede47d38d10 | 209 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 210 | #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) |
| phungductung | 0:8ede47d38d10 | 211 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) |
| phungductung | 0:8ede47d38d10 | 212 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040) |
| phungductung | 0:8ede47d38d10 | 213 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080) |
| phungductung | 0:8ede47d38d10 | 214 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100) |
| phungductung | 0:8ede47d38d10 | 215 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200) |
| phungductung | 0:8ede47d38d10 | 216 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400) |
| phungductung | 0:8ede47d38d10 | 217 | #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800) |
| phungductung | 0:8ede47d38d10 | 218 | #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000) |
| phungductung | 0:8ede47d38d10 | 219 | #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000) |
| phungductung | 0:8ede47d38d10 | 220 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000) |
| phungductung | 0:8ede47d38d10 | 221 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000) |
| phungductung | 0:8ede47d38d10 | 222 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000) |
| phungductung | 0:8ede47d38d10 | 223 | #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000) |
| phungductung | 0:8ede47d38d10 | 224 | #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000) |
| phungductung | 0:8ede47d38d10 | 225 | #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000) |
| phungductung | 0:8ede47d38d10 | 226 | #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000) |
| phungductung | 0:8ede47d38d10 | 227 | #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000) |
| phungductung | 0:8ede47d38d10 | 228 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000) |
| phungductung | 0:8ede47d38d10 | 229 | #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000) |
| phungductung | 0:8ede47d38d10 | 230 | #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000) |
| phungductung | 0:8ede47d38d10 | 231 | #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000) |
| phungductung | 0:8ede47d38d10 | 232 | |
| phungductung | 0:8ede47d38d10 | 233 | /** |
| phungductung | 0:8ede47d38d10 | 234 | * @} |
| phungductung | 0:8ede47d38d10 | 235 | */ |
| phungductung | 0:8ede47d38d10 | 236 | |
| phungductung | 0:8ede47d38d10 | 237 | /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider |
| phungductung | 0:8ede47d38d10 | 238 | * @{ |
| phungductung | 0:8ede47d38d10 | 239 | */ |
| phungductung | 0:8ede47d38d10 | 240 | #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 241 | #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001) |
| phungductung | 0:8ede47d38d10 | 242 | #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002) |
| phungductung | 0:8ede47d38d10 | 243 | #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003) |
| phungductung | 0:8ede47d38d10 | 244 | /** |
| phungductung | 0:8ede47d38d10 | 245 | * @} |
| phungductung | 0:8ede47d38d10 | 246 | */ |
| phungductung | 0:8ede47d38d10 | 247 | |
| phungductung | 0:8ede47d38d10 | 248 | /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider |
| phungductung | 0:8ede47d38d10 | 249 | * @{ |
| phungductung | 0:8ede47d38d10 | 250 | */ |
| phungductung | 0:8ede47d38d10 | 251 | #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 252 | #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001) |
| phungductung | 0:8ede47d38d10 | 253 | #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002) |
| phungductung | 0:8ede47d38d10 | 254 | #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003) |
| phungductung | 0:8ede47d38d10 | 255 | /** |
| phungductung | 0:8ede47d38d10 | 256 | * @} |
| phungductung | 0:8ede47d38d10 | 257 | */ |
| phungductung | 0:8ede47d38d10 | 258 | |
| phungductung | 0:8ede47d38d10 | 259 | /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR |
| phungductung | 0:8ede47d38d10 | 260 | * @{ |
| phungductung | 0:8ede47d38d10 | 261 | */ |
| phungductung | 0:8ede47d38d10 | 262 | #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 263 | #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 |
| phungductung | 0:8ede47d38d10 | 264 | #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 |
| phungductung | 0:8ede47d38d10 | 265 | #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR |
| phungductung | 0:8ede47d38d10 | 266 | /** |
| phungductung | 0:8ede47d38d10 | 267 | * @} |
| phungductung | 0:8ede47d38d10 | 268 | */ |
| phungductung | 0:8ede47d38d10 | 269 | |
| phungductung | 0:8ede47d38d10 | 270 | /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source |
| phungductung | 0:8ede47d38d10 | 271 | * @{ |
| phungductung | 0:8ede47d38d10 | 272 | */ |
| phungductung | 0:8ede47d38d10 | 273 | #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 274 | #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC |
| phungductung | 0:8ede47d38d10 | 275 | |
| phungductung | 0:8ede47d38d10 | 276 | /** |
| phungductung | 0:8ede47d38d10 | 277 | * @} |
| phungductung | 0:8ede47d38d10 | 278 | */ |
| phungductung | 0:8ede47d38d10 | 279 | |
| phungductung | 0:8ede47d38d10 | 280 | |
| phungductung | 0:8ede47d38d10 | 281 | /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source |
| phungductung | 0:8ede47d38d10 | 282 | * @{ |
| phungductung | 0:8ede47d38d10 | 283 | */ |
| phungductung | 0:8ede47d38d10 | 284 | #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 285 | #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 |
| phungductung | 0:8ede47d38d10 | 286 | #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 |
| phungductung | 0:8ede47d38d10 | 287 | |
| phungductung | 0:8ede47d38d10 | 288 | /** |
| phungductung | 0:8ede47d38d10 | 289 | * @} |
| phungductung | 0:8ede47d38d10 | 290 | */ |
| phungductung | 0:8ede47d38d10 | 291 | |
| phungductung | 0:8ede47d38d10 | 292 | /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source |
| phungductung | 0:8ede47d38d10 | 293 | * @{ |
| phungductung | 0:8ede47d38d10 | 294 | */ |
| phungductung | 0:8ede47d38d10 | 295 | #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 296 | #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 |
| phungductung | 0:8ede47d38d10 | 297 | #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 |
| phungductung | 0:8ede47d38d10 | 298 | /** |
| phungductung | 0:8ede47d38d10 | 299 | * @} |
| phungductung | 0:8ede47d38d10 | 300 | */ |
| phungductung | 0:8ede47d38d10 | 301 | |
| phungductung | 0:8ede47d38d10 | 302 | /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source |
| phungductung | 0:8ede47d38d10 | 303 | * @{ |
| phungductung | 0:8ede47d38d10 | 304 | */ |
| phungductung | 0:8ede47d38d10 | 305 | #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 306 | #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ |
| phungductung | 0:8ede47d38d10 | 307 | /** |
| phungductung | 0:8ede47d38d10 | 308 | * @} |
| phungductung | 0:8ede47d38d10 | 309 | */ |
| phungductung | 0:8ede47d38d10 | 310 | |
| phungductung | 0:8ede47d38d10 | 311 | /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source |
| phungductung | 0:8ede47d38d10 | 312 | * @{ |
| phungductung | 0:8ede47d38d10 | 313 | */ |
| phungductung | 0:8ede47d38d10 | 314 | #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 315 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 |
| phungductung | 0:8ede47d38d10 | 316 | #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 |
| phungductung | 0:8ede47d38d10 | 317 | #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL |
| phungductung | 0:8ede47d38d10 | 318 | /** |
| phungductung | 0:8ede47d38d10 | 319 | * @} |
| phungductung | 0:8ede47d38d10 | 320 | */ |
| phungductung | 0:8ede47d38d10 | 321 | |
| phungductung | 0:8ede47d38d10 | 322 | /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source |
| phungductung | 0:8ede47d38d10 | 323 | * @{ |
| phungductung | 0:8ede47d38d10 | 324 | */ |
| phungductung | 0:8ede47d38d10 | 325 | #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 326 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 |
| phungductung | 0:8ede47d38d10 | 327 | #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 |
| phungductung | 0:8ede47d38d10 | 328 | #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL |
| phungductung | 0:8ede47d38d10 | 329 | /** |
| phungductung | 0:8ede47d38d10 | 330 | * @} |
| phungductung | 0:8ede47d38d10 | 331 | */ |
| phungductung | 0:8ede47d38d10 | 332 | |
| phungductung | 0:8ede47d38d10 | 333 | /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source |
| phungductung | 0:8ede47d38d10 | 334 | * @{ |
| phungductung | 0:8ede47d38d10 | 335 | */ |
| phungductung | 0:8ede47d38d10 | 336 | #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 337 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 |
| phungductung | 0:8ede47d38d10 | 338 | #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 |
| phungductung | 0:8ede47d38d10 | 339 | #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL |
| phungductung | 0:8ede47d38d10 | 340 | /** |
| phungductung | 0:8ede47d38d10 | 341 | * @} |
| phungductung | 0:8ede47d38d10 | 342 | */ |
| phungductung | 0:8ede47d38d10 | 343 | |
| phungductung | 0:8ede47d38d10 | 344 | /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source |
| phungductung | 0:8ede47d38d10 | 345 | * @{ |
| phungductung | 0:8ede47d38d10 | 346 | */ |
| phungductung | 0:8ede47d38d10 | 347 | #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 348 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 |
| phungductung | 0:8ede47d38d10 | 349 | #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 |
| phungductung | 0:8ede47d38d10 | 350 | #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL |
| phungductung | 0:8ede47d38d10 | 351 | /** |
| phungductung | 0:8ede47d38d10 | 352 | * @} |
| phungductung | 0:8ede47d38d10 | 353 | */ |
| phungductung | 0:8ede47d38d10 | 354 | |
| phungductung | 0:8ede47d38d10 | 355 | /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source |
| phungductung | 0:8ede47d38d10 | 356 | * @{ |
| phungductung | 0:8ede47d38d10 | 357 | */ |
| phungductung | 0:8ede47d38d10 | 358 | #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 359 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 |
| phungductung | 0:8ede47d38d10 | 360 | #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 |
| phungductung | 0:8ede47d38d10 | 361 | #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL |
| phungductung | 0:8ede47d38d10 | 362 | /** |
| phungductung | 0:8ede47d38d10 | 363 | * @} |
| phungductung | 0:8ede47d38d10 | 364 | */ |
| phungductung | 0:8ede47d38d10 | 365 | |
| phungductung | 0:8ede47d38d10 | 366 | /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source |
| phungductung | 0:8ede47d38d10 | 367 | * @{ |
| phungductung | 0:8ede47d38d10 | 368 | */ |
| phungductung | 0:8ede47d38d10 | 369 | #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 370 | #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 |
| phungductung | 0:8ede47d38d10 | 371 | #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 |
| phungductung | 0:8ede47d38d10 | 372 | #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL |
| phungductung | 0:8ede47d38d10 | 373 | /** |
| phungductung | 0:8ede47d38d10 | 374 | * @} |
| phungductung | 0:8ede47d38d10 | 375 | */ |
| phungductung | 0:8ede47d38d10 | 376 | |
| phungductung | 0:8ede47d38d10 | 377 | /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source |
| phungductung | 0:8ede47d38d10 | 378 | * @{ |
| phungductung | 0:8ede47d38d10 | 379 | */ |
| phungductung | 0:8ede47d38d10 | 380 | #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 381 | #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 |
| phungductung | 0:8ede47d38d10 | 382 | #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 |
| phungductung | 0:8ede47d38d10 | 383 | #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL |
| phungductung | 0:8ede47d38d10 | 384 | /** |
| phungductung | 0:8ede47d38d10 | 385 | * @} |
| phungductung | 0:8ede47d38d10 | 386 | */ |
| phungductung | 0:8ede47d38d10 | 387 | |
| phungductung | 0:8ede47d38d10 | 388 | /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source |
| phungductung | 0:8ede47d38d10 | 389 | * @{ |
| phungductung | 0:8ede47d38d10 | 390 | */ |
| phungductung | 0:8ede47d38d10 | 391 | #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 392 | #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 |
| phungductung | 0:8ede47d38d10 | 393 | #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 |
| phungductung | 0:8ede47d38d10 | 394 | #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL |
| phungductung | 0:8ede47d38d10 | 395 | /** |
| phungductung | 0:8ede47d38d10 | 396 | * @} |
| phungductung | 0:8ede47d38d10 | 397 | */ |
| phungductung | 0:8ede47d38d10 | 398 | |
| phungductung | 0:8ede47d38d10 | 399 | /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source |
| phungductung | 0:8ede47d38d10 | 400 | * @{ |
| phungductung | 0:8ede47d38d10 | 401 | */ |
| phungductung | 0:8ede47d38d10 | 402 | #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 403 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 |
| phungductung | 0:8ede47d38d10 | 404 | #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 |
| phungductung | 0:8ede47d38d10 | 405 | /** |
| phungductung | 0:8ede47d38d10 | 406 | * @} |
| phungductung | 0:8ede47d38d10 | 407 | */ |
| phungductung | 0:8ede47d38d10 | 408 | |
| phungductung | 0:8ede47d38d10 | 409 | /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source |
| phungductung | 0:8ede47d38d10 | 410 | * @{ |
| phungductung | 0:8ede47d38d10 | 411 | */ |
| phungductung | 0:8ede47d38d10 | 412 | #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 413 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 |
| phungductung | 0:8ede47d38d10 | 414 | #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 |
| phungductung | 0:8ede47d38d10 | 415 | |
| phungductung | 0:8ede47d38d10 | 416 | /** |
| phungductung | 0:8ede47d38d10 | 417 | * @} |
| phungductung | 0:8ede47d38d10 | 418 | */ |
| phungductung | 0:8ede47d38d10 | 419 | |
| phungductung | 0:8ede47d38d10 | 420 | /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source |
| phungductung | 0:8ede47d38d10 | 421 | * @{ |
| phungductung | 0:8ede47d38d10 | 422 | */ |
| phungductung | 0:8ede47d38d10 | 423 | #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 424 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 |
| phungductung | 0:8ede47d38d10 | 425 | #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 |
| phungductung | 0:8ede47d38d10 | 426 | /** |
| phungductung | 0:8ede47d38d10 | 427 | * @} |
| phungductung | 0:8ede47d38d10 | 428 | */ |
| phungductung | 0:8ede47d38d10 | 429 | |
| phungductung | 0:8ede47d38d10 | 430 | /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source |
| phungductung | 0:8ede47d38d10 | 431 | * @{ |
| phungductung | 0:8ede47d38d10 | 432 | */ |
| phungductung | 0:8ede47d38d10 | 433 | #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 434 | #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 |
| phungductung | 0:8ede47d38d10 | 435 | #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 |
| phungductung | 0:8ede47d38d10 | 436 | /** |
| phungductung | 0:8ede47d38d10 | 437 | * @} |
| phungductung | 0:8ede47d38d10 | 438 | */ |
| phungductung | 0:8ede47d38d10 | 439 | |
| phungductung | 0:8ede47d38d10 | 440 | /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source |
| phungductung | 0:8ede47d38d10 | 441 | * @{ |
| phungductung | 0:8ede47d38d10 | 442 | */ |
| phungductung | 0:8ede47d38d10 | 443 | #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 444 | #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 |
| phungductung | 0:8ede47d38d10 | 445 | #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 |
| phungductung | 0:8ede47d38d10 | 446 | #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL |
| phungductung | 0:8ede47d38d10 | 447 | |
| phungductung | 0:8ede47d38d10 | 448 | /** |
| phungductung | 0:8ede47d38d10 | 449 | * @} |
| phungductung | 0:8ede47d38d10 | 450 | */ |
| phungductung | 0:8ede47d38d10 | 451 | |
| phungductung | 0:8ede47d38d10 | 452 | /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source |
| phungductung | 0:8ede47d38d10 | 453 | * @{ |
| phungductung | 0:8ede47d38d10 | 454 | */ |
| phungductung | 0:8ede47d38d10 | 455 | #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 456 | #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL |
| phungductung | 0:8ede47d38d10 | 457 | /** |
| phungductung | 0:8ede47d38d10 | 458 | * @} |
| phungductung | 0:8ede47d38d10 | 459 | */ |
| phungductung | 0:8ede47d38d10 | 460 | |
| phungductung | 0:8ede47d38d10 | 461 | /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection |
| phungductung | 0:8ede47d38d10 | 462 | * @{ |
| phungductung | 0:8ede47d38d10 | 463 | */ |
| phungductung | 0:8ede47d38d10 | 464 | #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 465 | #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE |
| phungductung | 0:8ede47d38d10 | 466 | /** |
| phungductung | 0:8ede47d38d10 | 467 | * @} |
| phungductung | 0:8ede47d38d10 | 468 | */ |
| phungductung | 0:8ede47d38d10 | 469 | |
| phungductung | 0:8ede47d38d10 | 470 | /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source |
| phungductung | 0:8ede47d38d10 | 471 | * @{ |
| phungductung | 0:8ede47d38d10 | 472 | */ |
| phungductung | 0:8ede47d38d10 | 473 | #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000) |
| phungductung | 0:8ede47d38d10 | 474 | #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL |
| phungductung | 0:8ede47d38d10 | 475 | /** |
| phungductung | 0:8ede47d38d10 | 476 | * @} |
| phungductung | 0:8ede47d38d10 | 477 | */ |
| phungductung | 0:8ede47d38d10 | 478 | |
| phungductung | 0:8ede47d38d10 | 479 | /** |
| phungductung | 0:8ede47d38d10 | 480 | * @} |
| phungductung | 0:8ede47d38d10 | 481 | */ |
| phungductung | 0:8ede47d38d10 | 482 | |
| phungductung | 0:8ede47d38d10 | 483 | /* Exported macro ------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 484 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
| phungductung | 0:8ede47d38d10 | 485 | * @{ |
| phungductung | 0:8ede47d38d10 | 486 | */ |
| phungductung | 0:8ede47d38d10 | 487 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
| phungductung | 0:8ede47d38d10 | 488 | * @brief Enables or disables the AHB/APB peripheral clock. |
| phungductung | 0:8ede47d38d10 | 489 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 490 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 491 | * using it. |
| phungductung | 0:8ede47d38d10 | 492 | * @{ |
| phungductung | 0:8ede47d38d10 | 493 | */ |
| phungductung | 0:8ede47d38d10 | 494 | |
| phungductung | 0:8ede47d38d10 | 495 | /** @brief Enables or disables the AHB1 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 496 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 497 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 498 | * using it. |
| phungductung | 0:8ede47d38d10 | 499 | */ |
| phungductung | 0:8ede47d38d10 | 500 | #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 501 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 502 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
| phungductung | 0:8ede47d38d10 | 503 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 504 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
| phungductung | 0:8ede47d38d10 | 505 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 506 | } while(0) |
| phungductung | 0:8ede47d38d10 | 507 | |
| phungductung | 0:8ede47d38d10 | 508 | #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 509 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 510 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ |
| phungductung | 0:8ede47d38d10 | 511 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 512 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ |
| phungductung | 0:8ede47d38d10 | 513 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 514 | } while(0) |
| phungductung | 0:8ede47d38d10 | 515 | |
| phungductung | 0:8ede47d38d10 | 516 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 517 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 518 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
| phungductung | 0:8ede47d38d10 | 519 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 520 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
| phungductung | 0:8ede47d38d10 | 521 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 522 | } while(0) |
| phungductung | 0:8ede47d38d10 | 523 | |
| phungductung | 0:8ede47d38d10 | 524 | #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 525 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 526 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
| phungductung | 0:8ede47d38d10 | 527 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 528 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
| phungductung | 0:8ede47d38d10 | 529 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 530 | } while(0) |
| phungductung | 0:8ede47d38d10 | 531 | |
| phungductung | 0:8ede47d38d10 | 532 | #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 533 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 534 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
| phungductung | 0:8ede47d38d10 | 535 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 536 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
| phungductung | 0:8ede47d38d10 | 537 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 538 | } while(0) |
| phungductung | 0:8ede47d38d10 | 539 | |
| phungductung | 0:8ede47d38d10 | 540 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 541 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 542 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
| phungductung | 0:8ede47d38d10 | 543 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 544 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
| phungductung | 0:8ede47d38d10 | 545 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 546 | } while(0) |
| phungductung | 0:8ede47d38d10 | 547 | |
| phungductung | 0:8ede47d38d10 | 548 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 549 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 550 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
| phungductung | 0:8ede47d38d10 | 551 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 552 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
| phungductung | 0:8ede47d38d10 | 553 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 554 | } while(0) |
| phungductung | 0:8ede47d38d10 | 555 | |
| phungductung | 0:8ede47d38d10 | 556 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 557 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 558 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
| phungductung | 0:8ede47d38d10 | 559 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 560 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
| phungductung | 0:8ede47d38d10 | 561 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 562 | } while(0) |
| phungductung | 0:8ede47d38d10 | 563 | |
| phungductung | 0:8ede47d38d10 | 564 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 565 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 566 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
| phungductung | 0:8ede47d38d10 | 567 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 568 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
| phungductung | 0:8ede47d38d10 | 569 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 570 | } while(0) |
| phungductung | 0:8ede47d38d10 | 571 | |
| phungductung | 0:8ede47d38d10 | 572 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 573 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 574 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
| phungductung | 0:8ede47d38d10 | 575 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 576 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
| phungductung | 0:8ede47d38d10 | 577 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 578 | } while(0) |
| phungductung | 0:8ede47d38d10 | 579 | |
| phungductung | 0:8ede47d38d10 | 580 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 581 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 582 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
| phungductung | 0:8ede47d38d10 | 583 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 584 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
| phungductung | 0:8ede47d38d10 | 585 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 586 | } while(0) |
| phungductung | 0:8ede47d38d10 | 587 | |
| phungductung | 0:8ede47d38d10 | 588 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 589 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 590 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
| phungductung | 0:8ede47d38d10 | 591 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 592 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
| phungductung | 0:8ede47d38d10 | 593 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 594 | } while(0) |
| phungductung | 0:8ede47d38d10 | 595 | |
| phungductung | 0:8ede47d38d10 | 596 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 597 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 598 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
| phungductung | 0:8ede47d38d10 | 599 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 600 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
| phungductung | 0:8ede47d38d10 | 601 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 602 | } while(0) |
| phungductung | 0:8ede47d38d10 | 603 | |
| phungductung | 0:8ede47d38d10 | 604 | #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 605 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 606 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
| phungductung | 0:8ede47d38d10 | 607 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 608 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
| phungductung | 0:8ede47d38d10 | 609 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 610 | } while(0) |
| phungductung | 0:8ede47d38d10 | 611 | |
| phungductung | 0:8ede47d38d10 | 612 | #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 613 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 614 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
| phungductung | 0:8ede47d38d10 | 615 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 616 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
| phungductung | 0:8ede47d38d10 | 617 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 618 | } while(0) |
| phungductung | 0:8ede47d38d10 | 619 | |
| phungductung | 0:8ede47d38d10 | 620 | #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 621 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 622 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
| phungductung | 0:8ede47d38d10 | 623 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 624 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
| phungductung | 0:8ede47d38d10 | 625 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 626 | } while(0) |
| phungductung | 0:8ede47d38d10 | 627 | |
| phungductung | 0:8ede47d38d10 | 628 | #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 629 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 630 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
| phungductung | 0:8ede47d38d10 | 631 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 632 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
| phungductung | 0:8ede47d38d10 | 633 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 634 | } while(0) |
| phungductung | 0:8ede47d38d10 | 635 | |
| phungductung | 0:8ede47d38d10 | 636 | #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) |
| phungductung | 0:8ede47d38d10 | 637 | #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) |
| phungductung | 0:8ede47d38d10 | 638 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) |
| phungductung | 0:8ede47d38d10 | 639 | #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) |
| phungductung | 0:8ede47d38d10 | 640 | #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
| phungductung | 0:8ede47d38d10 | 641 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
| phungductung | 0:8ede47d38d10 | 642 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) |
| phungductung | 0:8ede47d38d10 | 643 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) |
| phungductung | 0:8ede47d38d10 | 644 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) |
| phungductung | 0:8ede47d38d10 | 645 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) |
| phungductung | 0:8ede47d38d10 | 646 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) |
| phungductung | 0:8ede47d38d10 | 647 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
| phungductung | 0:8ede47d38d10 | 648 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
| phungductung | 0:8ede47d38d10 | 649 | #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) |
| phungductung | 0:8ede47d38d10 | 650 | #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
| phungductung | 0:8ede47d38d10 | 651 | #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) |
| phungductung | 0:8ede47d38d10 | 652 | #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) |
| phungductung | 0:8ede47d38d10 | 653 | /** |
| phungductung | 0:8ede47d38d10 | 654 | * @brief Enable ETHERNET clock. |
| phungductung | 0:8ede47d38d10 | 655 | */ |
| phungductung | 0:8ede47d38d10 | 656 | #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 657 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 658 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| phungductung | 0:8ede47d38d10 | 659 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 660 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| phungductung | 0:8ede47d38d10 | 661 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 662 | } while(0) |
| phungductung | 0:8ede47d38d10 | 663 | |
| phungductung | 0:8ede47d38d10 | 664 | #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 665 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 666 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| phungductung | 0:8ede47d38d10 | 667 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 668 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| phungductung | 0:8ede47d38d10 | 669 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 670 | } while(0) |
| phungductung | 0:8ede47d38d10 | 671 | |
| phungductung | 0:8ede47d38d10 | 672 | #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 673 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 674 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| phungductung | 0:8ede47d38d10 | 675 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 676 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| phungductung | 0:8ede47d38d10 | 677 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 678 | } while(0) |
| phungductung | 0:8ede47d38d10 | 679 | |
| phungductung | 0:8ede47d38d10 | 680 | #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 681 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 682 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| phungductung | 0:8ede47d38d10 | 683 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 684 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| phungductung | 0:8ede47d38d10 | 685 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 686 | } while(0) |
| phungductung | 0:8ede47d38d10 | 687 | |
| phungductung | 0:8ede47d38d10 | 688 | #define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 689 | __HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
| phungductung | 0:8ede47d38d10 | 690 | __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
| phungductung | 0:8ede47d38d10 | 691 | __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
| phungductung | 0:8ede47d38d10 | 692 | } while(0) |
| phungductung | 0:8ede47d38d10 | 693 | /** |
| phungductung | 0:8ede47d38d10 | 694 | * @brief Disable ETHERNET clock. |
| phungductung | 0:8ede47d38d10 | 695 | */ |
| phungductung | 0:8ede47d38d10 | 696 | #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
| phungductung | 0:8ede47d38d10 | 697 | #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
| phungductung | 0:8ede47d38d10 | 698 | #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
| phungductung | 0:8ede47d38d10 | 699 | #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
| phungductung | 0:8ede47d38d10 | 700 | #define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 701 | __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
| phungductung | 0:8ede47d38d10 | 702 | __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
| phungductung | 0:8ede47d38d10 | 703 | __HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
| phungductung | 0:8ede47d38d10 | 704 | } while(0) |
| phungductung | 0:8ede47d38d10 | 705 | |
| phungductung | 0:8ede47d38d10 | 706 | /** @brief Enable or disable the AHB2 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 707 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 708 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 709 | * using it. |
| phungductung | 0:8ede47d38d10 | 710 | */ |
| phungductung | 0:8ede47d38d10 | 711 | #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 712 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 713 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| phungductung | 0:8ede47d38d10 | 714 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 715 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| phungductung | 0:8ede47d38d10 | 716 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 717 | } while(0) |
| phungductung | 0:8ede47d38d10 | 718 | |
| phungductung | 0:8ede47d38d10 | 719 | #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 720 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 721 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| phungductung | 0:8ede47d38d10 | 722 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 723 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| phungductung | 0:8ede47d38d10 | 724 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 725 | } while(0) |
| phungductung | 0:8ede47d38d10 | 726 | |
| phungductung | 0:8ede47d38d10 | 727 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 728 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 729 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ |
| phungductung | 0:8ede47d38d10 | 730 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 731 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ |
| phungductung | 0:8ede47d38d10 | 732 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 733 | __HAL_RCC_SYSCFG_CLK_ENABLE();\ |
| phungductung | 0:8ede47d38d10 | 734 | } while(0) |
| phungductung | 0:8ede47d38d10 | 735 | |
| phungductung | 0:8ede47d38d10 | 736 | #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
| phungductung | 0:8ede47d38d10 | 737 | #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) |
| phungductung | 0:8ede47d38d10 | 738 | |
| phungductung | 0:8ede47d38d10 | 739 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) |
| phungductung | 0:8ede47d38d10 | 740 | #if defined(STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 741 | #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 742 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 743 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| phungductung | 0:8ede47d38d10 | 744 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 745 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| phungductung | 0:8ede47d38d10 | 746 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 747 | } while(0) |
| phungductung | 0:8ede47d38d10 | 748 | |
| phungductung | 0:8ede47d38d10 | 749 | #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 750 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 751 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| phungductung | 0:8ede47d38d10 | 752 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 753 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| phungductung | 0:8ede47d38d10 | 754 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 755 | } while(0) |
| phungductung | 0:8ede47d38d10 | 756 | |
| phungductung | 0:8ede47d38d10 | 757 | #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
| phungductung | 0:8ede47d38d10 | 758 | #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
| phungductung | 0:8ede47d38d10 | 759 | #endif /* STM32F756x */ |
| phungductung | 0:8ede47d38d10 | 760 | |
| phungductung | 0:8ede47d38d10 | 761 | /** @brief Enables or disables the AHB3 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 762 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 763 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 764 | * using it. |
| phungductung | 0:8ede47d38d10 | 765 | */ |
| phungductung | 0:8ede47d38d10 | 766 | #define __HAL_RCC_FMC_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 767 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 768 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
| phungductung | 0:8ede47d38d10 | 769 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 770 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
| phungductung | 0:8ede47d38d10 | 771 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 772 | } while(0) |
| phungductung | 0:8ede47d38d10 | 773 | |
| phungductung | 0:8ede47d38d10 | 774 | #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 775 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 776 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
| phungductung | 0:8ede47d38d10 | 777 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 778 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
| phungductung | 0:8ede47d38d10 | 779 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 780 | } while(0) |
| phungductung | 0:8ede47d38d10 | 781 | |
| phungductung | 0:8ede47d38d10 | 782 | #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) |
| phungductung | 0:8ede47d38d10 | 783 | #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) |
| phungductung | 0:8ede47d38d10 | 784 | |
| phungductung | 0:8ede47d38d10 | 785 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
| phungductung | 0:8ede47d38d10 | 786 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 787 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 788 | * using it. |
| phungductung | 0:8ede47d38d10 | 789 | */ |
| phungductung | 0:8ede47d38d10 | 790 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 791 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 792 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| phungductung | 0:8ede47d38d10 | 793 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 794 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| phungductung | 0:8ede47d38d10 | 795 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 796 | } while(0) |
| phungductung | 0:8ede47d38d10 | 797 | |
| phungductung | 0:8ede47d38d10 | 798 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 799 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 800 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| phungductung | 0:8ede47d38d10 | 801 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 802 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| phungductung | 0:8ede47d38d10 | 803 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 804 | } while(0) |
| phungductung | 0:8ede47d38d10 | 805 | |
| phungductung | 0:8ede47d38d10 | 806 | #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 807 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 808 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
| phungductung | 0:8ede47d38d10 | 809 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 810 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
| phungductung | 0:8ede47d38d10 | 811 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 812 | } while(0) |
| phungductung | 0:8ede47d38d10 | 813 | |
| phungductung | 0:8ede47d38d10 | 814 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 815 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 816 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
| phungductung | 0:8ede47d38d10 | 817 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 818 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
| phungductung | 0:8ede47d38d10 | 819 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 820 | } while(0) |
| phungductung | 0:8ede47d38d10 | 821 | |
| phungductung | 0:8ede47d38d10 | 822 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 823 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 824 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
| phungductung | 0:8ede47d38d10 | 825 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 826 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
| phungductung | 0:8ede47d38d10 | 827 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 828 | } while(0) |
| phungductung | 0:8ede47d38d10 | 829 | |
| phungductung | 0:8ede47d38d10 | 830 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 831 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 832 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
| phungductung | 0:8ede47d38d10 | 833 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 834 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
| phungductung | 0:8ede47d38d10 | 835 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 836 | } while(0) |
| phungductung | 0:8ede47d38d10 | 837 | |
| phungductung | 0:8ede47d38d10 | 838 | #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 839 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 840 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
| phungductung | 0:8ede47d38d10 | 841 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 842 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
| phungductung | 0:8ede47d38d10 | 843 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 844 | } while(0) |
| phungductung | 0:8ede47d38d10 | 845 | |
| phungductung | 0:8ede47d38d10 | 846 | #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 847 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 848 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
| phungductung | 0:8ede47d38d10 | 849 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 850 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
| phungductung | 0:8ede47d38d10 | 851 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 852 | } while(0) |
| phungductung | 0:8ede47d38d10 | 853 | |
| phungductung | 0:8ede47d38d10 | 854 | #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 855 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 856 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| phungductung | 0:8ede47d38d10 | 857 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 858 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
| phungductung | 0:8ede47d38d10 | 859 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 860 | } while(0) |
| phungductung | 0:8ede47d38d10 | 861 | |
| phungductung | 0:8ede47d38d10 | 862 | #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 863 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 864 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ |
| phungductung | 0:8ede47d38d10 | 865 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 866 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ |
| phungductung | 0:8ede47d38d10 | 867 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 868 | } while(0) |
| phungductung | 0:8ede47d38d10 | 869 | |
| phungductung | 0:8ede47d38d10 | 870 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 871 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 872 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
| phungductung | 0:8ede47d38d10 | 873 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 874 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
| phungductung | 0:8ede47d38d10 | 875 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 876 | } while(0) |
| phungductung | 0:8ede47d38d10 | 877 | |
| phungductung | 0:8ede47d38d10 | 878 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 879 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 880 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| phungductung | 0:8ede47d38d10 | 881 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 882 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| phungductung | 0:8ede47d38d10 | 883 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 884 | } while(0) |
| phungductung | 0:8ede47d38d10 | 885 | |
| phungductung | 0:8ede47d38d10 | 886 | #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 887 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 888 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ |
| phungductung | 0:8ede47d38d10 | 889 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 890 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ |
| phungductung | 0:8ede47d38d10 | 891 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 892 | } while(0) |
| phungductung | 0:8ede47d38d10 | 893 | |
| phungductung | 0:8ede47d38d10 | 894 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 895 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 896 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
| phungductung | 0:8ede47d38d10 | 897 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 898 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
| phungductung | 0:8ede47d38d10 | 899 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 900 | } while(0) |
| phungductung | 0:8ede47d38d10 | 901 | |
| phungductung | 0:8ede47d38d10 | 902 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 903 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 904 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
| phungductung | 0:8ede47d38d10 | 905 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 906 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
| phungductung | 0:8ede47d38d10 | 907 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 908 | } while(0) |
| phungductung | 0:8ede47d38d10 | 909 | |
| phungductung | 0:8ede47d38d10 | 910 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 911 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 912 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| phungductung | 0:8ede47d38d10 | 913 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 914 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| phungductung | 0:8ede47d38d10 | 915 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 916 | } while(0) |
| phungductung | 0:8ede47d38d10 | 917 | |
| phungductung | 0:8ede47d38d10 | 918 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 919 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 920 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| phungductung | 0:8ede47d38d10 | 921 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 922 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| phungductung | 0:8ede47d38d10 | 923 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 924 | } while(0) |
| phungductung | 0:8ede47d38d10 | 925 | |
| phungductung | 0:8ede47d38d10 | 926 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 927 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 928 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
| phungductung | 0:8ede47d38d10 | 929 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 930 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
| phungductung | 0:8ede47d38d10 | 931 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 932 | } while(0) |
| phungductung | 0:8ede47d38d10 | 933 | |
| phungductung | 0:8ede47d38d10 | 934 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 935 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 936 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
| phungductung | 0:8ede47d38d10 | 937 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 938 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
| phungductung | 0:8ede47d38d10 | 939 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 940 | } while(0) |
| phungductung | 0:8ede47d38d10 | 941 | |
| phungductung | 0:8ede47d38d10 | 942 | #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 943 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 944 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
| phungductung | 0:8ede47d38d10 | 945 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 946 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
| phungductung | 0:8ede47d38d10 | 947 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 948 | } while(0) |
| phungductung | 0:8ede47d38d10 | 949 | |
| phungductung | 0:8ede47d38d10 | 950 | #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 951 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 952 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ |
| phungductung | 0:8ede47d38d10 | 953 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 954 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ |
| phungductung | 0:8ede47d38d10 | 955 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 956 | } while(0) |
| phungductung | 0:8ede47d38d10 | 957 | |
| phungductung | 0:8ede47d38d10 | 958 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 959 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 960 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
| phungductung | 0:8ede47d38d10 | 961 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 962 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
| phungductung | 0:8ede47d38d10 | 963 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 964 | } while(0) |
| phungductung | 0:8ede47d38d10 | 965 | |
| phungductung | 0:8ede47d38d10 | 966 | #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 967 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 968 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
| phungductung | 0:8ede47d38d10 | 969 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 970 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
| phungductung | 0:8ede47d38d10 | 971 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 972 | } while(0) |
| phungductung | 0:8ede47d38d10 | 973 | |
| phungductung | 0:8ede47d38d10 | 974 | #define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 975 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 976 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
| phungductung | 0:8ede47d38d10 | 977 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 978 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
| phungductung | 0:8ede47d38d10 | 979 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 980 | } while(0) |
| phungductung | 0:8ede47d38d10 | 981 | |
| phungductung | 0:8ede47d38d10 | 982 | #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 983 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 984 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
| phungductung | 0:8ede47d38d10 | 985 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 986 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
| phungductung | 0:8ede47d38d10 | 987 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 988 | } while(0) |
| phungductung | 0:8ede47d38d10 | 989 | |
| phungductung | 0:8ede47d38d10 | 990 | #define __HAL_RCC_UART7_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 991 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 992 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
| phungductung | 0:8ede47d38d10 | 993 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 994 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
| phungductung | 0:8ede47d38d10 | 995 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 996 | } while(0) |
| phungductung | 0:8ede47d38d10 | 997 | |
| phungductung | 0:8ede47d38d10 | 998 | #define __HAL_RCC_UART8_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 999 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1000 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
| phungductung | 0:8ede47d38d10 | 1001 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1002 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
| phungductung | 0:8ede47d38d10 | 1003 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1004 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1005 | |
| phungductung | 0:8ede47d38d10 | 1006 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
| phungductung | 0:8ede47d38d10 | 1007 | #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
| phungductung | 0:8ede47d38d10 | 1008 | #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
| phungductung | 0:8ede47d38d10 | 1009 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
| phungductung | 0:8ede47d38d10 | 1010 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
| phungductung | 0:8ede47d38d10 | 1011 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
| phungductung | 0:8ede47d38d10 | 1012 | #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
| phungductung | 0:8ede47d38d10 | 1013 | #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
| phungductung | 0:8ede47d38d10 | 1014 | #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
| phungductung | 0:8ede47d38d10 | 1015 | #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) |
| phungductung | 0:8ede47d38d10 | 1016 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
| phungductung | 0:8ede47d38d10 | 1017 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
| phungductung | 0:8ede47d38d10 | 1018 | #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) |
| phungductung | 0:8ede47d38d10 | 1019 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
| phungductung | 0:8ede47d38d10 | 1020 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
| phungductung | 0:8ede47d38d10 | 1021 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| phungductung | 0:8ede47d38d10 | 1022 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
| phungductung | 0:8ede47d38d10 | 1023 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
| phungductung | 0:8ede47d38d10 | 1024 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
| phungductung | 0:8ede47d38d10 | 1025 | #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
| phungductung | 0:8ede47d38d10 | 1026 | #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) |
| phungductung | 0:8ede47d38d10 | 1027 | #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
| phungductung | 0:8ede47d38d10 | 1028 | #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
| phungductung | 0:8ede47d38d10 | 1029 | #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
| phungductung | 0:8ede47d38d10 | 1030 | #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
| phungductung | 0:8ede47d38d10 | 1031 | #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
| phungductung | 0:8ede47d38d10 | 1032 | #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
| phungductung | 0:8ede47d38d10 | 1033 | |
| phungductung | 0:8ede47d38d10 | 1034 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1035 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1036 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1037 | * using it. |
| phungductung | 0:8ede47d38d10 | 1038 | */ |
| phungductung | 0:8ede47d38d10 | 1039 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1040 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1041 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
| phungductung | 0:8ede47d38d10 | 1042 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1043 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
| phungductung | 0:8ede47d38d10 | 1044 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1045 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1046 | |
| phungductung | 0:8ede47d38d10 | 1047 | #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1048 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1049 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
| phungductung | 0:8ede47d38d10 | 1050 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1051 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
| phungductung | 0:8ede47d38d10 | 1052 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1053 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1054 | |
| phungductung | 0:8ede47d38d10 | 1055 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1056 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1057 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
| phungductung | 0:8ede47d38d10 | 1058 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1059 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
| phungductung | 0:8ede47d38d10 | 1060 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1061 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1062 | |
| phungductung | 0:8ede47d38d10 | 1063 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1064 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1065 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
| phungductung | 0:8ede47d38d10 | 1066 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1067 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
| phungductung | 0:8ede47d38d10 | 1068 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1069 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1070 | |
| phungductung | 0:8ede47d38d10 | 1071 | #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1072 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1073 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
| phungductung | 0:8ede47d38d10 | 1074 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1075 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
| phungductung | 0:8ede47d38d10 | 1076 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1077 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1078 | |
| phungductung | 0:8ede47d38d10 | 1079 | #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1080 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1081 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
| phungductung | 0:8ede47d38d10 | 1082 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1083 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
| phungductung | 0:8ede47d38d10 | 1084 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1085 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1086 | |
| phungductung | 0:8ede47d38d10 | 1087 | #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1088 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1089 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
| phungductung | 0:8ede47d38d10 | 1090 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1091 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
| phungductung | 0:8ede47d38d10 | 1092 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1093 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1094 | |
| phungductung | 0:8ede47d38d10 | 1095 | #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1096 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1097 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ |
| phungductung | 0:8ede47d38d10 | 1098 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1099 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ |
| phungductung | 0:8ede47d38d10 | 1100 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1101 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1102 | |
| phungductung | 0:8ede47d38d10 | 1103 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1104 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1105 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
| phungductung | 0:8ede47d38d10 | 1106 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1107 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
| phungductung | 0:8ede47d38d10 | 1108 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1109 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1110 | |
| phungductung | 0:8ede47d38d10 | 1111 | #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1112 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1113 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
| phungductung | 0:8ede47d38d10 | 1114 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1115 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
| phungductung | 0:8ede47d38d10 | 1116 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1117 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1118 | |
| phungductung | 0:8ede47d38d10 | 1119 | #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1120 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1121 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
| phungductung | 0:8ede47d38d10 | 1122 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1123 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
| phungductung | 0:8ede47d38d10 | 1124 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1125 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1126 | |
| phungductung | 0:8ede47d38d10 | 1127 | #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1128 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1129 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
| phungductung | 0:8ede47d38d10 | 1130 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1131 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
| phungductung | 0:8ede47d38d10 | 1132 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1133 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1134 | |
| phungductung | 0:8ede47d38d10 | 1135 | #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1136 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1137 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
| phungductung | 0:8ede47d38d10 | 1138 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1139 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
| phungductung | 0:8ede47d38d10 | 1140 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1141 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1142 | |
| phungductung | 0:8ede47d38d10 | 1143 | #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1144 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1145 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
| phungductung | 0:8ede47d38d10 | 1146 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1147 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
| phungductung | 0:8ede47d38d10 | 1148 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1149 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1150 | |
| phungductung | 0:8ede47d38d10 | 1151 | #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1152 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1153 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
| phungductung | 0:8ede47d38d10 | 1154 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1155 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
| phungductung | 0:8ede47d38d10 | 1156 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1157 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1158 | |
| phungductung | 0:8ede47d38d10 | 1159 | #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1160 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1161 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
| phungductung | 0:8ede47d38d10 | 1162 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1163 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
| phungductung | 0:8ede47d38d10 | 1164 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1165 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1166 | |
| phungductung | 0:8ede47d38d10 | 1167 | #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1168 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1169 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
| phungductung | 0:8ede47d38d10 | 1170 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1171 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
| phungductung | 0:8ede47d38d10 | 1172 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1173 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1174 | |
| phungductung | 0:8ede47d38d10 | 1175 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1176 | #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ |
| phungductung | 0:8ede47d38d10 | 1177 | __IO uint32_t tmpreg = 0x00; \ |
| phungductung | 0:8ede47d38d10 | 1178 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
| phungductung | 0:8ede47d38d10 | 1179 | /* Delay after an RCC peripheral clock enabling */ \ |
| phungductung | 0:8ede47d38d10 | 1180 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
| phungductung | 0:8ede47d38d10 | 1181 | UNUSED(tmpreg); \ |
| phungductung | 0:8ede47d38d10 | 1182 | } while(0) |
| phungductung | 0:8ede47d38d10 | 1183 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1184 | |
| phungductung | 0:8ede47d38d10 | 1185 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
| phungductung | 0:8ede47d38d10 | 1186 | #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
| phungductung | 0:8ede47d38d10 | 1187 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
| phungductung | 0:8ede47d38d10 | 1188 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
| phungductung | 0:8ede47d38d10 | 1189 | #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
| phungductung | 0:8ede47d38d10 | 1190 | #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
| phungductung | 0:8ede47d38d10 | 1191 | #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
| phungductung | 0:8ede47d38d10 | 1192 | #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) |
| phungductung | 0:8ede47d38d10 | 1193 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
| phungductung | 0:8ede47d38d10 | 1194 | #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
| phungductung | 0:8ede47d38d10 | 1195 | #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
| phungductung | 0:8ede47d38d10 | 1196 | #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
| phungductung | 0:8ede47d38d10 | 1197 | #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
| phungductung | 0:8ede47d38d10 | 1198 | #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
| phungductung | 0:8ede47d38d10 | 1199 | #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
| phungductung | 0:8ede47d38d10 | 1200 | #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
| phungductung | 0:8ede47d38d10 | 1201 | #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) |
| phungductung | 0:8ede47d38d10 | 1202 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1203 | #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
| phungductung | 0:8ede47d38d10 | 1204 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1205 | /** |
| phungductung | 0:8ede47d38d10 | 1206 | * @} |
| phungductung | 0:8ede47d38d10 | 1207 | */ |
| phungductung | 0:8ede47d38d10 | 1208 | |
| phungductung | 0:8ede47d38d10 | 1209 | |
| phungductung | 0:8ede47d38d10 | 1210 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status |
| phungductung | 0:8ede47d38d10 | 1211 | * @brief Get the enable or disable status of the AHB/APB peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1212 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1213 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1214 | * using it. |
| phungductung | 0:8ede47d38d10 | 1215 | * @{ |
| phungductung | 0:8ede47d38d10 | 1216 | */ |
| phungductung | 0:8ede47d38d10 | 1217 | |
| phungductung | 0:8ede47d38d10 | 1218 | /** @brief Get the enable or disable status of the AHB1 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1219 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1220 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1221 | * using it. |
| phungductung | 0:8ede47d38d10 | 1222 | */ |
| phungductung | 0:8ede47d38d10 | 1223 | #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1224 | #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1225 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1226 | #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1227 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1228 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1229 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1230 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1231 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1232 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1233 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1234 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1235 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1236 | #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1237 | #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1238 | #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1239 | #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1240 | |
| phungductung | 0:8ede47d38d10 | 1241 | #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1242 | #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1243 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1244 | #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1245 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1246 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1247 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1248 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1249 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1250 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1251 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1252 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1253 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1254 | #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1255 | #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1256 | #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1257 | #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1258 | /** |
| phungductung | 0:8ede47d38d10 | 1259 | * @brief Enable ETHERNET clock. |
| phungductung | 0:8ede47d38d10 | 1260 | */ |
| phungductung | 0:8ede47d38d10 | 1261 | #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1262 | #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1263 | #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1264 | #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1265 | #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ |
| phungductung | 0:8ede47d38d10 | 1266 | __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ |
| phungductung | 0:8ede47d38d10 | 1267 | __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) |
| phungductung | 0:8ede47d38d10 | 1268 | |
| phungductung | 0:8ede47d38d10 | 1269 | /** |
| phungductung | 0:8ede47d38d10 | 1270 | * @brief Disable ETHERNET clock. |
| phungductung | 0:8ede47d38d10 | 1271 | */ |
| phungductung | 0:8ede47d38d10 | 1272 | #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1273 | #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1274 | #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1275 | #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1276 | #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ |
| phungductung | 0:8ede47d38d10 | 1277 | __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ |
| phungductung | 0:8ede47d38d10 | 1278 | __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) |
| phungductung | 0:8ede47d38d10 | 1279 | |
| phungductung | 0:8ede47d38d10 | 1280 | /** @brief Get the enable or disable status of the AHB2 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1281 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1282 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1283 | * using it. |
| phungductung | 0:8ede47d38d10 | 1284 | */ |
| phungductung | 0:8ede47d38d10 | 1285 | #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1286 | #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1287 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1288 | |
| phungductung | 0:8ede47d38d10 | 1289 | #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1290 | #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1291 | #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1292 | |
| phungductung | 0:8ede47d38d10 | 1293 | #if defined(STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1294 | #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1295 | #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1296 | #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1297 | #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1298 | #endif /* STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1299 | |
| phungductung | 0:8ede47d38d10 | 1300 | /** @brief Get the enable or disable status of the AHB3 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1301 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1302 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1303 | * using it. |
| phungductung | 0:8ede47d38d10 | 1304 | */ |
| phungductung | 0:8ede47d38d10 | 1305 | #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1306 | #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1307 | |
| phungductung | 0:8ede47d38d10 | 1308 | #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1309 | #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1310 | |
| phungductung | 0:8ede47d38d10 | 1311 | /** @brief Get the enable or disable status of the APB1 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1312 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1313 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1314 | * using it. |
| phungductung | 0:8ede47d38d10 | 1315 | */ |
| phungductung | 0:8ede47d38d10 | 1316 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1317 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1318 | #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1319 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1320 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1321 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1322 | #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1323 | #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1324 | #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1325 | #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1326 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1327 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1328 | #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1329 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1330 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1331 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1332 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1333 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1334 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1335 | #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1336 | #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1337 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1338 | #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1339 | #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1340 | #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1341 | #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1342 | #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1343 | |
| phungductung | 0:8ede47d38d10 | 1344 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1345 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1346 | #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1347 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1348 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1349 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1350 | #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1351 | #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1352 | #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1353 | #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1354 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1355 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1356 | #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1357 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1358 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1359 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1360 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1361 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1362 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1363 | #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1364 | #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1365 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1366 | #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1367 | #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1368 | #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1369 | #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1370 | #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1371 | |
| phungductung | 0:8ede47d38d10 | 1372 | /** @brief Get the enable or disable status of the APB2 peripheral clock. |
| phungductung | 0:8ede47d38d10 | 1373 | * @note After reset, the peripheral clock (used for registers read/write access) |
| phungductung | 0:8ede47d38d10 | 1374 | * is disabled and the application software has to enable this clock before |
| phungductung | 0:8ede47d38d10 | 1375 | * using it. |
| phungductung | 0:8ede47d38d10 | 1376 | */ |
| phungductung | 0:8ede47d38d10 | 1377 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1378 | #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1379 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1380 | #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1381 | #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1382 | #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1383 | #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1384 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1385 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1386 | #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1387 | #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1388 | #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1389 | #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1390 | #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1391 | #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1392 | #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1393 | #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1394 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1395 | #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1396 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1397 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1398 | #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1399 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1400 | #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1401 | #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1402 | #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1403 | #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1404 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1405 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1406 | #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1407 | #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1408 | #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1409 | #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1410 | #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1411 | #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1412 | #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1413 | #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1414 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1415 | #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1416 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1417 | /** |
| phungductung | 0:8ede47d38d10 | 1418 | * @} |
| phungductung | 0:8ede47d38d10 | 1419 | */ |
| phungductung | 0:8ede47d38d10 | 1420 | |
| phungductung | 0:8ede47d38d10 | 1421 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
| phungductung | 0:8ede47d38d10 | 1422 | * @brief Forces or releases AHB/APB peripheral reset. |
| phungductung | 0:8ede47d38d10 | 1423 | * @{ |
| phungductung | 0:8ede47d38d10 | 1424 | */ |
| phungductung | 0:8ede47d38d10 | 1425 | |
| phungductung | 0:8ede47d38d10 | 1426 | /** @brief Force or release AHB1 peripheral reset. |
| phungductung | 0:8ede47d38d10 | 1427 | */ |
| phungductung | 0:8ede47d38d10 | 1428 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) |
| phungductung | 0:8ede47d38d10 | 1429 | #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) |
| phungductung | 0:8ede47d38d10 | 1430 | #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
| phungductung | 0:8ede47d38d10 | 1431 | #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
| phungductung | 0:8ede47d38d10 | 1432 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) |
| phungductung | 0:8ede47d38d10 | 1433 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) |
| phungductung | 0:8ede47d38d10 | 1434 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) |
| phungductung | 0:8ede47d38d10 | 1435 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) |
| phungductung | 0:8ede47d38d10 | 1436 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) |
| phungductung | 0:8ede47d38d10 | 1437 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
| phungductung | 0:8ede47d38d10 | 1438 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
| phungductung | 0:8ede47d38d10 | 1439 | #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) |
| phungductung | 0:8ede47d38d10 | 1440 | #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
| phungductung | 0:8ede47d38d10 | 1441 | #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) |
| phungductung | 0:8ede47d38d10 | 1442 | #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) |
| phungductung | 0:8ede47d38d10 | 1443 | |
| phungductung | 0:8ede47d38d10 | 1444 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) |
| phungductung | 0:8ede47d38d10 | 1445 | #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) |
| phungductung | 0:8ede47d38d10 | 1446 | #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
| phungductung | 0:8ede47d38d10 | 1447 | #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
| phungductung | 0:8ede47d38d10 | 1448 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) |
| phungductung | 0:8ede47d38d10 | 1449 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) |
| phungductung | 0:8ede47d38d10 | 1450 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) |
| phungductung | 0:8ede47d38d10 | 1451 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) |
| phungductung | 0:8ede47d38d10 | 1452 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) |
| phungductung | 0:8ede47d38d10 | 1453 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
| phungductung | 0:8ede47d38d10 | 1454 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
| phungductung | 0:8ede47d38d10 | 1455 | #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) |
| phungductung | 0:8ede47d38d10 | 1456 | #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
| phungductung | 0:8ede47d38d10 | 1457 | #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) |
| phungductung | 0:8ede47d38d10 | 1458 | #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) |
| phungductung | 0:8ede47d38d10 | 1459 | |
| phungductung | 0:8ede47d38d10 | 1460 | /** @brief Force or release AHB2 peripheral reset. |
| phungductung | 0:8ede47d38d10 | 1461 | */ |
| phungductung | 0:8ede47d38d10 | 1462 | #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) |
| phungductung | 0:8ede47d38d10 | 1463 | #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
| phungductung | 0:8ede47d38d10 | 1464 | #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) |
| phungductung | 0:8ede47d38d10 | 1465 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) |
| phungductung | 0:8ede47d38d10 | 1466 | |
| phungductung | 0:8ede47d38d10 | 1467 | #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) |
| phungductung | 0:8ede47d38d10 | 1468 | #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
| phungductung | 0:8ede47d38d10 | 1469 | #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) |
| phungductung | 0:8ede47d38d10 | 1470 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) |
| phungductung | 0:8ede47d38d10 | 1471 | |
| phungductung | 0:8ede47d38d10 | 1472 | #if defined(STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1473 | #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
| phungductung | 0:8ede47d38d10 | 1474 | #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
| phungductung | 0:8ede47d38d10 | 1475 | #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
| phungductung | 0:8ede47d38d10 | 1476 | #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
| phungductung | 0:8ede47d38d10 | 1477 | #endif /* STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1478 | |
| phungductung | 0:8ede47d38d10 | 1479 | /** @brief Force or release AHB3 peripheral reset |
| phungductung | 0:8ede47d38d10 | 1480 | */ |
| phungductung | 0:8ede47d38d10 | 1481 | #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) |
| phungductung | 0:8ede47d38d10 | 1482 | #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) |
| phungductung | 0:8ede47d38d10 | 1483 | #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) |
| phungductung | 0:8ede47d38d10 | 1484 | |
| phungductung | 0:8ede47d38d10 | 1485 | #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) |
| phungductung | 0:8ede47d38d10 | 1486 | #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) |
| phungductung | 0:8ede47d38d10 | 1487 | #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) |
| phungductung | 0:8ede47d38d10 | 1488 | |
| phungductung | 0:8ede47d38d10 | 1489 | /** @brief Force or release APB1 peripheral reset. |
| phungductung | 0:8ede47d38d10 | 1490 | */ |
| phungductung | 0:8ede47d38d10 | 1491 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
| phungductung | 0:8ede47d38d10 | 1492 | #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
| phungductung | 0:8ede47d38d10 | 1493 | #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
| phungductung | 0:8ede47d38d10 | 1494 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
| phungductung | 0:8ede47d38d10 | 1495 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
| phungductung | 0:8ede47d38d10 | 1496 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
| phungductung | 0:8ede47d38d10 | 1497 | #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
| phungductung | 0:8ede47d38d10 | 1498 | #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
| phungductung | 0:8ede47d38d10 | 1499 | #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
| phungductung | 0:8ede47d38d10 | 1500 | #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) |
| phungductung | 0:8ede47d38d10 | 1501 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
| phungductung | 0:8ede47d38d10 | 1502 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
| phungductung | 0:8ede47d38d10 | 1503 | #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) |
| phungductung | 0:8ede47d38d10 | 1504 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
| phungductung | 0:8ede47d38d10 | 1505 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
| phungductung | 0:8ede47d38d10 | 1506 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
| phungductung | 0:8ede47d38d10 | 1507 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
| phungductung | 0:8ede47d38d10 | 1508 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
| phungductung | 0:8ede47d38d10 | 1509 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
| phungductung | 0:8ede47d38d10 | 1510 | #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
| phungductung | 0:8ede47d38d10 | 1511 | #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) |
| phungductung | 0:8ede47d38d10 | 1512 | #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
| phungductung | 0:8ede47d38d10 | 1513 | #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
| phungductung | 0:8ede47d38d10 | 1514 | #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
| phungductung | 0:8ede47d38d10 | 1515 | #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
| phungductung | 0:8ede47d38d10 | 1516 | #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) |
| phungductung | 0:8ede47d38d10 | 1517 | #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) |
| phungductung | 0:8ede47d38d10 | 1518 | |
| phungductung | 0:8ede47d38d10 | 1519 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
| phungductung | 0:8ede47d38d10 | 1520 | #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
| phungductung | 0:8ede47d38d10 | 1521 | #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
| phungductung | 0:8ede47d38d10 | 1522 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
| phungductung | 0:8ede47d38d10 | 1523 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
| phungductung | 0:8ede47d38d10 | 1524 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
| phungductung | 0:8ede47d38d10 | 1525 | #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
| phungductung | 0:8ede47d38d10 | 1526 | #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
| phungductung | 0:8ede47d38d10 | 1527 | #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
| phungductung | 0:8ede47d38d10 | 1528 | #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) |
| phungductung | 0:8ede47d38d10 | 1529 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
| phungductung | 0:8ede47d38d10 | 1530 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
| phungductung | 0:8ede47d38d10 | 1531 | #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) |
| phungductung | 0:8ede47d38d10 | 1532 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
| phungductung | 0:8ede47d38d10 | 1533 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
| phungductung | 0:8ede47d38d10 | 1534 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
| phungductung | 0:8ede47d38d10 | 1535 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
| phungductung | 0:8ede47d38d10 | 1536 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
| phungductung | 0:8ede47d38d10 | 1537 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
| phungductung | 0:8ede47d38d10 | 1538 | #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
| phungductung | 0:8ede47d38d10 | 1539 | #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) |
| phungductung | 0:8ede47d38d10 | 1540 | #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
| phungductung | 0:8ede47d38d10 | 1541 | #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
| phungductung | 0:8ede47d38d10 | 1542 | #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
| phungductung | 0:8ede47d38d10 | 1543 | #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
| phungductung | 0:8ede47d38d10 | 1544 | #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) |
| phungductung | 0:8ede47d38d10 | 1545 | #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) |
| phungductung | 0:8ede47d38d10 | 1546 | |
| phungductung | 0:8ede47d38d10 | 1547 | /** @brief Force or release APB2 peripheral reset. |
| phungductung | 0:8ede47d38d10 | 1548 | */ |
| phungductung | 0:8ede47d38d10 | 1549 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
| phungductung | 0:8ede47d38d10 | 1550 | #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
| phungductung | 0:8ede47d38d10 | 1551 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
| phungductung | 0:8ede47d38d10 | 1552 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) |
| phungductung | 0:8ede47d38d10 | 1553 | #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) |
| phungductung | 0:8ede47d38d10 | 1554 | #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) |
| phungductung | 0:8ede47d38d10 | 1555 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
| phungductung | 0:8ede47d38d10 | 1556 | #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) |
| phungductung | 0:8ede47d38d10 | 1557 | #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) |
| phungductung | 0:8ede47d38d10 | 1558 | #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) |
| phungductung | 0:8ede47d38d10 | 1559 | #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) |
| phungductung | 0:8ede47d38d10 | 1560 | #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) |
| phungductung | 0:8ede47d38d10 | 1561 | #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) |
| phungductung | 0:8ede47d38d10 | 1562 | #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) |
| phungductung | 0:8ede47d38d10 | 1563 | #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) |
| phungductung | 0:8ede47d38d10 | 1564 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1565 | #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) |
| phungductung | 0:8ede47d38d10 | 1566 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1567 | |
| phungductung | 0:8ede47d38d10 | 1568 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
| phungductung | 0:8ede47d38d10 | 1569 | #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
| phungductung | 0:8ede47d38d10 | 1570 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
| phungductung | 0:8ede47d38d10 | 1571 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) |
| phungductung | 0:8ede47d38d10 | 1572 | #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) |
| phungductung | 0:8ede47d38d10 | 1573 | #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) |
| phungductung | 0:8ede47d38d10 | 1574 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
| phungductung | 0:8ede47d38d10 | 1575 | #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) |
| phungductung | 0:8ede47d38d10 | 1576 | #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) |
| phungductung | 0:8ede47d38d10 | 1577 | #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) |
| phungductung | 0:8ede47d38d10 | 1578 | #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) |
| phungductung | 0:8ede47d38d10 | 1579 | #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) |
| phungductung | 0:8ede47d38d10 | 1580 | #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) |
| phungductung | 0:8ede47d38d10 | 1581 | #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) |
| phungductung | 0:8ede47d38d10 | 1582 | #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) |
| phungductung | 0:8ede47d38d10 | 1583 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1584 | #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) |
| phungductung | 0:8ede47d38d10 | 1585 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1586 | |
| phungductung | 0:8ede47d38d10 | 1587 | /** |
| phungductung | 0:8ede47d38d10 | 1588 | * @} |
| phungductung | 0:8ede47d38d10 | 1589 | */ |
| phungductung | 0:8ede47d38d10 | 1590 | |
| phungductung | 0:8ede47d38d10 | 1591 | /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable |
| phungductung | 0:8ede47d38d10 | 1592 | * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1593 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1594 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1595 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1596 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1597 | * @{ |
| phungductung | 0:8ede47d38d10 | 1598 | */ |
| phungductung | 0:8ede47d38d10 | 1599 | |
| phungductung | 0:8ede47d38d10 | 1600 | /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1601 | */ |
| phungductung | 0:8ede47d38d10 | 1602 | #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) |
| phungductung | 0:8ede47d38d10 | 1603 | #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) |
| phungductung | 0:8ede47d38d10 | 1604 | #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1605 | #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1606 | #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) |
| phungductung | 0:8ede47d38d10 | 1607 | #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) |
| phungductung | 0:8ede47d38d10 | 1608 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1609 | #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) |
| phungductung | 0:8ede47d38d10 | 1610 | #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
| phungductung | 0:8ede47d38d10 | 1611 | #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
| phungductung | 0:8ede47d38d10 | 1612 | #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
| phungductung | 0:8ede47d38d10 | 1613 | #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| phungductung | 0:8ede47d38d10 | 1614 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
| phungductung | 0:8ede47d38d10 | 1615 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
| phungductung | 0:8ede47d38d10 | 1616 | #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) |
| phungductung | 0:8ede47d38d10 | 1617 | #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) |
| phungductung | 0:8ede47d38d10 | 1618 | #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) |
| phungductung | 0:8ede47d38d10 | 1619 | #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) |
| phungductung | 0:8ede47d38d10 | 1620 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) |
| phungductung | 0:8ede47d38d10 | 1621 | #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
| phungductung | 0:8ede47d38d10 | 1622 | #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
| phungductung | 0:8ede47d38d10 | 1623 | #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) |
| phungductung | 0:8ede47d38d10 | 1624 | #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
| phungductung | 0:8ede47d38d10 | 1625 | #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) |
| phungductung | 0:8ede47d38d10 | 1626 | #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) |
| phungductung | 0:8ede47d38d10 | 1627 | |
| phungductung | 0:8ede47d38d10 | 1628 | #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) |
| phungductung | 0:8ede47d38d10 | 1629 | #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) |
| phungductung | 0:8ede47d38d10 | 1630 | #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1631 | #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1632 | #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) |
| phungductung | 0:8ede47d38d10 | 1633 | #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) |
| phungductung | 0:8ede47d38d10 | 1634 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1635 | #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) |
| phungductung | 0:8ede47d38d10 | 1636 | #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
| phungductung | 0:8ede47d38d10 | 1637 | #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
| phungductung | 0:8ede47d38d10 | 1638 | #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
| phungductung | 0:8ede47d38d10 | 1639 | #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| phungductung | 0:8ede47d38d10 | 1640 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
| phungductung | 0:8ede47d38d10 | 1641 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
| phungductung | 0:8ede47d38d10 | 1642 | #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) |
| phungductung | 0:8ede47d38d10 | 1643 | #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) |
| phungductung | 0:8ede47d38d10 | 1644 | #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) |
| phungductung | 0:8ede47d38d10 | 1645 | #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) |
| phungductung | 0:8ede47d38d10 | 1646 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) |
| phungductung | 0:8ede47d38d10 | 1647 | #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
| phungductung | 0:8ede47d38d10 | 1648 | #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
| phungductung | 0:8ede47d38d10 | 1649 | #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) |
| phungductung | 0:8ede47d38d10 | 1650 | #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
| phungductung | 0:8ede47d38d10 | 1651 | #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) |
| phungductung | 0:8ede47d38d10 | 1652 | #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) |
| phungductung | 0:8ede47d38d10 | 1653 | |
| phungductung | 0:8ede47d38d10 | 1654 | /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1655 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1656 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1657 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1658 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1659 | */ |
| phungductung | 0:8ede47d38d10 | 1660 | #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
| phungductung | 0:8ede47d38d10 | 1661 | #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
| phungductung | 0:8ede47d38d10 | 1662 | |
| phungductung | 0:8ede47d38d10 | 1663 | #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) |
| phungductung | 0:8ede47d38d10 | 1664 | #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) |
| phungductung | 0:8ede47d38d10 | 1665 | |
| phungductung | 0:8ede47d38d10 | 1666 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) |
| phungductung | 0:8ede47d38d10 | 1667 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) |
| phungductung | 0:8ede47d38d10 | 1668 | |
| phungductung | 0:8ede47d38d10 | 1669 | #if defined(STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1670 | #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
| phungductung | 0:8ede47d38d10 | 1671 | #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
| phungductung | 0:8ede47d38d10 | 1672 | |
| phungductung | 0:8ede47d38d10 | 1673 | #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
| phungductung | 0:8ede47d38d10 | 1674 | #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
| phungductung | 0:8ede47d38d10 | 1675 | #endif /* STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1676 | |
| phungductung | 0:8ede47d38d10 | 1677 | /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1678 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1679 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1680 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1681 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1682 | */ |
| phungductung | 0:8ede47d38d10 | 1683 | #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) |
| phungductung | 0:8ede47d38d10 | 1684 | #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) |
| phungductung | 0:8ede47d38d10 | 1685 | |
| phungductung | 0:8ede47d38d10 | 1686 | #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) |
| phungductung | 0:8ede47d38d10 | 1687 | #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) |
| phungductung | 0:8ede47d38d10 | 1688 | |
| phungductung | 0:8ede47d38d10 | 1689 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1690 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1691 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1692 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1693 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1694 | */ |
| phungductung | 0:8ede47d38d10 | 1695 | #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1696 | #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1697 | #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1698 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) |
| phungductung | 0:8ede47d38d10 | 1699 | #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
| phungductung | 0:8ede47d38d10 | 1700 | #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
| phungductung | 0:8ede47d38d10 | 1701 | #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
| phungductung | 0:8ede47d38d10 | 1702 | #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
| phungductung | 0:8ede47d38d10 | 1703 | #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
| phungductung | 0:8ede47d38d10 | 1704 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1705 | #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1706 | #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1707 | #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) |
| phungductung | 0:8ede47d38d10 | 1708 | #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1709 | #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1710 | #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1711 | #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
| phungductung | 0:8ede47d38d10 | 1712 | #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1713 | #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1714 | #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1715 | #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1716 | #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1717 | #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1718 | #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) |
| phungductung | 0:8ede47d38d10 | 1719 | #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
| phungductung | 0:8ede47d38d10 | 1720 | #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) |
| phungductung | 0:8ede47d38d10 | 1721 | #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) |
| phungductung | 0:8ede47d38d10 | 1722 | |
| phungductung | 0:8ede47d38d10 | 1723 | #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1724 | #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1725 | #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1726 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) |
| phungductung | 0:8ede47d38d10 | 1727 | #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
| phungductung | 0:8ede47d38d10 | 1728 | #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
| phungductung | 0:8ede47d38d10 | 1729 | #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
| phungductung | 0:8ede47d38d10 | 1730 | #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
| phungductung | 0:8ede47d38d10 | 1731 | #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
| phungductung | 0:8ede47d38d10 | 1732 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1733 | #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1734 | #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1735 | #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) |
| phungductung | 0:8ede47d38d10 | 1736 | #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1737 | #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1738 | #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1739 | #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
| phungductung | 0:8ede47d38d10 | 1740 | #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1741 | #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1742 | #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1743 | #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1744 | #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1745 | #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1746 | #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) |
| phungductung | 0:8ede47d38d10 | 1747 | #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
| phungductung | 0:8ede47d38d10 | 1748 | #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) |
| phungductung | 0:8ede47d38d10 | 1749 | #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) |
| phungductung | 0:8ede47d38d10 | 1750 | |
| phungductung | 0:8ede47d38d10 | 1751 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1752 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1753 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1754 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1755 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1756 | */ |
| phungductung | 0:8ede47d38d10 | 1757 | #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1758 | #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
| phungductung | 0:8ede47d38d10 | 1759 | #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1760 | #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) |
| phungductung | 0:8ede47d38d10 | 1761 | #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1762 | #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1763 | #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1764 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1765 | #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1766 | #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1767 | #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) |
| phungductung | 0:8ede47d38d10 | 1768 | #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) |
| phungductung | 0:8ede47d38d10 | 1769 | #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) |
| phungductung | 0:8ede47d38d10 | 1770 | #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) |
| phungductung | 0:8ede47d38d10 | 1771 | #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) |
| phungductung | 0:8ede47d38d10 | 1772 | #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1773 | #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1774 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1775 | #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) |
| phungductung | 0:8ede47d38d10 | 1776 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1777 | |
| phungductung | 0:8ede47d38d10 | 1778 | #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1779 | #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
| phungductung | 0:8ede47d38d10 | 1780 | #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1781 | #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) |
| phungductung | 0:8ede47d38d10 | 1782 | #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1783 | #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1784 | #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
| phungductung | 0:8ede47d38d10 | 1785 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1786 | #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1787 | #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) |
| phungductung | 0:8ede47d38d10 | 1788 | #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) |
| phungductung | 0:8ede47d38d10 | 1789 | #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) |
| phungductung | 0:8ede47d38d10 | 1790 | #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) |
| phungductung | 0:8ede47d38d10 | 1791 | #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) |
| phungductung | 0:8ede47d38d10 | 1792 | #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) |
| phungductung | 0:8ede47d38d10 | 1793 | #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) |
| phungductung | 0:8ede47d38d10 | 1794 | #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) |
| phungductung | 0:8ede47d38d10 | 1795 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1796 | #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) |
| phungductung | 0:8ede47d38d10 | 1797 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1798 | |
| phungductung | 0:8ede47d38d10 | 1799 | /** |
| phungductung | 0:8ede47d38d10 | 1800 | * @} |
| phungductung | 0:8ede47d38d10 | 1801 | */ |
| phungductung | 0:8ede47d38d10 | 1802 | |
| phungductung | 0:8ede47d38d10 | 1803 | /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status |
| phungductung | 0:8ede47d38d10 | 1804 | * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1805 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1806 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1807 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1808 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1809 | * @{ |
| phungductung | 0:8ede47d38d10 | 1810 | */ |
| phungductung | 0:8ede47d38d10 | 1811 | |
| phungductung | 0:8ede47d38d10 | 1812 | /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1813 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1814 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1815 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1816 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1817 | */ |
| phungductung | 0:8ede47d38d10 | 1818 | #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1819 | #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1820 | #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1821 | #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1822 | #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1823 | #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1824 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1825 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1826 | #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1827 | #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1828 | #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1829 | #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1830 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1831 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1832 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1833 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1834 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1835 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1836 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1837 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1838 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1839 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1840 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1841 | #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1842 | #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1843 | |
| phungductung | 0:8ede47d38d10 | 1844 | #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1845 | #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1846 | #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1847 | #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1848 | #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1849 | #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1850 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1851 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1852 | #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1853 | #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1854 | #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1855 | #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1856 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1857 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1858 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1859 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1860 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1861 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1862 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1863 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1864 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1865 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1866 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1867 | #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1868 | #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1869 | |
| phungductung | 0:8ede47d38d10 | 1870 | /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1871 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1872 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1873 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1874 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1875 | */ |
| phungductung | 0:8ede47d38d10 | 1876 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1877 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1878 | |
| phungductung | 0:8ede47d38d10 | 1879 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1880 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1881 | |
| phungductung | 0:8ede47d38d10 | 1882 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1883 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1884 | |
| phungductung | 0:8ede47d38d10 | 1885 | #if defined(STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1886 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1887 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1888 | |
| phungductung | 0:8ede47d38d10 | 1889 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1890 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1891 | #endif /* STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1892 | |
| phungductung | 0:8ede47d38d10 | 1893 | /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1894 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1895 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1896 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1897 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1898 | */ |
| phungductung | 0:8ede47d38d10 | 1899 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1900 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1901 | |
| phungductung | 0:8ede47d38d10 | 1902 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1903 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1904 | |
| phungductung | 0:8ede47d38d10 | 1905 | /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1906 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1907 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1908 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1909 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1910 | */ |
| phungductung | 0:8ede47d38d10 | 1911 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1912 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1913 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1914 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1915 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1916 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1917 | #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1918 | #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1919 | #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1920 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1921 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1922 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1923 | #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1924 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1925 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1926 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1927 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1928 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1929 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1930 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1931 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1932 | #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1933 | #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1934 | #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1935 | #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1936 | #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1937 | #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1938 | |
| phungductung | 0:8ede47d38d10 | 1939 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1940 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1941 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1942 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1943 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1944 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1945 | #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1946 | #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1947 | #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1948 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1949 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1950 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1951 | #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1952 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1953 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1954 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1955 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1956 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1957 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1958 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1959 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1960 | #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1961 | #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1962 | #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1963 | #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1964 | #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1965 | #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1966 | |
| phungductung | 0:8ede47d38d10 | 1967 | /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. |
| phungductung | 0:8ede47d38d10 | 1968 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| phungductung | 0:8ede47d38d10 | 1969 | * power consumption. |
| phungductung | 0:8ede47d38d10 | 1970 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| phungductung | 0:8ede47d38d10 | 1971 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| phungductung | 0:8ede47d38d10 | 1972 | */ |
| phungductung | 0:8ede47d38d10 | 1973 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1974 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1975 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1976 | #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1977 | #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1978 | #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1979 | #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1980 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1981 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1982 | #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1983 | #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1984 | #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1985 | #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1986 | #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1987 | #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1988 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1989 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1990 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 1991 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) |
| phungductung | 0:8ede47d38d10 | 1992 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 1993 | |
| phungductung | 0:8ede47d38d10 | 1994 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1995 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1996 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1997 | #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1998 | #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 1999 | #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2000 | #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2001 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2002 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2003 | #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2004 | #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2005 | #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2006 | #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2007 | #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2008 | #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2009 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2010 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2011 | #if defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 2012 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) |
| phungductung | 0:8ede47d38d10 | 2013 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 2014 | |
| phungductung | 0:8ede47d38d10 | 2015 | /** |
| phungductung | 0:8ede47d38d10 | 2016 | * @} |
| phungductung | 0:8ede47d38d10 | 2017 | */ |
| phungductung | 0:8ede47d38d10 | 2018 | |
| phungductung | 0:8ede47d38d10 | 2019 | /*---------------------------------------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 2020 | |
| phungductung | 0:8ede47d38d10 | 2021 | /** @brief Macro to configure the Timers clocks prescalers |
| phungductung | 0:8ede47d38d10 | 2022 | * @param __PRESC__ : specifies the Timers clocks prescalers selection |
| phungductung | 0:8ede47d38d10 | 2023 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2024 | * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is |
| phungductung | 0:8ede47d38d10 | 2025 | * equal to HPRE if PPREx is corresponding to division by 1 or 2, |
| phungductung | 0:8ede47d38d10 | 2026 | * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to |
| phungductung | 0:8ede47d38d10 | 2027 | * division by 4 or more. |
| phungductung | 0:8ede47d38d10 | 2028 | * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is |
| phungductung | 0:8ede47d38d10 | 2029 | * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, |
| phungductung | 0:8ede47d38d10 | 2030 | * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding |
| phungductung | 0:8ede47d38d10 | 2031 | * to division by 8 or more. |
| phungductung | 0:8ede47d38d10 | 2032 | */ |
| phungductung | 0:8ede47d38d10 | 2033 | #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ |
| phungductung | 0:8ede47d38d10 | 2034 | RCC->DCKCFGR1 |= (__PRESC__); \ |
| phungductung | 0:8ede47d38d10 | 2035 | }while(0) |
| phungductung | 0:8ede47d38d10 | 2036 | |
| phungductung | 0:8ede47d38d10 | 2037 | /** @brief Macros to Enable or Disable the PLLISAI. |
| phungductung | 0:8ede47d38d10 | 2038 | * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. |
| phungductung | 0:8ede47d38d10 | 2039 | */ |
| phungductung | 0:8ede47d38d10 | 2040 | #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) |
| phungductung | 0:8ede47d38d10 | 2041 | #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) |
| phungductung | 0:8ede47d38d10 | 2042 | |
| phungductung | 0:8ede47d38d10 | 2043 | /** @brief Macro to configure the PLLSAI clock multiplication and division factors. |
| phungductung | 0:8ede47d38d10 | 2044 | * @note This function must be used only when the PLLSAI is disabled. |
| phungductung | 0:8ede47d38d10 | 2045 | * @note PLLSAI clock source is common with the main PLL (configured in |
| phungductung | 0:8ede47d38d10 | 2046 | * RCC_PLLConfig function ) |
| phungductung | 0:8ede47d38d10 | 2047 | * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. |
| phungductung | 0:8ede47d38d10 | 2048 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
| phungductung | 0:8ede47d38d10 | 2049 | * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO |
| phungductung | 0:8ede47d38d10 | 2050 | * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
| phungductung | 0:8ede47d38d10 | 2051 | * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks |
| phungductung | 0:8ede47d38d10 | 2052 | * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. |
| phungductung | 0:8ede47d38d10 | 2053 | * @param __PLLSAIQ__: specifies the division factor for SAI clock |
| phungductung | 0:8ede47d38d10 | 2054 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| phungductung | 0:8ede47d38d10 | 2055 | * @param __PLLSAIR__: specifies the division factor for LTDC clock |
| phungductung | 0:8ede47d38d10 | 2056 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| phungductung | 0:8ede47d38d10 | 2057 | */ |
| phungductung | 0:8ede47d38d10 | 2058 | #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ |
| phungductung | 0:8ede47d38d10 | 2059 | (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ |
| phungductung | 0:8ede47d38d10 | 2060 | ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ |
| phungductung | 0:8ede47d38d10 | 2061 | ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ |
| phungductung | 0:8ede47d38d10 | 2062 | ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))) |
| phungductung | 0:8ede47d38d10 | 2063 | |
| phungductung | 0:8ede47d38d10 | 2064 | /** @brief Macro to configure the PLLI2S clock multiplication and division factors. |
| phungductung | 0:8ede47d38d10 | 2065 | * @note This macro must be used only when the PLLI2S is disabled. |
| phungductung | 0:8ede47d38d10 | 2066 | * @note PLLI2S clock source is common with the main PLL (configured in |
| phungductung | 0:8ede47d38d10 | 2067 | * HAL_RCC_ClockConfig() API) |
| phungductung | 0:8ede47d38d10 | 2068 | * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. |
| phungductung | 0:8ede47d38d10 | 2069 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
| phungductung | 0:8ede47d38d10 | 2070 | * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
| phungductung | 0:8ede47d38d10 | 2071 | * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
| phungductung | 0:8ede47d38d10 | 2072 | * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. |
| phungductung | 0:8ede47d38d10 | 2073 | * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. |
| phungductung | 0:8ede47d38d10 | 2074 | * @param __PLLI2SQ__: specifies the division factor for SAI clock. |
| phungductung | 0:8ede47d38d10 | 2075 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
| phungductung | 0:8ede47d38d10 | 2076 | * @param __PLLI2SR__: specifies the division factor for I2S clock |
| phungductung | 0:8ede47d38d10 | 2077 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| phungductung | 0:8ede47d38d10 | 2078 | * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
| phungductung | 0:8ede47d38d10 | 2079 | * on the I2S clock frequency. |
| phungductung | 0:8ede47d38d10 | 2080 | */ |
| phungductung | 0:8ede47d38d10 | 2081 | #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ |
| phungductung | 0:8ede47d38d10 | 2082 | (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ |
| phungductung | 0:8ede47d38d10 | 2083 | ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ |
| phungductung | 0:8ede47d38d10 | 2084 | ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ |
| phungductung | 0:8ede47d38d10 | 2085 | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) |
| phungductung | 0:8ede47d38d10 | 2086 | |
| phungductung | 0:8ede47d38d10 | 2087 | /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. |
| phungductung | 0:8ede47d38d10 | 2088 | * @note This function must be called before enabling the PLLI2S. |
| phungductung | 0:8ede47d38d10 | 2089 | * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock . |
| phungductung | 0:8ede47d38d10 | 2090 | * This parameter must be a number between 1 and 32. |
| phungductung | 0:8ede47d38d10 | 2091 | * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ |
| phungductung | 0:8ede47d38d10 | 2092 | */ |
| phungductung | 0:8ede47d38d10 | 2093 | #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) |
| phungductung | 0:8ede47d38d10 | 2094 | |
| phungductung | 0:8ede47d38d10 | 2095 | /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. |
| phungductung | 0:8ede47d38d10 | 2096 | * @note This function must be called before enabling the PLLSAI. |
| phungductung | 0:8ede47d38d10 | 2097 | * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock . |
| phungductung | 0:8ede47d38d10 | 2098 | * This parameter must be a number between Min_Data = 1 and Max_Data = 32. |
| phungductung | 0:8ede47d38d10 | 2099 | * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ |
| phungductung | 0:8ede47d38d10 | 2100 | */ |
| phungductung | 0:8ede47d38d10 | 2101 | #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) |
| phungductung | 0:8ede47d38d10 | 2102 | |
| phungductung | 0:8ede47d38d10 | 2103 | /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. |
| phungductung | 0:8ede47d38d10 | 2104 | * |
| phungductung | 0:8ede47d38d10 | 2105 | * @note This function must be called before enabling the PLLSAI. |
| phungductung | 0:8ede47d38d10 | 2106 | * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . |
| phungductung | 0:8ede47d38d10 | 2107 | * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. |
| phungductung | 0:8ede47d38d10 | 2108 | * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ |
| phungductung | 0:8ede47d38d10 | 2109 | */ |
| phungductung | 0:8ede47d38d10 | 2110 | #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ |
| phungductung | 0:8ede47d38d10 | 2111 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) |
| phungductung | 0:8ede47d38d10 | 2112 | |
| phungductung | 0:8ede47d38d10 | 2113 | /** @brief Macro to configure SAI1 clock source selection. |
| phungductung | 0:8ede47d38d10 | 2114 | * @note This function must be called before enabling PLLSAI, PLLI2S and |
| phungductung | 0:8ede47d38d10 | 2115 | * the SAI clock. |
| phungductung | 0:8ede47d38d10 | 2116 | * @param __SOURCE__: specifies the SAI1 clock source. |
| phungductung | 0:8ede47d38d10 | 2117 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2118 | * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
| phungductung | 0:8ede47d38d10 | 2119 | * as SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 2120 | * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
| phungductung | 0:8ede47d38d10 | 2121 | * as SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 2122 | * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
| phungductung | 0:8ede47d38d10 | 2123 | * used as SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 2124 | */ |
| phungductung | 0:8ede47d38d10 | 2125 | #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ |
| phungductung | 0:8ede47d38d10 | 2126 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2127 | |
| phungductung | 0:8ede47d38d10 | 2128 | /** @brief Macro to get the SAI1 clock source. |
| phungductung | 0:8ede47d38d10 | 2129 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2130 | * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
| phungductung | 0:8ede47d38d10 | 2131 | * as SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 2132 | * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
| phungductung | 0:8ede47d38d10 | 2133 | * as SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 2134 | * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
| phungductung | 0:8ede47d38d10 | 2135 | * used as SAI1 clock. |
| phungductung | 0:8ede47d38d10 | 2136 | */ |
| phungductung | 0:8ede47d38d10 | 2137 | #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) |
| phungductung | 0:8ede47d38d10 | 2138 | |
| phungductung | 0:8ede47d38d10 | 2139 | |
| phungductung | 0:8ede47d38d10 | 2140 | /** @brief Macro to configure SAI2 clock source selection. |
| phungductung | 0:8ede47d38d10 | 2141 | * @note This function must be called before enabling PLLSAI, PLLI2S and |
| phungductung | 0:8ede47d38d10 | 2142 | * the SAI clock. |
| phungductung | 0:8ede47d38d10 | 2143 | * @param __SOURCE__: specifies the SAI2 clock source. |
| phungductung | 0:8ede47d38d10 | 2144 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2145 | * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
| phungductung | 0:8ede47d38d10 | 2146 | * as SAI2 clock. |
| phungductung | 0:8ede47d38d10 | 2147 | * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
| phungductung | 0:8ede47d38d10 | 2148 | * as SAI2 clock. |
| phungductung | 0:8ede47d38d10 | 2149 | * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
| phungductung | 0:8ede47d38d10 | 2150 | * used as SAI2 clock. |
| phungductung | 0:8ede47d38d10 | 2151 | */ |
| phungductung | 0:8ede47d38d10 | 2152 | #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ |
| phungductung | 0:8ede47d38d10 | 2153 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2154 | |
| phungductung | 0:8ede47d38d10 | 2155 | |
| phungductung | 0:8ede47d38d10 | 2156 | /** @brief Macro to get the SAI2 clock source. |
| phungductung | 0:8ede47d38d10 | 2157 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2158 | * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
| phungductung | 0:8ede47d38d10 | 2159 | * as SAI2 clock. |
| phungductung | 0:8ede47d38d10 | 2160 | * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
| phungductung | 0:8ede47d38d10 | 2161 | * as SAI2 clock. |
| phungductung | 0:8ede47d38d10 | 2162 | * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
| phungductung | 0:8ede47d38d10 | 2163 | * used as SAI2 clock. |
| phungductung | 0:8ede47d38d10 | 2164 | */ |
| phungductung | 0:8ede47d38d10 | 2165 | #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) |
| phungductung | 0:8ede47d38d10 | 2166 | |
| phungductung | 0:8ede47d38d10 | 2167 | |
| phungductung | 0:8ede47d38d10 | 2168 | /** @brief Enable PLLSAI_RDY interrupt. |
| phungductung | 0:8ede47d38d10 | 2169 | */ |
| phungductung | 0:8ede47d38d10 | 2170 | #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
| phungductung | 0:8ede47d38d10 | 2171 | |
| phungductung | 0:8ede47d38d10 | 2172 | /** @brief Disable PLLSAI_RDY interrupt. |
| phungductung | 0:8ede47d38d10 | 2173 | */ |
| phungductung | 0:8ede47d38d10 | 2174 | #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
| phungductung | 0:8ede47d38d10 | 2175 | |
| phungductung | 0:8ede47d38d10 | 2176 | /** @brief Clear the PLLSAI RDY interrupt pending bits. |
| phungductung | 0:8ede47d38d10 | 2177 | */ |
| phungductung | 0:8ede47d38d10 | 2178 | #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
| phungductung | 0:8ede47d38d10 | 2179 | |
| phungductung | 0:8ede47d38d10 | 2180 | /** @brief Check the PLLSAI RDY interrupt has occurred or not. |
| phungductung | 0:8ede47d38d10 | 2181 | * @retval The new state (TRUE or FALSE). |
| phungductung | 0:8ede47d38d10 | 2182 | */ |
| phungductung | 0:8ede47d38d10 | 2183 | #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
| phungductung | 0:8ede47d38d10 | 2184 | |
| phungductung | 0:8ede47d38d10 | 2185 | /** @brief Check PLLSAI RDY flag is set or not. |
| phungductung | 0:8ede47d38d10 | 2186 | * @retval The new state (TRUE or FALSE). |
| phungductung | 0:8ede47d38d10 | 2187 | */ |
| phungductung | 0:8ede47d38d10 | 2188 | #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
| phungductung | 0:8ede47d38d10 | 2189 | |
| phungductung | 0:8ede47d38d10 | 2190 | /** @brief Macro to Get I2S clock source selection. |
| phungductung | 0:8ede47d38d10 | 2191 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2192 | * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. |
| phungductung | 0:8ede47d38d10 | 2193 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source |
| phungductung | 0:8ede47d38d10 | 2194 | */ |
| phungductung | 0:8ede47d38d10 | 2195 | #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) |
| phungductung | 0:8ede47d38d10 | 2196 | |
| phungductung | 0:8ede47d38d10 | 2197 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
| phungductung | 0:8ede47d38d10 | 2198 | * |
| phungductung | 0:8ede47d38d10 | 2199 | * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source. |
| phungductung | 0:8ede47d38d10 | 2200 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2201 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
| phungductung | 0:8ede47d38d10 | 2202 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
| phungductung | 0:8ede47d38d10 | 2203 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
| phungductung | 0:8ede47d38d10 | 2204 | */ |
| phungductung | 0:8ede47d38d10 | 2205 | #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2206 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2207 | |
| phungductung | 0:8ede47d38d10 | 2208 | /** @brief Macro to get the I2C1 clock source. |
| phungductung | 0:8ede47d38d10 | 2209 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2210 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
| phungductung | 0:8ede47d38d10 | 2211 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
| phungductung | 0:8ede47d38d10 | 2212 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
| phungductung | 0:8ede47d38d10 | 2213 | */ |
| phungductung | 0:8ede47d38d10 | 2214 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) |
| phungductung | 0:8ede47d38d10 | 2215 | |
| phungductung | 0:8ede47d38d10 | 2216 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
| phungductung | 0:8ede47d38d10 | 2217 | * |
| phungductung | 0:8ede47d38d10 | 2218 | * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source. |
| phungductung | 0:8ede47d38d10 | 2219 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2220 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
| phungductung | 0:8ede47d38d10 | 2221 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
| phungductung | 0:8ede47d38d10 | 2222 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
| phungductung | 0:8ede47d38d10 | 2223 | */ |
| phungductung | 0:8ede47d38d10 | 2224 | #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2225 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2226 | |
| phungductung | 0:8ede47d38d10 | 2227 | /** @brief Macro to get the I2C2 clock source. |
| phungductung | 0:8ede47d38d10 | 2228 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2229 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
| phungductung | 0:8ede47d38d10 | 2230 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
| phungductung | 0:8ede47d38d10 | 2231 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
| phungductung | 0:8ede47d38d10 | 2232 | */ |
| phungductung | 0:8ede47d38d10 | 2233 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) |
| phungductung | 0:8ede47d38d10 | 2234 | |
| phungductung | 0:8ede47d38d10 | 2235 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
| phungductung | 0:8ede47d38d10 | 2236 | * |
| phungductung | 0:8ede47d38d10 | 2237 | * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source. |
| phungductung | 0:8ede47d38d10 | 2238 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2239 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
| phungductung | 0:8ede47d38d10 | 2240 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
| phungductung | 0:8ede47d38d10 | 2241 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
| phungductung | 0:8ede47d38d10 | 2242 | */ |
| phungductung | 0:8ede47d38d10 | 2243 | #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2244 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2245 | |
| phungductung | 0:8ede47d38d10 | 2246 | /** @brief macro to get the I2C3 clock source. |
| phungductung | 0:8ede47d38d10 | 2247 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2248 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
| phungductung | 0:8ede47d38d10 | 2249 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
| phungductung | 0:8ede47d38d10 | 2250 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
| phungductung | 0:8ede47d38d10 | 2251 | */ |
| phungductung | 0:8ede47d38d10 | 2252 | #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) |
| phungductung | 0:8ede47d38d10 | 2253 | |
| phungductung | 0:8ede47d38d10 | 2254 | /** @brief Macro to configure the I2C4 clock (I2C4CLK). |
| phungductung | 0:8ede47d38d10 | 2255 | * |
| phungductung | 0:8ede47d38d10 | 2256 | * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source. |
| phungductung | 0:8ede47d38d10 | 2257 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2258 | * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock |
| phungductung | 0:8ede47d38d10 | 2259 | * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock |
| phungductung | 0:8ede47d38d10 | 2260 | * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock |
| phungductung | 0:8ede47d38d10 | 2261 | */ |
| phungductung | 0:8ede47d38d10 | 2262 | #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2263 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2264 | |
| phungductung | 0:8ede47d38d10 | 2265 | /** @brief macro to get the I2C4 clock source. |
| phungductung | 0:8ede47d38d10 | 2266 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2267 | * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock |
| phungductung | 0:8ede47d38d10 | 2268 | * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock |
| phungductung | 0:8ede47d38d10 | 2269 | * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock |
| phungductung | 0:8ede47d38d10 | 2270 | */ |
| phungductung | 0:8ede47d38d10 | 2271 | #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) |
| phungductung | 0:8ede47d38d10 | 2272 | |
| phungductung | 0:8ede47d38d10 | 2273 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
| phungductung | 0:8ede47d38d10 | 2274 | * |
| phungductung | 0:8ede47d38d10 | 2275 | * @param __USART1_CLKSOURCE__: specifies the USART1 clock source. |
| phungductung | 0:8ede47d38d10 | 2276 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2277 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2278 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2279 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2280 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2281 | */ |
| phungductung | 0:8ede47d38d10 | 2282 | #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2283 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2284 | |
| phungductung | 0:8ede47d38d10 | 2285 | /** @brief macro to get the USART1 clock source. |
| phungductung | 0:8ede47d38d10 | 2286 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2287 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2288 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2289 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2290 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
| phungductung | 0:8ede47d38d10 | 2291 | */ |
| phungductung | 0:8ede47d38d10 | 2292 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) |
| phungductung | 0:8ede47d38d10 | 2293 | |
| phungductung | 0:8ede47d38d10 | 2294 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
| phungductung | 0:8ede47d38d10 | 2295 | * |
| phungductung | 0:8ede47d38d10 | 2296 | * @param __USART2_CLKSOURCE__: specifies the USART2 clock source. |
| phungductung | 0:8ede47d38d10 | 2297 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2298 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2299 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2300 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2301 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2302 | */ |
| phungductung | 0:8ede47d38d10 | 2303 | #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2304 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2305 | |
| phungductung | 0:8ede47d38d10 | 2306 | /** @brief macro to get the USART2 clock source. |
| phungductung | 0:8ede47d38d10 | 2307 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2308 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2309 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2310 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2311 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
| phungductung | 0:8ede47d38d10 | 2312 | */ |
| phungductung | 0:8ede47d38d10 | 2313 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) |
| phungductung | 0:8ede47d38d10 | 2314 | |
| phungductung | 0:8ede47d38d10 | 2315 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
| phungductung | 0:8ede47d38d10 | 2316 | * |
| phungductung | 0:8ede47d38d10 | 2317 | * @param __USART3_CLKSOURCE__: specifies the USART3 clock source. |
| phungductung | 0:8ede47d38d10 | 2318 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2319 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2320 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2321 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2322 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2323 | */ |
| phungductung | 0:8ede47d38d10 | 2324 | #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2325 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2326 | |
| phungductung | 0:8ede47d38d10 | 2327 | /** @brief macro to get the USART3 clock source. |
| phungductung | 0:8ede47d38d10 | 2328 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2329 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2330 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2331 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2332 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
| phungductung | 0:8ede47d38d10 | 2333 | */ |
| phungductung | 0:8ede47d38d10 | 2334 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) |
| phungductung | 0:8ede47d38d10 | 2335 | |
| phungductung | 0:8ede47d38d10 | 2336 | /** @brief Macro to configure the UART4 clock (UART4CLK). |
| phungductung | 0:8ede47d38d10 | 2337 | * |
| phungductung | 0:8ede47d38d10 | 2338 | * @param __UART4_CLKSOURCE__: specifies the UART4 clock source. |
| phungductung | 0:8ede47d38d10 | 2339 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2340 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2341 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2342 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2343 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2344 | */ |
| phungductung | 0:8ede47d38d10 | 2345 | #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2346 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2347 | |
| phungductung | 0:8ede47d38d10 | 2348 | /** @brief macro to get the UART4 clock source. |
| phungductung | 0:8ede47d38d10 | 2349 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2350 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2351 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2352 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2353 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
| phungductung | 0:8ede47d38d10 | 2354 | */ |
| phungductung | 0:8ede47d38d10 | 2355 | #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) |
| phungductung | 0:8ede47d38d10 | 2356 | |
| phungductung | 0:8ede47d38d10 | 2357 | /** @brief Macro to configure the UART5 clock (UART5CLK). |
| phungductung | 0:8ede47d38d10 | 2358 | * |
| phungductung | 0:8ede47d38d10 | 2359 | * @param __UART5_CLKSOURCE__: specifies the UART5 clock source. |
| phungductung | 0:8ede47d38d10 | 2360 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2361 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2362 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2363 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2364 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2365 | */ |
| phungductung | 0:8ede47d38d10 | 2366 | #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2367 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2368 | |
| phungductung | 0:8ede47d38d10 | 2369 | /** @brief macro to get the UART5 clock source. |
| phungductung | 0:8ede47d38d10 | 2370 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2371 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2372 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2373 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2374 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
| phungductung | 0:8ede47d38d10 | 2375 | */ |
| phungductung | 0:8ede47d38d10 | 2376 | #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) |
| phungductung | 0:8ede47d38d10 | 2377 | |
| phungductung | 0:8ede47d38d10 | 2378 | /** @brief Macro to configure the USART6 clock (USART6CLK). |
| phungductung | 0:8ede47d38d10 | 2379 | * |
| phungductung | 0:8ede47d38d10 | 2380 | * @param __USART6_CLKSOURCE__: specifies the USART6 clock source. |
| phungductung | 0:8ede47d38d10 | 2381 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2382 | * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2383 | * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2384 | * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2385 | * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2386 | */ |
| phungductung | 0:8ede47d38d10 | 2387 | #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2388 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2389 | |
| phungductung | 0:8ede47d38d10 | 2390 | /** @brief macro to get the USART6 clock source. |
| phungductung | 0:8ede47d38d10 | 2391 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2392 | * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2393 | * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2394 | * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2395 | * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock |
| phungductung | 0:8ede47d38d10 | 2396 | */ |
| phungductung | 0:8ede47d38d10 | 2397 | #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) |
| phungductung | 0:8ede47d38d10 | 2398 | |
| phungductung | 0:8ede47d38d10 | 2399 | /** @brief Macro to configure the UART7 clock (UART7CLK). |
| phungductung | 0:8ede47d38d10 | 2400 | * |
| phungductung | 0:8ede47d38d10 | 2401 | * @param __UART7_CLKSOURCE__: specifies the UART7 clock source. |
| phungductung | 0:8ede47d38d10 | 2402 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2403 | * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2404 | * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2405 | * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2406 | * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2407 | */ |
| phungductung | 0:8ede47d38d10 | 2408 | #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2409 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2410 | |
| phungductung | 0:8ede47d38d10 | 2411 | /** @brief macro to get the UART7 clock source. |
| phungductung | 0:8ede47d38d10 | 2412 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2413 | * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2414 | * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2415 | * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2416 | * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock |
| phungductung | 0:8ede47d38d10 | 2417 | */ |
| phungductung | 0:8ede47d38d10 | 2418 | #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) |
| phungductung | 0:8ede47d38d10 | 2419 | |
| phungductung | 0:8ede47d38d10 | 2420 | /** @brief Macro to configure the UART8 clock (UART8CLK). |
| phungductung | 0:8ede47d38d10 | 2421 | * |
| phungductung | 0:8ede47d38d10 | 2422 | * @param __UART8_CLKSOURCE__: specifies the UART8 clock source. |
| phungductung | 0:8ede47d38d10 | 2423 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2424 | * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2425 | * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2426 | * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2427 | * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2428 | */ |
| phungductung | 0:8ede47d38d10 | 2429 | #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2430 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2431 | |
| phungductung | 0:8ede47d38d10 | 2432 | /** @brief macro to get the UART8 clock source. |
| phungductung | 0:8ede47d38d10 | 2433 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2434 | * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2435 | * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2436 | * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2437 | * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock |
| phungductung | 0:8ede47d38d10 | 2438 | */ |
| phungductung | 0:8ede47d38d10 | 2439 | #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) |
| phungductung | 0:8ede47d38d10 | 2440 | |
| phungductung | 0:8ede47d38d10 | 2441 | /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). |
| phungductung | 0:8ede47d38d10 | 2442 | * |
| phungductung | 0:8ede47d38d10 | 2443 | * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source. |
| phungductung | 0:8ede47d38d10 | 2444 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2445 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2446 | * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2447 | * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2448 | * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2449 | */ |
| phungductung | 0:8ede47d38d10 | 2450 | #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2451 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2452 | |
| phungductung | 0:8ede47d38d10 | 2453 | /** @brief macro to get the LPTIM1 clock source. |
| phungductung | 0:8ede47d38d10 | 2454 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2455 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2456 | * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2457 | * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2458 | * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock |
| phungductung | 0:8ede47d38d10 | 2459 | */ |
| phungductung | 0:8ede47d38d10 | 2460 | #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) |
| phungductung | 0:8ede47d38d10 | 2461 | |
| phungductung | 0:8ede47d38d10 | 2462 | /** @brief Macro to configure the CEC clock (CECCLK). |
| phungductung | 0:8ede47d38d10 | 2463 | * |
| phungductung | 0:8ede47d38d10 | 2464 | * @param __CEC_CLKSOURCE__: specifies the CEC clock source. |
| phungductung | 0:8ede47d38d10 | 2465 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2466 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
| phungductung | 0:8ede47d38d10 | 2467 | * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock |
| phungductung | 0:8ede47d38d10 | 2468 | */ |
| phungductung | 0:8ede47d38d10 | 2469 | #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2470 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2471 | |
| phungductung | 0:8ede47d38d10 | 2472 | /** @brief macro to get the CEC clock source. |
| phungductung | 0:8ede47d38d10 | 2473 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2474 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
| phungductung | 0:8ede47d38d10 | 2475 | * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
| phungductung | 0:8ede47d38d10 | 2476 | */ |
| phungductung | 0:8ede47d38d10 | 2477 | #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) |
| phungductung | 0:8ede47d38d10 | 2478 | |
| phungductung | 0:8ede47d38d10 | 2479 | /** @brief Macro to configure the CLK48 source (CLK48CLK). |
| phungductung | 0:8ede47d38d10 | 2480 | * |
| phungductung | 0:8ede47d38d10 | 2481 | * @param __CLK48_SOURCE__: specifies the CLK48 clock source. |
| phungductung | 0:8ede47d38d10 | 2482 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2483 | * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source |
| phungductung | 0:8ede47d38d10 | 2484 | * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source |
| phungductung | 0:8ede47d38d10 | 2485 | */ |
| phungductung | 0:8ede47d38d10 | 2486 | #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2487 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2488 | |
| phungductung | 0:8ede47d38d10 | 2489 | /** @brief macro to get the CLK48 source. |
| phungductung | 0:8ede47d38d10 | 2490 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2491 | * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source |
| phungductung | 0:8ede47d38d10 | 2492 | * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source |
| phungductung | 0:8ede47d38d10 | 2493 | */ |
| phungductung | 0:8ede47d38d10 | 2494 | #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) |
| phungductung | 0:8ede47d38d10 | 2495 | |
| phungductung | 0:8ede47d38d10 | 2496 | /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). |
| phungductung | 0:8ede47d38d10 | 2497 | * |
| phungductung | 0:8ede47d38d10 | 2498 | * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. |
| phungductung | 0:8ede47d38d10 | 2499 | * This parameter can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2500 | * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock |
| phungductung | 0:8ede47d38d10 | 2501 | * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock |
| phungductung | 0:8ede47d38d10 | 2502 | */ |
| phungductung | 0:8ede47d38d10 | 2503 | #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
| phungductung | 0:8ede47d38d10 | 2504 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
| phungductung | 0:8ede47d38d10 | 2505 | |
| phungductung | 0:8ede47d38d10 | 2506 | /** @brief macro to get the SDMMC1 clock source. |
| phungductung | 0:8ede47d38d10 | 2507 | * @retval The clock source can be one of the following values: |
| phungductung | 0:8ede47d38d10 | 2508 | * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock |
| phungductung | 0:8ede47d38d10 | 2509 | * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock |
| phungductung | 0:8ede47d38d10 | 2510 | */ |
| phungductung | 0:8ede47d38d10 | 2511 | #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) |
| phungductung | 0:8ede47d38d10 | 2512 | |
| phungductung | 0:8ede47d38d10 | 2513 | /** |
| phungductung | 0:8ede47d38d10 | 2514 | * @} |
| phungductung | 0:8ede47d38d10 | 2515 | */ |
| phungductung | 0:8ede47d38d10 | 2516 | |
| phungductung | 0:8ede47d38d10 | 2517 | /* Exported functions --------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 2518 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
| phungductung | 0:8ede47d38d10 | 2519 | * @{ |
| phungductung | 0:8ede47d38d10 | 2520 | */ |
| phungductung | 0:8ede47d38d10 | 2521 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| phungductung | 0:8ede47d38d10 | 2522 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| phungductung | 0:8ede47d38d10 | 2523 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
| phungductung | 0:8ede47d38d10 | 2524 | |
| phungductung | 0:8ede47d38d10 | 2525 | /** |
| phungductung | 0:8ede47d38d10 | 2526 | * @} |
| phungductung | 0:8ede47d38d10 | 2527 | */ |
| phungductung | 0:8ede47d38d10 | 2528 | /* Private macros ------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 2529 | /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros |
| phungductung | 0:8ede47d38d10 | 2530 | * @{ |
| phungductung | 0:8ede47d38d10 | 2531 | */ |
| phungductung | 0:8ede47d38d10 | 2532 | /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters |
| phungductung | 0:8ede47d38d10 | 2533 | * @{ |
| phungductung | 0:8ede47d38d10 | 2534 | */ |
| phungductung | 0:8ede47d38d10 | 2535 | #if defined(STM32F756xx) || defined(STM32F746xx) |
| phungductung | 0:8ede47d38d10 | 2536 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
| phungductung | 0:8ede47d38d10 | 2537 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
| phungductung | 0:8ede47d38d10 | 2538 | (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ |
| phungductung | 0:8ede47d38d10 | 2539 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
| phungductung | 0:8ede47d38d10 | 2540 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
| phungductung | 0:8ede47d38d10 | 2541 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
| phungductung | 0:8ede47d38d10 | 2542 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
| phungductung | 0:8ede47d38d10 | 2543 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
| phungductung | 0:8ede47d38d10 | 2544 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
| phungductung | 0:8ede47d38d10 | 2545 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
| phungductung | 0:8ede47d38d10 | 2546 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
| phungductung | 0:8ede47d38d10 | 2547 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
| phungductung | 0:8ede47d38d10 | 2548 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
| phungductung | 0:8ede47d38d10 | 2549 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
| phungductung | 0:8ede47d38d10 | 2550 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
| phungductung | 0:8ede47d38d10 | 2551 | (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
| phungductung | 0:8ede47d38d10 | 2552 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
| phungductung | 0:8ede47d38d10 | 2553 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
| phungductung | 0:8ede47d38d10 | 2554 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
| phungductung | 0:8ede47d38d10 | 2555 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
| phungductung | 0:8ede47d38d10 | 2556 | (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
| phungductung | 0:8ede47d38d10 | 2557 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
| phungductung | 0:8ede47d38d10 | 2558 | (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
| phungductung | 0:8ede47d38d10 | 2559 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
| phungductung | 0:8ede47d38d10 | 2560 | #elif defined(STM32F745xx) |
| phungductung | 0:8ede47d38d10 | 2561 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
| phungductung | 0:8ede47d38d10 | 2562 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
| phungductung | 0:8ede47d38d10 | 2563 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
| phungductung | 0:8ede47d38d10 | 2564 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
| phungductung | 0:8ede47d38d10 | 2565 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
| phungductung | 0:8ede47d38d10 | 2566 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
| phungductung | 0:8ede47d38d10 | 2567 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
| phungductung | 0:8ede47d38d10 | 2568 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
| phungductung | 0:8ede47d38d10 | 2569 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
| phungductung | 0:8ede47d38d10 | 2570 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
| phungductung | 0:8ede47d38d10 | 2571 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
| phungductung | 0:8ede47d38d10 | 2572 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
| phungductung | 0:8ede47d38d10 | 2573 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
| phungductung | 0:8ede47d38d10 | 2574 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
| phungductung | 0:8ede47d38d10 | 2575 | (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
| phungductung | 0:8ede47d38d10 | 2576 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
| phungductung | 0:8ede47d38d10 | 2577 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
| phungductung | 0:8ede47d38d10 | 2578 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
| phungductung | 0:8ede47d38d10 | 2579 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
| phungductung | 0:8ede47d38d10 | 2580 | (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
| phungductung | 0:8ede47d38d10 | 2581 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
| phungductung | 0:8ede47d38d10 | 2582 | (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
| phungductung | 0:8ede47d38d10 | 2583 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
| phungductung | 0:8ede47d38d10 | 2584 | #endif /* STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 2585 | #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
| phungductung | 0:8ede47d38d10 | 2586 | #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ |
| phungductung | 0:8ede47d38d10 | 2587 | ((VALUE) == RCC_PLLI2SP_DIV4) ||\ |
| phungductung | 0:8ede47d38d10 | 2588 | ((VALUE) == RCC_PLLI2SP_DIV6) ||\ |
| phungductung | 0:8ede47d38d10 | 2589 | ((VALUE) == RCC_PLLI2SP_DIV8)) |
| phungductung | 0:8ede47d38d10 | 2590 | #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
| phungductung | 0:8ede47d38d10 | 2591 | #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
| phungductung | 0:8ede47d38d10 | 2592 | |
| phungductung | 0:8ede47d38d10 | 2593 | #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
| phungductung | 0:8ede47d38d10 | 2594 | #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ |
| phungductung | 0:8ede47d38d10 | 2595 | ((VALUE) == RCC_PLLSAIP_DIV4) ||\ |
| phungductung | 0:8ede47d38d10 | 2596 | ((VALUE) == RCC_PLLSAIP_DIV6) ||\ |
| phungductung | 0:8ede47d38d10 | 2597 | ((VALUE) == RCC_PLLSAIP_DIV8)) |
| phungductung | 0:8ede47d38d10 | 2598 | #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
| phungductung | 0:8ede47d38d10 | 2599 | #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
| phungductung | 0:8ede47d38d10 | 2600 | |
| phungductung | 0:8ede47d38d10 | 2601 | #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
| phungductung | 0:8ede47d38d10 | 2602 | |
| phungductung | 0:8ede47d38d10 | 2603 | #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
| phungductung | 0:8ede47d38d10 | 2604 | |
| phungductung | 0:8ede47d38d10 | 2605 | #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ |
| phungductung | 0:8ede47d38d10 | 2606 | ((VALUE) == RCC_PLLSAIDIVR_4) ||\ |
| phungductung | 0:8ede47d38d10 | 2607 | ((VALUE) == RCC_PLLSAIDIVR_8) ||\ |
| phungductung | 0:8ede47d38d10 | 2608 | ((VALUE) == RCC_PLLSAIDIVR_16)) |
| phungductung | 0:8ede47d38d10 | 2609 | #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ |
| phungductung | 0:8ede47d38d10 | 2610 | ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) |
| phungductung | 0:8ede47d38d10 | 2611 | |
| phungductung | 0:8ede47d38d10 | 2612 | #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2613 | ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) |
| phungductung | 0:8ede47d38d10 | 2614 | |
| phungductung | 0:8ede47d38d10 | 2615 | #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
| phungductung | 0:8ede47d38d10 | 2616 | ((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
| phungductung | 0:8ede47d38d10 | 2617 | #define IS_RCC_USART1CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2618 | (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
| phungductung | 0:8ede47d38d10 | 2619 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2620 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2621 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2622 | |
| phungductung | 0:8ede47d38d10 | 2623 | #define IS_RCC_USART2CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2624 | (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2625 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2626 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2627 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2628 | #define IS_RCC_USART3CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2629 | (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2630 | ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2631 | ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2632 | ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2633 | |
| phungductung | 0:8ede47d38d10 | 2634 | #define IS_RCC_UART4CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2635 | (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2636 | ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2637 | ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2638 | ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2639 | |
| phungductung | 0:8ede47d38d10 | 2640 | #define IS_RCC_UART5CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2641 | (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2642 | ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2643 | ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2644 | ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2645 | |
| phungductung | 0:8ede47d38d10 | 2646 | #define IS_RCC_USART6CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2647 | (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ |
| phungductung | 0:8ede47d38d10 | 2648 | ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2649 | ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2650 | ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2651 | |
| phungductung | 0:8ede47d38d10 | 2652 | #define IS_RCC_UART7CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2653 | (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2654 | ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2655 | ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2656 | ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2657 | |
| phungductung | 0:8ede47d38d10 | 2658 | #define IS_RCC_UART8CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2659 | (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2660 | ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2661 | ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ |
| phungductung | 0:8ede47d38d10 | 2662 | ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2663 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2664 | (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2665 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
| phungductung | 0:8ede47d38d10 | 2666 | ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2667 | #define IS_RCC_I2C2CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2668 | (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2669 | ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ |
| phungductung | 0:8ede47d38d10 | 2670 | ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2671 | |
| phungductung | 0:8ede47d38d10 | 2672 | #define IS_RCC_I2C3CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2673 | (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2674 | ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ |
| phungductung | 0:8ede47d38d10 | 2675 | ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2676 | #define IS_RCC_I2C4CLKSOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2677 | (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ |
| phungductung | 0:8ede47d38d10 | 2678 | ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ |
| phungductung | 0:8ede47d38d10 | 2679 | ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) |
| phungductung | 0:8ede47d38d10 | 2680 | #define IS_RCC_LPTIM1CLK(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2681 | (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \ |
| phungductung | 0:8ede47d38d10 | 2682 | ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
| phungductung | 0:8ede47d38d10 | 2683 | ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
| phungductung | 0:8ede47d38d10 | 2684 | ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) |
| phungductung | 0:8ede47d38d10 | 2685 | #define IS_RCC_CLK48SOURCE(SOURCE) \ |
| phungductung | 0:8ede47d38d10 | 2686 | (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ |
| phungductung | 0:8ede47d38d10 | 2687 | ((SOURCE) == RCC_CLK48SOURCE_PLL)) |
| phungductung | 0:8ede47d38d10 | 2688 | #define IS_RCC_TIMPRES(VALUE) \ |
| phungductung | 0:8ede47d38d10 | 2689 | (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ |
| phungductung | 0:8ede47d38d10 | 2690 | ((VALUE) == RCC_TIMPRES_ACTIVATED)) |
| phungductung | 0:8ede47d38d10 | 2691 | |
| phungductung | 0:8ede47d38d10 | 2692 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) |
| phungductung | 0:8ede47d38d10 | 2693 | #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ |
| phungductung | 0:8ede47d38d10 | 2694 | ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ |
| phungductung | 0:8ede47d38d10 | 2695 | ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) |
| phungductung | 0:8ede47d38d10 | 2696 | #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ |
| phungductung | 0:8ede47d38d10 | 2697 | ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ |
| phungductung | 0:8ede47d38d10 | 2698 | ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) |
| phungductung | 0:8ede47d38d10 | 2699 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx */ |
| phungductung | 0:8ede47d38d10 | 2700 | |
| phungductung | 0:8ede47d38d10 | 2701 | /** |
| phungductung | 0:8ede47d38d10 | 2702 | * @} |
| phungductung | 0:8ede47d38d10 | 2703 | */ |
| phungductung | 0:8ede47d38d10 | 2704 | |
| phungductung | 0:8ede47d38d10 | 2705 | /** |
| phungductung | 0:8ede47d38d10 | 2706 | * @} |
| phungductung | 0:8ede47d38d10 | 2707 | */ |
| phungductung | 0:8ede47d38d10 | 2708 | |
| phungductung | 0:8ede47d38d10 | 2709 | /** |
| phungductung | 0:8ede47d38d10 | 2710 | * @} |
| phungductung | 0:8ede47d38d10 | 2711 | */ |
| phungductung | 0:8ede47d38d10 | 2712 | |
| phungductung | 0:8ede47d38d10 | 2713 | /** |
| phungductung | 0:8ede47d38d10 | 2714 | * @} |
| phungductung | 0:8ede47d38d10 | 2715 | */ |
| phungductung | 0:8ede47d38d10 | 2716 | |
| phungductung | 0:8ede47d38d10 | 2717 | #ifdef __cplusplus |
| phungductung | 0:8ede47d38d10 | 2718 | } |
| phungductung | 0:8ede47d38d10 | 2719 | #endif |
| phungductung | 0:8ede47d38d10 | 2720 | |
| phungductung | 0:8ede47d38d10 | 2721 | #endif /* __STM32F7xx_HAL_RCC_EX_H */ |
| phungductung | 0:8ede47d38d10 | 2722 | |
| phungductung | 0:8ede47d38d10 | 2723 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |