David Jung / Mbed OS MAXREFDES101_SOURCE_CODE_HEART_RATE

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Dependencies:   max32630fthr Adafruit_FeatherOLED USBDevice

Drivers/MAX30001/MAX30001.h@1:f60eafbf009a, 2019-04-10 (annotated)

Committer:
gmehmet
Date:
Wed Apr 10 14:56:25 2019 +0300
Revision:
1:f60eafbf009a
upload from local

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmehmet 1:f60eafbf009a 1 /*******************************************************************************
gmehmet 1:f60eafbf009a 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
gmehmet 1:f60eafbf009a 3 *
gmehmet 1:f60eafbf009a 4 * Permission is hereby granted, free of charge, to any person obtaining a
gmehmet 1:f60eafbf009a 5 * copy of this software and associated documentation files (the "Software"),
gmehmet 1:f60eafbf009a 6 * to deal in the Software without restriction, including without limitation
gmehmet 1:f60eafbf009a 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
gmehmet 1:f60eafbf009a 8 * and/or sell copies of the Software, and to permit persons to whom the
gmehmet 1:f60eafbf009a 9 * Software is furnished to do so, subject to the following conditions:
gmehmet 1:f60eafbf009a 10 *
gmehmet 1:f60eafbf009a 11 * The above copyright notice and this permission notice shall be included
gmehmet 1:f60eafbf009a 12 * in all copies or substantial portions of the Software.
gmehmet 1:f60eafbf009a 13 *
gmehmet 1:f60eafbf009a 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
gmehmet 1:f60eafbf009a 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
gmehmet 1:f60eafbf009a 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
gmehmet 1:f60eafbf009a 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
gmehmet 1:f60eafbf009a 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
gmehmet 1:f60eafbf009a 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
gmehmet 1:f60eafbf009a 20 * OTHER DEALINGS IN THE SOFTWARE.
gmehmet 1:f60eafbf009a 21 *
gmehmet 1:f60eafbf009a 22 * Except as contained in this notice, the name of Maxim Integrated
gmehmet 1:f60eafbf009a 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
gmehmet 1:f60eafbf009a 24 * Products, Inc. Branding Policy.
gmehmet 1:f60eafbf009a 25 *
gmehmet 1:f60eafbf009a 26 * The mere transfer of this software does not imply any licenses
gmehmet 1:f60eafbf009a 27 * of trade secrets, proprietary technology, copyrights, patents,
gmehmet 1:f60eafbf009a 28 * trademarks, maskwork rights, or any other form of intellectual
gmehmet 1:f60eafbf009a 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
gmehmet 1:f60eafbf009a 30 * ownership rights.
gmehmet 1:f60eafbf009a 31 *******************************************************************************/
gmehmet 1:f60eafbf009a 32 /*
gmehmet 1:f60eafbf009a 33 * max30001.h
gmehmet 1:f60eafbf009a 34 *
gmehmet 1:f60eafbf009a 35 * Created on: Oct 9, 2015
gmehmet 1:f60eafbf009a 36 * Author: faisal.tariq
gmehmet 1:f60eafbf009a 37 */
gmehmet 1:f60eafbf009a 38
gmehmet 1:f60eafbf009a 39 #ifndef MAX30001_H_
gmehmet 1:f60eafbf009a 40 #define MAX30001_H_
gmehmet 1:f60eafbf009a 41
gmehmet 1:f60eafbf009a 42 #include "mbed.h"
gmehmet 1:f60eafbf009a 43 #include "USBSerial.h"
gmehmet 1:f60eafbf009a 44
gmehmet 1:f60eafbf009a 45 #define mbed_COMPLIANT // Uncomment to Use timer for MAX30001 FCLK (for mbed)
gmehmet 1:f60eafbf009a 46 // Comment to use the RTC clock
gmehmet 1:f60eafbf009a 47
gmehmet 1:f60eafbf009a 48
gmehmet 1:f60eafbf009a 49
gmehmet 1:f60eafbf009a 50 #define ASYNC_SPI_BUFFER_SIZE (32 * 3) // Maximimum buffer size for async byte transfers
gmehmet 1:f60eafbf009a 51
gmehmet 1:f60eafbf009a 52 // Defines for data callbacks
gmehmet 1:f60eafbf009a 53 #define MAX30001_DATA_ECG 0x30
gmehmet 1:f60eafbf009a 54 #define MAX30001_DATA_PACE 0x31
gmehmet 1:f60eafbf009a 55 #define MAX30001_DATA_RTOR 0x32
gmehmet 1:f60eafbf009a 56 #define MAX30001_DATA_BIOZ 0x33
gmehmet 1:f60eafbf009a 57 #define MAX30001_DATA_LEADOFF_DC 0x34
gmehmet 1:f60eafbf009a 58 #define MAX30001_DATA_LEADOFF_AC 0x35
gmehmet 1:f60eafbf009a 59 #define MAX30001_DATA_BCGMON 0x36
gmehmet 1:f60eafbf009a 60 #define MAX30001_DATA_ACLEADON 0x37
gmehmet 1:f60eafbf009a 61
gmehmet 1:f60eafbf009a 62 #define MAX30001_SPI_MASTER_PORT 0
gmehmet 1:f60eafbf009a 63 #define MAX30001_SPI_SS_INDEX 0
gmehmet 1:f60eafbf009a 64
gmehmet 1:f60eafbf009a 65 #define MAX30001_INT_PORT_B 3
gmehmet 1:f60eafbf009a 66 #define MAX30001_INT_PIN_B 6
gmehmet 1:f60eafbf009a 67
gmehmet 1:f60eafbf009a 68 #define MAX30001_INT_PORT_2B 4
gmehmet 1:f60eafbf009a 69 #define MAX30001_INT_PIN_2B 5
gmehmet 1:f60eafbf009a 70
gmehmet 1:f60eafbf009a 71 #define MAX30001_INT_PORT_FCLK 1
gmehmet 1:f60eafbf009a 72 #define MAX30001_INT_PIN_FCLK 7
gmehmet 1:f60eafbf009a 73
gmehmet 1:f60eafbf009a 74 #define MAX30001_FUNC_SEL_TMR 2 // 0=FW Control, 1= Pulse Train, 2=Timer
gmehmet 1:f60eafbf009a 75
gmehmet 1:f60eafbf009a 76 #define MAX30001_INDEX 3
gmehmet 1:f60eafbf009a 77 #define MAX30001_POLARITY 0
gmehmet 1:f60eafbf009a 78 #define MAX30001_PERIOD 30518
gmehmet 1:f60eafbf009a 79 #define MAX30001_CYCLE 50
gmehmet 1:f60eafbf009a 80
gmehmet 1:f60eafbf009a 81 #define MAX30001_IOMUX_IO_ENABLE 1
gmehmet 1:f60eafbf009a 82
gmehmet 1:f60eafbf009a 83 #define MAX30001_SPI_PORT 0
gmehmet 1:f60eafbf009a 84 #define MAX30001_CS_PIN 0
gmehmet 1:f60eafbf009a 85 #define MAX30001_CS_POLARITY 0
gmehmet 1:f60eafbf009a 86 #define MAX30001_CS_ACTIVITY_DELAY 0
gmehmet 1:f60eafbf009a 87 #define MAX30001_CS_INACTIVITY_DELAY 0
gmehmet 1:f60eafbf009a 88 #define MAX30001_CLK_HI 1
gmehmet 1:f60eafbf009a 89 #define MAX30001_CLK_LOW 1
gmehmet 1:f60eafbf009a 90 #define MAX30001_ALT_CLK 0
gmehmet 1:f60eafbf009a 91 #define MAX30001_CLK_POLARITY 0
gmehmet 1:f60eafbf009a 92 #define MAX30001_CLK_PHASE 0
gmehmet 1:f60eafbf009a 93 #define MAX30001_WRITE 1
gmehmet 1:f60eafbf009a 94 #define MAX30001_READ 0
gmehmet 1:f60eafbf009a 95
gmehmet 1:f60eafbf009a 96 #define MAX30001_INT_PORT_B 3
gmehmet 1:f60eafbf009a 97 #define MAX30001INT_PIN_B 6
gmehmet 1:f60eafbf009a 98
gmehmet 1:f60eafbf009a 99 void MAX30001_AllowInterrupts(int state);
gmehmet 1:f60eafbf009a 100
gmehmet 1:f60eafbf009a 101 /**
gmehmet 1:f60eafbf009a 102 * Maxim Integrated MAX30001 ECG/BIOZ chip
gmehmet 1:f60eafbf009a 103 */
gmehmet 1:f60eafbf009a 104 class MAX30001 {
gmehmet 1:f60eafbf009a 105
gmehmet 1:f60eafbf009a 106 public:
gmehmet 1:f60eafbf009a 107 typedef enum { // MAX30001 Register addresses
gmehmet 1:f60eafbf009a 108 STATUS = 0x01,
gmehmet 1:f60eafbf009a 109 EN_INT = 0x02,
gmehmet 1:f60eafbf009a 110 EN_INT2 = 0x03,
gmehmet 1:f60eafbf009a 111 MNGR_INT = 0x04,
gmehmet 1:f60eafbf009a 112 MNGR_DYN = 0x05,
gmehmet 1:f60eafbf009a 113 SW_RST = 0x08,
gmehmet 1:f60eafbf009a 114 SYNCH = 0x09,
gmehmet 1:f60eafbf009a 115 FIFO_RST = 0x0A,
gmehmet 1:f60eafbf009a 116 INFO = 0x0F,
gmehmet 1:f60eafbf009a 117 CNFG_GEN = 0x10,
gmehmet 1:f60eafbf009a 118 CNFG_CAL = 0x12,
gmehmet 1:f60eafbf009a 119 CNFG_EMUX = 0x14,
gmehmet 1:f60eafbf009a 120 CNFG_ECG = 0x15,
gmehmet 1:f60eafbf009a 121 CNFG_BMUX = 0x17,
gmehmet 1:f60eafbf009a 122 CNFG_BIOZ = 0x18,
gmehmet 1:f60eafbf009a 123 CNFG_PACE = 0x1A,
gmehmet 1:f60eafbf009a 124 CNFG_RTOR1 = 0x1D,
gmehmet 1:f60eafbf009a 125 CNFG_RTOR2 = 0x1E,
gmehmet 1:f60eafbf009a 126
gmehmet 1:f60eafbf009a 127 // Data locations
gmehmet 1:f60eafbf009a 128 ECG_FIFO_BURST = 0x20,
gmehmet 1:f60eafbf009a 129 ECG_FIFO = 0x21,
gmehmet 1:f60eafbf009a 130 FIFO_BURST = 0x22,
gmehmet 1:f60eafbf009a 131 BIOZ_FIFO = 0x23,
gmehmet 1:f60eafbf009a 132 RTOR = 0x25,
gmehmet 1:f60eafbf009a 133
gmehmet 1:f60eafbf009a 134 PACE0_FIFO_BURST = 0x30,
gmehmet 1:f60eafbf009a 135 PACE0_A = 0x31,
gmehmet 1:f60eafbf009a 136 PACE0_B = 0x32,
gmehmet 1:f60eafbf009a 137 PACE0_C = 0x33,
gmehmet 1:f60eafbf009a 138
gmehmet 1:f60eafbf009a 139 PACE1_FIFO_BURST = 0x34,
gmehmet 1:f60eafbf009a 140 PACE1_A = 0x35,
gmehmet 1:f60eafbf009a 141 PACE1_B = 0x36,
gmehmet 1:f60eafbf009a 142 PACE1_C = 0x37,
gmehmet 1:f60eafbf009a 143
gmehmet 1:f60eafbf009a 144 PACE2_FIFO_BURST = 0x38,
gmehmet 1:f60eafbf009a 145 PACE2_A = 0x39,
gmehmet 1:f60eafbf009a 146 PACE2_B = 0x3A,
gmehmet 1:f60eafbf009a 147 PACE2_C = 0x3B,
gmehmet 1:f60eafbf009a 148
gmehmet 1:f60eafbf009a 149 PACE3_FIFO_BURST = 0x3C,
gmehmet 1:f60eafbf009a 150 PACE3_A = 0x3D,
gmehmet 1:f60eafbf009a 151 PACE3_B = 0x3E,
gmehmet 1:f60eafbf009a 152 PACE3_C = 0x3F,
gmehmet 1:f60eafbf009a 153
gmehmet 1:f60eafbf009a 154 PACE4_FIFO_BURST = 0x40,
gmehmet 1:f60eafbf009a 155 PACE4_A = 0x41,
gmehmet 1:f60eafbf009a 156 PACE4_B = 0x42,
gmehmet 1:f60eafbf009a 157 PACE4_C = 0x43,
gmehmet 1:f60eafbf009a 158
gmehmet 1:f60eafbf009a 159 PACE5_FIFO_BURST = 0x44,
gmehmet 1:f60eafbf009a 160 PACE5_A = 0x45,
gmehmet 1:f60eafbf009a 161 PACE5_B = 0x46,
gmehmet 1:f60eafbf009a 162 PACE5_C = 0x47,
gmehmet 1:f60eafbf009a 163
gmehmet 1:f60eafbf009a 164 } MAX30001_REG_map_t;
gmehmet 1:f60eafbf009a 165
gmehmet 1:f60eafbf009a 166 /**
gmehmet 1:f60eafbf009a 167 * @brief STATUS (0x01)
gmehmet 1:f60eafbf009a 168 */
gmehmet 1:f60eafbf009a 169 union max30001_status_reg {
gmehmet 1:f60eafbf009a 170 uint32_t all;
gmehmet 1:f60eafbf009a 171
gmehmet 1:f60eafbf009a 172 struct {
gmehmet 1:f60eafbf009a 173 uint32_t loff_nl : 1;
gmehmet 1:f60eafbf009a 174 uint32_t loff_nh : 1;
gmehmet 1:f60eafbf009a 175 uint32_t loff_pl : 1;
gmehmet 1:f60eafbf009a 176 uint32_t loff_ph : 1;
gmehmet 1:f60eafbf009a 177
gmehmet 1:f60eafbf009a 178 uint32_t bcgmn : 1;
gmehmet 1:f60eafbf009a 179 uint32_t bcgmp : 1;
gmehmet 1:f60eafbf009a 180 uint32_t reserved1 : 1;
gmehmet 1:f60eafbf009a 181 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 182
gmehmet 1:f60eafbf009a 183 uint32_t pllint : 1;
gmehmet 1:f60eafbf009a 184 uint32_t samp : 1;
gmehmet 1:f60eafbf009a 185 uint32_t rrint : 1;
gmehmet 1:f60eafbf009a 186 uint32_t lonint : 1;
gmehmet 1:f60eafbf009a 187
gmehmet 1:f60eafbf009a 188 uint32_t pedge : 1;
gmehmet 1:f60eafbf009a 189 uint32_t povf : 1;
gmehmet 1:f60eafbf009a 190 uint32_t pint : 1;
gmehmet 1:f60eafbf009a 191 uint32_t bcgmon : 1;
gmehmet 1:f60eafbf009a 192
gmehmet 1:f60eafbf009a 193 uint32_t bundr : 1;
gmehmet 1:f60eafbf009a 194 uint32_t bover : 1;
gmehmet 1:f60eafbf009a 195 uint32_t bovf : 1;
gmehmet 1:f60eafbf009a 196 uint32_t bint : 1;
gmehmet 1:f60eafbf009a 197
gmehmet 1:f60eafbf009a 198 uint32_t dcloffint : 1;
gmehmet 1:f60eafbf009a 199 uint32_t fstint : 1;
gmehmet 1:f60eafbf009a 200 uint32_t eovf : 1;
gmehmet 1:f60eafbf009a 201 uint32_t eint : 1;
gmehmet 1:f60eafbf009a 202
gmehmet 1:f60eafbf009a 203 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 204
gmehmet 1:f60eafbf009a 205 } bit;
gmehmet 1:f60eafbf009a 206
gmehmet 1:f60eafbf009a 207 } max30001_status;
gmehmet 1:f60eafbf009a 208
gmehmet 1:f60eafbf009a 209
gmehmet 1:f60eafbf009a 210 /**
gmehmet 1:f60eafbf009a 211 * @brief EN_INT (0x02)
gmehmet 1:f60eafbf009a 212 */
gmehmet 1:f60eafbf009a 213
gmehmet 1:f60eafbf009a 214 union max30001_en_int_reg {
gmehmet 1:f60eafbf009a 215 uint32_t all;
gmehmet 1:f60eafbf009a 216
gmehmet 1:f60eafbf009a 217 struct {
gmehmet 1:f60eafbf009a 218 uint32_t intb_type : 2;
gmehmet 1:f60eafbf009a 219 uint32_t reserved1 : 1;
gmehmet 1:f60eafbf009a 220 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 221
gmehmet 1:f60eafbf009a 222 uint32_t reserved3 : 1;
gmehmet 1:f60eafbf009a 223 uint32_t reserved4 : 1;
gmehmet 1:f60eafbf009a 224 uint32_t reserved5 : 1;
gmehmet 1:f60eafbf009a 225 uint32_t reserved6 : 1;
gmehmet 1:f60eafbf009a 226
gmehmet 1:f60eafbf009a 227 uint32_t en_pllint : 1;
gmehmet 1:f60eafbf009a 228 uint32_t en_samp : 1;
gmehmet 1:f60eafbf009a 229 uint32_t en_rrint : 1;
gmehmet 1:f60eafbf009a 230 uint32_t en_lonint : 1;
gmehmet 1:f60eafbf009a 231
gmehmet 1:f60eafbf009a 232 uint32_t en_pedge : 1;
gmehmet 1:f60eafbf009a 233 uint32_t en_povf : 1;
gmehmet 1:f60eafbf009a 234 uint32_t en_pint : 1;
gmehmet 1:f60eafbf009a 235 uint32_t en_bcgmon : 1;
gmehmet 1:f60eafbf009a 236
gmehmet 1:f60eafbf009a 237 uint32_t en_bundr : 1;
gmehmet 1:f60eafbf009a 238 uint32_t en_bover : 1;
gmehmet 1:f60eafbf009a 239 uint32_t en_bovf : 1;
gmehmet 1:f60eafbf009a 240 uint32_t en_bint : 1;
gmehmet 1:f60eafbf009a 241
gmehmet 1:f60eafbf009a 242 uint32_t en_dcloffint : 1;
gmehmet 1:f60eafbf009a 243 uint32_t en_fstint : 1;
gmehmet 1:f60eafbf009a 244 uint32_t en_eovf : 1;
gmehmet 1:f60eafbf009a 245 uint32_t en_eint : 1;
gmehmet 1:f60eafbf009a 246
gmehmet 1:f60eafbf009a 247 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 248
gmehmet 1:f60eafbf009a 249 } bit;
gmehmet 1:f60eafbf009a 250
gmehmet 1:f60eafbf009a 251 } max30001_en_int;
gmehmet 1:f60eafbf009a 252
gmehmet 1:f60eafbf009a 253
gmehmet 1:f60eafbf009a 254 /**
gmehmet 1:f60eafbf009a 255 * @brief EN_INT2 (0x03)
gmehmet 1:f60eafbf009a 256 */
gmehmet 1:f60eafbf009a 257 union max30001_en_int2_reg {
gmehmet 1:f60eafbf009a 258 uint32_t all;
gmehmet 1:f60eafbf009a 259
gmehmet 1:f60eafbf009a 260 struct {
gmehmet 1:f60eafbf009a 261 uint32_t intb_type : 2;
gmehmet 1:f60eafbf009a 262 uint32_t reserved1 : 1;
gmehmet 1:f60eafbf009a 263 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 264
gmehmet 1:f60eafbf009a 265 uint32_t reserved3 : 1;
gmehmet 1:f60eafbf009a 266 uint32_t reserved4 : 1;
gmehmet 1:f60eafbf009a 267 uint32_t reserved5 : 1;
gmehmet 1:f60eafbf009a 268 uint32_t reserved6 : 1;
gmehmet 1:f60eafbf009a 269
gmehmet 1:f60eafbf009a 270 uint32_t en_pllint : 1;
gmehmet 1:f60eafbf009a 271 uint32_t en_samp : 1;
gmehmet 1:f60eafbf009a 272 uint32_t en_rrint : 1;
gmehmet 1:f60eafbf009a 273 uint32_t en_lonint : 1;
gmehmet 1:f60eafbf009a 274
gmehmet 1:f60eafbf009a 275 uint32_t en_pedge : 1;
gmehmet 1:f60eafbf009a 276 uint32_t en_povf : 1;
gmehmet 1:f60eafbf009a 277 uint32_t en_pint : 1;
gmehmet 1:f60eafbf009a 278 uint32_t en_bcgmon : 1;
gmehmet 1:f60eafbf009a 279
gmehmet 1:f60eafbf009a 280 uint32_t en_bundr : 1;
gmehmet 1:f60eafbf009a 281 uint32_t en_bover : 1;
gmehmet 1:f60eafbf009a 282 uint32_t en_bovf : 1;
gmehmet 1:f60eafbf009a 283 uint32_t en_bint : 1;
gmehmet 1:f60eafbf009a 284
gmehmet 1:f60eafbf009a 285 uint32_t en_dcloffint : 1;
gmehmet 1:f60eafbf009a 286 uint32_t en_fstint : 1;
gmehmet 1:f60eafbf009a 287 uint32_t en_eovf : 1;
gmehmet 1:f60eafbf009a 288 uint32_t en_eint : 1;
gmehmet 1:f60eafbf009a 289
gmehmet 1:f60eafbf009a 290 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 291
gmehmet 1:f60eafbf009a 292 } bit;
gmehmet 1:f60eafbf009a 293
gmehmet 1:f60eafbf009a 294 } max30001_en_int2;
gmehmet 1:f60eafbf009a 295
gmehmet 1:f60eafbf009a 296 /**
gmehmet 1:f60eafbf009a 297 * @brief MNGR_INT (0x04)
gmehmet 1:f60eafbf009a 298 */
gmehmet 1:f60eafbf009a 299 union max30001_mngr_int_reg {
gmehmet 1:f60eafbf009a 300 uint32_t all;
gmehmet 1:f60eafbf009a 301
gmehmet 1:f60eafbf009a 302 struct {
gmehmet 1:f60eafbf009a 303 uint32_t samp_it : 2;
gmehmet 1:f60eafbf009a 304 uint32_t clr_samp : 1;
gmehmet 1:f60eafbf009a 305 uint32_t clr_pedge : 1;
gmehmet 1:f60eafbf009a 306 uint32_t clr_rrint : 2;
gmehmet 1:f60eafbf009a 307 uint32_t clr_fast : 1;
gmehmet 1:f60eafbf009a 308 uint32_t reserved1 : 1;
gmehmet 1:f60eafbf009a 309 uint32_t reserved2 : 4;
gmehmet 1:f60eafbf009a 310 uint32_t reserved3 : 4;
gmehmet 1:f60eafbf009a 311
gmehmet 1:f60eafbf009a 312 uint32_t b_fit : 3;
gmehmet 1:f60eafbf009a 313 uint32_t e_fit : 5;
gmehmet 1:f60eafbf009a 314
gmehmet 1:f60eafbf009a 315 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 316
gmehmet 1:f60eafbf009a 317 } bit;
gmehmet 1:f60eafbf009a 318
gmehmet 1:f60eafbf009a 319 } max30001_mngr_int;
gmehmet 1:f60eafbf009a 320
gmehmet 1:f60eafbf009a 321 /**
gmehmet 1:f60eafbf009a 322 * @brief MNGR_DYN (0x05)
gmehmet 1:f60eafbf009a 323 */
gmehmet 1:f60eafbf009a 324 union max30001_mngr_dyn_reg {
gmehmet 1:f60eafbf009a 325 uint32_t all;
gmehmet 1:f60eafbf009a 326
gmehmet 1:f60eafbf009a 327 struct {
gmehmet 1:f60eafbf009a 328 uint32_t bloff_lo_it : 8;
gmehmet 1:f60eafbf009a 329 uint32_t bloff_hi_it : 8;
gmehmet 1:f60eafbf009a 330 uint32_t fast_th : 6;
gmehmet 1:f60eafbf009a 331 uint32_t fast : 2;
gmehmet 1:f60eafbf009a 332 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 333 } bit;
gmehmet 1:f60eafbf009a 334
gmehmet 1:f60eafbf009a 335 } max30001_mngr_dyn;
gmehmet 1:f60eafbf009a 336
gmehmet 1:f60eafbf009a 337 // 0x08
gmehmet 1:f60eafbf009a 338 // uint32_t max30001_sw_rst;
gmehmet 1:f60eafbf009a 339
gmehmet 1:f60eafbf009a 340 // 0x09
gmehmet 1:f60eafbf009a 341 // uint32_t max30001_synch;
gmehmet 1:f60eafbf009a 342
gmehmet 1:f60eafbf009a 343 // 0x0A
gmehmet 1:f60eafbf009a 344 // uint32_t max30001_fifo_rst;
gmehmet 1:f60eafbf009a 345
gmehmet 1:f60eafbf009a 346
gmehmet 1:f60eafbf009a 347 /**
gmehmet 1:f60eafbf009a 348 * @brief INFO (0x0F)
gmehmet 1:f60eafbf009a 349 */
gmehmet 1:f60eafbf009a 350 union max30001_info_reg {
gmehmet 1:f60eafbf009a 351 uint32_t all;
gmehmet 1:f60eafbf009a 352 struct {
gmehmet 1:f60eafbf009a 353 uint32_t serial : 12;
gmehmet 1:f60eafbf009a 354 uint32_t part_id : 2;
gmehmet 1:f60eafbf009a 355 uint32_t sample : 1;
gmehmet 1:f60eafbf009a 356 uint32_t reserved1 : 1;
gmehmet 1:f60eafbf009a 357 uint32_t rev_id : 4;
gmehmet 1:f60eafbf009a 358 uint32_t pattern : 4;
gmehmet 1:f60eafbf009a 359 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 360 } bit;
gmehmet 1:f60eafbf009a 361
gmehmet 1:f60eafbf009a 362 } max30001_info;
gmehmet 1:f60eafbf009a 363
gmehmet 1:f60eafbf009a 364 /**
gmehmet 1:f60eafbf009a 365 * @brief CNFG_GEN (0x10)
gmehmet 1:f60eafbf009a 366 */
gmehmet 1:f60eafbf009a 367 union max30001_cnfg_gen_reg {
gmehmet 1:f60eafbf009a 368 uint32_t all;
gmehmet 1:f60eafbf009a 369 struct {
gmehmet 1:f60eafbf009a 370 uint32_t rbiasn : 1;
gmehmet 1:f60eafbf009a 371 uint32_t rbiasp : 1;
gmehmet 1:f60eafbf009a 372 uint32_t rbiasv : 2;
gmehmet 1:f60eafbf009a 373 uint32_t en_rbias : 2;
gmehmet 1:f60eafbf009a 374 uint32_t vth : 2;
gmehmet 1:f60eafbf009a 375 uint32_t imag : 3;
gmehmet 1:f60eafbf009a 376 uint32_t ipol : 1;
gmehmet 1:f60eafbf009a 377 uint32_t en_dcloff : 2;
gmehmet 1:f60eafbf009a 378 uint32_t en_bloff : 2;
gmehmet 1:f60eafbf009a 379 uint32_t reserved1 : 1;
gmehmet 1:f60eafbf009a 380 uint32_t en_pace : 1;
gmehmet 1:f60eafbf009a 381 uint32_t en_bioz : 1;
gmehmet 1:f60eafbf009a 382 uint32_t en_ecg : 1;
gmehmet 1:f60eafbf009a 383 uint32_t fmstr : 2;
gmehmet 1:f60eafbf009a 384 uint32_t en_ulp_lon : 2;
gmehmet 1:f60eafbf009a 385 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 386 } bit;
gmehmet 1:f60eafbf009a 387
gmehmet 1:f60eafbf009a 388 } max30001_cnfg_gen;
gmehmet 1:f60eafbf009a 389
gmehmet 1:f60eafbf009a 390
gmehmet 1:f60eafbf009a 391 /**
gmehmet 1:f60eafbf009a 392 * @brief CNFG_CAL (0x12)
gmehmet 1:f60eafbf009a 393 */
gmehmet 1:f60eafbf009a 394 union max30001_cnfg_cal_reg {
gmehmet 1:f60eafbf009a 395 uint32_t all;
gmehmet 1:f60eafbf009a 396 struct {
gmehmet 1:f60eafbf009a 397 uint32_t thigh : 11;
gmehmet 1:f60eafbf009a 398 uint32_t fifty : 1;
gmehmet 1:f60eafbf009a 399 uint32_t fcal : 3;
gmehmet 1:f60eafbf009a 400 uint32_t reserved1 : 5;
gmehmet 1:f60eafbf009a 401 uint32_t vmag : 1;
gmehmet 1:f60eafbf009a 402 uint32_t vmode : 1;
gmehmet 1:f60eafbf009a 403 uint32_t en_vcal : 1;
gmehmet 1:f60eafbf009a 404 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 405 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 406 } bit;
gmehmet 1:f60eafbf009a 407
gmehmet 1:f60eafbf009a 408 } max30001_cnfg_cal;
gmehmet 1:f60eafbf009a 409
gmehmet 1:f60eafbf009a 410 /**
gmehmet 1:f60eafbf009a 411 * @brief CNFG_EMUX (0x14)
gmehmet 1:f60eafbf009a 412 */
gmehmet 1:f60eafbf009a 413 union max30001_cnfg_emux_reg {
gmehmet 1:f60eafbf009a 414 uint32_t all;
gmehmet 1:f60eafbf009a 415 struct {
gmehmet 1:f60eafbf009a 416 uint32_t reserved1 : 16;
gmehmet 1:f60eafbf009a 417 uint32_t caln_sel : 2;
gmehmet 1:f60eafbf009a 418 uint32_t calp_sel : 2;
gmehmet 1:f60eafbf009a 419 uint32_t openn : 1;
gmehmet 1:f60eafbf009a 420 uint32_t openp : 1;
gmehmet 1:f60eafbf009a 421 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 422 uint32_t pol : 1;
gmehmet 1:f60eafbf009a 423 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 424 } bit;
gmehmet 1:f60eafbf009a 425
gmehmet 1:f60eafbf009a 426 } max30001_cnfg_emux;
gmehmet 1:f60eafbf009a 427
gmehmet 1:f60eafbf009a 428
gmehmet 1:f60eafbf009a 429 /**
gmehmet 1:f60eafbf009a 430 * @brief CNFG_ECG (0x15)
gmehmet 1:f60eafbf009a 431 */
gmehmet 1:f60eafbf009a 432 union max30001_cnfg_ecg_reg {
gmehmet 1:f60eafbf009a 433 uint32_t all;
gmehmet 1:f60eafbf009a 434 struct {
gmehmet 1:f60eafbf009a 435 uint32_t reserved1 : 12;
gmehmet 1:f60eafbf009a 436 uint32_t dlpf : 2;
gmehmet 1:f60eafbf009a 437 uint32_t dhpf : 1;
gmehmet 1:f60eafbf009a 438 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 439 uint32_t gain : 2;
gmehmet 1:f60eafbf009a 440 uint32_t reserved3 : 4;
gmehmet 1:f60eafbf009a 441 uint32_t rate : 2;
gmehmet 1:f60eafbf009a 442
gmehmet 1:f60eafbf009a 443 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 444 } bit;
gmehmet 1:f60eafbf009a 445
gmehmet 1:f60eafbf009a 446 } max30001_cnfg_ecg;
gmehmet 1:f60eafbf009a 447
gmehmet 1:f60eafbf009a 448 /**
gmehmet 1:f60eafbf009a 449 * @brief CNFG_BMUX (0x17)
gmehmet 1:f60eafbf009a 450 */
gmehmet 1:f60eafbf009a 451 union max30001_cnfg_bmux_reg {
gmehmet 1:f60eafbf009a 452 uint32_t all;
gmehmet 1:f60eafbf009a 453 struct {
gmehmet 1:f60eafbf009a 454 uint32_t fbist : 2;
gmehmet 1:f60eafbf009a 455 uint32_t reserved1 : 2;
gmehmet 1:f60eafbf009a 456 uint32_t rmod : 3;
gmehmet 1:f60eafbf009a 457 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 458 uint32_t rnom : 3;
gmehmet 1:f60eafbf009a 459 uint32_t en_bist : 1;
gmehmet 1:f60eafbf009a 460 uint32_t cg_mode : 2;
gmehmet 1:f60eafbf009a 461 uint32_t reserved3 : 2;
gmehmet 1:f60eafbf009a 462 uint32_t caln_sel : 2;
gmehmet 1:f60eafbf009a 463 uint32_t calp_sel : 2;
gmehmet 1:f60eafbf009a 464 uint32_t openn : 1;
gmehmet 1:f60eafbf009a 465 uint32_t openp : 1;
gmehmet 1:f60eafbf009a 466 uint32_t reserved4 : 2;
gmehmet 1:f60eafbf009a 467 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 468 } bit;
gmehmet 1:f60eafbf009a 469
gmehmet 1:f60eafbf009a 470 } max30001_cnfg_bmux;
gmehmet 1:f60eafbf009a 471
gmehmet 1:f60eafbf009a 472 /**
gmehmet 1:f60eafbf009a 473 * @brief CNFG_BIOZ (0x18)
gmehmet 1:f60eafbf009a 474 */
gmehmet 1:f60eafbf009a 475 union max30001_bioz_reg {
gmehmet 1:f60eafbf009a 476 uint32_t all;
gmehmet 1:f60eafbf009a 477 struct {
gmehmet 1:f60eafbf009a 478 uint32_t phoff : 4;
gmehmet 1:f60eafbf009a 479 uint32_t cgmag : 3;
gmehmet 1:f60eafbf009a 480 uint32_t cgmon : 1;
gmehmet 1:f60eafbf009a 481 uint32_t fcgen : 4;
gmehmet 1:f60eafbf009a 482 uint32_t dlpf : 2;
gmehmet 1:f60eafbf009a 483 uint32_t dhpf : 2;
gmehmet 1:f60eafbf009a 484 uint32_t gain : 2;
gmehmet 1:f60eafbf009a 485 uint32_t inapow_mode : 1;
gmehmet 1:f60eafbf009a 486 uint32_t ext_rbias : 1;
gmehmet 1:f60eafbf009a 487 uint32_t ahpf : 3;
gmehmet 1:f60eafbf009a 488 uint32_t rate : 1;
gmehmet 1:f60eafbf009a 489 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 490 } bit;
gmehmet 1:f60eafbf009a 491
gmehmet 1:f60eafbf009a 492 } max30001_cnfg_bioz;
gmehmet 1:f60eafbf009a 493
gmehmet 1:f60eafbf009a 494
gmehmet 1:f60eafbf009a 495 /**
gmehmet 1:f60eafbf009a 496 * @brief CNFG_PACE (0x1A)
gmehmet 1:f60eafbf009a 497 */
gmehmet 1:f60eafbf009a 498 union max30001_cnfg_pace_reg {
gmehmet 1:f60eafbf009a 499 uint32_t all;
gmehmet 1:f60eafbf009a 500
gmehmet 1:f60eafbf009a 501 struct {
gmehmet 1:f60eafbf009a 502 uint32_t dacn : 4;
gmehmet 1:f60eafbf009a 503 uint32_t dacp : 4;
gmehmet 1:f60eafbf009a 504 uint32_t reserved1 : 4;
gmehmet 1:f60eafbf009a 505 uint32_t aout : 2;
gmehmet 1:f60eafbf009a 506 uint32_t aout_lbw : 1;
gmehmet 1:f60eafbf009a 507 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 508 uint32_t gain : 3;
gmehmet 1:f60eafbf009a 509 uint32_t gn_diff_off : 1;
gmehmet 1:f60eafbf009a 510 uint32_t reserved3 : 3;
gmehmet 1:f60eafbf009a 511 uint32_t pol : 1;
gmehmet 1:f60eafbf009a 512 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 513 } bit;
gmehmet 1:f60eafbf009a 514
gmehmet 1:f60eafbf009a 515 } max30001_cnfg_pace;
gmehmet 1:f60eafbf009a 516
gmehmet 1:f60eafbf009a 517 /**
gmehmet 1:f60eafbf009a 518 * @brief CNFG_RTOR1 (0x1D)
gmehmet 1:f60eafbf009a 519 */
gmehmet 1:f60eafbf009a 520 union max30001_cnfg_rtor1_reg {
gmehmet 1:f60eafbf009a 521 uint32_t all;
gmehmet 1:f60eafbf009a 522 struct {
gmehmet 1:f60eafbf009a 523 uint32_t reserved1 : 8;
gmehmet 1:f60eafbf009a 524 uint32_t ptsf : 4;
gmehmet 1:f60eafbf009a 525 uint32_t pavg : 2;
gmehmet 1:f60eafbf009a 526 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 527 uint32_t en_rtor : 1;
gmehmet 1:f60eafbf009a 528 uint32_t gain : 4;
gmehmet 1:f60eafbf009a 529 uint32_t wndw : 4;
gmehmet 1:f60eafbf009a 530 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 531 } bit;
gmehmet 1:f60eafbf009a 532
gmehmet 1:f60eafbf009a 533 } max30001_cnfg_rtor1;
gmehmet 1:f60eafbf009a 534
gmehmet 1:f60eafbf009a 535 /**
gmehmet 1:f60eafbf009a 536 * @brief CNFG_RTOR2 (0x1E)
gmehmet 1:f60eafbf009a 537 */
gmehmet 1:f60eafbf009a 538 union max30001_cnfg_rtor2_reg {
gmehmet 1:f60eafbf009a 539 uint32_t all;
gmehmet 1:f60eafbf009a 540 struct {
gmehmet 1:f60eafbf009a 541 uint32_t reserved1 : 8;
gmehmet 1:f60eafbf009a 542 uint32_t rhsf : 3;
gmehmet 1:f60eafbf009a 543 uint32_t reserved2 : 1;
gmehmet 1:f60eafbf009a 544 uint32_t ravg : 2;
gmehmet 1:f60eafbf009a 545 uint32_t reserved3 : 2;
gmehmet 1:f60eafbf009a 546 uint32_t hoff : 6;
gmehmet 1:f60eafbf009a 547 uint32_t reserved4 : 2;
gmehmet 1:f60eafbf009a 548 uint32_t reserved : 8;
gmehmet 1:f60eafbf009a 549 } bit;
gmehmet 1:f60eafbf009a 550
gmehmet 1:f60eafbf009a 551 } max30001_cnfg_rtor2;
gmehmet 1:f60eafbf009a 552
gmehmet 1:f60eafbf009a 553 /*********************************************************************************/
gmehmet 1:f60eafbf009a 554
gmehmet 1:f60eafbf009a 555 typedef enum {
gmehmet 1:f60eafbf009a 556 MAX30001_NO_INT = 0, // No interrupt
gmehmet 1:f60eafbf009a 557 MAX30001_INT_B = 1, // INTB selected for interrupt
gmehmet 1:f60eafbf009a 558 MAX30001_INT_2B = 2 // INT2B selected for interrupt
gmehmet 1:f60eafbf009a 559 } max30001_intrpt_Location_t;
gmehmet 1:f60eafbf009a 560
gmehmet 1:f60eafbf009a 561 typedef enum {
gmehmet 1:f60eafbf009a 562 MAX30001_INT_DISABLED = 0b00,
gmehmet 1:f60eafbf009a 563 MAX30001_INT_CMOS = 0b01,
gmehmet 1:f60eafbf009a 564 MAX30001_INT_ODN = 0b10,
gmehmet 1:f60eafbf009a 565 MAX30001_INT_ODNR = 0b11
gmehmet 1:f60eafbf009a 566 } max30001_intrpt_type_t;
gmehmet 1:f60eafbf009a 567
gmehmet 1:f60eafbf009a 568 typedef enum { // Input Polarity selection
gmehmet 1:f60eafbf009a 569 MAX30001_NON_INV = 0, // Non-Inverted
gmehmet 1:f60eafbf009a 570 MAX30001_INV = 1 // Inverted
gmehmet 1:f60eafbf009a 571 } max30001_emux_pol;
gmehmet 1:f60eafbf009a 572
gmehmet 1:f60eafbf009a 573 typedef enum { // OPENP and OPENN setting
gmehmet 1:f60eafbf009a 574 MAX30001_ECG_CON_AFE = 0, // ECGx is connected to AFE channel
gmehmet 1:f60eafbf009a 575 MAX30001_ECG_ISO_AFE = 1 // ECGx is isolated from AFE channel
gmehmet 1:f60eafbf009a 576 } max30001_emux_openx;
gmehmet 1:f60eafbf009a 577
gmehmet 1:f60eafbf009a 578 typedef enum { // EMUX_CALP_SEL & EMUX_CALN_SEL
gmehmet 1:f60eafbf009a 579 MAX30001_NO_CAL_SIG = 0b00, // No calibration signal is applied
gmehmet 1:f60eafbf009a 580 MAX30001_INPT_VMID = 0b01, // Input is connected to VMID
gmehmet 1:f60eafbf009a 581 MAX30001_INPT_VCALP = 0b10, // Input is connected to VCALP
gmehmet 1:f60eafbf009a 582 MAX30001_INPT_VCALN = 0b11 // Input is connected to VCALN
gmehmet 1:f60eafbf009a 583 } max30001_emux_calx_sel;
gmehmet 1:f60eafbf009a 584
gmehmet 1:f60eafbf009a 585 typedef enum { // EN_ECG, EN_BIOZ, EN_PACE
gmehmet 1:f60eafbf009a 586 MAX30001_CHANNEL_DISABLED = 0b0, //
gmehmet 1:f60eafbf009a 587 MAX30001_CHANNEL_ENABLED = 0b1
gmehmet 1:f60eafbf009a 588 } max30001_en_feature;
gmehmet 1:f60eafbf009a 589
gmehmet 1:f60eafbf009a 590 /*********************************************************************************/
gmehmet 1:f60eafbf009a 591 // Data
gmehmet 1:f60eafbf009a 592 uint32_t max30001_ECG_FIFO_buffer[32]; // (303 for internal test)
gmehmet 1:f60eafbf009a 593 uint32_t max30001_BIOZ_FIFO_buffer[8]; // (303 for internal test)
gmehmet 1:f60eafbf009a 594
gmehmet 1:f60eafbf009a 595 uint32_t max30001_PACE[18]; // Pace Data 0-5
gmehmet 1:f60eafbf009a 596
gmehmet 1:f60eafbf009a 597 uint32_t max30001_RtoR_data; // This holds the RtoR data
gmehmet 1:f60eafbf009a 598
gmehmet 1:f60eafbf009a 599 uint32_t max30001_DCLeadOff; // This holds the LeadOff data, Last 4 bits give
gmehmet 1:f60eafbf009a 600 // the status, BIT3=LOFF_PH, BIT2=LOFF_PL,
gmehmet 1:f60eafbf009a 601 // BIT1=LOFF_NH, BIT0=LOFF_NL
gmehmet 1:f60eafbf009a 602 // 8th and 9th bits tell Lead off is due to ECG or BIOZ.
gmehmet 1:f60eafbf009a 603 // 0b01 = ECG Lead Off and 0b10 = BIOZ Lead off
gmehmet 1:f60eafbf009a 604
gmehmet 1:f60eafbf009a 605 uint32_t max30001_ACLeadOff; // This gives the state of the BIOZ AC Lead Off
gmehmet 1:f60eafbf009a 606 // state. BIT 1 = BOVER, BIT 0 = BUNDR
gmehmet 1:f60eafbf009a 607
gmehmet 1:f60eafbf009a 608 uint32_t max30001_bcgmon; // This holds the BCGMON data, BIT 1 = BCGMP, BIT0 =
gmehmet 1:f60eafbf009a 609 // BCGMN
gmehmet 1:f60eafbf009a 610
gmehmet 1:f60eafbf009a 611 uint32_t max30001_LeadOn; // This holds the LeadOn data, BIT1 = BIOZ Lead ON,
gmehmet 1:f60eafbf009a 612 // BIT0 = ECG Lead ON, BIT8= Lead On Status Bit
gmehmet 1:f60eafbf009a 613
gmehmet 1:f60eafbf009a 614 uint32_t max30001_timeout; // If the PLL does not respond, timeout and get out.
gmehmet 1:f60eafbf009a 615
gmehmet 1:f60eafbf009a 616 typedef struct { // Creating a structure for BLE data
gmehmet 1:f60eafbf009a 617 int16_t R2R;
gmehmet 1:f60eafbf009a 618 int16_t fmstr;
gmehmet 1:f60eafbf009a 619 } max30001_t;
gmehmet 1:f60eafbf009a 620
gmehmet 1:f60eafbf009a 621 max30001_t hspValMax30001; // R2R, FMSTR
gmehmet 1:f60eafbf009a 622
gmehmet 1:f60eafbf009a 623 //jjj 14MAR17
gmehmet 1:f60eafbf009a 624 //added DigitalOut so we can use any pin for cs
gmehmet 1:f60eafbf009a 625 //jjj
gmehmet 1:f60eafbf009a 626 MAX30001(SPI *spi, DigitalOut *cs);
gmehmet 1:f60eafbf009a 627
gmehmet 1:f60eafbf009a 628
gmehmet 1:f60eafbf009a 629 /**
gmehmet 1:f60eafbf009a 630 * @brief Constructor that accepts pin names for the SPI interface
gmehmet 1:f60eafbf009a 631 * @param mosi master out slave in pin name
gmehmet 1:f60eafbf009a 632 * @param miso master in slave out pin name
gmehmet 1:f60eafbf009a 633 * @param sclk serial clock pin name
gmehmet 1:f60eafbf009a 634 * @param cs chip select pin name
gmehmet 1:f60eafbf009a 635 */
gmehmet 1:f60eafbf009a 636 MAX30001(PinName mosi, PinName miso, PinName sclk, PinName cs);
gmehmet 1:f60eafbf009a 637
gmehmet 1:f60eafbf009a 638 /**
gmehmet 1:f60eafbf009a 639 * MAX30001 destructor
gmehmet 1:f60eafbf009a 640 */
gmehmet 1:f60eafbf009a 641 ~MAX30001(void);
gmehmet 1:f60eafbf009a 642
gmehmet 1:f60eafbf009a 643 /**
gmehmet 1:f60eafbf009a 644 * @brief This function sets up the Resistive Bias mode and also selects the master clock frequency.
gmehmet 1:f60eafbf009a 645 * @brief Uses Register: CNFG_GEN-0x10
gmehmet 1:f60eafbf009a 646 * @param En_rbias: Enable and Select Resitive Lead Bias Mode
gmehmet 1:f60eafbf009a 647 * @param Rbiasv: Resistive Bias Mode Value Selection
gmehmet 1:f60eafbf009a 648 * @param Rbiasp: Enables Resistive Bias on Positive Input
gmehmet 1:f60eafbf009a 649 * @param Rbiasn: Enables Resistive Bias on Negative Input
gmehmet 1:f60eafbf009a 650 * @param Fmstr: Selects Master Clock Frequency
gmehmet 1:f60eafbf009a 651 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 652 *
gmehmet 1:f60eafbf009a 653 */
gmehmet 1:f60eafbf009a 654 int max30001_Rbias_FMSTR_Init(uint8_t En_rbias, uint8_t Rbiasv,
gmehmet 1:f60eafbf009a 655 uint8_t Rbiasp, uint8_t Rbiasn, uint8_t Fmstr);
gmehmet 1:f60eafbf009a 656
gmehmet 1:f60eafbf009a 657 /**
gmehmet 1:f60eafbf009a 658 * @brief This function uses sets up the calibration signal internally. If it is desired to use the internal signal, then
gmehmet 1:f60eafbf009a 659 * @brief this function must be called and the registers set, prior to setting the CALP_SEL and CALN_SEL in the ECG_InitStart
gmehmet 1:f60eafbf009a 660 * @brief and BIOZ_InitStart functions.
gmehmet 1:f60eafbf009a 661 * @brief Uses Register: CNFG_CAL-0x12
gmehmet 1:f60eafbf009a 662 * @param En_Vcal: Calibration Source (VCALP and VCALN) Enable
gmehmet 1:f60eafbf009a 663 * @param Vmode: Calibration Source Mode Selection
gmehmet 1:f60eafbf009a 664 * @param Vmag: Calibration Source Magnitude Selection (VMAG)
gmehmet 1:f60eafbf009a 665 * @param Fcal: Calibration Source Frequency Selection (FCAL)
gmehmet 1:f60eafbf009a 666 * @param Thigh: Calibration Source Time High Selection
gmehmet 1:f60eafbf009a 667 * @param Fifty: Calibration Source Duty Cycle Mode Selection
gmehmet 1:f60eafbf009a 668 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 669 *
gmehmet 1:f60eafbf009a 670 */
gmehmet 1:f60eafbf009a 671 int max30001_CAL_InitStart(uint8_t En_Vcal, uint8_t Vmode, uint8_t Vmag,
gmehmet 1:f60eafbf009a 672 uint8_t Fcal, uint16_t Thigh, uint8_t Fifty);
gmehmet 1:f60eafbf009a 673
gmehmet 1:f60eafbf009a 674 /**
gmehmet 1:f60eafbf009a 675 * @brief This function disables the VCAL signal
gmehmet 1:f60eafbf009a 676 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 677 */
gmehmet 1:f60eafbf009a 678 int max30001_CAL_Stop(void);
gmehmet 1:f60eafbf009a 679
gmehmet 1:f60eafbf009a 680 /**
gmehmet 1:f60eafbf009a 681 * @brief This function handles the assignment of the two interrupt pins (INTB & INT2B) with various
gmehmet 1:f60eafbf009a 682 * @brief functions/behaviors of the MAX30001. Also, each pin can be configured for different drive capability.
gmehmet 1:f60eafbf009a 683 * @brief Uses Registers: EN_INT-0x02 and EN_INT2-0x03.
gmehmet 1:f60eafbf009a 684 * @param max30001_intrpt_Locatio_t <argument>: All the arguments with the aforementioned enumeration essentially
gmehmet 1:f60eafbf009a 685 * can be configured to generate an interrupt on either INTB or INT2B or NONE.
gmehmet 1:f60eafbf009a 686 * @param max30001_intrpt_type_t intb_Type: INTB Port Type (EN_INT Selections).
gmehmet 1:f60eafbf009a 687 * @param max30001_intrpt_type _t int2b_Type: INT2B Port Type (EN_INT2 Selections)
gmehmet 1:f60eafbf009a 688 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 689 *
gmehmet 1:f60eafbf009a 690 */
gmehmet 1:f60eafbf009a 691 int max30001_INT_assignment(max30001_intrpt_Location_t en_enint_loc, max30001_intrpt_Location_t en_eovf_loc, max30001_intrpt_Location_t en_fstint_loc,
gmehmet 1:f60eafbf009a 692 max30001_intrpt_Location_t en_dcloffint_loc, max30001_intrpt_Location_t en_bint_loc, max30001_intrpt_Location_t en_bovf_loc,
gmehmet 1:f60eafbf009a 693 max30001_intrpt_Location_t en_bover_loc, max30001_intrpt_Location_t en_bundr_loc, max30001_intrpt_Location_t en_bcgmon_loc,
gmehmet 1:f60eafbf009a 694 max30001_intrpt_Location_t en_pint_loc, max30001_intrpt_Location_t en_povf_loc, max30001_intrpt_Location_t en_pedge_loc,
gmehmet 1:f60eafbf009a 695 max30001_intrpt_Location_t en_lonint_loc, max30001_intrpt_Location_t en_rrint_loc, max30001_intrpt_Location_t en_samp_loc,
gmehmet 1:f60eafbf009a 696 max30001_intrpt_type_t intb_Type, max30001_intrpt_type_t int2b_Type);
gmehmet 1:f60eafbf009a 697
gmehmet 1:f60eafbf009a 698
gmehmet 1:f60eafbf009a 699
gmehmet 1:f60eafbf009a 700 /**
gmehmet 1:f60eafbf009a 701 * @brief For MAX30001/3 ONLY
gmehmet 1:f60eafbf009a 702 * @brief This function sets up the MAX30001 for the ECG measurements.
gmehmet 1:f60eafbf009a 703 * @brief Registers used: CNFG_EMUX, CNFG_GEN, MNGR_INT, CNFG_ECG.
gmehmet 1:f60eafbf009a 704 * @param En_ecg: ECG Channel Enable <CNFG_GEN register bits>
gmehmet 1:f60eafbf009a 705 * @param Openp: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits>
gmehmet 1:f60eafbf009a 706 * @param Openn: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits>
gmehmet 1:f60eafbf009a 707 * @param Calp_sel: ECGP Calibration Selection <CNFG_EMUX register bits>
gmehmet 1:f60eafbf009a 708 * @param Caln_sel: ECGN Calibration Selection <CNFG_EMUX register bits>
gmehmet 1:f60eafbf009a 709 * @param E_fit: ECG FIFO Interrupt Threshold (issues EINT based on number of unread FIFO records) <CNFG_GEN register bits>
gmehmet 1:f60eafbf009a 710 * @param Clr_rrint: RTOR R Detect Interrupt (RRINT) Clear Behavior <CNFG_GEN register bits>
gmehmet 1:f60eafbf009a 711 * @param Rate: ECG Data Rate
gmehmet 1:f60eafbf009a 712 * @param Gain: ECG Channel Gain Setting
gmehmet 1:f60eafbf009a 713 * @param Dhpf: ECG Channel Digital High Pass Filter Cutoff Frequency
gmehmet 1:f60eafbf009a 714 * @param Dlpf: ECG Channel Digital Low Pass Filter Cutoff Frequency
gmehmet 1:f60eafbf009a 715 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 716 *
gmehmet 1:f60eafbf009a 717 */
gmehmet 1:f60eafbf009a 718 int max30001_ECG_InitStart(uint8_t En_ecg, uint8_t Openp, uint8_t Openn,
gmehmet 1:f60eafbf009a 719 uint8_t Pol, uint8_t Calp_sel, uint8_t Caln_sel,
gmehmet 1:f60eafbf009a 720 uint8_t E_fit, uint8_t Rate, uint8_t Gain,
gmehmet 1:f60eafbf009a 721 uint8_t Dhpf, uint8_t Dlpf);
gmehmet 1:f60eafbf009a 722
gmehmet 1:f60eafbf009a 723 /**
gmehmet 1:f60eafbf009a 724 * @brief For MAX30001/3 ONLY
gmehmet 1:f60eafbf009a 725 * @brief This function enables the Fast mode feature of the ECG.
gmehmet 1:f60eafbf009a 726 * @brief Registers used: MNGR_INT-0x04, MNGR_DYN-0x05
gmehmet 1:f60eafbf009a 727 * @param Clr_Fast: FAST MODE Interrupt Clear Behavior <MNGR_INT Register>
gmehmet 1:f60eafbf009a 728 * @param Fast: ECG Channel Fast Recovery Mode Selection (ECG High Pass Filter Bypass) <MNGR_DYN Register>
gmehmet 1:f60eafbf009a 729 * @param Fast_Th: Automatic Fast Recovery Threshold
gmehmet 1:f60eafbf009a 730 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 731 *
gmehmet 1:f60eafbf009a 732 */
gmehmet 1:f60eafbf009a 733 int max30001_ECGFast_Init(uint8_t Clr_Fast, uint8_t Fast, uint8_t Fast_Th);
gmehmet 1:f60eafbf009a 734
gmehmet 1:f60eafbf009a 735 /**
gmehmet 1:f60eafbf009a 736 * @brief For MAX30001/3 ONLY
gmehmet 1:f60eafbf009a 737 * @brief This function disables the ECG.
gmehmet 1:f60eafbf009a 738 * @brief Uses Register CNFG_GEN-0x10.
gmehmet 1:f60eafbf009a 739 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 740 *
gmehmet 1:f60eafbf009a 741 */
gmehmet 1:f60eafbf009a 742 int max30001_Stop_ECG(void);
gmehmet 1:f60eafbf009a 743
gmehmet 1:f60eafbf009a 744 /**
gmehmet 1:f60eafbf009a 745 * @brief For MAX30001 ONLY
gmehmet 1:f60eafbf009a 746 * @brief This function sets up the MAX30001 for pace signal detection.
gmehmet 1:f60eafbf009a 747 * @brief If both PACE and BIOZ are turned ON, then make sure Fcgen is set for 80K or 40K in the
gmehmet 1:f60eafbf009a 748 * @brief max30001_BIOZ_InitStart() function. However, if Only PACE is on but BIOZ off, then Fcgen can be set
gmehmet 1:f60eafbf009a 749 * @brief for 80K only, in the max30001_BIOZ_InitStart() function
gmehmet 1:f60eafbf009a 750 * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0x37, CNFG_PACE-0x1A.
gmehmet 1:f60eafbf009a 751 * @param En_pace : PACE Channel Enable <CNFG_GEN Register>
gmehmet 1:f60eafbf009a 752 * @param Clr_pedge : PACE Edge Detect Interrupt (PEDGE) Clear Behavior <MNGR_INT Register>
gmehmet 1:f60eafbf009a 753 * @param Pol: PACE Input Polarity Selection <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 754 * @param Gn_diff_off: PACE Differentiator Mode <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 755 * @param Gain: PACE Channel Gain Selection <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 756 * @param Aout_lbw: PACE Analog Output Buffer Bandwidth Mode <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 757 * @param Aout: PACE Single Ended Analog Output Buffer Signal Monitoring Selection <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 758 * @param Dacp (4bits): PACE Detector Positive Comparator Threshold <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 759 * @param Dacn(4bits): PACE Detector Negative Comparator Threshold <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 760 * @returns 0-if no error. A non-zero value indicates an error <CNFG_PACE Register>
gmehmet 1:f60eafbf009a 761 *
gmehmet 1:f60eafbf009a 762 */
gmehmet 1:f60eafbf009a 763 int max30001_PACE_InitStart(uint8_t En_pace, uint8_t Clr_pedge, uint8_t Pol,
gmehmet 1:f60eafbf009a 764 uint8_t Gn_diff_off, uint8_t Gain,
gmehmet 1:f60eafbf009a 765 uint8_t Aout_lbw, uint8_t Aout, uint8_t Dacp,
gmehmet 1:f60eafbf009a 766 uint8_t Dacn);
gmehmet 1:f60eafbf009a 767
gmehmet 1:f60eafbf009a 768 /**
gmehmet 1:f60eafbf009a 769 *@brief For MAX30001 ONLY
gmehmet 1:f60eafbf009a 770 *@param This function disables the PACE. Uses Register CNFG_GEN-0x10.
gmehmet 1:f60eafbf009a 771 *@returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 772 *
gmehmet 1:f60eafbf009a 773 */
gmehmet 1:f60eafbf009a 774 int max30001_Stop_PACE(void);
gmehmet 1:f60eafbf009a 775
gmehmet 1:f60eafbf009a 776 /**
gmehmet 1:f60eafbf009a 777 * @brief For MAX30001/2 ONLY
gmehmet 1:f60eafbf009a 778 * @brief This function sets up the MAX30001 for BIOZ measurement.
gmehmet 1:f60eafbf009a 779 * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0X10, CNFG_BMUX-0x17,CNFG_BIOZ-0x18.
gmehmet 1:f60eafbf009a 780 * @param En_bioz: BIOZ Channel Enable <CNFG_GEN Register>
gmehmet 1:f60eafbf009a 781 * @param Openp: Open the BIP Input Switch <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 782 * @param Openn: Open the BIN Input Switch <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 783 * @param Calp_sel: BIP Calibration Selection <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 784 * @param Caln_sel: BIN Calibration Selection <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 785 * @param CG_mode: BIOZ Current Generator Mode Selection <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 786 * @param B_fit: BIOZ FIFO Interrupt Threshold (issues BINT based on number of unread FIFO records) <MNGR_INT Register>
gmehmet 1:f60eafbf009a 787 * @param Rate: BIOZ Data Rate <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 788 * @param Ahpf: BIOZ/PACE Channel Analog High Pass Filter Cutoff Frequency and Bypass <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 789 * @param Ext_rbias: External Resistor Bias Enable <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 790 * @param Gain: BIOZ Channel Gain Setting <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 791 * @param Dhpf: BIOZ Channel Digital High Pass Filter Cutoff Frequency <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 792 * @param Dlpf: BIOZ Channel Digital Low Pass Filter Cutoff Frequency <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 793 * @param Fcgen: BIOZ Current Generator Modulation Frequency <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 794 * @param Cgmon: BIOZ Current Generator Monitor <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 795 * @param Cgmag: BIOZ Current Generator Magnitude <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 796 * @param Phoff: BIOZ Current Generator Modulation Phase Offset <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 797 * @param Inapow_mode: BIOZ Channel Instrumentation Amplifier (INA) Power Mode <CNFG_BIOZ Register>
gmehmet 1:f60eafbf009a 798 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 799 *
gmehmet 1:f60eafbf009a 800 */
gmehmet 1:f60eafbf009a 801 int max30001_BIOZ_InitStart(uint8_t En_bioz, uint8_t Openp, uint8_t Openn,
gmehmet 1:f60eafbf009a 802 uint8_t Calp_sel, uint8_t Caln_sel,
gmehmet 1:f60eafbf009a 803 uint8_t CG_mode,
gmehmet 1:f60eafbf009a 804 /* uint8_t En_bioz,*/ uint8_t B_fit, uint8_t Rate,
gmehmet 1:f60eafbf009a 805 uint8_t Ahpf, uint8_t Ext_rbias, uint8_t Gain,
gmehmet 1:f60eafbf009a 806 uint8_t Dhpf, uint8_t Dlpf, uint8_t Fcgen,
gmehmet 1:f60eafbf009a 807 uint8_t Cgmon, uint8_t Cgmag, uint8_t Phoff, uint8_t Inapow_mode);
gmehmet 1:f60eafbf009a 808
gmehmet 1:f60eafbf009a 809 /**
gmehmet 1:f60eafbf009a 810 * @brief For MAX30001/2 ONLY
gmehmet 1:f60eafbf009a 811 * @brief This function disables the BIOZ. Uses Register CNFG_GEN-0x10.
gmehmet 1:f60eafbf009a 812 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 813 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 814 *
gmehmet 1:f60eafbf009a 815 */
gmehmet 1:f60eafbf009a 816 int max30001_Stop_BIOZ(void);
gmehmet 1:f60eafbf009a 817
gmehmet 1:f60eafbf009a 818 /**
gmehmet 1:f60eafbf009a 819 * @brief For MAX30001/2 ONLY
gmehmet 1:f60eafbf009a 820 * @brief BIOZ modulated Resistance Built-in-Self-Test, Registers used: CNFG_BMUX-0x17
gmehmet 1:f60eafbf009a 821 * @param En_bist: Enable Modulated Resistance Built-in-Self-test <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 822 * @param Rnom: BIOZ RMOD BIST Nominal Resistance Selection <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 823 * @param Rmod: BIOZ RMOD BIST Modulated Resistance Selection <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 824 * @param Fbist: BIOZ RMOD BIST Frequency Selection <CNFG_BMUX Register>
gmehmet 1:f60eafbf009a 825 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 826 *
gmehmet 1:f60eafbf009a 827 */
gmehmet 1:f60eafbf009a 828 int max30001_BIOZ_InitBist(uint8_t En_bist, uint8_t Rnom, uint8_t Rmod,
gmehmet 1:f60eafbf009a 829 uint8_t Fbist);
gmehmet 1:f60eafbf009a 830
gmehmet 1:f60eafbf009a 831 /**
gmehmet 1:f60eafbf009a 832 * @brief For MAX30001/3/4 ONLY
gmehmet 1:f60eafbf009a 833 * @brief Sets up the device for RtoR measurement
gmehmet 1:f60eafbf009a 834 * @param EN_rtor: ECG RTOR Detection Enable <RTOR1 Register>
gmehmet 1:f60eafbf009a 835 * @param Wndw: R to R Window Averaging (Window Width = RTOR_WNDW[3:0]*8mS) <RTOR1 Register>
gmehmet 1:f60eafbf009a 836 * @param Gain: R to R Gain (where Gain = 2^RTOR_GAIN[3:0], plus an auto-scale option) <RTOR1 Register>
gmehmet 1:f60eafbf009a 837 * @param Pavg: R to R Peak Averaging Weight Factor <RTOR1 Register>
gmehmet 1:f60eafbf009a 838 * @param Ptsf: R to R Peak Threshold Scaling Factor <RTOR1 Register>
gmehmet 1:f60eafbf009a 839 * @param Hoff: R to R minimum Hold Off <RTOR2 Register>
gmehmet 1:f60eafbf009a 840 * @param Ravg: R to R Interval Averaging Weight Factor <RTOR2 Register>
gmehmet 1:f60eafbf009a 841 * @param Rhsf: R to R Interval Hold Off Scaling Factor <RTOR2 Register>
gmehmet 1:f60eafbf009a 842 * @param Clr_rrint: RTOR Detect Interrupt Clear behaviour <MNGR_INT Register>
gmehmet 1:f60eafbf009a 843 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 844 *
gmehmet 1:f60eafbf009a 845 */
gmehmet 1:f60eafbf009a 846 int max30001_RtoR_InitStart(uint8_t En_rtor, uint8_t Wndw, uint8_t Gain,
gmehmet 1:f60eafbf009a 847 uint8_t Pavg, uint8_t Ptsf, uint8_t Hoff,
gmehmet 1:f60eafbf009a 848 uint8_t Ravg, uint8_t Rhsf, uint8_t Clr_rrint);
gmehmet 1:f60eafbf009a 849
gmehmet 1:f60eafbf009a 850 /**
gmehmet 1:f60eafbf009a 851 * @brief For MAX30001/3/4 ONLY
gmehmet 1:f60eafbf009a 852 * @brief This function disables the RtoR. Uses Register CNFG_RTOR1-0x1D
gmehmet 1:f60eafbf009a 853 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 854 *
gmehmet 1:f60eafbf009a 855 */
gmehmet 1:f60eafbf009a 856 int max30001_Stop_RtoR(void);
gmehmet 1:f60eafbf009a 857
gmehmet 1:f60eafbf009a 858 /**
gmehmet 1:f60eafbf009a 859 * @brief This is a function that waits for the PLL to lock; once a lock is achieved it exits out. (For convenience only)
gmehmet 1:f60eafbf009a 860 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 861 *
gmehmet 1:f60eafbf009a 862 */
gmehmet 1:f60eafbf009a 863 int max30001_PLL_lock(void);
gmehmet 1:f60eafbf009a 864
gmehmet 1:f60eafbf009a 865 /**
gmehmet 1:f60eafbf009a 866 * @brief This function causes the MAX30001 to reset. Uses Register SW_RST-0x08
gmehmet 1:f60eafbf009a 867 * @return 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 868 *
gmehmet 1:f60eafbf009a 869 */
gmehmet 1:f60eafbf009a 870 int max30001_sw_rst(void);
gmehmet 1:f60eafbf009a 871
gmehmet 1:f60eafbf009a 872 /**
gmehmet 1:f60eafbf009a 873 * @brief This function provides a SYNCH operation. Uses Register SYCNH-0x09. Please refer to the data sheet for
gmehmet 1:f60eafbf009a 874 * @brief the details on how to use this.
gmehmet 1:f60eafbf009a 875 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 876 *
gmehmet 1:f60eafbf009a 877 */
gmehmet 1:f60eafbf009a 878 int max30001_synch(void);
gmehmet 1:f60eafbf009a 879
gmehmet 1:f60eafbf009a 880 /**
gmehmet 1:f60eafbf009a 881 * @brief This function performs a FIFO Reset. Uses Register FIFO_RST-0x0A. Please refer to the data sheet
gmehmet 1:f60eafbf009a 882 * @brief for the details on how to use this.
gmehmet 1:f60eafbf009a 883 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 884 */
gmehmet 1:f60eafbf009a 885 int max300001_fifo_rst(void);
gmehmet 1:f60eafbf009a 886
gmehmet 1:f60eafbf009a 887 /**
gmehmet 1:f60eafbf009a 888 *
gmehmet 1:f60eafbf009a 889 * @brief This is a callback function which collects all the data from the ECG, BIOZ, PACE and RtoR. It also handles
gmehmet 1:f60eafbf009a 890 * @brief Lead On/Off. This function is passed through the argument of max30001_COMMinit().
gmehmet 1:f60eafbf009a 891 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 892 *
gmehmet 1:f60eafbf009a 893 */
gmehmet 1:f60eafbf009a 894 int max30001_int_handler(void);
gmehmet 1:f60eafbf009a 895
gmehmet 1:f60eafbf009a 896 /**
gmehmet 1:f60eafbf009a 897 * @brief This is function called from the max30001_int_handler() function and processes all the ECG, BIOZ, PACE
gmehmet 1:f60eafbf009a 898 * @brief and the RtoR data and sticks them in appropriate arrays and variables each unsigned 32 bits.
gmehmet 1:f60eafbf009a 899 * @param ECG data will be in the array (input): max30001_ECG_FIFO_buffer[]
gmehmet 1:f60eafbf009a 900 * @param Pace data will be in the array (input): max30001_PACE[]
gmehmet 1:f60eafbf009a 901 * @param RtoRdata will be in the variable (input): max30001_RtoR_data
gmehmet 1:f60eafbf009a 902 * @param BIOZ data will be in the array (input): max30001_BIOZ_FIFO_buffer[]
gmehmet 1:f60eafbf009a 903 * @param global max30001_ECG_FIFO_buffer[]
gmehmet 1:f60eafbf009a 904 * @param global max30001_PACE[]
gmehmet 1:f60eafbf009a 905 * @param global max30001_BIOZ_FIFO_buffer[]
gmehmet 1:f60eafbf009a 906 * @param global max30001_RtoR_data
gmehmet 1:f60eafbf009a 907 * @param global max30001_DCLeadOff
gmehmet 1:f60eafbf009a 908 * @param global max30001_ACLeadOff
gmehmet 1:f60eafbf009a 909 * @param global max30001_LeadON
gmehmet 1:f60eafbf009a 910 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 911 *
gmehmet 1:f60eafbf009a 912 */
gmehmet 1:f60eafbf009a 913 int max30001_FIFO_LeadONOff_Read(void);
gmehmet 1:f60eafbf009a 914
gmehmet 1:f60eafbf009a 915 /**
gmehmet 1:f60eafbf009a 916 * @brief This function allows writing to a register.
gmehmet 1:f60eafbf009a 917 * @param addr: Address of the register to write to
gmehmet 1:f60eafbf009a 918 * @param data: 24-bit data read from the register.
gmehmet 1:f60eafbf009a 919 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 920 *
gmehmet 1:f60eafbf009a 921 */
gmehmet 1:f60eafbf009a 922 int max30001_reg_write(MAX30001_REG_map_t addr, uint32_t data);
gmehmet 1:f60eafbf009a 923
gmehmet 1:f60eafbf009a 924 /**
gmehmet 1:f60eafbf009a 925 * @brief This function allows reading from a register
gmehmet 1:f60eafbf009a 926 * @param addr: Address of the register to read from.
gmehmet 1:f60eafbf009a 927 * @param *return_data: pointer to the value read from the register.
gmehmet 1:f60eafbf009a 928 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 929 *
gmehmet 1:f60eafbf009a 930 */
gmehmet 1:f60eafbf009a 931 int max30001_reg_read(MAX30001_REG_map_t addr, uint32_t *return_data);
gmehmet 1:f60eafbf009a 932
gmehmet 1:f60eafbf009a 933 /**
gmehmet 1:f60eafbf009a 934 * @brief This function enables the DC Lead Off detection. Either ECG or BIOZ can be detected, one at a time.
gmehmet 1:f60eafbf009a 935 * @brief Registers Used: CNFG_GEN-0x10
gmehmet 1:f60eafbf009a 936 * @param En_dcloff: BIOZ Digital Lead Off Detection Enable
gmehmet 1:f60eafbf009a 937 * @param Ipol: DC Lead Off Current Polarity (if current sources are enabled/connected)
gmehmet 1:f60eafbf009a 938 * @param Imag: DC Lead off current Magnitude Selection
gmehmet 1:f60eafbf009a 939 * @param Vth: DC Lead Off Voltage Threshold Selection
gmehmet 1:f60eafbf009a 940 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 941 *
gmehmet 1:f60eafbf009a 942 */
gmehmet 1:f60eafbf009a 943 int max30001_Enable_DcLeadOFF_Init(int8_t En_dcloff, int8_t Ipol, int8_t Imag,
gmehmet 1:f60eafbf009a 944 int8_t Vth);
gmehmet 1:f60eafbf009a 945
gmehmet 1:f60eafbf009a 946 /**
gmehmet 1:f60eafbf009a 947 * @brief This function disables the DC Lead OFF feature, whichever is active.
gmehmet 1:f60eafbf009a 948 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 949 *
gmehmet 1:f60eafbf009a 950 */
gmehmet 1:f60eafbf009a 951 int max30001_Disable_DcLeadOFF(void);
gmehmet 1:f60eafbf009a 952
gmehmet 1:f60eafbf009a 953 /**
gmehmet 1:f60eafbf009a 954 * @brief This function sets up the BIOZ for AC Lead Off test.
gmehmet 1:f60eafbf009a 955 * @brief Registers Used: CNFG_GEN-0x10, MNGR_DYN-0x05
gmehmet 1:f60eafbf009a 956 * @param En_bloff: BIOZ Digital Lead Off Detection Enable <CNFG_GEN register>
gmehmet 1:f60eafbf009a 957 * @param Bloff_hi_it: DC Lead Off Current Polarity (if current sources are enabled/connected) <MNGR_DYN register>
gmehmet 1:f60eafbf009a 958 * @param Bloff_lo_it: DC Lead off current Magnitude Selection <MNGR_DYN register>
gmehmet 1:f60eafbf009a 959 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 960 *
gmehmet 1:f60eafbf009a 961 */
gmehmet 1:f60eafbf009a 962 int max30001_BIOZ_Enable_ACLeadOFF_Init(uint8_t En_bloff, uint8_t Bloff_hi_it,
gmehmet 1:f60eafbf009a 963 uint8_t Bloff_lo_it);
gmehmet 1:f60eafbf009a 964
gmehmet 1:f60eafbf009a 965 /**
gmehmet 1:f60eafbf009a 966 * @brief This function Turns of the BIOZ AC Lead OFF feature
gmehmet 1:f60eafbf009a 967 * @brief Registers Used: CNFG_GEN-0x10
gmehmet 1:f60eafbf009a 968 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 969 *
gmehmet 1:f60eafbf009a 970 */
gmehmet 1:f60eafbf009a 971 int max30001_BIOZ_Disable_ACleadOFF(void);
gmehmet 1:f60eafbf009a 972
gmehmet 1:f60eafbf009a 973 /**
gmehmet 1:f60eafbf009a 974 * @brief This function enables the Current Gnerator Monitor
gmehmet 1:f60eafbf009a 975 * @brief Registers Used: CNFG_BIOZ-0x18
gmehmet 1:f60eafbf009a 976 * @returns 0-if no error. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 977 *
gmehmet 1:f60eafbf009a 978 */
gmehmet 1:f60eafbf009a 979 int max30001_BIOZ_Enable_BCGMON(void);
gmehmet 1:f60eafbf009a 980
gmehmet 1:f60eafbf009a 981 /**
gmehmet 1:f60eafbf009a 982 *
gmehmet 1:f60eafbf009a 983 * @brief This function enables the Lead ON detection. Either ECG or BIOZ can be detected, one at a time.
gmehmet 1:f60eafbf009a 984 * @brief Also, the en_bioz, en_ecg, en_pace setting is saved so that when this feature is disabled through the
gmehmet 1:f60eafbf009a 985 * @brief max30001_Disable_LeadON() function (or otherwise) the enable/disable state of those features can be retrieved.
gmehmet 1:f60eafbf009a 986 * @param Channel: ECG or BIOZ detection
gmehmet 1:f60eafbf009a 987 * @returns 0-if everything is good. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 988 *
gmehmet 1:f60eafbf009a 989 */
gmehmet 1:f60eafbf009a 990 int max30001_Enable_LeadON(int8_t Channel);
gmehmet 1:f60eafbf009a 991
gmehmet 1:f60eafbf009a 992 /**
gmehmet 1:f60eafbf009a 993 * @brief This function turns off the Lead ON feature, whichever one is active. Also, retrieves the en_bioz,
gmehmet 1:f60eafbf009a 994 * @brief en_ecg, en_pace and sets it back to as it was.
gmehmet 1:f60eafbf009a 995 * @param 0-if everything is good. A non-zero value indicates an error.
gmehmet 1:f60eafbf009a 996 *
gmehmet 1:f60eafbf009a 997 */
gmehmet 1:f60eafbf009a 998 int max30001_Disable_LeadON(void);
gmehmet 1:f60eafbf009a 999
gmehmet 1:f60eafbf009a 1000 /**
gmehmet 1:f60eafbf009a 1001 *
gmehmet 1:f60eafbf009a 1002 * @brief This function is toggled every 2 seconds to switch between ECG Lead ON and BIOZ Lead ON detect
gmehmet 1:f60eafbf009a 1003 * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles.
gmehmet 1:f60eafbf009a 1004 * @param CurrentTime - This gets fed the time by RTC_GetValue function
gmehmet 1:f60eafbf009a 1005 *
gmehmet 1:f60eafbf009a 1006 */
gmehmet 1:f60eafbf009a 1007 void max30001_ServiceLeadON(uint32_t currentTime);
gmehmet 1:f60eafbf009a 1008
gmehmet 1:f60eafbf009a 1009 /**
gmehmet 1:f60eafbf009a 1010 *
gmehmet 1:f60eafbf009a 1011 * @brief This function is toggled every 2 seconds to switch between ECG DC Lead Off and BIOZ DC Lead Off
gmehmet 1:f60eafbf009a 1012 * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles.
gmehmet 1:f60eafbf009a 1013 * @param CurrentTime - This gets fed the time by RTC_GetValue function
gmehmet 1:f60eafbf009a 1014 *
gmehmet 1:f60eafbf009a 1015 */
gmehmet 1:f60eafbf009a 1016 void max30001_ServiceLeadoff(uint32_t currentTime);
gmehmet 1:f60eafbf009a 1017
gmehmet 1:f60eafbf009a 1018 /**
gmehmet 1:f60eafbf009a 1019 *
gmehmet 1:f60eafbf009a 1020 * @brief This function sets current RtoR values and fmstr values in a pointer structure
gmehmet 1:f60eafbf009a 1021 * @param hspValMax30001 - Pointer to a structure where to store the values
gmehmet 1:f60eafbf009a 1022 *
gmehmet 1:f60eafbf009a 1023 */
gmehmet 1:f60eafbf009a 1024 void max30001_ReadHeartrateData(max30001_t *_hspValMax30001);
gmehmet 1:f60eafbf009a 1025
gmehmet 1:f60eafbf009a 1026 /**
gmehmet 1:f60eafbf009a 1027 * @brief type definition for data interrupt
gmehmet 1:f60eafbf009a 1028 */
gmehmet 1:f60eafbf009a 1029 typedef void (*PtrFunction)(uint32_t id, uint32_t *buffer, uint32_t length);
gmehmet 1:f60eafbf009a 1030
gmehmet 1:f60eafbf009a 1031 /**
gmehmet 1:f60eafbf009a 1032 * @brief Used to connect a callback for when interrupt data is available
gmehmet 1:f60eafbf009a 1033 */
gmehmet 1:f60eafbf009a 1034 void onDataAvailable(PtrFunction _onDataAvailable);
gmehmet 1:f60eafbf009a 1035
gmehmet 1:f60eafbf009a 1036 static MAX30001 *instance;
gmehmet 1:f60eafbf009a 1037
gmehmet 1:f60eafbf009a 1038 /// Interrupt status tracking variable
gmehmet 1:f60eafbf009a 1039 bool m_max30001_int_happened_;
gmehmet 1:f60eafbf009a 1040
gmehmet 1:f60eafbf009a 1041
gmehmet 1:f60eafbf009a 1042 private:
gmehmet 1:f60eafbf009a 1043 void dataAvailable(uint32_t id, uint32_t *buffer, uint32_t length);
gmehmet 1:f60eafbf009a 1044 /// interrupt handler for async spi events
gmehmet 1:f60eafbf009a 1045 static void spiHandler(int events);
gmehmet 1:f60eafbf009a 1046 /// wrapper method to transmit and recieve SPI data
gmehmet 1:f60eafbf009a 1047 int SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size, uint8_t *rx_buf,
gmehmet 1:f60eafbf009a 1048 uint32_t rx_size);
gmehmet 1:f60eafbf009a 1049 uint32_t readPace(int group, uint8_t* result);
gmehmet 1:f60eafbf009a 1050
gmehmet 1:f60eafbf009a 1051 //jjj 14MAR17
gmehmet 1:f60eafbf009a 1052 //pointer to DigitalOut for cs
gmehmet 1:f60eafbf009a 1053 DigitalOut * m_cs;
gmehmet 1:f60eafbf009a 1054 //jjj
gmehmet 1:f60eafbf009a 1055 /// pointer to mbed SPI object
gmehmet 1:f60eafbf009a 1056 SPI *m_spi;
gmehmet 1:f60eafbf009a 1057 /// is this object the owner of the spi object
gmehmet 1:f60eafbf009a 1058 bool spi_owner;
gmehmet 1:f60eafbf009a 1059 /// buffer to use for async transfers
gmehmet 1:f60eafbf009a 1060 uint8_t buffer[ASYNC_SPI_BUFFER_SIZE];
gmehmet 1:f60eafbf009a 1061 /// function pointer to the async callback
gmehmet 1:f60eafbf009a 1062 event_callback_t functionpointer;
gmehmet 1:f60eafbf009a 1063 /// callback function when interrupt data is available
gmehmet 1:f60eafbf009a 1064 PtrFunction onDataAvailableCallback;
gmehmet 1:f60eafbf009a 1065
gmehmet 1:f60eafbf009a 1066 }; // End of MAX30001 Class
gmehmet 1:f60eafbf009a 1067
gmehmet 1:f60eafbf009a 1068 /**
gmehmet 1:f60eafbf009a 1069 * @brief Preventive measure used to dismiss interrupts that fire too early during
gmehmet 1:f60eafbf009a 1070 * @brief initialization on INTB line
gmehmet 1:f60eafbf009a 1071 *
gmehmet 1:f60eafbf009a 1072 */
gmehmet 1:f60eafbf009a 1073 void MAX30001Mid_IntB_Handler(void);
gmehmet 1:f60eafbf009a 1074
gmehmet 1:f60eafbf009a 1075 /**
gmehmet 1:f60eafbf009a 1076 * @brief Preventive measure used to dismiss interrupts that fire too early during
gmehmet 1:f60eafbf009a 1077 * @brief initialization on INT2B line
gmehmet 1:f60eafbf009a 1078 *
gmehmet 1:f60eafbf009a 1079 */
gmehmet 1:f60eafbf009a 1080 void MAX30001Mid_Int2B_Handler(void);
gmehmet 1:f60eafbf009a 1081
gmehmet 1:f60eafbf009a 1082 /**
gmehmet 1:f60eafbf009a 1083 * @brief Allows Interrupts to be accepted as valid.
gmehmet 1:f60eafbf009a 1084 * @param state: 1-Allow interrupts, Any-Don't allow interrupts.
gmehmet 1:f60eafbf009a 1085 *
gmehmet 1:f60eafbf009a 1086 */
gmehmet 1:f60eafbf009a 1087 void MAX30001_AllowInterrupts(int state);
gmehmet 1:f60eafbf009a 1088
gmehmet 1:f60eafbf009a 1089 #endif /* MAX30001_H_ */