Thierry Pébayle / mbed-src-KL05Z-internal-clk

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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma.h@525:c320967f86b9, 2015-04-28 (annotated)

Committer:
mbed_official
Date:
Tue Apr 28 11:45:12 2015 +0100
Revision:
525:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553



Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/



Add in Silicon Labs targets with asynchronous API support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 525:c320967f86b9 1 /**************************************************************************//**
mbed_official 525:c320967f86b9 2 * @file efm32gg_dma.h
mbed_official 525:c320967f86b9 3 * @brief EFM32GG_DMA register and bit field definitions
mbed_official 525:c320967f86b9 4 * @version 3.20.6
mbed_official 525:c320967f86b9 5 ******************************************************************************
mbed_official 525:c320967f86b9 6 * @section License
mbed_official 525:c320967f86b9 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
mbed_official 525:c320967f86b9 8 ******************************************************************************
mbed_official 525:c320967f86b9 9 *
mbed_official 525:c320967f86b9 10 * Permission is granted to anyone to use this software for any purpose,
mbed_official 525:c320967f86b9 11 * including commercial applications, and to alter it and redistribute it
mbed_official 525:c320967f86b9 12 * freely, subject to the following restrictions:
mbed_official 525:c320967f86b9 13 *
mbed_official 525:c320967f86b9 14 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 525:c320967f86b9 15 * claim that you wrote the original software.@n
mbed_official 525:c320967f86b9 16 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 525:c320967f86b9 17 * misrepresented as being the original software.@n
mbed_official 525:c320967f86b9 18 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 525:c320967f86b9 19 *
mbed_official 525:c320967f86b9 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
mbed_official 525:c320967f86b9 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
mbed_official 525:c320967f86b9 22 * providing the Software "AS IS", with no express or implied warranties of any
mbed_official 525:c320967f86b9 23 * kind, including, but not limited to, any implied warranties of
mbed_official 525:c320967f86b9 24 * merchantability or fitness for any particular purpose or warranties against
mbed_official 525:c320967f86b9 25 * infringement of any proprietary rights of a third party.
mbed_official 525:c320967f86b9 26 *
mbed_official 525:c320967f86b9 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
mbed_official 525:c320967f86b9 28 * incidental, or special damages, or any other relief, or for any claim by
mbed_official 525:c320967f86b9 29 * any third party, arising from your use of this Software.
mbed_official 525:c320967f86b9 30 *
mbed_official 525:c320967f86b9 31 *****************************************************************************/
mbed_official 525:c320967f86b9 32 /**************************************************************************//**
mbed_official 525:c320967f86b9 33 * @defgroup EFM32GG_DMA
mbed_official 525:c320967f86b9 34 * @{
mbed_official 525:c320967f86b9 35 * @brief EFM32GG_DMA Register Declaration
mbed_official 525:c320967f86b9 36 *****************************************************************************/
mbed_official 525:c320967f86b9 37 typedef struct
mbed_official 525:c320967f86b9 38 {
mbed_official 525:c320967f86b9 39 __I uint32_t STATUS; /**< DMA Status Registers */
mbed_official 525:c320967f86b9 40 __O uint32_t CONFIG; /**< DMA Configuration Register */
mbed_official 525:c320967f86b9 41 __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
mbed_official 525:c320967f86b9 42 __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
mbed_official 525:c320967f86b9 43 __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
mbed_official 525:c320967f86b9 44 __O uint32_t CHSWREQ; /**< Channel Software Request Register */
mbed_official 525:c320967f86b9 45 __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
mbed_official 525:c320967f86b9 46 __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
mbed_official 525:c320967f86b9 47 __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
mbed_official 525:c320967f86b9 48 __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
mbed_official 525:c320967f86b9 49 __IO uint32_t CHENS; /**< Channel Enable Set Register */
mbed_official 525:c320967f86b9 50 __O uint32_t CHENC; /**< Channel Enable Clear Register */
mbed_official 525:c320967f86b9 51 __IO uint32_t CHALTS; /**< Channel Alternate Set Register */
mbed_official 525:c320967f86b9 52 __O uint32_t CHALTC; /**< Channel Alternate Clear Register */
mbed_official 525:c320967f86b9 53 __IO uint32_t CHPRIS; /**< Channel Priority Set Register */
mbed_official 525:c320967f86b9 54 __O uint32_t CHPRIC; /**< Channel Priority Clear Register */
mbed_official 525:c320967f86b9 55 uint32_t RESERVED0[3]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 56 __IO uint32_t ERRORC; /**< Bus Error Clear Register */
mbed_official 525:c320967f86b9 57
mbed_official 525:c320967f86b9 58 uint32_t RESERVED1[880]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 59 __I uint32_t CHREQSTATUS; /**< Channel Request Status */
mbed_official 525:c320967f86b9 60 uint32_t RESERVED2[1]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 61 __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
mbed_official 525:c320967f86b9 62
mbed_official 525:c320967f86b9 63 uint32_t RESERVED3[121]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 64 __I uint32_t IF; /**< Interrupt Flag Register */
mbed_official 525:c320967f86b9 65 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
mbed_official 525:c320967f86b9 66 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
mbed_official 525:c320967f86b9 67 __IO uint32_t IEN; /**< Interrupt Enable register */
mbed_official 525:c320967f86b9 68 __IO uint32_t CTRL; /**< DMA Control Register */
mbed_official 525:c320967f86b9 69 __IO uint32_t RDS; /**< DMA Retain Descriptor State */
mbed_official 525:c320967f86b9 70
mbed_official 525:c320967f86b9 71 uint32_t RESERVED4[2]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 72 __IO uint32_t LOOP0; /**< Channel 0 Loop Register */
mbed_official 525:c320967f86b9 73 __IO uint32_t LOOP1; /**< Channel 1 Loop Register */
mbed_official 525:c320967f86b9 74 uint32_t RESERVED5[14]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 75 __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */
mbed_official 525:c320967f86b9 76
mbed_official 525:c320967f86b9 77 uint32_t RESERVED6[39]; /**< Reserved registers */
mbed_official 525:c320967f86b9 78
mbed_official 525:c320967f86b9 79 DMA_CH_TypeDef CH[12]; /**< Channel registers */
mbed_official 525:c320967f86b9 80 } DMA_TypeDef; /** @} */
mbed_official 525:c320967f86b9 81
mbed_official 525:c320967f86b9 82 /**************************************************************************//**
mbed_official 525:c320967f86b9 83 * @defgroup EFM32GG_DMA_BitFields
mbed_official 525:c320967f86b9 84 * @{
mbed_official 525:c320967f86b9 85 *****************************************************************************/
mbed_official 525:c320967f86b9 86
mbed_official 525:c320967f86b9 87 /* Bit fields for DMA STATUS */
mbed_official 525:c320967f86b9 88 #define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */
mbed_official 525:c320967f86b9 89 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
mbed_official 525:c320967f86b9 90 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
mbed_official 525:c320967f86b9 91 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
mbed_official 525:c320967f86b9 92 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
mbed_official 525:c320967f86b9 93 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
mbed_official 525:c320967f86b9 94 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
mbed_official 525:c320967f86b9 95 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
mbed_official 525:c320967f86b9 96 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
mbed_official 525:c320967f86b9 97 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
mbed_official 525:c320967f86b9 98 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
mbed_official 525:c320967f86b9 99 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 100 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
mbed_official 525:c320967f86b9 101 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
mbed_official 525:c320967f86b9 102 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 103 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 104 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
mbed_official 525:c320967f86b9 105 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 106 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
mbed_official 525:c320967f86b9 107 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
mbed_official 525:c320967f86b9 108 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
mbed_official 525:c320967f86b9 109 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
mbed_official 525:c320967f86b9 110 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
mbed_official 525:c320967f86b9 111 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 112 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
mbed_official 525:c320967f86b9 113 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
mbed_official 525:c320967f86b9 114 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 115 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 116 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
mbed_official 525:c320967f86b9 117 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
mbed_official 525:c320967f86b9 118 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
mbed_official 525:c320967f86b9 119 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
mbed_official 525:c320967f86b9 120 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
mbed_official 525:c320967f86b9 121 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
mbed_official 525:c320967f86b9 122 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
mbed_official 525:c320967f86b9 123 #define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */
mbed_official 525:c320967f86b9 124 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
mbed_official 525:c320967f86b9 125
mbed_official 525:c320967f86b9 126 /* Bit fields for DMA CONFIG */
mbed_official 525:c320967f86b9 127 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
mbed_official 525:c320967f86b9 128 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
mbed_official 525:c320967f86b9 129 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
mbed_official 525:c320967f86b9 130 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
mbed_official 525:c320967f86b9 131 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
mbed_official 525:c320967f86b9 132 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
mbed_official 525:c320967f86b9 133 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
mbed_official 525:c320967f86b9 134 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
mbed_official 525:c320967f86b9 135 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
mbed_official 525:c320967f86b9 136 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
mbed_official 525:c320967f86b9 137 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
mbed_official 525:c320967f86b9 138 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
mbed_official 525:c320967f86b9 139
mbed_official 525:c320967f86b9 140 /* Bit fields for DMA CTRLBASE */
mbed_official 525:c320967f86b9 141 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
mbed_official 525:c320967f86b9 142 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
mbed_official 525:c320967f86b9 143 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
mbed_official 525:c320967f86b9 144 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
mbed_official 525:c320967f86b9 145 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
mbed_official 525:c320967f86b9 146 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
mbed_official 525:c320967f86b9 147
mbed_official 525:c320967f86b9 148 /* Bit fields for DMA ALTCTRLBASE */
mbed_official 525:c320967f86b9 149 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */
mbed_official 525:c320967f86b9 150 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
mbed_official 525:c320967f86b9 151 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
mbed_official 525:c320967f86b9 152 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
mbed_official 525:c320967f86b9 153 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
mbed_official 525:c320967f86b9 154 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
mbed_official 525:c320967f86b9 155
mbed_official 525:c320967f86b9 156 /* Bit fields for DMA CHWAITSTATUS */
mbed_official 525:c320967f86b9 157 #define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 158 #define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 159 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
mbed_official 525:c320967f86b9 160 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
mbed_official 525:c320967f86b9 161 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
mbed_official 525:c320967f86b9 162 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 163 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 164 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
mbed_official 525:c320967f86b9 165 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
mbed_official 525:c320967f86b9 166 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
mbed_official 525:c320967f86b9 167 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 168 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 169 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
mbed_official 525:c320967f86b9 170 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
mbed_official 525:c320967f86b9 171 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
mbed_official 525:c320967f86b9 172 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 173 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 174 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
mbed_official 525:c320967f86b9 175 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
mbed_official 525:c320967f86b9 176 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
mbed_official 525:c320967f86b9 177 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 178 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 179 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
mbed_official 525:c320967f86b9 180 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
mbed_official 525:c320967f86b9 181 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
mbed_official 525:c320967f86b9 182 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 183 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 184 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
mbed_official 525:c320967f86b9 185 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
mbed_official 525:c320967f86b9 186 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
mbed_official 525:c320967f86b9 187 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 188 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 189 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */
mbed_official 525:c320967f86b9 190 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */
mbed_official 525:c320967f86b9 191 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */
mbed_official 525:c320967f86b9 192 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 193 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 194 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */
mbed_official 525:c320967f86b9 195 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */
mbed_official 525:c320967f86b9 196 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */
mbed_official 525:c320967f86b9 197 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 198 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 199 #define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */
mbed_official 525:c320967f86b9 200 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */
mbed_official 525:c320967f86b9 201 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */
mbed_official 525:c320967f86b9 202 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 203 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 204 #define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */
mbed_official 525:c320967f86b9 205 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */
mbed_official 525:c320967f86b9 206 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */
mbed_official 525:c320967f86b9 207 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 208 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 209 #define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */
mbed_official 525:c320967f86b9 210 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */
mbed_official 525:c320967f86b9 211 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */
mbed_official 525:c320967f86b9 212 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 213 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 214 #define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */
mbed_official 525:c320967f86b9 215 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */
mbed_official 525:c320967f86b9 216 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */
mbed_official 525:c320967f86b9 217 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 218 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
mbed_official 525:c320967f86b9 219
mbed_official 525:c320967f86b9 220 /* Bit fields for DMA CHSWREQ */
mbed_official 525:c320967f86b9 221 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 222 #define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 223 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
mbed_official 525:c320967f86b9 224 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
mbed_official 525:c320967f86b9 225 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
mbed_official 525:c320967f86b9 226 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 227 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 228 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
mbed_official 525:c320967f86b9 229 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
mbed_official 525:c320967f86b9 230 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
mbed_official 525:c320967f86b9 231 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 232 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 233 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
mbed_official 525:c320967f86b9 234 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
mbed_official 525:c320967f86b9 235 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
mbed_official 525:c320967f86b9 236 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 237 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 238 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
mbed_official 525:c320967f86b9 239 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
mbed_official 525:c320967f86b9 240 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
mbed_official 525:c320967f86b9 241 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 242 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 243 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
mbed_official 525:c320967f86b9 244 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
mbed_official 525:c320967f86b9 245 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
mbed_official 525:c320967f86b9 246 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 247 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 248 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
mbed_official 525:c320967f86b9 249 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
mbed_official 525:c320967f86b9 250 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
mbed_official 525:c320967f86b9 251 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 252 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 253 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */
mbed_official 525:c320967f86b9 254 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */
mbed_official 525:c320967f86b9 255 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */
mbed_official 525:c320967f86b9 256 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 257 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 258 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */
mbed_official 525:c320967f86b9 259 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */
mbed_official 525:c320967f86b9 260 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */
mbed_official 525:c320967f86b9 261 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 262 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 263 #define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */
mbed_official 525:c320967f86b9 264 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */
mbed_official 525:c320967f86b9 265 #define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */
mbed_official 525:c320967f86b9 266 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 267 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 268 #define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */
mbed_official 525:c320967f86b9 269 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */
mbed_official 525:c320967f86b9 270 #define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */
mbed_official 525:c320967f86b9 271 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 272 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 273 #define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */
mbed_official 525:c320967f86b9 274 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */
mbed_official 525:c320967f86b9 275 #define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */
mbed_official 525:c320967f86b9 276 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 277 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 278 #define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */
mbed_official 525:c320967f86b9 279 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */
mbed_official 525:c320967f86b9 280 #define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */
mbed_official 525:c320967f86b9 281 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 282 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
mbed_official 525:c320967f86b9 283
mbed_official 525:c320967f86b9 284 /* Bit fields for DMA CHUSEBURSTS */
mbed_official 525:c320967f86b9 285 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 286 #define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 287 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
mbed_official 525:c320967f86b9 288 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
mbed_official 525:c320967f86b9 289 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
mbed_official 525:c320967f86b9 290 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 291 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 292 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 293 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 294 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 295 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 296 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
mbed_official 525:c320967f86b9 297 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
mbed_official 525:c320967f86b9 298 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
mbed_official 525:c320967f86b9 299 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 300 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 301 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
mbed_official 525:c320967f86b9 302 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
mbed_official 525:c320967f86b9 303 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
mbed_official 525:c320967f86b9 304 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 305 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 306 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
mbed_official 525:c320967f86b9 307 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
mbed_official 525:c320967f86b9 308 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
mbed_official 525:c320967f86b9 309 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 310 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 311 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
mbed_official 525:c320967f86b9 312 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
mbed_official 525:c320967f86b9 313 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
mbed_official 525:c320967f86b9 314 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 315 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 316 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
mbed_official 525:c320967f86b9 317 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
mbed_official 525:c320967f86b9 318 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
mbed_official 525:c320967f86b9 319 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 320 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 321 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */
mbed_official 525:c320967f86b9 322 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */
mbed_official 525:c320967f86b9 323 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */
mbed_official 525:c320967f86b9 324 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 325 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 326 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */
mbed_official 525:c320967f86b9 327 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */
mbed_official 525:c320967f86b9 328 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */
mbed_official 525:c320967f86b9 329 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 330 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 331 #define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */
mbed_official 525:c320967f86b9 332 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */
mbed_official 525:c320967f86b9 333 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */
mbed_official 525:c320967f86b9 334 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 335 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 336 #define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */
mbed_official 525:c320967f86b9 337 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */
mbed_official 525:c320967f86b9 338 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */
mbed_official 525:c320967f86b9 339 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 340 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 341 #define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */
mbed_official 525:c320967f86b9 342 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */
mbed_official 525:c320967f86b9 343 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */
mbed_official 525:c320967f86b9 344 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 345 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 346 #define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */
mbed_official 525:c320967f86b9 347 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */
mbed_official 525:c320967f86b9 348 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */
mbed_official 525:c320967f86b9 349 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 350 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
mbed_official 525:c320967f86b9 351
mbed_official 525:c320967f86b9 352 /* Bit fields for DMA CHUSEBURSTC */
mbed_official 525:c320967f86b9 353 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 354 #define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 355 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
mbed_official 525:c320967f86b9 356 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
mbed_official 525:c320967f86b9 357 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
mbed_official 525:c320967f86b9 358 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 359 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 360 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
mbed_official 525:c320967f86b9 361 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
mbed_official 525:c320967f86b9 362 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
mbed_official 525:c320967f86b9 363 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 364 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 365 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
mbed_official 525:c320967f86b9 366 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
mbed_official 525:c320967f86b9 367 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
mbed_official 525:c320967f86b9 368 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 369 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 370 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
mbed_official 525:c320967f86b9 371 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
mbed_official 525:c320967f86b9 372 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
mbed_official 525:c320967f86b9 373 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 374 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 375 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
mbed_official 525:c320967f86b9 376 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
mbed_official 525:c320967f86b9 377 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
mbed_official 525:c320967f86b9 378 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 379 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 380 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
mbed_official 525:c320967f86b9 381 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
mbed_official 525:c320967f86b9 382 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
mbed_official 525:c320967f86b9 383 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 384 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 385 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */
mbed_official 525:c320967f86b9 386 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */
mbed_official 525:c320967f86b9 387 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */
mbed_official 525:c320967f86b9 388 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 389 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 390 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */
mbed_official 525:c320967f86b9 391 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */
mbed_official 525:c320967f86b9 392 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */
mbed_official 525:c320967f86b9 393 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 394 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 395 #define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */
mbed_official 525:c320967f86b9 396 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */
mbed_official 525:c320967f86b9 397 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */
mbed_official 525:c320967f86b9 398 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 399 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 400 #define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */
mbed_official 525:c320967f86b9 401 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */
mbed_official 525:c320967f86b9 402 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */
mbed_official 525:c320967f86b9 403 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 404 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 405 #define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */
mbed_official 525:c320967f86b9 406 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */
mbed_official 525:c320967f86b9 407 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */
mbed_official 525:c320967f86b9 408 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 409 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 410 #define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */
mbed_official 525:c320967f86b9 411 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */
mbed_official 525:c320967f86b9 412 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */
mbed_official 525:c320967f86b9 413 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 414 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
mbed_official 525:c320967f86b9 415
mbed_official 525:c320967f86b9 416 /* Bit fields for DMA CHREQMASKS */
mbed_official 525:c320967f86b9 417 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 418 #define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 419 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
mbed_official 525:c320967f86b9 420 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
mbed_official 525:c320967f86b9 421 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
mbed_official 525:c320967f86b9 422 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 423 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 424 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
mbed_official 525:c320967f86b9 425 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
mbed_official 525:c320967f86b9 426 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
mbed_official 525:c320967f86b9 427 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 428 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 429 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
mbed_official 525:c320967f86b9 430 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
mbed_official 525:c320967f86b9 431 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
mbed_official 525:c320967f86b9 432 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 433 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 434 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
mbed_official 525:c320967f86b9 435 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
mbed_official 525:c320967f86b9 436 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
mbed_official 525:c320967f86b9 437 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 438 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 439 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
mbed_official 525:c320967f86b9 440 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
mbed_official 525:c320967f86b9 441 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
mbed_official 525:c320967f86b9 442 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 443 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 444 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
mbed_official 525:c320967f86b9 445 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
mbed_official 525:c320967f86b9 446 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
mbed_official 525:c320967f86b9 447 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 448 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 449 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */
mbed_official 525:c320967f86b9 450 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */
mbed_official 525:c320967f86b9 451 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */
mbed_official 525:c320967f86b9 452 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 453 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 454 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */
mbed_official 525:c320967f86b9 455 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */
mbed_official 525:c320967f86b9 456 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */
mbed_official 525:c320967f86b9 457 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 458 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 459 #define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */
mbed_official 525:c320967f86b9 460 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */
mbed_official 525:c320967f86b9 461 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */
mbed_official 525:c320967f86b9 462 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 463 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 464 #define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */
mbed_official 525:c320967f86b9 465 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */
mbed_official 525:c320967f86b9 466 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */
mbed_official 525:c320967f86b9 467 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 468 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 469 #define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */
mbed_official 525:c320967f86b9 470 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */
mbed_official 525:c320967f86b9 471 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */
mbed_official 525:c320967f86b9 472 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 473 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 474 #define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */
mbed_official 525:c320967f86b9 475 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */
mbed_official 525:c320967f86b9 476 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */
mbed_official 525:c320967f86b9 477 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 478 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
mbed_official 525:c320967f86b9 479
mbed_official 525:c320967f86b9 480 /* Bit fields for DMA CHREQMASKC */
mbed_official 525:c320967f86b9 481 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 482 #define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 483 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
mbed_official 525:c320967f86b9 484 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
mbed_official 525:c320967f86b9 485 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
mbed_official 525:c320967f86b9 486 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 487 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 488 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
mbed_official 525:c320967f86b9 489 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
mbed_official 525:c320967f86b9 490 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
mbed_official 525:c320967f86b9 491 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 492 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 493 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
mbed_official 525:c320967f86b9 494 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
mbed_official 525:c320967f86b9 495 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
mbed_official 525:c320967f86b9 496 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 497 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 498 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
mbed_official 525:c320967f86b9 499 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
mbed_official 525:c320967f86b9 500 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
mbed_official 525:c320967f86b9 501 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 502 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 503 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
mbed_official 525:c320967f86b9 504 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
mbed_official 525:c320967f86b9 505 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
mbed_official 525:c320967f86b9 506 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 507 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 508 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
mbed_official 525:c320967f86b9 509 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
mbed_official 525:c320967f86b9 510 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
mbed_official 525:c320967f86b9 511 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 512 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 513 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */
mbed_official 525:c320967f86b9 514 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */
mbed_official 525:c320967f86b9 515 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */
mbed_official 525:c320967f86b9 516 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 517 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 518 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */
mbed_official 525:c320967f86b9 519 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */
mbed_official 525:c320967f86b9 520 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */
mbed_official 525:c320967f86b9 521 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 522 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 523 #define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */
mbed_official 525:c320967f86b9 524 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */
mbed_official 525:c320967f86b9 525 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */
mbed_official 525:c320967f86b9 526 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 527 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 528 #define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */
mbed_official 525:c320967f86b9 529 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */
mbed_official 525:c320967f86b9 530 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */
mbed_official 525:c320967f86b9 531 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 532 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 533 #define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */
mbed_official 525:c320967f86b9 534 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */
mbed_official 525:c320967f86b9 535 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */
mbed_official 525:c320967f86b9 536 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 537 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 538 #define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */
mbed_official 525:c320967f86b9 539 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */
mbed_official 525:c320967f86b9 540 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */
mbed_official 525:c320967f86b9 541 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 542 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
mbed_official 525:c320967f86b9 543
mbed_official 525:c320967f86b9 544 /* Bit fields for DMA CHENS */
mbed_official 525:c320967f86b9 545 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
mbed_official 525:c320967f86b9 546 #define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */
mbed_official 525:c320967f86b9 547 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
mbed_official 525:c320967f86b9 548 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
mbed_official 525:c320967f86b9 549 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
mbed_official 525:c320967f86b9 550 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 551 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 552 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
mbed_official 525:c320967f86b9 553 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
mbed_official 525:c320967f86b9 554 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
mbed_official 525:c320967f86b9 555 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 556 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 557 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
mbed_official 525:c320967f86b9 558 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
mbed_official 525:c320967f86b9 559 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
mbed_official 525:c320967f86b9 560 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 561 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 562 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
mbed_official 525:c320967f86b9 563 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
mbed_official 525:c320967f86b9 564 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
mbed_official 525:c320967f86b9 565 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 566 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 567 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
mbed_official 525:c320967f86b9 568 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
mbed_official 525:c320967f86b9 569 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
mbed_official 525:c320967f86b9 570 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 571 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 572 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
mbed_official 525:c320967f86b9 573 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
mbed_official 525:c320967f86b9 574 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
mbed_official 525:c320967f86b9 575 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 576 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 577 #define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */
mbed_official 525:c320967f86b9 578 #define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */
mbed_official 525:c320967f86b9 579 #define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */
mbed_official 525:c320967f86b9 580 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 581 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 582 #define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */
mbed_official 525:c320967f86b9 583 #define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */
mbed_official 525:c320967f86b9 584 #define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */
mbed_official 525:c320967f86b9 585 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 586 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 587 #define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */
mbed_official 525:c320967f86b9 588 #define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */
mbed_official 525:c320967f86b9 589 #define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */
mbed_official 525:c320967f86b9 590 #define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 591 #define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 592 #define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */
mbed_official 525:c320967f86b9 593 #define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */
mbed_official 525:c320967f86b9 594 #define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */
mbed_official 525:c320967f86b9 595 #define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 596 #define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 597 #define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */
mbed_official 525:c320967f86b9 598 #define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */
mbed_official 525:c320967f86b9 599 #define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */
mbed_official 525:c320967f86b9 600 #define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 601 #define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 602 #define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */
mbed_official 525:c320967f86b9 603 #define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */
mbed_official 525:c320967f86b9 604 #define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */
mbed_official 525:c320967f86b9 605 #define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 606 #define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */
mbed_official 525:c320967f86b9 607
mbed_official 525:c320967f86b9 608 /* Bit fields for DMA CHENC */
mbed_official 525:c320967f86b9 609 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
mbed_official 525:c320967f86b9 610 #define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */
mbed_official 525:c320967f86b9 611 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
mbed_official 525:c320967f86b9 612 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
mbed_official 525:c320967f86b9 613 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
mbed_official 525:c320967f86b9 614 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 615 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 616 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
mbed_official 525:c320967f86b9 617 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
mbed_official 525:c320967f86b9 618 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
mbed_official 525:c320967f86b9 619 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 620 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 621 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
mbed_official 525:c320967f86b9 622 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
mbed_official 525:c320967f86b9 623 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
mbed_official 525:c320967f86b9 624 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 625 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 626 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
mbed_official 525:c320967f86b9 627 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
mbed_official 525:c320967f86b9 628 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
mbed_official 525:c320967f86b9 629 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 630 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 631 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
mbed_official 525:c320967f86b9 632 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
mbed_official 525:c320967f86b9 633 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
mbed_official 525:c320967f86b9 634 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 635 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 636 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
mbed_official 525:c320967f86b9 637 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
mbed_official 525:c320967f86b9 638 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
mbed_official 525:c320967f86b9 639 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 640 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 641 #define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */
mbed_official 525:c320967f86b9 642 #define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */
mbed_official 525:c320967f86b9 643 #define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */
mbed_official 525:c320967f86b9 644 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 645 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 646 #define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */
mbed_official 525:c320967f86b9 647 #define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */
mbed_official 525:c320967f86b9 648 #define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */
mbed_official 525:c320967f86b9 649 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 650 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 651 #define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */
mbed_official 525:c320967f86b9 652 #define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */
mbed_official 525:c320967f86b9 653 #define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */
mbed_official 525:c320967f86b9 654 #define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 655 #define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 656 #define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */
mbed_official 525:c320967f86b9 657 #define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */
mbed_official 525:c320967f86b9 658 #define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */
mbed_official 525:c320967f86b9 659 #define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 660 #define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 661 #define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */
mbed_official 525:c320967f86b9 662 #define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */
mbed_official 525:c320967f86b9 663 #define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */
mbed_official 525:c320967f86b9 664 #define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 665 #define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 666 #define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */
mbed_official 525:c320967f86b9 667 #define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */
mbed_official 525:c320967f86b9 668 #define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */
mbed_official 525:c320967f86b9 669 #define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 670 #define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */
mbed_official 525:c320967f86b9 671
mbed_official 525:c320967f86b9 672 /* Bit fields for DMA CHALTS */
mbed_official 525:c320967f86b9 673 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
mbed_official 525:c320967f86b9 674 #define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */
mbed_official 525:c320967f86b9 675 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
mbed_official 525:c320967f86b9 676 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
mbed_official 525:c320967f86b9 677 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
mbed_official 525:c320967f86b9 678 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 679 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 680 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
mbed_official 525:c320967f86b9 681 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
mbed_official 525:c320967f86b9 682 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
mbed_official 525:c320967f86b9 683 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 684 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 685 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
mbed_official 525:c320967f86b9 686 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
mbed_official 525:c320967f86b9 687 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
mbed_official 525:c320967f86b9 688 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 689 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 690 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
mbed_official 525:c320967f86b9 691 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
mbed_official 525:c320967f86b9 692 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
mbed_official 525:c320967f86b9 693 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 694 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 695 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
mbed_official 525:c320967f86b9 696 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
mbed_official 525:c320967f86b9 697 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
mbed_official 525:c320967f86b9 698 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 699 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 700 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
mbed_official 525:c320967f86b9 701 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
mbed_official 525:c320967f86b9 702 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
mbed_official 525:c320967f86b9 703 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 704 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 705 #define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */
mbed_official 525:c320967f86b9 706 #define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */
mbed_official 525:c320967f86b9 707 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */
mbed_official 525:c320967f86b9 708 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 709 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 710 #define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */
mbed_official 525:c320967f86b9 711 #define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */
mbed_official 525:c320967f86b9 712 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */
mbed_official 525:c320967f86b9 713 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 714 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 715 #define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */
mbed_official 525:c320967f86b9 716 #define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */
mbed_official 525:c320967f86b9 717 #define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */
mbed_official 525:c320967f86b9 718 #define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 719 #define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 720 #define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */
mbed_official 525:c320967f86b9 721 #define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */
mbed_official 525:c320967f86b9 722 #define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */
mbed_official 525:c320967f86b9 723 #define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 724 #define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 725 #define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */
mbed_official 525:c320967f86b9 726 #define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */
mbed_official 525:c320967f86b9 727 #define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */
mbed_official 525:c320967f86b9 728 #define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 729 #define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 730 #define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */
mbed_official 525:c320967f86b9 731 #define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */
mbed_official 525:c320967f86b9 732 #define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */
mbed_official 525:c320967f86b9 733 #define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 734 #define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */
mbed_official 525:c320967f86b9 735
mbed_official 525:c320967f86b9 736 /* Bit fields for DMA CHALTC */
mbed_official 525:c320967f86b9 737 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
mbed_official 525:c320967f86b9 738 #define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */
mbed_official 525:c320967f86b9 739 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
mbed_official 525:c320967f86b9 740 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
mbed_official 525:c320967f86b9 741 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
mbed_official 525:c320967f86b9 742 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 743 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 744 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
mbed_official 525:c320967f86b9 745 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
mbed_official 525:c320967f86b9 746 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
mbed_official 525:c320967f86b9 747 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 748 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 749 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
mbed_official 525:c320967f86b9 750 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
mbed_official 525:c320967f86b9 751 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
mbed_official 525:c320967f86b9 752 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 753 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 754 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
mbed_official 525:c320967f86b9 755 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
mbed_official 525:c320967f86b9 756 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
mbed_official 525:c320967f86b9 757 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 758 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 759 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
mbed_official 525:c320967f86b9 760 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
mbed_official 525:c320967f86b9 761 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
mbed_official 525:c320967f86b9 762 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 763 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 764 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
mbed_official 525:c320967f86b9 765 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
mbed_official 525:c320967f86b9 766 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
mbed_official 525:c320967f86b9 767 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 768 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 769 #define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */
mbed_official 525:c320967f86b9 770 #define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */
mbed_official 525:c320967f86b9 771 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */
mbed_official 525:c320967f86b9 772 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 773 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 774 #define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */
mbed_official 525:c320967f86b9 775 #define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */
mbed_official 525:c320967f86b9 776 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */
mbed_official 525:c320967f86b9 777 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 778 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 779 #define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */
mbed_official 525:c320967f86b9 780 #define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */
mbed_official 525:c320967f86b9 781 #define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */
mbed_official 525:c320967f86b9 782 #define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 783 #define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 784 #define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */
mbed_official 525:c320967f86b9 785 #define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */
mbed_official 525:c320967f86b9 786 #define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */
mbed_official 525:c320967f86b9 787 #define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 788 #define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 789 #define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */
mbed_official 525:c320967f86b9 790 #define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */
mbed_official 525:c320967f86b9 791 #define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */
mbed_official 525:c320967f86b9 792 #define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 793 #define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 794 #define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */
mbed_official 525:c320967f86b9 795 #define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */
mbed_official 525:c320967f86b9 796 #define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */
mbed_official 525:c320967f86b9 797 #define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 798 #define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */
mbed_official 525:c320967f86b9 799
mbed_official 525:c320967f86b9 800 /* Bit fields for DMA CHPRIS */
mbed_official 525:c320967f86b9 801 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
mbed_official 525:c320967f86b9 802 #define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */
mbed_official 525:c320967f86b9 803 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
mbed_official 525:c320967f86b9 804 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
mbed_official 525:c320967f86b9 805 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
mbed_official 525:c320967f86b9 806 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 807 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 808 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
mbed_official 525:c320967f86b9 809 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
mbed_official 525:c320967f86b9 810 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
mbed_official 525:c320967f86b9 811 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 812 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 813 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
mbed_official 525:c320967f86b9 814 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
mbed_official 525:c320967f86b9 815 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
mbed_official 525:c320967f86b9 816 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 817 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 818 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
mbed_official 525:c320967f86b9 819 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
mbed_official 525:c320967f86b9 820 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
mbed_official 525:c320967f86b9 821 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 822 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 823 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
mbed_official 525:c320967f86b9 824 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
mbed_official 525:c320967f86b9 825 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
mbed_official 525:c320967f86b9 826 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 827 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 828 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
mbed_official 525:c320967f86b9 829 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
mbed_official 525:c320967f86b9 830 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
mbed_official 525:c320967f86b9 831 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 832 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 833 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */
mbed_official 525:c320967f86b9 834 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */
mbed_official 525:c320967f86b9 835 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */
mbed_official 525:c320967f86b9 836 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 837 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 838 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */
mbed_official 525:c320967f86b9 839 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */
mbed_official 525:c320967f86b9 840 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */
mbed_official 525:c320967f86b9 841 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 842 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 843 #define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */
mbed_official 525:c320967f86b9 844 #define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */
mbed_official 525:c320967f86b9 845 #define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */
mbed_official 525:c320967f86b9 846 #define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 847 #define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 848 #define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */
mbed_official 525:c320967f86b9 849 #define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */
mbed_official 525:c320967f86b9 850 #define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */
mbed_official 525:c320967f86b9 851 #define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 852 #define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 853 #define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */
mbed_official 525:c320967f86b9 854 #define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */
mbed_official 525:c320967f86b9 855 #define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */
mbed_official 525:c320967f86b9 856 #define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 857 #define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 858 #define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */
mbed_official 525:c320967f86b9 859 #define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */
mbed_official 525:c320967f86b9 860 #define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */
mbed_official 525:c320967f86b9 861 #define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 862 #define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */
mbed_official 525:c320967f86b9 863
mbed_official 525:c320967f86b9 864 /* Bit fields for DMA CHPRIC */
mbed_official 525:c320967f86b9 865 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
mbed_official 525:c320967f86b9 866 #define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */
mbed_official 525:c320967f86b9 867 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
mbed_official 525:c320967f86b9 868 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
mbed_official 525:c320967f86b9 869 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
mbed_official 525:c320967f86b9 870 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 871 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 872 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
mbed_official 525:c320967f86b9 873 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
mbed_official 525:c320967f86b9 874 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
mbed_official 525:c320967f86b9 875 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 876 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 877 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
mbed_official 525:c320967f86b9 878 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
mbed_official 525:c320967f86b9 879 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
mbed_official 525:c320967f86b9 880 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 881 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 882 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
mbed_official 525:c320967f86b9 883 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
mbed_official 525:c320967f86b9 884 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
mbed_official 525:c320967f86b9 885 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 886 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 887 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
mbed_official 525:c320967f86b9 888 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
mbed_official 525:c320967f86b9 889 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
mbed_official 525:c320967f86b9 890 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 891 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 892 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
mbed_official 525:c320967f86b9 893 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
mbed_official 525:c320967f86b9 894 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
mbed_official 525:c320967f86b9 895 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 896 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 897 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */
mbed_official 525:c320967f86b9 898 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */
mbed_official 525:c320967f86b9 899 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */
mbed_official 525:c320967f86b9 900 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 901 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 902 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */
mbed_official 525:c320967f86b9 903 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */
mbed_official 525:c320967f86b9 904 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */
mbed_official 525:c320967f86b9 905 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 906 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 907 #define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */
mbed_official 525:c320967f86b9 908 #define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */
mbed_official 525:c320967f86b9 909 #define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */
mbed_official 525:c320967f86b9 910 #define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 911 #define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 912 #define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */
mbed_official 525:c320967f86b9 913 #define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */
mbed_official 525:c320967f86b9 914 #define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */
mbed_official 525:c320967f86b9 915 #define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 916 #define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 917 #define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */
mbed_official 525:c320967f86b9 918 #define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */
mbed_official 525:c320967f86b9 919 #define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */
mbed_official 525:c320967f86b9 920 #define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 921 #define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 922 #define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */
mbed_official 525:c320967f86b9 923 #define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */
mbed_official 525:c320967f86b9 924 #define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */
mbed_official 525:c320967f86b9 925 #define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 926 #define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */
mbed_official 525:c320967f86b9 927
mbed_official 525:c320967f86b9 928 /* Bit fields for DMA ERRORC */
mbed_official 525:c320967f86b9 929 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
mbed_official 525:c320967f86b9 930 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
mbed_official 525:c320967f86b9 931 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
mbed_official 525:c320967f86b9 932 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
mbed_official 525:c320967f86b9 933 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
mbed_official 525:c320967f86b9 934 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
mbed_official 525:c320967f86b9 935 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
mbed_official 525:c320967f86b9 936
mbed_official 525:c320967f86b9 937 /* Bit fields for DMA CHREQSTATUS */
mbed_official 525:c320967f86b9 938 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 939 #define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 940 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
mbed_official 525:c320967f86b9 941 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
mbed_official 525:c320967f86b9 942 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
mbed_official 525:c320967f86b9 943 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 944 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 945 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
mbed_official 525:c320967f86b9 946 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
mbed_official 525:c320967f86b9 947 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
mbed_official 525:c320967f86b9 948 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 949 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 950 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
mbed_official 525:c320967f86b9 951 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
mbed_official 525:c320967f86b9 952 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
mbed_official 525:c320967f86b9 953 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 954 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 955 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
mbed_official 525:c320967f86b9 956 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
mbed_official 525:c320967f86b9 957 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
mbed_official 525:c320967f86b9 958 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 959 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 960 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
mbed_official 525:c320967f86b9 961 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
mbed_official 525:c320967f86b9 962 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
mbed_official 525:c320967f86b9 963 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 964 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 965 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
mbed_official 525:c320967f86b9 966 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
mbed_official 525:c320967f86b9 967 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
mbed_official 525:c320967f86b9 968 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 969 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 970 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */
mbed_official 525:c320967f86b9 971 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */
mbed_official 525:c320967f86b9 972 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */
mbed_official 525:c320967f86b9 973 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 974 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 975 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */
mbed_official 525:c320967f86b9 976 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */
mbed_official 525:c320967f86b9 977 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */
mbed_official 525:c320967f86b9 978 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 979 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 980 #define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */
mbed_official 525:c320967f86b9 981 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */
mbed_official 525:c320967f86b9 982 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */
mbed_official 525:c320967f86b9 983 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 984 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 985 #define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */
mbed_official 525:c320967f86b9 986 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */
mbed_official 525:c320967f86b9 987 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */
mbed_official 525:c320967f86b9 988 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 989 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 990 #define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */
mbed_official 525:c320967f86b9 991 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */
mbed_official 525:c320967f86b9 992 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */
mbed_official 525:c320967f86b9 993 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 994 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 995 #define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */
mbed_official 525:c320967f86b9 996 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */
mbed_official 525:c320967f86b9 997 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */
mbed_official 525:c320967f86b9 998 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 999 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
mbed_official 525:c320967f86b9 1000
mbed_official 525:c320967f86b9 1001 /* Bit fields for DMA CHSREQSTATUS */
mbed_official 525:c320967f86b9 1002 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1003 #define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1004 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
mbed_official 525:c320967f86b9 1005 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
mbed_official 525:c320967f86b9 1006 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
mbed_official 525:c320967f86b9 1007 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1008 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1009 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
mbed_official 525:c320967f86b9 1010 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
mbed_official 525:c320967f86b9 1011 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
mbed_official 525:c320967f86b9 1012 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1013 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1014 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
mbed_official 525:c320967f86b9 1015 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
mbed_official 525:c320967f86b9 1016 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
mbed_official 525:c320967f86b9 1017 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1018 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1019 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
mbed_official 525:c320967f86b9 1020 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
mbed_official 525:c320967f86b9 1021 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
mbed_official 525:c320967f86b9 1022 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1023 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1024 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
mbed_official 525:c320967f86b9 1025 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
mbed_official 525:c320967f86b9 1026 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
mbed_official 525:c320967f86b9 1027 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1028 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1029 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
mbed_official 525:c320967f86b9 1030 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
mbed_official 525:c320967f86b9 1031 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
mbed_official 525:c320967f86b9 1032 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1033 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1034 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */
mbed_official 525:c320967f86b9 1035 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */
mbed_official 525:c320967f86b9 1036 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */
mbed_official 525:c320967f86b9 1037 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1038 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1039 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */
mbed_official 525:c320967f86b9 1040 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */
mbed_official 525:c320967f86b9 1041 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */
mbed_official 525:c320967f86b9 1042 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1043 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1044 #define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */
mbed_official 525:c320967f86b9 1045 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */
mbed_official 525:c320967f86b9 1046 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */
mbed_official 525:c320967f86b9 1047 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1048 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1049 #define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */
mbed_official 525:c320967f86b9 1050 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */
mbed_official 525:c320967f86b9 1051 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */
mbed_official 525:c320967f86b9 1052 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1053 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1054 #define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */
mbed_official 525:c320967f86b9 1055 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */
mbed_official 525:c320967f86b9 1056 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */
mbed_official 525:c320967f86b9 1057 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1058 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1059 #define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */
mbed_official 525:c320967f86b9 1060 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */
mbed_official 525:c320967f86b9 1061 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */
mbed_official 525:c320967f86b9 1062 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1063 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
mbed_official 525:c320967f86b9 1064
mbed_official 525:c320967f86b9 1065 /* Bit fields for DMA IF */
mbed_official 525:c320967f86b9 1066 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
mbed_official 525:c320967f86b9 1067 #define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */
mbed_official 525:c320967f86b9 1068 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1069 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1070 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1071 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1072 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1073 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1074 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1075 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1076 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1077 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1078 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1079 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1080 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1081 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1082 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1083 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1084 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1085 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1086 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1087 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1088 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1089 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1090 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1091 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1092 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1093 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1094 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1095 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1096 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1097 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1098 #define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1099 #define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1100 #define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1101 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1102 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1103 #define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1104 #define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1105 #define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1106 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1107 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1108 #define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1109 #define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1110 #define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1111 #define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1112 #define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1113 #define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1114 #define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1115 #define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1116 #define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1117 #define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1118 #define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1119 #define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1120 #define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1121 #define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1122 #define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1123 #define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */
mbed_official 525:c320967f86b9 1124 #define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1125 #define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1126 #define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1127 #define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1128 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
mbed_official 525:c320967f86b9 1129 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
mbed_official 525:c320967f86b9 1130 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
mbed_official 525:c320967f86b9 1131 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1132 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
mbed_official 525:c320967f86b9 1133
mbed_official 525:c320967f86b9 1134 /* Bit fields for DMA IFS */
mbed_official 525:c320967f86b9 1135 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
mbed_official 525:c320967f86b9 1136 #define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */
mbed_official 525:c320967f86b9 1137 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1138 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1139 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1140 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1141 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1142 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1143 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1144 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1145 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1146 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1147 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1148 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1149 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1150 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1151 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1152 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1153 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1154 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1155 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1156 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1157 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1158 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1159 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1160 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1161 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1162 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1163 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1164 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1165 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1166 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1167 #define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1168 #define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1169 #define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1170 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1171 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1172 #define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1173 #define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1174 #define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1175 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1176 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1177 #define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1178 #define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1179 #define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1180 #define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1181 #define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1182 #define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1183 #define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1184 #define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1185 #define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1186 #define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1187 #define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1188 #define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1189 #define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1190 #define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1191 #define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1192 #define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 1193 #define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1194 #define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1195 #define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1196 #define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1197 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
mbed_official 525:c320967f86b9 1198 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
mbed_official 525:c320967f86b9 1199 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
mbed_official 525:c320967f86b9 1200 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1201 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
mbed_official 525:c320967f86b9 1202
mbed_official 525:c320967f86b9 1203 /* Bit fields for DMA IFC */
mbed_official 525:c320967f86b9 1204 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
mbed_official 525:c320967f86b9 1205 #define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */
mbed_official 525:c320967f86b9 1206 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1207 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1208 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1209 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1210 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1211 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1212 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1213 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1214 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1215 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1216 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1217 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1218 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1219 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1220 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1221 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1222 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1223 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1224 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1225 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1226 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1227 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1228 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1229 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1230 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1231 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1232 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1233 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1234 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1235 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1236 #define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1237 #define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1238 #define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1239 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1240 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1241 #define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1242 #define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1243 #define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1244 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1245 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1246 #define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1247 #define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1248 #define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1249 #define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1250 #define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1251 #define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1252 #define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1253 #define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1254 #define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1255 #define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1256 #define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1257 #define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1258 #define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1259 #define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1260 #define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1261 #define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1262 #define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1263 #define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1264 #define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1265 #define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1266 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
mbed_official 525:c320967f86b9 1267 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
mbed_official 525:c320967f86b9 1268 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
mbed_official 525:c320967f86b9 1269 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1270 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
mbed_official 525:c320967f86b9 1271
mbed_official 525:c320967f86b9 1272 /* Bit fields for DMA IEN */
mbed_official 525:c320967f86b9 1273 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
mbed_official 525:c320967f86b9 1274 #define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */
mbed_official 525:c320967f86b9 1275 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1276 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1277 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
mbed_official 525:c320967f86b9 1278 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1279 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1280 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1281 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1282 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
mbed_official 525:c320967f86b9 1283 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1284 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1285 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1286 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1287 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
mbed_official 525:c320967f86b9 1288 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1289 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1290 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1291 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1292 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
mbed_official 525:c320967f86b9 1293 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1294 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1295 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1296 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1297 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
mbed_official 525:c320967f86b9 1298 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1299 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1300 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1301 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1302 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
mbed_official 525:c320967f86b9 1303 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1304 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1305 #define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1306 #define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1307 #define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
mbed_official 525:c320967f86b9 1308 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1309 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1310 #define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1311 #define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1312 #define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
mbed_official 525:c320967f86b9 1313 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1314 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1315 #define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1316 #define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1317 #define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
mbed_official 525:c320967f86b9 1318 #define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1319 #define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1320 #define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1321 #define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1322 #define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
mbed_official 525:c320967f86b9 1323 #define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1324 #define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1325 #define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1326 #define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1327 #define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
mbed_official 525:c320967f86b9 1328 #define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1329 #define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1330 #define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */
mbed_official 525:c320967f86b9 1331 #define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1332 #define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
mbed_official 525:c320967f86b9 1333 #define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1334 #define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1335 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
mbed_official 525:c320967f86b9 1336 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
mbed_official 525:c320967f86b9 1337 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
mbed_official 525:c320967f86b9 1338 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1339 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
mbed_official 525:c320967f86b9 1340
mbed_official 525:c320967f86b9 1341 /* Bit fields for DMA CTRL */
mbed_official 525:c320967f86b9 1342 #define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */
mbed_official 525:c320967f86b9 1343 #define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */
mbed_official 525:c320967f86b9 1344 #define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */
mbed_official 525:c320967f86b9 1345 #define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */
mbed_official 525:c320967f86b9 1346 #define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */
mbed_official 525:c320967f86b9 1347 #define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
mbed_official 525:c320967f86b9 1348 #define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */
mbed_official 525:c320967f86b9 1349 #define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */
mbed_official 525:c320967f86b9 1350 #define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */
mbed_official 525:c320967f86b9 1351 #define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */
mbed_official 525:c320967f86b9 1352 #define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
mbed_official 525:c320967f86b9 1353 #define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */
mbed_official 525:c320967f86b9 1354
mbed_official 525:c320967f86b9 1355 /* Bit fields for DMA RDS */
mbed_official 525:c320967f86b9 1356 #define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */
mbed_official 525:c320967f86b9 1357 #define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */
mbed_official 525:c320967f86b9 1358 #define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1359 #define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */
mbed_official 525:c320967f86b9 1360 #define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */
mbed_official 525:c320967f86b9 1361 #define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1362 #define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1363 #define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1364 #define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */
mbed_official 525:c320967f86b9 1365 #define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */
mbed_official 525:c320967f86b9 1366 #define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1367 #define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1368 #define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1369 #define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */
mbed_official 525:c320967f86b9 1370 #define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */
mbed_official 525:c320967f86b9 1371 #define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1372 #define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1373 #define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1374 #define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */
mbed_official 525:c320967f86b9 1375 #define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */
mbed_official 525:c320967f86b9 1376 #define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1377 #define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1378 #define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1379 #define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */
mbed_official 525:c320967f86b9 1380 #define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */
mbed_official 525:c320967f86b9 1381 #define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1382 #define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1383 #define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1384 #define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */
mbed_official 525:c320967f86b9 1385 #define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */
mbed_official 525:c320967f86b9 1386 #define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1387 #define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1388 #define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1389 #define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */
mbed_official 525:c320967f86b9 1390 #define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */
mbed_official 525:c320967f86b9 1391 #define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1392 #define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1393 #define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1394 #define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */
mbed_official 525:c320967f86b9 1395 #define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */
mbed_official 525:c320967f86b9 1396 #define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1397 #define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1398 #define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1399 #define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */
mbed_official 525:c320967f86b9 1400 #define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */
mbed_official 525:c320967f86b9 1401 #define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1402 #define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1403 #define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1404 #define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */
mbed_official 525:c320967f86b9 1405 #define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */
mbed_official 525:c320967f86b9 1406 #define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1407 #define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1408 #define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1409 #define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */
mbed_official 525:c320967f86b9 1410 #define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */
mbed_official 525:c320967f86b9 1411 #define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1412 #define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1413 #define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */
mbed_official 525:c320967f86b9 1414 #define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */
mbed_official 525:c320967f86b9 1415 #define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */
mbed_official 525:c320967f86b9 1416 #define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1417 #define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */
mbed_official 525:c320967f86b9 1418
mbed_official 525:c320967f86b9 1419 /* Bit fields for DMA LOOP0 */
mbed_official 525:c320967f86b9 1420 #define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */
mbed_official 525:c320967f86b9 1421 #define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */
mbed_official 525:c320967f86b9 1422 #define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
mbed_official 525:c320967f86b9 1423 #define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
mbed_official 525:c320967f86b9 1424 #define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
mbed_official 525:c320967f86b9 1425 #define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */
mbed_official 525:c320967f86b9 1426 #define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */
mbed_official 525:c320967f86b9 1427 #define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */
mbed_official 525:c320967f86b9 1428 #define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
mbed_official 525:c320967f86b9 1429 #define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
mbed_official 525:c320967f86b9 1430 #define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */
mbed_official 525:c320967f86b9 1431
mbed_official 525:c320967f86b9 1432 /* Bit fields for DMA LOOP1 */
mbed_official 525:c320967f86b9 1433 #define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */
mbed_official 525:c320967f86b9 1434 #define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */
mbed_official 525:c320967f86b9 1435 #define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
mbed_official 525:c320967f86b9 1436 #define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
mbed_official 525:c320967f86b9 1437 #define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
mbed_official 525:c320967f86b9 1438 #define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */
mbed_official 525:c320967f86b9 1439 #define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */
mbed_official 525:c320967f86b9 1440 #define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */
mbed_official 525:c320967f86b9 1441 #define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
mbed_official 525:c320967f86b9 1442 #define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
mbed_official 525:c320967f86b9 1443 #define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */
mbed_official 525:c320967f86b9 1444
mbed_official 525:c320967f86b9 1445 /* Bit fields for DMA RECT0 */
mbed_official 525:c320967f86b9 1446 #define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */
mbed_official 525:c320967f86b9 1447 #define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */
mbed_official 525:c320967f86b9 1448 #define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */
mbed_official 525:c320967f86b9 1449 #define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */
mbed_official 525:c320967f86b9 1450 #define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
mbed_official 525:c320967f86b9 1451 #define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */
mbed_official 525:c320967f86b9 1452 #define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */
mbed_official 525:c320967f86b9 1453 #define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */
mbed_official 525:c320967f86b9 1454 #define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
mbed_official 525:c320967f86b9 1455 #define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */
mbed_official 525:c320967f86b9 1456 #define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */
mbed_official 525:c320967f86b9 1457 #define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */
mbed_official 525:c320967f86b9 1458 #define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
mbed_official 525:c320967f86b9 1459 #define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */
mbed_official 525:c320967f86b9 1460
mbed_official 525:c320967f86b9 1461 /* Bit fields for DMA CH_CTRL */
mbed_official 525:c320967f86b9 1462 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1463 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1464 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
mbed_official 525:c320967f86b9 1465 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
mbed_official 525:c320967f86b9 1466 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1467 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1468 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1469 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1470 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1471 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1472 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1473 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1474 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1475 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1476 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1477 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1478 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1479 #define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1480 #define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1481 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1482 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1483 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1484 #define _DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1485 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1486 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1487 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1488 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1489 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1490 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1491 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1492 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1493 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1494 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1495 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1496 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1497 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1498 #define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1499 #define _DMA_CH_CTRL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1500 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1501 #define _DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1502 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1503 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1504 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1505 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1506 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1507 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1508 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1509 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1510 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1511 #define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1512 #define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1513 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1514 #define _DMA_CH_CTRL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1515 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1516 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1517 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1518 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1519 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1520 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1521 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1522 #define _DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1523 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1524 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1525 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1526 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1527 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1528 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1529 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1530 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1531 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1532 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1533 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1534 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1535 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1536 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1537 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1538 #define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1539 #define DMA_CH_CTRL_SIGSEL_UART1RXDATAV (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1540 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1541 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1542 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1543 #define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1544 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1545 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1546 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1547 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1548 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1549 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1550 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1551 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1552 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1553 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1554 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1555 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1556 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1557 #define DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1558 #define DMA_CH_CTRL_SIGSEL_UART1TXBL (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1559 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1560 #define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1561 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1562 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1563 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1564 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1565 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1566 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1567 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1568 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1569 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1570 #define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1571 #define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1572 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1573 #define DMA_CH_CTRL_SIGSEL_EBIPXLFULL (_DMA_CH_CTRL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1574 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1575 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1576 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1577 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1578 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1579 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1580 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1581 #define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY (_DMA_CH_CTRL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1582 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1583 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1584 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
mbed_official 525:c320967f86b9 1585 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
mbed_official 525:c320967f86b9 1586 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1587 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1588 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1589 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1590 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1591 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1592 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1593 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1594 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1595 #define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1596 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1597 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1598 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1599 #define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1600 #define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /**< Mode UART0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1601 #define _DMA_CH_CTRL_SOURCESEL_UART1 0x0000002DUL /**< Mode UART1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1602 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1603 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1604 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1605 #define _DMA_CH_CTRL_SOURCESEL_EBI 0x00000033UL /**< Mode EBI for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1606 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1607 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1608 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1609 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1610 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1611 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1612 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1613 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1614 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1615 #define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1616 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1617 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1618 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1619 #define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1620 #define DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1621 #define DMA_CH_CTRL_SOURCESEL_UART1 (_DMA_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1622 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1623 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1624 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1625 #define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for DMA_CH_CTRL */
mbed_official 525:c320967f86b9 1626
mbed_official 525:c320967f86b9 1627 /** @} End of group EFM32GG_DMA */
mbed_official 525:c320967f86b9 1628
mbed_official 525:c320967f86b9 1629