Thierry Pébayle / mbed-STM32F030K6

Modified mbed library sources only for STM32F030K6, LQFP32 (0.8mm pitch) package, 32K Flash, 4K SRAM. Compiler target: Nucleo 32F030R8

Fork of mbed-src by mbed official

hal/gpio_irq_api.h@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Parent:
9:0ce32e54c9a7
Child:
13:0645d8841f51
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #ifndef MBED_GPIO_IRQ_API_H
emilmont 10:3bc89ef62ce7 17 #define MBED_GPIO_IRQ_API_H
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 #include "device.h"
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 #if DEVICE_INTERRUPTIN
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 24 extern "C" {
emilmont 10:3bc89ef62ce7 25 #endif
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 typedef enum {
emilmont 10:3bc89ef62ce7 28 IRQ_NONE,
emilmont 10:3bc89ef62ce7 29 IRQ_RISE,
emilmont 10:3bc89ef62ce7 30 IRQ_FALL
emilmont 10:3bc89ef62ce7 31 } gpio_irq_event;
emilmont 10:3bc89ef62ce7 32
emilmont 10:3bc89ef62ce7 33 typedef struct gpio_irq_s gpio_irq_t;
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35 typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
emilmont 10:3bc89ef62ce7 38 void gpio_irq_free(gpio_irq_t *obj);
emilmont 10:3bc89ef62ce7 39 void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
emilmont 10:3bc89ef62ce7 40
emilmont 10:3bc89ef62ce7 41 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 42 }
emilmont 10:3bc89ef62ce7 43 #endif
emilmont 10:3bc89ef62ce7 44
emilmont 10:3bc89ef62ce7 45 #endif
emilmont 10:3bc89ef62ce7 46
emilmont 10:3bc89ef62ce7 47 #endif