![](/media/cache/img/default_profile.jpg.50x50_q85.jpg)
k
Dependencies: MAX30003 max32630fthr DS1307
main.cpp
- Committer:
- coreyharris
- Date:
- 2017-08-22
- Revision:
- 3:420d5efbd967
- Parent:
- 2:812d40f1853d
- Child:
- 4:06e258ff0b97
File content as of revision 3:420d5efbd967:
#include "mbed.h" #include "max32630fthr.h" #include "MAX30003.h" MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3); void ecg_config(MAX30003 &ecgAFE); /* ECG FIFO nearly full callback */ volatile bool ecgFIFOIntFlag = 0; void ecgFIFO_callback() { ecgFIFOIntFlag = 1; } int main() { const int RTOR_STATUS_MASK = ( 1<<10 ); const int EINT_STATUS_MASK = ( 1<<23 ); Serial pc(USBTX, USBRX); // Use USB debug probe for serial link pc.baud(115200); // Baud rate = 115200 DigitalOut rLed(LED1, LED_OFF); // Debug LEDs DigitalOut gLed(LED2, LED_OFF); DigitalOut bLed(LED3, LED_OFF); InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI, // P5_2 = MISO, P5_0 = SCK MAX30003 * ecgAFE; ecgAFE = new MAX30003(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3 ecg_config(*ecgAFE); // Config ECG ecgAFE->writeRegister( MAX30003::SYNCH , 0); uint32_t ecgFIFO, readSamples, idx, ETAG[32], status, RtoR; int16_t ecgSample[32]; float BPM; while(1) { /* Read back ECG samples from the FIFO */ if( ecgFIFOIntFlag ) { pc.printf("Interrupt received....\r\n"); status = ecgAFE->readRegister( MAX30003::STATUS ); // Read the STATUS register pc.printf("Status : 0x%x\r\n" "Current BPM is %3.2f\r\n\r\n", status, BPM); // Check if R-to-R interrupt asserted if( ( status & RTOR_STATUS_MASK ) == RTOR_STATUS_MASK ){ // Check if RtoR update ecgFIFOIntFlag = 0; pc.printf("R-to-R Interrupt \r\n"); RtoR = ecgAFE->readRegister( MAX30003::RTOR ); // Read RtoR register BPM = 60.0*RtoR/32768.0; // Convert to BPM pc.printf("RtoR : %d\r\n\r\n", RtoR); // Print BPM/RtoR } // Check if EINT interrupt asserted if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) { ecgFIFOIntFlag = 0; pc.printf("FIFO Interrupt \r\n"); readSamples = 0; // Reset sample counter do { ecgFIFO = ecgAFE->readRegister( MAX30003::ECG_FIFO ); // Read FIFO ecgSample[readSamples] = ecgFIFO >> 8; // Isolate voltage data ETAG[readSamples] = ( ecgFIFO >> 3 ) & 0b111; // Isolate ETAG readSamples++; // Increment sample counter // Check that sample is not last sample in FIFO } while ( ETAG[readSamples-1] == 0x0 || ETAG[readSamples-1] == 0x1 ); pc.printf("%d samples read from FIFO \r\n", readSamples); // Check if FIFO has overflowed if( ETAG[readECGSamples - 1] == 0x7 ){ ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO } /* Print results */ for( idx = 0; idx < readSamples; idx++ ) { pc.printf("Sample : %6d, \tETAG : 0x%x\r\n", ecgSample[idx], ETAG[idx]); } pc.printf("\r\n\r\n\r\n"); } } } } void ecg_config(MAX30003& ecgAFE) { // Reset ECG to clear registers ecgAFE.writeRegister( MAX30003::SW_RST , 0); // General config register setting MAX30003::GeneralConfiguration_u CNFG_GEN_r; CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all); // ECG Config register setting MAX30003::ECGConfiguration_u CNFG_ECG_r; CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all); //R-to-R configuration MAX30003::RtoR1Configuration_u CNFG_RTOR_r; CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all); //Manage interrupts register setting MAX30003::ManageInterrupts_u MNG_INT_r; MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all); //Enable interrupts register setting MAX30003::EnableInterrupts_u EN_INT_r; EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt EN_INT_r.bits.en_rrint = 1; // Enable R-to-R interrupt EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all); //Dyanmic modes config MAX30003::ManageDynamicModes_u MNG_DYN_r; MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all); return; }