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Dependencies: MAX30003 max32630fthr DS1307
Diff: main.cpp
- Revision:
- 1:86843c27cc81
- Parent:
- 0:38c49bc37c7c
- Child:
- 2:812d40f1853d
--- a/main.cpp Wed Aug 16 22:59:59 2017 +0000 +++ b/main.cpp Thu Aug 17 19:56:40 2017 +0000 @@ -16,48 +16,55 @@ int main() { - DigitalOut rLed(LED1, LED_OFF); + Serial pc(USBTX, USBRX); // Use USB debug probe for serial link + pc.baud(115200); // Baud rate = 115200 + + DigitalOut rLed(LED1, LED_OFF); // Debug LEDs DigitalOut gLed(LED2, LED_OFF); DigitalOut bLed(LED3, LED_OFF); - Serial pc(USBTX, USBRX); - pc.baud(115200); + InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the + ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt - pc.printf("Running.... \r\n\r\n"); - wait(0.5); - - SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); + SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI, + // P5_2 = MISO, P5_0 = SCK MAX30003 *ecgAFE; - ecgAFE = new MAX30003(spiBus, P5_3); - ecg_config(*ecgAFE); + ecgAFE = new MAX30003(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3 + ecg_config(*ecgAFE); // Config ECG + - /* Peripehral configuration */ - InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the ecg FIFO almost full interrupt - ecgFIFO_int.fall(&ecgFIFO_callback); // + ecgAFE->writeRegister( MAX30003::SYNCH , 0); - pc.printf("Config. complete.... \r\n\r\n"); - wait(0.5); - - uint32_t ecgFIFO[32]; - int16_t ecgSample, ETAG; - while(1) - { + uint32_t ecgFIFO, readSamples, idx, ETAG[32]; + int16_t ecgSample[32]; + while(1) { + + bLed = LED_ON; + /* Read back ECG samples from the FIFO */ if( ecgFIFOIntFlag ) { - - for( int i = 0; i < 16; i++ ){ - ecgFIFO[i] = ecgAFE->readRegister( MAX30003::ECG_FIFO ); - ecgSample = ecgFIFO[i] >> 8; - ETAG = ( ecgFIFO[i] >> 3 ) && 0x07; - - pc.printf("Sample : %5d, \t ETAG : 0x%x \r\n", ecgSample, ETAG); + pc.printf("Interrupt received....\r\n\r\n"); + bLed = LED_OFF; + ecgFIFOIntFlag = 0; // Clear interrupt flag + readSamples = 0; // Reset sample counter + do { + ecgFIFO = ecgAFE->readRegister( MAX30003::ECG_FIFO ); // Read FIFO + ecgSample[readSamples] = ecgFIFO >> 8; // Isolate voltage data + ETAG[readSamples] = ( ecgFIFO >> 3 ) & 0b111; // Isolate ETAG + readSamples++; // Increment sample counter + } while ( ETAG[readSamples-1] == 0x0 || ETAG[readSamples-1] == 0x1 ); // Check that sample is valid + + pc.printf("%d samples read from FIFO \r\n", readSamples); + + for( idx = 0; idx < readSamples; idx++ ) { + pc.printf("Sample : %6d, \tETAG : 0x%x\r\n", ecgSample[idx], ETAG[idx]); } - - bLed = !bLed; - ecgFIFOIntFlag = 0; - + + pc.printf("\r\n\r\n\r\n"); + } + } } @@ -66,70 +73,62 @@ void ecg_config(MAX30003& ecgAFE) { - // Reset ECG to clear registers - ecgAFE.writeRegister( MAX30003::SW_RST , 0); - - - - // General config register setting - MAX30003::GeneralConfiguration_u CNFG_GEN_r; - CNFG_GEN_r.bits.en_ecg = 1; - CNFG_GEN_r.bits.rbiasn = 1; - CNFG_GEN_r.bits.rbiasp = 1; - CNFG_GEN_r.bits.en_rbias = 1; - CNFG_GEN_r.bits.imag = 2; - CNFG_GEN_r.bits.en_dcloff = 1; - ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all); - - - - // ECG Config register setting - MAX30003::ECGConfiguration_u CNFG_ECG_r; - CNFG_ECG_r.bits.dlpf = 1; - CNFG_ECG_r.bits.dhpf = 1; - CNFG_ECG_r.bits.gain = 3; - CNFG_ECG_r.bits.rate = 3; - ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all); + // Reset ECG to clear registers + ecgAFE.writeRegister( MAX30003::SW_RST , 0); - //R-to-R configuration - MAX30003::RtoR1Configuration_u CNFG_RTOR_r; - CNFG_RTOR_r.bits.en_rtor = 1; - ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all); + // General config register setting + MAX30003::GeneralConfiguration_u CNFG_GEN_r; + CNFG_GEN_r.bits.en_ecg = 1; + CNFG_GEN_r.bits.rbiasn = 1; + CNFG_GEN_r.bits.rbiasp = 1; + CNFG_GEN_r.bits.en_rbias = 1; + CNFG_GEN_r.bits.imag = 2; + CNFG_GEN_r.bits.en_dcloff = 1; + ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all); + + + // ECG Config register setting + MAX30003::ECGConfiguration_u CNFG_ECG_r; + CNFG_ECG_r.bits.dlpf = 1; + CNFG_ECG_r.bits.dhpf = 1; + CNFG_ECG_r.bits.gain = 3; + CNFG_ECG_r.bits.rate = 3; + ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all); + + + //R-to-R configuration + MAX30003::RtoR1Configuration_u CNFG_RTOR_r; + CNFG_RTOR_r.bits.en_rtor = 1; + ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all); + + + //Manage interrupts register setting + MAX30003::ManageInterrupts_u MNG_INT_r; + MNG_INT_r.bits.efit = 0b00011; + ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all); - - // Manage interrupts register setting - MAX30003::ManageInterrupts_u MNG_INT_r; - MNG_INT_r.bits.efit = 0b01111; - ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all); - - - - // Enable interrupts register setting - MAX30003::EnableInterrupts_u EN_INT_r; - EN_INT_r.all = 0; - EN_INT_r.bits.en_eint = 1; - EN_INT_r.bits.intb_type = 0b11; - ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all); - + //Enable interrupts register setting + MAX30003::EnableInterrupts_u EN_INT_r; + EN_INT_r.all = 0; + EN_INT_r.bits.en_eint = 1; + EN_INT_r.bits.intb_type = 0b11; + ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all); + + + //Dyanmic modes config + MAX30003::ManageDynamicModes_u MNG_DYN_r; + MNG_DYN_r.bits.fast = 0; + ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all); + - - // Dyanmic modes config - MAX30003::ManageDynamicModes_u MNG_DYN_r; - MNG_DYN_r.bits.fast = 0; - ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all); - - + //MUX Config + MAX30003::MuxConfiguration_u CNFG_MUX_r; + CNFG_MUX_r.bits.pol = 0; + ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all); - // MUX Config - MAX30003::MuxConfiguration_u CNFG_MUX_r; - CNFG_MUX_r.bits.pol = 0; - ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all); - - - ecgAFE.writeRegister( MAX30003::SYNCH , 0); - + return; }