It is the library published by sparkfun, edited accordingly to make it work under mbed platform.
Dependents: MPU9250-dmp-bluepill MPU9250-dmp
MPU9250_RegisterMap.h@4:2c4e849b8ecf, 2017-08-15 (annotated)
- Committer:
- mbedoguz
- Date:
- Tue Aug 15 10:49:44 2017 +0000
- Revision:
- 4:2c4e849b8ecf
- Parent:
- 0:d1f0ae13f4a7
computeEulerAngles are corrected to below issue ; https://github.com/sparkfun/SparkFun_MPU-9250-DMP_Arduino_Library/issues/5
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbedoguz | 0:d1f0ae13f4a7 | 1 | /****************************************************************************** |
mbedoguz | 0:d1f0ae13f4a7 | 2 | MPU9250_RegisterMap.h - MPU-9250 Digital Motion Processor Arduino Library |
mbedoguz | 0:d1f0ae13f4a7 | 3 | Jim Lindblom @ SparkFun Electronics |
mbedoguz | 0:d1f0ae13f4a7 | 4 | original creation date: November 23, 2016 |
mbedoguz | 0:d1f0ae13f4a7 | 5 | https://github.com/sparkfun/SparkFun_MPU9250_DMP_Arduino_Library |
mbedoguz | 0:d1f0ae13f4a7 | 6 | |
mbedoguz | 0:d1f0ae13f4a7 | 7 | This library implements motion processing functions of Invensense's MPU-9250. |
mbedoguz | 0:d1f0ae13f4a7 | 8 | It is based on their Emedded MotionDriver 6.12 library. |
mbedoguz | 0:d1f0ae13f4a7 | 9 | https://www.invensense.com/developers/software-downloads/ |
mbedoguz | 0:d1f0ae13f4a7 | 10 | |
mbedoguz | 0:d1f0ae13f4a7 | 11 | Development environment specifics: |
mbedoguz | 0:d1f0ae13f4a7 | 12 | Arduino IDE 1.6.12 |
mbedoguz | 0:d1f0ae13f4a7 | 13 | SparkFun 9DoF Razor IMU M0 |
mbedoguz | 0:d1f0ae13f4a7 | 14 | |
mbedoguz | 0:d1f0ae13f4a7 | 15 | Supported Platforms: |
mbedoguz | 0:d1f0ae13f4a7 | 16 | - ATSAMD21 (Arduino Zero, SparkFun SAMD21 Breakouts) |
mbedoguz | 0:d1f0ae13f4a7 | 17 | ******************************************************************************/ |
mbedoguz | 0:d1f0ae13f4a7 | 18 | #ifndef _MPU9250_REGISTER_MAP_H_ |
mbedoguz | 0:d1f0ae13f4a7 | 19 | #define _MPU9250_REGISTER_MAP_H_ |
mbedoguz | 0:d1f0ae13f4a7 | 20 | |
mbedoguz | 0:d1f0ae13f4a7 | 21 | enum mpu9250_register { |
mbedoguz | 0:d1f0ae13f4a7 | 22 | MPU9250_SELF_TEST_X_GYRO = 0x00, |
mbedoguz | 0:d1f0ae13f4a7 | 23 | MPU9250_SELF_TEST_Y_GYRO = 0x01, |
mbedoguz | 0:d1f0ae13f4a7 | 24 | MPU9250_SELF_TEST_Z_GYRO = 0x02, |
mbedoguz | 0:d1f0ae13f4a7 | 25 | MPU9250_SELF_TEST_X_ACCEL = 0x0D, |
mbedoguz | 0:d1f0ae13f4a7 | 26 | MPU9250_SELF_TEST_Y_ACCEL = 0x0E, |
mbedoguz | 0:d1f0ae13f4a7 | 27 | MPU9250_SELF_TEST_Z_ACCEL = 0x0F, |
mbedoguz | 0:d1f0ae13f4a7 | 28 | MPU9250_XG_OFFSET_H = 0x13, |
mbedoguz | 0:d1f0ae13f4a7 | 29 | MPU9250_XG_OFFSET_L = 0x14, |
mbedoguz | 0:d1f0ae13f4a7 | 30 | MPU9250_YG_OFFSET_H = 0x15, |
mbedoguz | 0:d1f0ae13f4a7 | 31 | MPU9250_YG_OFFSET_L = 0x16, |
mbedoguz | 0:d1f0ae13f4a7 | 32 | MPU9250_ZG_OFFSET_H = 0x17, |
mbedoguz | 0:d1f0ae13f4a7 | 33 | MPU9250_ZG_OFFSET_L = 0x18, |
mbedoguz | 0:d1f0ae13f4a7 | 34 | MPU9250_SMPLRT_DIV = 0x19, |
mbedoguz | 0:d1f0ae13f4a7 | 35 | MPU9250_CONFIG = 0x1A, |
mbedoguz | 0:d1f0ae13f4a7 | 36 | MPU9250_GYRO_CONFIG = 0x1B, |
mbedoguz | 0:d1f0ae13f4a7 | 37 | MPU9250_ACCEL_CONFIG = 0x1C, |
mbedoguz | 0:d1f0ae13f4a7 | 38 | MPU9250_ACCEL_CONFIG_2 = 0x1D, |
mbedoguz | 0:d1f0ae13f4a7 | 39 | MPU9250_LP_ACCEL_ODR = 0x1E, |
mbedoguz | 0:d1f0ae13f4a7 | 40 | MPU9250_WOM_THR = 0x1F, |
mbedoguz | 0:d1f0ae13f4a7 | 41 | MPU9250_FIFO_EN = 0x23, |
mbedoguz | 0:d1f0ae13f4a7 | 42 | MPU9250_I2C_MST_CTRL = 0x24, |
mbedoguz | 0:d1f0ae13f4a7 | 43 | MPU9250_I2C_SLV0_ADDR = 0x25, |
mbedoguz | 0:d1f0ae13f4a7 | 44 | MPU9250_I2C_SLV0_REG = 0x26, |
mbedoguz | 0:d1f0ae13f4a7 | 45 | MPU9250_I2C_SLV0_CTRL = 0x27, |
mbedoguz | 0:d1f0ae13f4a7 | 46 | MPU9250_I2C_SLV1_ADDR = 0x28, |
mbedoguz | 0:d1f0ae13f4a7 | 47 | MPU9250_I2C_SLV1_REG = 0x29, |
mbedoguz | 0:d1f0ae13f4a7 | 48 | MPU9250_I2C_SLV1_CTRL = 0x2A, |
mbedoguz | 0:d1f0ae13f4a7 | 49 | MPU9250_I2C_SLV2_ADDR = 0x2B, |
mbedoguz | 0:d1f0ae13f4a7 | 50 | MPU9250_I2C_SLV2_REG = 0x2C, |
mbedoguz | 0:d1f0ae13f4a7 | 51 | MPU9250_I2C_SLV2_CTRL = 0x2D, |
mbedoguz | 0:d1f0ae13f4a7 | 52 | MPU9250_I2C_SLV3_ADDR = 0x2E, |
mbedoguz | 0:d1f0ae13f4a7 | 53 | MPU9250_I2C_SLV3_REG = 0x2F, |
mbedoguz | 0:d1f0ae13f4a7 | 54 | MPU9250_I2C_SLV3_CTRL = 0x30, |
mbedoguz | 0:d1f0ae13f4a7 | 55 | MPU9250_I2C_SLV4_ADDR = 0x31, |
mbedoguz | 0:d1f0ae13f4a7 | 56 | MPU9250_I2C_SLV4_REG = 0x32, |
mbedoguz | 0:d1f0ae13f4a7 | 57 | MPU9250_I2C_SLV4_DO = 0x33, |
mbedoguz | 0:d1f0ae13f4a7 | 58 | MPU9250_I2C_SLV4_CTRL = 0x34, |
mbedoguz | 0:d1f0ae13f4a7 | 59 | MPU9250_I2C_SLV4_DI = 0x35, |
mbedoguz | 0:d1f0ae13f4a7 | 60 | MPU9250_I2C_MST_STATUS = 0x36, |
mbedoguz | 0:d1f0ae13f4a7 | 61 | MPU9250_INT_PIN_CFG = 0x37, |
mbedoguz | 0:d1f0ae13f4a7 | 62 | MPU9250_INT_ENABLE = 0x38, |
mbedoguz | 0:d1f0ae13f4a7 | 63 | MPU9250_INT_STATUS = 0x3A, |
mbedoguz | 0:d1f0ae13f4a7 | 64 | MPU9250_ACCEL_XOUT_H = 0x3B, |
mbedoguz | 0:d1f0ae13f4a7 | 65 | MPU9250_ACCEL_XOUT_L = 0x3C, |
mbedoguz | 0:d1f0ae13f4a7 | 66 | MPU9250_ACCEL_YOUT_H = 0x3D, |
mbedoguz | 0:d1f0ae13f4a7 | 67 | MPU9250_ACCEL_YOUT_L = 0x3E, |
mbedoguz | 0:d1f0ae13f4a7 | 68 | MPU9250_ACCEL_ZOUT_H = 0x3F, |
mbedoguz | 0:d1f0ae13f4a7 | 69 | MPU9250_ACCEL_ZOUT_L = 0x40, |
mbedoguz | 0:d1f0ae13f4a7 | 70 | MPU9250_TEMP_OUT_H = 0x41, |
mbedoguz | 0:d1f0ae13f4a7 | 71 | MPU9250_TEMP_OUT_L = 0x42, |
mbedoguz | 0:d1f0ae13f4a7 | 72 | MPU9250_GYRO_XOUT_H = 0x43, |
mbedoguz | 0:d1f0ae13f4a7 | 73 | MPU9250_GYRO_XOUT_L = 0x44, |
mbedoguz | 0:d1f0ae13f4a7 | 74 | MPU9250_GYRO_YOUT_H = 0x45, |
mbedoguz | 0:d1f0ae13f4a7 | 75 | MPU9250_GYRO_YOUT_L = 0x46, |
mbedoguz | 0:d1f0ae13f4a7 | 76 | MPU9250_GYRO_ZOUT_H = 0x47, |
mbedoguz | 0:d1f0ae13f4a7 | 77 | MPU9250_GYRO_ZOUT_L = 0x48, |
mbedoguz | 0:d1f0ae13f4a7 | 78 | MPU9250_EXT_SENS_DATA_00 = 0x49, |
mbedoguz | 0:d1f0ae13f4a7 | 79 | MPU9250_EXT_SENS_DATA_01 = 0x4A, |
mbedoguz | 0:d1f0ae13f4a7 | 80 | MPU9250_EXT_SENS_DATA_02 = 0x4B, |
mbedoguz | 0:d1f0ae13f4a7 | 81 | MPU9250_EXT_SENS_DATA_03 = 0x4C, |
mbedoguz | 0:d1f0ae13f4a7 | 82 | MPU9250_EXT_SENS_DATA_04 = 0x4D, |
mbedoguz | 0:d1f0ae13f4a7 | 83 | MPU9250_EXT_SENS_DATA_05 = 0x4E, |
mbedoguz | 0:d1f0ae13f4a7 | 84 | MPU9250_EXT_SENS_DATA_06 = 0x4F, |
mbedoguz | 0:d1f0ae13f4a7 | 85 | MPU9250_EXT_SENS_DATA_07 = 0x50, |
mbedoguz | 0:d1f0ae13f4a7 | 86 | MPU9250_EXT_SENS_DATA_08 = 0x51, |
mbedoguz | 0:d1f0ae13f4a7 | 87 | MPU9250_EXT_SENS_DATA_09 = 0x52, |
mbedoguz | 0:d1f0ae13f4a7 | 88 | MPU9250_EXT_SENS_DATA_10 = 0x53, |
mbedoguz | 0:d1f0ae13f4a7 | 89 | MPU9250_EXT_SENS_DATA_11 = 0x54, |
mbedoguz | 0:d1f0ae13f4a7 | 90 | MPU9250_EXT_SENS_DATA_12 = 0x55, |
mbedoguz | 0:d1f0ae13f4a7 | 91 | MPU9250_EXT_SENS_DATA_13 = 0x56, |
mbedoguz | 0:d1f0ae13f4a7 | 92 | MPU9250_EXT_SENS_DATA_14 = 0x57, |
mbedoguz | 0:d1f0ae13f4a7 | 93 | MPU9250_EXT_SENS_DATA_15 = 0x58, |
mbedoguz | 0:d1f0ae13f4a7 | 94 | MPU9250_EXT_SENS_DATA_16 = 0x59, |
mbedoguz | 0:d1f0ae13f4a7 | 95 | MPU9250_EXT_SENS_DATA_17 = 0x5A, |
mbedoguz | 0:d1f0ae13f4a7 | 96 | MPU9250_EXT_SENS_DATA_18 = 0x5B, |
mbedoguz | 0:d1f0ae13f4a7 | 97 | MPU9250_EXT_SENS_DATA_19 = 0x5C, |
mbedoguz | 0:d1f0ae13f4a7 | 98 | MPU9250_EXT_SENS_DATA_20 = 0x5D, |
mbedoguz | 0:d1f0ae13f4a7 | 99 | MPU9250_EXT_SENS_DATA_21 = 0x5E, |
mbedoguz | 0:d1f0ae13f4a7 | 100 | MPU9250_EXT_SENS_DATA_22 = 0x5F, |
mbedoguz | 0:d1f0ae13f4a7 | 101 | MPU9250_EXT_SENS_DATA_23 = 0x60, |
mbedoguz | 0:d1f0ae13f4a7 | 102 | MPU9250_I2C_SLV0_DO = 0x63, |
mbedoguz | 0:d1f0ae13f4a7 | 103 | MPU9250_I2C_SLV1_DO = 0x64, |
mbedoguz | 0:d1f0ae13f4a7 | 104 | MPU9250_I2C_SLV2_DO = 0x65, |
mbedoguz | 0:d1f0ae13f4a7 | 105 | MPU9250_I2C_SLV3_DO = 0x66, |
mbedoguz | 0:d1f0ae13f4a7 | 106 | MPU9250_I2C_MST_DELAY_CTRL =0x67, |
mbedoguz | 0:d1f0ae13f4a7 | 107 | MPU9250_SIGNAL_PATH_RESET = 0x68, |
mbedoguz | 0:d1f0ae13f4a7 | 108 | MPU9250_MOT_DETECT_CTRL = 0x69, |
mbedoguz | 0:d1f0ae13f4a7 | 109 | MPU9250_USER_CTRL = 0x6A, |
mbedoguz | 0:d1f0ae13f4a7 | 110 | MPU9250_PWR_MGMT_1 = 0x6B, |
mbedoguz | 0:d1f0ae13f4a7 | 111 | MPU9250_PWR_MGMT_2 = 0x6C, |
mbedoguz | 0:d1f0ae13f4a7 | 112 | MPU9250_FIFO_COUNTH = 0x72, |
mbedoguz | 0:d1f0ae13f4a7 | 113 | MPU9250_FIFO_COUNTL = 0x73, |
mbedoguz | 0:d1f0ae13f4a7 | 114 | MPU9250_FIFO_R_W = 0x74, |
mbedoguz | 0:d1f0ae13f4a7 | 115 | MPU9250_WHO_AM_I = 0x75, |
mbedoguz | 0:d1f0ae13f4a7 | 116 | MPU9250_XA_OFFSET_H = 0x77, |
mbedoguz | 0:d1f0ae13f4a7 | 117 | MPU9250_XA_OFFSET_L = 0x78, |
mbedoguz | 0:d1f0ae13f4a7 | 118 | MPU9250_YA_OFFSET_H = 0x7A, |
mbedoguz | 0:d1f0ae13f4a7 | 119 | MPU9250_YA_OFFSET_L = 0x7B, |
mbedoguz | 0:d1f0ae13f4a7 | 120 | MPU9250_ZA_OFFSET_H = 0x7D, |
mbedoguz | 0:d1f0ae13f4a7 | 121 | MPU9250_ZA_OFFSET_L = 0x7E |
mbedoguz | 0:d1f0ae13f4a7 | 122 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 123 | |
mbedoguz | 0:d1f0ae13f4a7 | 124 | enum interrupt_status_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 125 | INT_STATUS_RAW_DATA_RDY_INT = 0, |
mbedoguz | 0:d1f0ae13f4a7 | 126 | INT_STATUS_FSYNC_INT = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 127 | INT_STATUS_FIFO_OVERFLOW_INT = 4, |
mbedoguz | 0:d1f0ae13f4a7 | 128 | INT_STATUS_WOM_INT = 6, |
mbedoguz | 0:d1f0ae13f4a7 | 129 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 130 | |
mbedoguz | 0:d1f0ae13f4a7 | 131 | enum gyro_config_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 132 | GYRO_CONFIG_FCHOICE_B = 0, |
mbedoguz | 0:d1f0ae13f4a7 | 133 | GYRO_CONFIG_GYRO_FS_SEL = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 134 | GYRO_CONFIG_ZGYRO_CTEN = 5, |
mbedoguz | 0:d1f0ae13f4a7 | 135 | GYRO_CONFIG_YGYRO_CTEN = 6, |
mbedoguz | 0:d1f0ae13f4a7 | 136 | GYRO_CONFIG_XGYRO_CTEN = 7, |
mbedoguz | 0:d1f0ae13f4a7 | 137 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 138 | #define MPU9250_GYRO_FS_SEL_MASK 0x3 |
mbedoguz | 0:d1f0ae13f4a7 | 139 | #define MPU9250_GYRO_FCHOICE_MASK 0x3 |
mbedoguz | 0:d1f0ae13f4a7 | 140 | |
mbedoguz | 0:d1f0ae13f4a7 | 141 | enum accel_config_bit { |
mbedoguz | 0:d1f0ae13f4a7 | 142 | ACCEL_CONFIG_ACCEL_FS_SEL = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 143 | ACCEL_CONFIG_AZ_ST_EN = 5, |
mbedoguz | 0:d1f0ae13f4a7 | 144 | ACCEL_CONFIG_AY_ST_EN = 6, |
mbedoguz | 0:d1f0ae13f4a7 | 145 | ACCEL_CONFIG_AX_ST_EN = 7, |
mbedoguz | 0:d1f0ae13f4a7 | 146 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 147 | #define MPU9250_ACCEL_FS_SEL_MASK 0x3 |
mbedoguz | 0:d1f0ae13f4a7 | 148 | |
mbedoguz | 0:d1f0ae13f4a7 | 149 | enum accel_config_2_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 150 | ACCEL_CONFIG_2_A_DLPFCFG = 0, |
mbedoguz | 0:d1f0ae13f4a7 | 151 | ACCEL_CONFIG_2_ACCEL_FCHOICE_B = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 152 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 153 | |
mbedoguz | 0:d1f0ae13f4a7 | 154 | enum pwr_mgmt_1_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 155 | PWR_MGMT_1_CLKSEL = 0, |
mbedoguz | 0:d1f0ae13f4a7 | 156 | PWR_MGMT_1_PD_PTAT = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 157 | PWR_MGMT_1_GYRO_STANDBY = 4, |
mbedoguz | 0:d1f0ae13f4a7 | 158 | PWR_MGMT_1_CYCLE = 5, |
mbedoguz | 0:d1f0ae13f4a7 | 159 | PWR_MGMT_1_SLEEP = 6, |
mbedoguz | 0:d1f0ae13f4a7 | 160 | PWR_MGMT_1_H_RESET = 7 |
mbedoguz | 0:d1f0ae13f4a7 | 161 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 162 | |
mbedoguz | 0:d1f0ae13f4a7 | 163 | enum pwr_mgmt_2_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 164 | PWR_MGMT_2_DISABLE_ZG = 0, |
mbedoguz | 0:d1f0ae13f4a7 | 165 | PWR_MGMT_2_DISABLE_YG = 1, |
mbedoguz | 0:d1f0ae13f4a7 | 166 | PWR_MGMT_2_DISABLE_XG = 2, |
mbedoguz | 0:d1f0ae13f4a7 | 167 | PWR_MGMT_2_DISABLE_ZA = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 168 | PWR_MGMT_2_DISABLE_YA = 4, |
mbedoguz | 0:d1f0ae13f4a7 | 169 | PWR_MGMT_2_DISABLE_XA = 5, |
mbedoguz | 0:d1f0ae13f4a7 | 170 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 171 | |
mbedoguz | 0:d1f0ae13f4a7 | 172 | enum int_enable_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 173 | INT_ENABLE_RAW_RDY_EN = 0, |
mbedoguz | 0:d1f0ae13f4a7 | 174 | INT_ENABLE_FSYNC_INT_EN = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 175 | INT_ENABLE_FIFO_OVERFLOW_EN = 4, |
mbedoguz | 0:d1f0ae13f4a7 | 176 | INT_ENABLE_WOM_EN = 6, |
mbedoguz | 0:d1f0ae13f4a7 | 177 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 178 | |
mbedoguz | 0:d1f0ae13f4a7 | 179 | enum int_pin_cfg_bits { |
mbedoguz | 0:d1f0ae13f4a7 | 180 | INT_PIN_CFG_BYPASS_EN = 1, |
mbedoguz | 0:d1f0ae13f4a7 | 181 | INT_PIN_CFG_FSYNC_INT_MODE_EN = 2, |
mbedoguz | 0:d1f0ae13f4a7 | 182 | INT_PIN_CFG_ACTL_FSYNC = 3, |
mbedoguz | 0:d1f0ae13f4a7 | 183 | INT_PIN_CFG_INT_ANYRD_2CLEAR = 4, |
mbedoguz | 0:d1f0ae13f4a7 | 184 | INT_PIN_CFG_LATCH_INT_EN = 5, |
mbedoguz | 0:d1f0ae13f4a7 | 185 | INT_PIN_CFG_OPEN = 6, |
mbedoguz | 0:d1f0ae13f4a7 | 186 | INT_PIN_CFG_ACTL = 7, |
mbedoguz | 0:d1f0ae13f4a7 | 187 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 188 | #define INT_PIN_CFG_INT_MASK 0xF0 |
mbedoguz | 0:d1f0ae13f4a7 | 189 | |
mbedoguz | 0:d1f0ae13f4a7 | 190 | #define MPU9250_WHO_AM_I_RESULT 0x71 |
mbedoguz | 0:d1f0ae13f4a7 | 191 | |
mbedoguz | 0:d1f0ae13f4a7 | 192 | enum ak8963_register { |
mbedoguz | 0:d1f0ae13f4a7 | 193 | AK8963_WIA = 0x0, |
mbedoguz | 0:d1f0ae13f4a7 | 194 | AK8963_INFO = 0x1, |
mbedoguz | 0:d1f0ae13f4a7 | 195 | AK8963_ST1 = 0x2, |
mbedoguz | 0:d1f0ae13f4a7 | 196 | AK8963_HXL = 0x3, |
mbedoguz | 0:d1f0ae13f4a7 | 197 | AK8963_HXH = 0x4, |
mbedoguz | 0:d1f0ae13f4a7 | 198 | AK8963_HYL = 0x5, |
mbedoguz | 0:d1f0ae13f4a7 | 199 | AK8963_HYH = 0x6, |
mbedoguz | 0:d1f0ae13f4a7 | 200 | AK8963_HZL = 0x7, |
mbedoguz | 0:d1f0ae13f4a7 | 201 | AK8963_HZH = 0x8, |
mbedoguz | 0:d1f0ae13f4a7 | 202 | AK8963_ST2 = 0x9, |
mbedoguz | 0:d1f0ae13f4a7 | 203 | AK8963_CNTL = 0xA, |
mbedoguz | 0:d1f0ae13f4a7 | 204 | AK8963_RSV = 0xB, |
mbedoguz | 0:d1f0ae13f4a7 | 205 | AK8963_ASTC = 0xC, |
mbedoguz | 0:d1f0ae13f4a7 | 206 | AK8963_TS1 = 0xD, |
mbedoguz | 0:d1f0ae13f4a7 | 207 | AK8963_TS2 = 0xE, |
mbedoguz | 0:d1f0ae13f4a7 | 208 | AK8963_I2CDIS = 0xF, |
mbedoguz | 0:d1f0ae13f4a7 | 209 | AK8963_ASAX = 0x10, |
mbedoguz | 0:d1f0ae13f4a7 | 210 | AK8963_ASAY = 0x11, |
mbedoguz | 0:d1f0ae13f4a7 | 211 | AK8963_ASAZ = 0x12, |
mbedoguz | 0:d1f0ae13f4a7 | 212 | }; |
mbedoguz | 0:d1f0ae13f4a7 | 213 | #define MAG_CTRL_OP_MODE_MASK 0xF |
mbedoguz | 0:d1f0ae13f4a7 | 214 | |
mbedoguz | 0:d1f0ae13f4a7 | 215 | #define AK8963_ST1_DRDY_BIT 0 |
mbedoguz | 0:d1f0ae13f4a7 | 216 | |
mbedoguz | 0:d1f0ae13f4a7 | 217 | #define AK8963_WHO_AM_I_RESULT 0x48 |
mbedoguz | 0:d1f0ae13f4a7 | 218 | |
mbedoguz | 0:d1f0ae13f4a7 | 219 | #endif // _MPU9250_REGISTER_MAP_H_ |